diff options
| -rw-r--r-- | src/common/gpe_util.h | 2 | ||||
| -rw-r--r-- | src/occ_405/amec/amec_sensors_fw.c | 261 | ||||
| -rwxr-xr-x | src/occ_405/amec/amec_sensors_fw.h | 3 | ||||
| -rwxr-xr-x | src/occ_405/occbuildname.c | 2 | ||||
| -rwxr-xr-x | src/occ_405/proc/proc_data.c | 2 | ||||
| -rwxr-xr-x | src/occ_405/rtls/rtls.h | 3 | ||||
| -rwxr-xr-x | src/occ_405/rtls/rtls_tables.c | 20 | ||||
| -rw-r--r-- | src/occ_gpe0/apss_read.c | 28 | ||||
| -rw-r--r-- | src/occ_gpe0/gpe_util.c | 35 |
9 files changed, 206 insertions, 150 deletions
diff --git a/src/common/gpe_util.h b/src/common/gpe_util.h index 07dcb39..43e9024 100644 --- a/src/common/gpe_util.h +++ b/src/common/gpe_util.h @@ -33,7 +33,7 @@ void gpe_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint64_t i_ffdc); -int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout); +int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint32_t timeout); // Read decrementer register #define MFDEC(reg_var) \ diff --git a/src/occ_405/amec/amec_sensors_fw.c b/src/occ_405/amec/amec_sensors_fw.c index 525890a..fb3b9fe 100644 --- a/src/occ_405/amec/amec_sensors_fw.c +++ b/src/occ_405/amec/amec_sensors_fw.c @@ -79,182 +79,203 @@ void amec_slv_update_smh_sensors(int i_smh_state, uint32_t i_duration) void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine) { // Update the duration in the fw timing table - G_fw_timing.gpe_dur[i_gpe_engine] = DURATION_IN_US_UNTIL_NOW_FROM(G_fw_timing.rtl_start_gpe); + G_fw_timing.gpe_dur[i_gpe_engine] = DURATION_IN_US_UNTIL_NOW_FROM(G_fw_timing.rtl_start_gpe[i_gpe_engine]); } - // Function Specification // -// Name: amec_update_fw_sensors +// Name: task_gpe_timings // -// Description: Updates sensors related to the OCC FW Timings +// Description: Kick off tasks to time GPEs // // Thread: RealTime Loop // // End Function Specification #define MAX_CONSEC_TRACE 4 -void amec_update_fw_sensors(void) +void task_gpe_timings(task_t * i_task) { errlHndl_t l_err = NULL; int rc = 0; int rc2 = 0; - static bool l_first_call = TRUE; + static bool L_first_call = TRUE; bool l_gpe0_idle, l_gpe1_idle; static uint8_t L_consec_trace_count[2] = {0}; - - // ------------------------------------------------------ - // Update OCC Firmware Sensors from last tick - // ------------------------------------------------------ - int l_last_state = G_fw_timing.amess_state; - // RTLtickdur = duration of last tick's RTL ISR (max = 250us) - sensor_update( AMECSENSOR_PTR(RTLtickdur), G_fw_timing.rtl_dur); - // AMEintdur = duration of last tick's AMEC portion of RTL ISR - sensor_update( AMECSENSOR_PTR(AMEintdur), G_fw_timing.ameint_dur); - // AMESSdurX = duration of last tick's AMEC state - if(l_last_state >= NUM_AMEC_SMH_STATES) - { - // Sanity check. Trace this out, even though it should never happen. - TRAC_INFO("AMEC State Invalid, Sensor Not Updated"); - } - else - { - // AMESSdurX = duration of last tick's AMEC state - sensor_update( AMECSENSOR_ARRAY_PTR(AMESSdur0, l_last_state), G_fw_timing.amess_dur); - } + gpe_gpenxiramdbg_t xsr_sprg0 = {0}; + gpe_gpenxiramedr_t ir_edr = {0}; + gpe_gpenxidbgpro_t iar_xsr = {0}; // ------------------------------------------------------ // Kick off GPE programs to track WorstCase time in GPE // and update the sensors. // ------------------------------------------------------ - if( (NULL != G_fw_timing.gpe0_timing_request) && - (NULL != G_fw_timing.gpe1_timing_request) ) + if(NULL != G_fw_timing.gpe0_timing_request) { - //Check if both GPE engines were able to complete the last GPE job on - //the queue within 1 tick. + //Check if GPE0 was able to complete the last GPE job within 1 tick l_gpe0_idle = async_request_is_idle(&G_fw_timing.gpe0_timing_request->request); - l_gpe1_idle = async_request_is_idle(&G_fw_timing.gpe1_timing_request->request); - if(l_gpe0_idle && l_gpe1_idle) + if(l_gpe0_idle) { - //reset the consecutive trace counts + //reset the consecutive trace count L_consec_trace_count[0] = 0; - L_consec_trace_count[1] = 0; - //Both GPE engines finished on time. Now check if they were - //successful too. - if( async_request_completed(&(G_fw_timing.gpe0_timing_request->request)) && - async_request_completed(&(G_fw_timing.gpe1_timing_request->request)) ) + //Now check if successful too. + if( async_request_completed(&(G_fw_timing.gpe0_timing_request->request)) ) { // GPEtickdur0 = duration of last tick's PORE-GPE0 duration sensor_update( AMECSENSOR_PTR(GPEtickdur0), G_fw_timing.gpe_dur[0]); - // GPEtickdur1 = duration of last tick's PORE-GPE1 duration - sensor_update( AMECSENSOR_PTR(GPEtickdur1), G_fw_timing.gpe_dur[1]); } - else + //This case is expected on the first call of the function. + //After that, this should not happen. + else if(!L_first_call) { - //This case is expected on the first call of the function. - //After that, this should not happen. - if(!l_first_call) - { - //Note: FFDC for this case is gathered by each task - //responsible for a GPE job. - TRAC_INFO("GPE task idle but GPE task did not complete"); - } - l_first_call = FALSE; + //Note: FFDC for this case is gathered by each task + //responsible for a GPE job. + TRAC_INFO("GPE0 task idle but GPE0 task did not complete"); } - // Update Time used to measure GPE duration. - G_fw_timing.rtl_start_gpe = G_fw_timing.rtl_start; - // Schedule the GPE Routines that will run and update the worst // case timings (via callback) after they complete. These GPE // routines are the last GPE routines added to the queue // during the RTL tick. + G_fw_timing.rtl_start_gpe[0] = G_fw_timing.rtl_start; rc = gpe_request_schedule(G_fw_timing.gpe0_timing_request); - rc2 = gpe_request_schedule(G_fw_timing.gpe1_timing_request); - - if(rc || rc2) - { - /* @ - * @errortype - * @moduleid AMEC_UPDATE_FW_SENSORS - * @reasoncode SSX_GENERIC_FAILURE - * @userdata1 return code - gpe0 - * @userdata2 return code - gpe1 - * @userdata4 OCC_NO_EXTENDED_RC - * @devdesc Failure to schedule PORE-GPE poreFlex object for FW timing - * analysis. - */ - l_err = createErrl( - AMEC_UPDATE_FW_SENSORS, //modId - SSX_GENERIC_FAILURE, //reasoncode - OCC_NO_EXTENDED_RC, //Extended reason code - ERRL_SEV_INFORMATIONAL, //Severity - NULL, //Trace Buf - DEFAULT_TRACE_SIZE, //Trace Size - rc, //userdata1 - rc2); //userdata2 - - // commit error log - commitErrl( &l_err ); - } } else { - gpe_gpenxiramdbg_t xsr_sprg0 = {0}; - gpe_gpenxiramedr_t ir_edr = {0}; - gpe_gpenxidbgpro_t iar_xsr = {0}; - // Reset will eventually be requested due to not having power measurement // data after X ticks, but add some additional FFDC to the trace that // will tell us what GPE job is currently executing. - if(!l_gpe0_idle) + INCREMENT_ERR_HISTORY(ERRH_GPE0_NOT_IDLE); + + if(L_consec_trace_count[0] < MAX_CONSEC_TRACE) { - INCREMENT_ERR_HISTORY(ERRH_GPE0_NOT_IDLE); + xsr_sprg0.fields.xsr = in32(GPE_GPE0XIXSR); + xsr_sprg0.fields.sprg0 = in32(GPE_GPE0XISPRG0); + ir_edr.fields.edr = in32(GPE_GPE0XIEDR); + ir_edr.fields.ir = in32(GPE_GPE0XIIR); + iar_xsr.fields.iar = in32(GPE_GPE0XIIAR); + TRAC_ERR("GPE0 programs did not complete within one tick. " + "XSR[0x%08x] IAR[0x%08x] IR[0x%08x] EDR[0x%08x] SPRG0[0x%08X]", + xsr_sprg0.fields.xsr, iar_xsr.fields.iar, + ir_edr.fields.ir, ir_edr.fields.edr, xsr_sprg0.fields.sprg0); + L_consec_trace_count[0]++; + } + } + + } + if(NULL != G_fw_timing.gpe1_timing_request) + { + //Check if GPE1 was able to complete the last GPE job within 1 tick + l_gpe1_idle = async_request_is_idle(&G_fw_timing.gpe1_timing_request->request); + + if(l_gpe1_idle) + { + //reset the consecutive trace count + L_consec_trace_count[1] = 0; - if(L_consec_trace_count[0] < MAX_CONSEC_TRACE) - { - xsr_sprg0.fields.xsr = in32(GPE_GPE0XIXSR); - xsr_sprg0.fields.sprg0 = in32(GPE_GPE0XISPRG0); - ir_edr.fields.edr = in32(GPE_GPE0XIEDR); - ir_edr.fields.ir = in32(GPE_GPE0XIIR); - iar_xsr.fields.iar = in32(GPE_GPE0XIIAR); - TRAC_ERR("GPE0 programs did not complete within one tick. " - "XSR[0x%08x] IAR[0x%08x] IR[0x%08x] EDR[0x%08x] SPRG0[0x%08X]", - xsr_sprg0.fields.xsr, iar_xsr.fields.iar, - ir_edr.fields.ir, ir_edr.fields.edr, xsr_sprg0.fields.sprg0); - L_consec_trace_count[0]++; - } + //Now check if successful too. + if( async_request_completed(&(G_fw_timing.gpe1_timing_request->request)) ) + { + // GPEtickdur1 = duration of last tick's PORE-GPE1 duration + sensor_update( AMECSENSOR_PTR(GPEtickdur1), G_fw_timing.gpe_dur[1]); } - else + //This case is expected on the first call of the function. + //After that, this should not happen. + else if(!L_first_call) { - L_consec_trace_count[0] = 0; + //Note: FFDC for this case is gathered by each task + //responsible for a GPE job. + TRAC_INFO("GPE1 task idle but GPE1 task did not complete"); } - if(!l_gpe1_idle) - { - INCREMENT_ERR_HISTORY(ERRH_GPE1_NOT_IDLE); + // Schedule the GPE Routines that will run and update the worst + // case timings (via callback) after they complete. These GPE + // routines are the last GPE routines added to the queue + // during the RTL tick. + G_fw_timing.rtl_start_gpe[1] = G_fw_timing.rtl_start; + rc2 = gpe_request_schedule(G_fw_timing.gpe1_timing_request); - if(L_consec_trace_count[1] < MAX_CONSEC_TRACE) - { - xsr_sprg0.fields.xsr = in32(GPE_GPE1XIXSR); - xsr_sprg0.fields.sprg0 = in32(GPE_GPE1XISPRG0); - ir_edr.fields.edr = in32(GPE_GPE1XIEDR); - ir_edr.fields.ir = in32(GPE_GPE1XIIR); - iar_xsr.fields.iar = in32(GPE_GPE1XIIAR); - TRAC_ERR("GPE1 programs did not complete within one tick. " - "XSR[0x%08x] IAR[0x%08x] IR[0x%08x] EDR[0x%08x] SPRG0[0x%08X]", - xsr_sprg0.fields.xsr, iar_xsr.fields.iar, - ir_edr.fields.ir, ir_edr.fields.edr, xsr_sprg0.fields.sprg0); - L_consec_trace_count[1]++; - } - } - else + } + else + { + INCREMENT_ERR_HISTORY(ERRH_GPE1_NOT_IDLE); + + if(L_consec_trace_count[1] < MAX_CONSEC_TRACE) { - L_consec_trace_count[1] = 0; + xsr_sprg0.fields.xsr = in32(GPE_GPE1XIXSR); + xsr_sprg0.fields.sprg0 = in32(GPE_GPE1XISPRG0); + ir_edr.fields.edr = in32(GPE_GPE1XIEDR); + ir_edr.fields.ir = in32(GPE_GPE1XIIR); + iar_xsr.fields.iar = in32(GPE_GPE1XIIAR); + TRAC_ERR("GPE1 programs did not complete within one tick. " + "XSR[0x%08x] IAR[0x%08x] IR[0x%08x] EDR[0x%08x] SPRG0[0x%08X]", + xsr_sprg0.fields.xsr, iar_xsr.fields.iar, + ir_edr.fields.ir, ir_edr.fields.edr, xsr_sprg0.fields.sprg0); + L_consec_trace_count[1]++; } } } + if(rc || rc2) + { + /* @ + * @errortype + * @moduleid AMEC_UPDATE_FW_SENSORS + * @reasoncode SSX_GENERIC_FAILURE + * @userdata1 return code - gpe0 + * @userdata2 return code - gpe1 + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Failure to schedule PORE-GPE poreFlex object for FW timing + * analysis. + */ + l_err = createErrl( + AMEC_UPDATE_FW_SENSORS, //modId + SSX_GENERIC_FAILURE, //reasoncode + OCC_NO_EXTENDED_RC, //Extended reason code + ERRL_SEV_INFORMATIONAL, //Severity + NULL, //Trace Buf + DEFAULT_TRACE_SIZE, //Trace Size + rc, //userdata1 + rc2); //userdata2 + + // commit error log + commitErrl( &l_err ); + } + + L_first_call = FALSE; +} + + +// Function Specification +// +// Name: amec_update_fw_sensors +// +// Description: Updates sensors related to the OCC FW Timings +// +// Thread: RealTime Loop +// +// End Function Specification +#define MAX_CONSEC_TRACE 4 +void amec_update_fw_sensors(void) +{ + // ------------------------------------------------------ + // Update OCC Firmware Sensors from last tick + // ------------------------------------------------------ + int l_last_state = G_fw_timing.amess_state; + // RTLtickdur = duration of last tick's RTL ISR (max = 250us) + sensor_update( AMECSENSOR_PTR(RTLtickdur), G_fw_timing.rtl_dur); + // AMEintdur = duration of last tick's AMEC portion of RTL ISR + sensor_update( AMECSENSOR_PTR(AMEintdur), G_fw_timing.ameint_dur); + // AMESSdurX = duration of last tick's AMEC state + if(l_last_state >= NUM_AMEC_SMH_STATES) + { + // Sanity check. Trace this out, even though it should never happen. + TRAC_INFO("AMEC State Invalid, Sensor Not Updated"); + } + else + { + // AMESSdurX = duration of last tick's AMEC state + sensor_update( AMECSENSOR_ARRAY_PTR(AMESSdur0, l_last_state), G_fw_timing.amess_dur); + } } /*----------------------------------------------------------------------------*/ diff --git a/src/occ_405/amec/amec_sensors_fw.h b/src/occ_405/amec/amec_sensors_fw.h index 015cc01..86a07a4 100755 --- a/src/occ_405/amec/amec_sensors_fw.h +++ b/src/occ_405/amec/amec_sensors_fw.h @@ -47,6 +47,9 @@ void amec_slv_update_smh_sensors(int i_smh_state, uint32_t i_duration); // Function that updates the AMEC interim structures with GPE Engine Durations void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine); +// Function to kick of GPE timing nop task on both GPEs +void task_gpe_timings( task_t * i_task ); + // Function that updates the AMEC FW sensors void amec_update_fw_sensors(void); diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c index 752d939..6056eeb 100755 --- a/src/occ_405/occbuildname.c +++ b/src/occ_405/occbuildname.c @@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = #else -volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_170724a\0" /*</BuildName>*/ ; +volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_170726a\0" /*</BuildName>*/ ; #endif diff --git a/src/occ_405/proc/proc_data.c b/src/occ_405/proc/proc_data.c index ab88c19..6f25118 100755 --- a/src/occ_405/proc/proc_data.c +++ b/src/occ_405/proc/proc_data.c @@ -242,8 +242,6 @@ void task_core_data( task_t * i_task ) if (G_get_per_core_data_max_schedule_intervals[l_current_core] < l_elapsed_us) { G_get_per_core_data_max_schedule_intervals[l_current_core] = l_elapsed_us; - INTR_TRAC_INFO("New max get_per_core_data interval: core=%d, interval(us)=%d", - l_current_core, l_elapsed_us); } // Also sniff if the request has actually completed, it is checked above but // the schedule proceeds regardless which could be dangerous... diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h index 6e248ec..2b8fbae 100755 --- a/src/occ_405/rtls/rtls.h +++ b/src/occ_405/rtls/rtls.h @@ -61,6 +61,7 @@ typedef enum { TASK_ID_MEMORY_CONTROL, // Memory (centaur/dimm) control task TASK_ID_NEST_DTS, TASK_ID_24X7, // 24x7 data collection task + TASK_ID_GPE_TIMINGS, TASK_END // This must always be the last enum in this list, // so that TASK_END always equals the last task ID + 1. } task_id_t; @@ -73,7 +74,7 @@ typedef struct uint32_t amess_dur; // Combined duration of last mstr & slv AMEC state uint8_t amess_state; // Last AMEC state that was run uint64_t rtl_start; // SsxTimebase of Start of current RTL Tick - uint64_t rtl_start_gpe; // SsxTimebase of Start of current RTL Tick (for GPE > 250us meas) + uint64_t rtl_start_gpe[2]; // SsxTimebase of Start of current RTL Tick (for GPE > 1 tick) uint32_t gpe_dur[2]; // Duration of the GPE Engines / tick GpeRequest* gpe0_timing_request; // GPE Request that facilitates GPE WC meas GpeRequest* gpe1_timing_request; // GPE Request that facilitates GPE WC meas diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c index aca6b88..2f67e5c 100755 --- a/src/occ_405/rtls/rtls_tables.c +++ b/src/occ_405/rtls/rtls_tables.c @@ -34,6 +34,7 @@ #include <centaur_control.h> #include "memory.h" #include "amec_master_smh.h" +#include "amec_sensors_fw.h" #include "dimm.h" #include <common.h> @@ -77,6 +78,8 @@ #define FLAGS_POKE_WDT RTL_FLAG_RUN | RTL_FLAG_MSTR | RTL_FLAG_NOTMSTR | RTL_FLAG_STANDBY | \ RTL_FLAG_OBS | RTL_FLAG_ACTIVE | RTL_FLAG_MSTR_READY | RTL_FLAG_NO_APSS | RTL_FLAG_APSS_NOT_INITD +#define FLAGS_GPE_TIMINGS RTL_FLAG_MSTR | RTL_FLAG_NOTMSTR | RTL_FLAG_OBS | RTL_FLAG_ACTIVE | RTL_FLAG_MSTR_READY | RTL_FLAG_NO_APSS | RTL_FLAG_RUN | RTL_FLAG_APSS_NOT_INITD + // TEMP/TODO RTC: 133824 - New GPU interface via main memory and SMBUS #define FLAGS_GPU_SM @@ -123,6 +126,7 @@ task_t G_task_table[TASK_END] = { { FLAGS_MEMORY_CONTROL, task_memory_control, (void *) &G_memory_control_task }, // TASK_ID_MEMORY_CONTROL { FLAGS_NEST_DTS, task_nest_dts, NULL }, { FLAGS_24X7, task_24x7, NULL }, // TASK_ID_24X7 + { FLAGS_GPE_TIMINGS, task_gpe_timings, NULL }, // TASK_ID_GPE_TIMINGS }; const uint8_t G_tick0_seq[] = { @@ -135,6 +139,7 @@ const uint8_t G_tick0_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -156,6 +161,7 @@ const uint8_t G_tick1_seq[] = { TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, TASK_ID_POKE_WDT, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -177,6 +183,7 @@ const uint8_t G_tick2_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -198,6 +205,7 @@ const uint8_t G_tick3_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -219,6 +227,7 @@ const uint8_t G_tick4_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -240,6 +249,7 @@ const uint8_t G_tick5_seq[] = { TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, TASK_ID_POKE_WDT, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -261,6 +271,7 @@ const uint8_t G_tick6_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -281,6 +292,7 @@ const uint8_t G_tick7_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -302,6 +314,7 @@ const uint8_t G_tick8_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -323,6 +336,7 @@ const uint8_t G_tick9_seq[] = { TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, TASK_ID_POKE_WDT, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -344,6 +358,7 @@ const uint8_t G_tick10_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -364,6 +379,7 @@ const uint8_t G_tick11_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -385,6 +401,7 @@ const uint8_t G_tick12_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -406,6 +423,7 @@ const uint8_t G_tick13_seq[] = { TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, TASK_ID_POKE_WDT, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -427,6 +445,7 @@ const uint8_t G_tick14_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, @@ -447,6 +466,7 @@ const uint8_t G_tick15_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, diff --git a/src/occ_gpe0/apss_read.c b/src/occ_gpe0/apss_read.c index 640e712..c6065bb 100644 --- a/src/occ_gpe0/apss_read.c +++ b/src/occ_gpe0/apss_read.c @@ -216,10 +216,10 @@ void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg) #endif do{ - // wait for ADC completion, or timeout after 100 micro seconds. + // wait for ADC completion, or timeout after 120us (from Jordan for 16 channels) // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) // indicates when completion occurs. - rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 100); + rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 120); if(rc) // Timeout Reached, and SPI transaction didn't complete { PK_TRACE("apss_continue_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x", @@ -360,18 +360,6 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg) apss_complete_args_t *args = (apss_complete_args_t*)async_cmd->cmd_data; uint32_t rdata_reg = 0; do { - // wait for ADC completion, or timeout after 100 micro seconds. - // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) - // indicates when completion occurs. - rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 100); - if(rc) // Timeout Reached, and SPI transaction didn't complete - { - PK_TRACE("apss_complete_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x", - rc); - // FFDC already set inside wait_spi_completion - break; - } - // Get Time of Day rc = getscom_abs(TOD_VALUE_REG, &args->meas_data[3]); if(rc) @@ -382,6 +370,18 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg) break; } + // wait for completion, or timeout after 40us (from Jordan for GPIOs) + // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) + // indicates when completion occurs. + rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 40); + if(rc) // Timeout Reached, and SPI transaction didn't complete + { + PK_TRACE("apss_complete_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x", + rc); + // FFDC already set inside wait_spi_completion + break; + } + // If we're in composite mode, collect the GPIO data if (APSS_MODE_COMPOSITE == G_apss_mode) { diff --git a/src/occ_gpe0/gpe_util.c b/src/occ_gpe0/gpe_util.c index 0879fc3..a58b5f7 100644 --- a/src/occ_gpe0/gpe_util.c +++ b/src/occ_gpe0/gpe_util.c @@ -77,11 +77,13 @@ void gpe_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint6 * End Function Specification */ -int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout) +int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint32_t i_timeout) { int i = 0; - int rc; - uint64_t status; + int rc = 0; + uint64_t status = 0; + uint32_t wait_time = 0; + uint32_t num_reads = 0; if((reg != SPIPSS_P2S_STATUS_REG) && (reg != SPIPSS_ADC_STATUS_REG)) { @@ -91,9 +93,23 @@ int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout) } else { - // Keep polling the P2S_ONGOING bits for timeout - for (i = 0; i< timeout; i++) + // Read the P2S_ONGOING bits every 10us for i_timeout, if i_timeout is less than 10 + // just wait i_timeout and check once + if(i_timeout >= 10) { + wait_time = 10; + num_reads = i_timeout / 10; + } + else + { + wait_time = i_timeout; + num_reads = 1; + } + + for (i = 0; i< num_reads; i++) + { + busy_wait(wait_time); + rc = getscom_abs(reg, &status); if(rc) { @@ -112,18 +128,15 @@ int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout) rc = 0; break; } - - // sleep for 1 microsecond before retry - busy_wait(1); } } - //Timed out waiting on P2S_ONGOING / HWCTRL_ONGOING bit. - if (i >= timeout) + // Check if timed out waiting on P2S_ONGOING / HWCTRL_ONGOING bit + if (i >= num_reads) { PK_TRACE("gpe0:wait_spi_completion Timed out waiting for p2s_ongoing to clear."); - gpe_set_ffdc(error, reg, GPE_RC_SPI_TIMEOUT, rc); rc = GPE_RC_SPI_TIMEOUT; + gpe_set_ffdc(error, reg, GPE_RC_SPI_TIMEOUT, rc); } return rc; |
