Core data initialization and 24-core support

RTC: 140187
RTC: 140186
Change-Id: I574acdc3933b4bc181a584226ea432b9abe72592
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22182
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>

19 files changed, 286 insertions, 556 deletions

diff --git a/src/ipc_func_ids.h b/src/ipc_func_ids.h
index e253e39..7dd43df 100644
--- a/src/ipc_func_ids.h
+++ b/src/ipc_func_ids.h
@@ -60,6 +60,9 @@ IPC_FUNCIDS_TABLE_START
         IPC_FUNC_ID(IPC_ST_APSS_START_PWR_MEAS_READ_FUNCID)
         IPC_FUNC_ID(IPC_ST_APSS_CONTINUE_PWR_MEAS_READ_FUNCID)
         IPC_FUNC_ID(IPC_ST_APSS_COMPLETE_PWR_MEAS_READ_FUNCID)
+        IPC_FUNC_ID(IPC_ST_SCOM_OPERATION)
+        IPC_FUNC_ID(IPC_ST_CORE_DATA_LOW_FUNCID)
+        IPC_FUNC_ID(IPC_ST_CORE_DATA_HIGH_FUNCID)
     IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE0)
 
     //Functions that are only supported by GPE1 should be defined here
diff --git a/src/lib/occlib/liboccfiles.mk b/src/lib/occlib/liboccfiles.mk
index 7b3c80a..8f1e7ba 100644
--- a/src/lib/occlib/liboccfiles.mk
+++ b/src/lib/occlib/liboccfiles.mk
@@ -42,6 +42,7 @@
 ##########################################################################
 
 C-SOURCES = \
+    core_data.c \
     ipc_core.c \
 	ipc_init.c \
 	ipc_msgq.c \
diff --git a/src/occ_405/amec/amec_smh.h b/src/occ_405/amec/amec_smh.h
index e66c339..ff03f4f 100755
--- a/src/occ_405/amec/amec_smh.h
+++ b/src/occ_405/amec/amec_smh.h
@@ -60,7 +60,8 @@
 
 // Number of uS in 1 RTL tick (250=250us)
 #define AMEC_US_PER_TICK         MICS_PER_TICK
-// Number of uS in 1 full period of the AMEC State Machine (2000=2mS, 8 RTL ticks)
+// Number of uS in 1 full period of the AMEC State Machine
+// We cycle through the 8 states twice per tick cycle (16 ticks), so 8 * 250us = 2ms
 #define AMEC_US_PER_SMH_PERIOD   (AMEC_SMH_STATES_PER_LVL * MICS_PER_TICK)
 // Number of <AMEC_US_PER_SMH_PERIOD> that happen in 1 second
 #define AMEC_SMH_PERIODS_IN_1SEC (10000000 / AMEC_US_PER_SMH_PERIOD)
diff --git a/src/occ_405/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index 76b777f..9cb3283 100755
--- a/src/occ_405/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
@@ -1263,6 +1263,8 @@ errlHndl_t cmdh_processTmgtRequest (const cmdh_fsp_cmd_t * i_cmd_ptr,
     i_rsp_ptr->data_length[1] = 0;
     i_rsp_ptr->rc             = ERRL_RC_SUCCESS;
 
+    CMDH_TRAC_INFO("cmdh_processTmgtRequest: Received command type 0x%02X", l_cmd_type);
+
     // Run command function based on cmd_type
     switch(l_cmd_type)
     {
diff --git a/src/occ_405/incl/common_types.h b/src/occ_405/incl/common_types.h
index 40fbc11..6066763 100755
--- a/src/occ_405/incl/common_types.h
+++ b/src/occ_405/incl/common_types.h
@@ -27,7 +27,7 @@
 #define _COMMON_TYPES_H
 
 #include <stdint.h>
-
+#include <core_data.h>
 #ifdef USE_SSX_APP_CFG_H
 #include <ssx_app_cfg.h>
 #endif
@@ -125,6 +125,22 @@ struct image_header
 
 typedef struct image_header imageHdr_t;
 
+typedef struct ipc_scom_op
+{
+    uint32_t    addr;   // Register address
+    uint64_t    data;   // Data for read/write
+    uint32_t    size;   // Size of data buffer
+    uint8_t     read;   // Read (1) or write (0)
+    int         rc;     // Error of SCOM operation
+} ipc_scom_op_t;
+
+typedef struct ipc_core_data_parms
+{
+    CoreData*  data;
+    uint32_t   core_num;
+    uint32_t   rc;
+} ipc_core_data_parms_t;
+
 extern uint32_t __READ_ONLY_DATA_LEN__;
 extern uint32_t __WRITEABLE_DATA_ADDR__;
 extern uint32_t __WRITEABLE_DATA_LEN__;
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index d489cfc..6355c41 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -1000,8 +1000,7 @@ void Main_thread_routine(void *private)
     //Initialize structures for collecting core data.
     //It needs to run before RTLoop start as pore initialization needs to be
     // done before task to collect core data starts.
-// TEMP -- NOT NEEDED IN PHASE1
-//    proc_core_init();
+    proc_core_init();
     CHECKPOINT(PROC_CORE_INITIALIZED);
 
     // Run slave OCC init on all OCCs. Master-only initialization will be
diff --git a/src/occ_405/occLinkInputFile b/src/occ_405/occLinkInputFile
index 4514bdf..c2e3c68 100644
--- a/src/occ_405/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
@@ -48,6 +48,7 @@ INPUT ( amec_data.o
         ppc405_lib_core.o
         ppc405_mmu_asm.o
         ppc405_thread_init.o
+        proc_data.o
         proc_pstate.o
         reset.o
         rtls_tables.o
diff --git a/src/occ_405/occ_service_codes.h b/src/occ_405/occ_service_codes.h
index fad1ecf..08918e6 100644
--- a/src/occ_405/occ_service_codes.h
+++ b/src/occ_405/occ_service_codes.h
@@ -125,9 +125,8 @@ enum occExtReasonCode
     ERC_CALLER_SEM_POSTING_FAILURE              = 0x0000000d,
     ERC_CREATE_SEM_FAILURE                      = 0x0000000e,
 
-    ERC_LOW_CORE_PORE_FLEX_CREATE_FAILURE       = 0x0000000f,
-    ERC_HIGH_CORE_PORE_FLEX_CREATE_FAILURE      = 0x00000010,
-    ERC_FAST_CORE_PORE_FLEX_CREATE_FAILURE      = 0x00000011,
+    ERC_LOW_CORE_GPE_REQUEST_CREATE_FAILURE     = 0x0000000f,
+    ERC_HIGH_CORE_GPE_REQUEST_CREATE_FAILURE    = 0x00000010,
 
     ERC_SSX_IRQ_SETUP_FAILURE                   = 0x00000012,
     ERC_SSX_IRQ_HANDLER_SET_FAILURE             = 0x00000013,
diff --git a/src/occ_405/proc/proc_data.c b/src/occ_405/proc/proc_data.c
index f1ce85c..a364f18 100755
--- a/src/occ_405/proc/proc_data.c
+++ b/src/occ_405/proc/proc_data.c
@@ -24,7 +24,7 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
 #include "proc_data.h"
-#include "pgp_async.h"
+#include "occhw_async.h"
 #include "threadSch.h"
 #include "pmc_register_addresses.h"
 #include "proc_data_service_codes.h"
@@ -35,23 +35,34 @@
 #include "apss.h"
 #include "state.h"
 #include "proc_data_control.h"
-
+#include "core_data.h"
 //Global array of core data buffers
-GPE_BUFFER(gpe_bulk_core_data_t G_core_data[MAX_NUM_FW_CORES+NUM_CORE_DATA_DOUBLE_BUF+NUM_CORE_DATA_EMPTY_BUF]) = {{{0}}};
+GPE_BUFFER(CoreData G_core_data[MAX_NUM_FW_CORES+NUM_CORE_DATA_DOUBLE_BUF+NUM_CORE_DATA_EMPTY_BUF]) = {{{0}}};
+
+// Pointers to the actual core data buffers
+CoreData * G_core_data_ptrs[MAX_NUM_FW_CORES] = {0};
 
-//Global array of core data pointers
-gpe_bulk_core_data_t * G_core_data_ptrs[MAX_NUM_FW_CORES] = { &G_core_data[0], &G_core_data[1],
-   &G_core_data[2], &G_core_data[3], &G_core_data[4], &G_core_data[5], &G_core_data[6],
-   &G_core_data[7], &G_core_data[8], &G_core_data[9], &G_core_data[10], &G_core_data[11] };
+// TEMP / TODO -- Only needed until we get the HWP for getting CORE_STATUS
+// Used to get GPE0 to do a getscom of the Core Config Status Reg
+GPE_BUFFER(ipc_scom_op_t G_core_stat_scom_op);
 
 //Global structures for gpe get core data parms
-GPE_BUFFER(GpeGetCoreDataParms G_low_cores_data_parms);
-GPE_BUFFER(GpeGetCoreDataParms G_high_cores_data_parms);
+GPE_BUFFER(ipc_core_data_parms_t G_low_cores_data_parms);
+GPE_BUFFER(ipc_core_data_parms_t G_high_cores_data_parms);
 
 //We will have separate bulk core data structure for low and high cores.
 //Global low and high cores structures used for task data pointers.
-bulk_core_data_task_t G_low_cores = { 0, 0, 5, &G_core_data[12] };
-bulk_core_data_task_t G_high_cores = { 6, 6, 11, &G_core_data[13] };
+bulk_core_data_task_t G_low_cores = {
+            0,                                  // Low core to start with (min)
+            0,                                  // Low core to start with (current)
+            CORE_MID_POINT - 1,                 // Low core to end with
+            &G_core_data[MAX_NUM_FW_CORES]      // Pointer to holding area for low coredata
+    };
+bulk_core_data_task_t G_high_cores = {
+            CORE_MID_POINT,                     // High core to start with (min)
+            CORE_MID_POINT,                     // High core to start with (current)
+            MAX_NUM_FW_CORES - 1,               // High core to end with
+            &G_core_data[MAX_NUM_FW_CORES+1] }; // Pointer to holding area for high coredata
 
 //AMEC needs to know when data for a core has been collected.
 uint32_t G_updated_core_mask = 0;
@@ -65,41 +76,20 @@ uint32_t G_empath_error_core_mask = 0;
 //(1 = present, 0 = not present. Core 0 has the most significant bit)
 uint32_t G_present_cores = 0;
 
-//Global double buffering for fast core data collection.
-GPE_BUFFER(gpe_fast_core_data_t G_fast_core_data[NUM_FAST_CORE_DATA_BUFF]) = {{0}};
-
-//Pointer to the latest fast core data that will be used by AMEC code.
-GPE_BUFFER(gpe_fast_core_data_t * G_read_fast_core_data_ptr) = { &G_fast_core_data[0] };
-
-//Pointer used by GPE code to write fast core data.
-GPE_BUFFER(gpe_fast_core_data_t * G_write_fast_core_data_ptr) = { &G_fast_core_data[1] };
-
-//Globals structure for gpe get chip data fast parms.
-//The Gpe parameter fields are set up each time before collect data start.
-GPE_BUFFER(GpeGetChipDataFastParms G_chip_data_fast_parms);
-
-//Pore flex request for GPE job. The initialization
-//will be done one time during pore flex create.
-PoreFlex G_fast_cores_req;
-
 //Global G_present_hw_cores is bitmask of all hardware cores
 //(1 = present, 0 = not present. Core 0 has the most significant bit)
 uint32_t G_present_hw_cores = 0;
 
 //OCC to HW core id mapping array
-uint8_t G_occ2hw_core_id[MAX_NUM_HW_CORES] = { 1, 2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 14, 0, 7, 8, 15 };
+uint8_t G_occ2hw_core_id[MAX_NUM_HW_CORES] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
 
 //HW to OCC core id mapping array
-uint8_t G_hw2occ_core_id[MAX_NUM_HW_CORES] = { 12, 0, 1, 2, 3, 4, 5, 13, 14, 6, 7, 8, 9, 10, 11, 15 };
+uint8_t G_hw2occ_core_id[MAX_NUM_HW_CORES] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
 
-//Flag to keep tract of one time trace for GPE running case
+//Flag to keep track of one time trace for GPE running case
 //for task core data.
 bool    G_queue_not_idle_traced = FALSE;
 
-//Flag to keep tract of one time trace for GPE running case
-//for Fast core data.
-bool    G_fast_core_queue_not_idle_traced = FALSE;
-
 // Global to track the maximum time elapsed between pore flex schedules of
 // per core get_per_core_data tasks.  The array is indexed by core number.
 uint32_t G_get_per_core_data_max_schedule_intervals[MAX_NUM_HW_CORES] = {0,};
@@ -108,7 +98,6 @@ uint32_t G_get_per_core_data_max_schedule_intervals[MAX_NUM_HW_CORES] = {0,};
 #ifdef PROC_DEBUG
 void print_core_data_sensors(uint8_t core);
 void print_core_status(uint8_t core);
-void print_fast_core_data(void);
 #endif
 
 // Function Specification
@@ -126,12 +115,14 @@ void print_fast_core_data(void);
 void task_core_data( task_t * i_task )
 {
 
-    errlHndl_t  l_err = NULL;       //Error handler
-    tracDesc_t  l_trace = NULL;     //Temporary trace descriptor
-    int         rc = 0;     //return code
+    errlHndl_t  l_err = NULL;  // Error handler
+    int         l_rc = 0;      // Return code
+    CoreData  * l_temp = NULL; // Used for pointer swapping
+    const trace_descriptor_array_t *l_trace = NULL; // Temporary trace descriptor
     bulk_core_data_task_t * l_bulk_core_data_ptr = (bulk_core_data_task_t *)i_task->data_ptr;
-    GpeGetCoreDataParms * l_parms = (GpeGetCoreDataParms *)(l_bulk_core_data_ptr->gpe_req.parameter);
-    gpe_bulk_core_data_t  * l_temp = NULL;
+    ipc_core_data_parms_t * l_parms = (ipc_core_data_parms_t*)(l_bulk_core_data_ptr->gpe_req.cmd_data);
+
+    INTR_TRAC_INFO("task_core_data: core %d", l_bulk_core_data_ptr->current_core);
 
     do
     {
@@ -194,113 +185,13 @@ void task_core_data( task_t * i_task )
             // Presumptively clear the empath error mask
             G_empath_error_core_mask &=
                     ~(CORE0_PRESENT_MASK >> (l_bulk_core_data_ptr->current_core));
-
-            // The gpe_data collection code has to handle the workaround for
-            // HW280375.  Two new flags have been added to the OHA_RO_STATUS_REG
-            // image to indicate whether the EMPATH collection failed, and
-            // whether it was due to an "expected" error that we can ignore
-            // (we can ignore the data as well), or an "unexpected" error that
-            // we will create an informational log one time.
-            //
-            // The "expected" errors are very rare in practice, in fact we may
-            // never even see them unless running a specific type of workload.
-            // If you want to test the handling of expected errors compile the
-            // GPE code with -DINJECT_HW280375_ERRORS which will inject an error
-            // approximately every 1024 samples
-            //
-            // To determine if the expected error has occurred inspect the
-            // CoreDataOha element of the CoreData structure written by the GPE
-            // core data job.  The OHA element contains the oha_ro_status_reg.
-            // Inside the OHA status register is a 16 bit reserved field.
-            // gpe_data.h defines two masks that can be applied against the
-            // reserved field to check for these errors:
-            // CORE_DATA_EXPECTED_EMPATH_ERROR
-            // CORE_DATA_UNEXPECTED_EMPATH_ERROR
-            // Also, a 4-bit PCB parity + error code is saved at bit position:
-            // CORE_DATA_EMPATH_ERROR_LOCATION, formally the length is
-            // specified by: CORE_DATA_EMPATH_ERROR_BITS
-            gpe_bulk_core_data_t *l_core_data =
-                    G_core_data_ptrs[l_bulk_core_data_ptr->current_core];
-
-            // We will trace the errors, but only a certain number of
-            // times, we will only log the unexpected error once.
-#define OCC_EMPATH_ERROR_THRESH 10
-            static uint32_t L_expected_emp_err_cnt = 0;
-            static uint32_t L_unexpected_emp_err_cnt = 0;
-
-            // Check the reserved field for the expected or the unexpected error flag
-            if ((l_core_data->oha.oha_ro_status_reg.fields._reserved0 & CORE_DATA_EXPECTED_EMPATH_ERROR)
-                ||
-                (l_core_data->oha.oha_ro_status_reg.fields._reserved0 & CORE_DATA_UNEXPECTED_EMPATH_ERROR))
-            {
-                // Indicate empath error on current core
-                G_empath_error_core_mask |=
-                        CORE0_PRESENT_MASK >> (l_bulk_core_data_ptr->current_core);
-
-                // Save the high and low order words of the OHA status reg
-                uint32_t l_oha_reg_high = l_core_data->oha.oha_ro_status_reg.words.high_order;
-                uint32_t l_oha_reg_low = l_core_data->oha.oha_ro_status_reg.words.low_order;
-
-                // Handle each error case
-                if ((l_core_data->oha.oha_ro_status_reg.fields._reserved0 & CORE_DATA_EXPECTED_EMPATH_ERROR)
-                    &&
-                    (L_expected_emp_err_cnt < OCC_EMPATH_ERROR_THRESH))
-                {
-                    L_expected_emp_err_cnt++;
-                    TRAC_IMP("Expected empath collection error occurred %d time(s)! Core = %d",
-                             L_expected_emp_err_cnt,
-                             l_bulk_core_data_ptr->current_core);
-                    TRAC_IMP("OHA status register: 0x%4.4x%4.4x",
-                             l_oha_reg_high, l_oha_reg_low);
-                }
-
-                if ((l_core_data->oha.oha_ro_status_reg.fields._reserved0 & CORE_DATA_UNEXPECTED_EMPATH_ERROR)
-                    &&
-                    (L_unexpected_emp_err_cnt < OCC_EMPATH_ERROR_THRESH))
-                {
-                    L_unexpected_emp_err_cnt++;
-                    TRAC_ERR("Unexpected empath collection error occurred %d time(s)! Core = %d",
-                             L_unexpected_emp_err_cnt,
-                             l_bulk_core_data_ptr->current_core);
-                    TRAC_ERR("OHA status register: 0x%4.4x%4.4x",
-                             l_oha_reg_high, l_oha_reg_low);
-
-                    // Create and commit an informational error the first
-                    // time this occurs.
-                    if (L_unexpected_emp_err_cnt == 1)
-                    {
-                        TRAC_IMP("Logging unexpected empath collection error 1 time only.");
-                        /*
-                        * @errortype
-                        * @moduleid    PROC_TASK_CORE_DATA_MOD
-                        * @reasoncode  INTERNAL_HW_FAILURE
-                        * @userdata1   OHA status reg high
-                        * @userdata2   OHA status reg low
-                        * @userdata4   ERC_PROC_CORE_DATA_EMPATH_ERROR
-                        * @devdesc     An unexpected error occurred while
-                        *              collecting core empath data.
-                        */
-                        l_err = createErrl(
-                                PROC_TASK_CORE_DATA_MOD, //modId
-                                INTERNAL_HW_FAILURE,     //reason code
-                                ERC_PROC_CORE_DATA_EMPATH_ERROR, //Extended reason code
-                                ERRL_SEV_INFORMATIONAL,  //Severity
-                                NULL,                    //Trace
-                                DEFAULT_TRACE_SIZE,      //Trace Size
-                                l_oha_reg_high,          //userdata1
-                                l_oha_reg_low);          //userdata2
-
-                        commitErrl(&l_err);
-                    }
-                }
-            }
         }
 
         // If the core is not present, then we need to point to the empty G_core_data
         // so that we don't use old/stale data from a leftover G_core_data
         if( !CORE_PRESENT(l_bulk_core_data_ptr->current_core))
         {
-            G_core_data_ptrs[l_bulk_core_data_ptr->current_core] = &G_core_data[14];
+            G_core_data_ptrs[l_bulk_core_data_ptr->current_core] = &G_core_data[MAX_NUM_FW_CORES+NUM_CORE_DATA_DOUBLE_BUF+NUM_CORE_DATA_EMPTY_BUF-1];
         }
 
         //Update current core
@@ -317,27 +208,11 @@ void task_core_data( task_t * i_task )
         //be idle during this time it would have collected the data.
         if( CORE_PRESENT(l_bulk_core_data_ptr->current_core) )
         {
-            PROC_DBG("Schedule PoreFlex OCC core [%x] or HW core [%x]\n",
-                      l_bulk_core_data_ptr->current_core, CORE_OCC2HW(l_bulk_core_data_ptr->current_core));
+            PROC_DBG("Schedule GpeRequest for core %d\n", l_bulk_core_data_ptr->current_core);
 
             //1. Setup the get core data parms
-            l_parms->config =
-                    ((uint64_t) CORE0_PRESENT_MASK_GPE) >> (CORE_OCC2HW(l_bulk_core_data_ptr->current_core));
-
-            if( (cfam_id() == CFAM_CHIP_ID_MURANO_10)
-                || (cfam_id() == CFAM_CHIP_ID_MURANO_11)
-                || (cfam_id() == CFAM_CHIP_ID_MURANO_12) )
-            {
-                // Due to HW243646 & HW243942 fallout, we will not be collecting EX core
-                // activity counter scoms until Murano DD1.3
-                l_parms->select = GPE_GET_CORE_DATA_DTS_CPM | GPE_GET_CORE_DATA_PCB_SLAVE;
-            }
-            else
-            {
-                l_parms->select = GPE_GET_CORE_DATA_ALL;
-            }
-
-            l_parms->data = (uint32_t) l_bulk_core_data_ptr->core_data_ptr;
+            l_parms->core_num = l_bulk_core_data_ptr->current_core;
+            l_parms->data = (CoreData*) l_bulk_core_data_ptr->core_data_ptr;
 
             // Static array to record the last timestamp a get_per_core_data task was
             // scheduled for a core.
@@ -375,28 +250,15 @@ void task_core_data( task_t * i_task )
                 }
             }
 
-            // The PCBS heartbeat timer may time out even though we are scheduling
-            // the get_per_core_data task for each core every 2ms.  Reason at time
-            // of this code change is still unknown but reproducible.  We are going
-            // to getscom the PMSTATEHISTOCC register (PCBS_PMSTATEHISTOCC_REG) for
-            // each configured core before scheduling the PORE job to try and make
-            // sure the heartbeat doesn't expire.
-            // Recent tests show the heartbeat is holding steady so the getscom is
-            // commented out and incomplete, the core number needs to be converted
-            // to a hardware core number if this code is activated.
-            //uint64_t l_dont_care = 0;
-            //uint32_t core = CORE_CHIPLET_ADDRESS(PCBS_PMSTATEHISTOCC_REG, ???);
-            //getscom(address???, &l_dont_care);
-
-            //2. Port flex schedule gpe_get_per_core_data
-            //   Check pore_flex_schedule return code if error
-            //   then request OCC reset.
-
-            rc = pore_flex_schedule( &l_bulk_core_data_ptr->gpe_req );
-            if( rc != 0 )
+            //2. Schedule the GPE Request to get the core data
+            //   Check gpe_request_schedule return code for an error
+            //   and if there is an error, request an OCC reset.
+
+            l_rc = gpe_request_schedule( &l_bulk_core_data_ptr->gpe_req );
+            if( l_rc != 0 )
             {
-                //Error in schedule gpe get core data
-                TRAC_ERR("Failed PoreFlex schedule core [%x] \n", rc);
+                // Error in schedule gpe get core data
+                TRAC_ERR("Failed GpeRequest schedule core [RC:0x%08X] \n", l_rc);
 
                 /*
                 * @errortype
@@ -413,7 +275,7 @@ void task_core_data( task_t * i_task )
                         ERRL_SEV_PREDICTIVE,                //Severity
                         l_trace, //TODO: create l_trace     //Trace Buf
                         DEFAULT_TRACE_SIZE,                 //Trace Size
-                        rc,                                 //userdata1
+                        l_rc,                               //userdata1
                         0                                   //userdata2
                 );
 
@@ -440,139 +302,85 @@ void task_core_data( task_t * i_task )
 
 void proc_core_init( void )
 {
-     errlHndl_t l_err = NULL;   //Error handler
-     tracDesc_t l_trace = NULL; //Temporary trace descriptor
-     int         rc = 0;    //Return code
-
-     do
-     {
-    //Before RTLoop starts to collect data. We need to determine what cores
-    //are present and configured. We have a register that has information
-    //of all cores that have been deconfigured in the chip so we need to read that.
-
-    G_present_hw_cores = in32(PMC_CORE_DECONFIGURATION_REG);
-
-    //Inverse the bitmask of the deconfigured register to get present
-    //cores and save it in the global present hardware cores.
-    G_present_hw_cores = ~G_present_hw_cores & HW_CORES_MASK;
-
-    //Convert hardware core numering to OCC core numering.
-    G_present_cores = ((G_present_hw_cores & LO_CORES_MASK) << 1) |
-                ((G_present_hw_cores & HI_CORES_MASK) << 3);
-
-    PROC_DBG("G_present_hw_cores =[%x] and G_present_cores =[%x] \n",
-            G_present_hw_cores, G_present_cores);
-
-    //Initializes low cores data PoreFlex object
-    rc = pore_flex_create(  &G_low_cores.gpe_req,   //gpe_req for the task
-                            &G_pore_gpe0_queue,     //queue
-                            gpe_get_per_core_data,  //entry point
-                                                    //parm for the task
-                            (uint32_t) &G_low_cores_data_parms,
-                            SSX_WAIT_FOREVER,       // no timeout
-                            NULL,                   //callback
-                            NULL,                   //callback argument
-                            0 );                    //options
-    if( rc )
+    errlHndl_t l_err = NULL;    // Error handler
+    int        l_rc = 0;        // Return code
+    const trace_descriptor_array_t *l_trace = NULL;  // Temporary trace descriptor
+    uint8_t i = 0;
+    GpeRequest l_req;
+
+    // Setup the array of CoreData pointers
+    for( i = 0; i < MAX_NUM_FW_CORES; i++ )
     {
-        //If fail to create pore flex object then there is a problem.
-        TRAC_ERR("Fail to create low cores poreFlex object[0x%x]", rc );
-
-        /*
-         * @errortype
-         * @moduleid    PROC_CORE_INIT_MOD
-         * @reasoncode  SSX_GENERIC_FAILURE
-         * @userdata1   pore_flex_create return code
-         * @userdata4   ERC_LOW_CORE_PORE_FLEX_CREATE_FAILURE
-         * @devdesc     Failure to create low cores poreflex object
-         */
-        l_err = createErrl(
-                PROC_CORE_INIT_MOD,                     //modId
-                SSX_GENERIC_FAILURE,                    //reasoncode
-                ERC_LOW_CORE_PORE_FLEX_CREATE_FAILURE,  //Extended reason code
-                ERRL_SEV_PREDICTIVE,                    //Severity
-                l_trace,    //TODO: create l_trace      //Trace Buf
-                DEFAULT_TRACE_SIZE,                     //Trace Size
-                rc,                                     //userdata1
-                0                                       //userdata2
-        );
-
-        // commit error log
-        REQUEST_RESET(l_err);
-        break;
+        G_core_data_ptrs[i] = &G_core_data[i];
     }
 
-    //Initializes existing PoreFlex object for high cores data
-    rc = pore_flex_create(  &G_high_cores.gpe_req,      //gpe_req for the task
-                            &G_pore_gpe0_queue,         //queue
-                            gpe_get_per_core_data,      //entry point
-                                                        //parm for the task
-                            (uint32_t) &G_high_cores_data_parms,
-                            SSX_WAIT_FOREVER,           //no timeout
-                            NULL,                       //callback
-                            NULL,                       //callback argument
-                            0 );                        //options
-    if( rc )
+    do
     {
-        //If fail to create pore flex object then there is a problem.
-        TRAC_ERR("Fail to create high cores poreFlex object[0x%x]", rc );
-
-        /*
-         * @errortype
-         * @moduleid    PROC_CORE_INIT_MOD
-         * @reasoncode  SSX_GENERIC_FAILURE
-         * @userdata1   pore_flex_create return code
-         * @userdata4   ERC_HIGH_CORE_PORE_FLEX_CREATE_FAILURE
-         * @devdesc     Failure to create high core poreFlex object
-         */
-        l_err = createErrl(
-                            PROC_CORE_INIT_MOD,                     //modId
-                            SSX_GENERIC_FAILURE,                    //reasoncode
-                            ERC_HIGH_CORE_PORE_FLEX_CREATE_FAILURE, //Extended reason code
-                            ERRL_SEV_PREDICTIVE,                    //Severity
-                            l_trace,    //TODO: create l_trace      //Trace Buf
-                            DEFAULT_TRACE_SIZE,                     //Trace Size
-                            rc,                                     //userdata1
-                            0                                       //userdata2
-        );
-
-        // commit error log
-        REQUEST_RESET(l_err);
-        break;
-    }
-
-        //Initializes PoreFlex object for fast core data
-        rc = pore_flex_create( &G_fast_cores_req,               //gpe_req for the task
-                                &G_pore_gpe0_queue,             //queue
-                                gpe_get_core_data_fast,         //entry point
-                                                                //parm for the task
-                                (uint32_t) &G_chip_data_fast_parms,
-                               SSX_WAIT_FOREVER,                //no timeout
-                                NULL,                           //callback
-                                NULL,                           //callback argument
-                                0 );                            //options
-        if( rc )
+        // Before the real time loop begins collecting data, we need to determine which
+        // cores are present and configured. The Core Configuration Status Register
+        // has this information, but only the GPEs can read this via a scom.
+
+        // TEMP/TODO: For now, we will use a generic IPC command to do this and other
+        //            scoms until the HW team can give us the hardware procedures.
+        G_core_stat_scom_op.addr = 0x6c090;
+        G_core_stat_scom_op.size = 8;
+        G_core_stat_scom_op.data = 0xFFFFFF00;
+        G_core_stat_scom_op.read = TRUE;
+
+        //Initializes the GpeRequest object for reading the configuration status register
+        l_rc = gpe_request_create(&l_req,                          // GpeRequest for the task
+                                  &G_async_gpe_queue0,             // Queue
+                                  IPC_ST_SCOM_OPERATION,           // Function ID
+                                  &G_core_stat_scom_op,            // Task parameters
+                                  SSX_WAIT_FOREVER,                // Timeout (none)
+                                  NULL,                            // Callback
+                                  NULL,                            // Callback arguments
+                                  0 );                             // Options
+        // Schedule the request
+        //l_rc = gpe_request_schedule(&l_req);
+
+        MAIN_TRAC_INFO("proc_core_init: generic scom read back 0x%08X%08X", G_core_stat_scom_op.data>>32, G_core_stat_scom_op.data);
+
+        // TODO: Store the present cores here
+        G_present_hw_cores = G_core_stat_scom_op.data & HW_CORES_MASK;
+
+        G_present_cores = G_present_hw_cores;
+
+        PROC_DBG("G_present_hw_cores =[%x] and G_present_cores =[%x] \n",
+                G_present_hw_cores, G_present_cores);
+
+        //Initializes the GpeRequest object for low core data collection
+        l_rc = gpe_request_create(&G_low_cores.gpe_req,            // GpeRequest for the task
+                                  &G_async_gpe_queue0,             // Queue
+                                  IPC_ST_CORE_DATA_LOW_FUNCID,     // Function ID
+                                  &G_low_cores_data_parms,         // Task parameters
+                                  SSX_WAIT_FOREVER,                // Timeout (none)
+                                  NULL,                            // Callback
+                                  NULL,                            // Callback arguments
+                                  0 );                             // Options
+
+        if( l_rc )
         {
-            //If fail to create pore flex object then there is a problem.
-            TRAC_ERR("Fail to create fast cores poreFlex object[0x%x]", rc );
+            // If we failed to create the GpeRequest then there is a serious problem.
+            MAIN_TRAC_ERR("Failure creating the low core data GpeRequest. [RC=0x%08x]", l_rc );
 
             /*
              * @errortype
              * @moduleid    PROC_CORE_INIT_MOD
              * @reasoncode  SSX_GENERIC_FAILURE
-             * @userdata1   pore_flex_create return code
-             * @userdata4   ERC_FAST_CORE_PORE_FLEX_CREATE_FAILURE
-             * @devdesc     Failure to create fast core data poreFlex object
+             * @userdata1   gpe_request_create return code
+             * @userdata4   ERC_LOW_CORE_GPE_REQUEST_CREATE_FAILURE
+             * @devdesc     Failure to create low cores GpeRequest object
              */
             l_err = createErrl(
-                            PROC_CORE_INIT_MOD,                     //modId
-                            SSX_GENERIC_FAILURE,                    //reasoncode
-                            ERC_FAST_CORE_PORE_FLEX_CREATE_FAILURE, //Extended reason code
-                            ERRL_SEV_PREDICTIVE,                    //Severity
-                            l_trace, //TODO: create l_trace point   //Trace Buf
-                            DEFAULT_TRACE_SIZE,                     //Trace Size
-                            rc,                                     //userdata1
-                            0                                       //userdata2
+                    PROC_CORE_INIT_MOD,                      //ModId
+                    SSX_GENERIC_FAILURE,                     //Reasoncode
+                    ERC_LOW_CORE_GPE_REQUEST_CREATE_FAILURE, //Extended reason code
+                    ERRL_SEV_PREDICTIVE,                     //Severity
+                    l_trace,                                 //Trace Buf
+                    DEFAULT_TRACE_SIZE,                      //Trace Size
+                    l_rc,                                    //Userdata1
+                    0                                        //Userdata2
             );
 
             // commit error log
@@ -580,115 +388,51 @@ void proc_core_init( void )
             break;
         }
 
-    } while(0);
-
-    // Initialize the core data control structures at the same time
-    proc_core_data_control_init();
-
-    return;
-}
-
-// Function Specification
-//
-// Name: task_fast_core_data
-//
-// Description: Collect fast core data for all configured cores on every tick.
-//
-// End Function Specification
-
-void task_fast_core_data( task_t * i_task )
-{
-
-    errlHndl_t  l_err = NULL;   //Error handler
-    tracDesc_t l_trace = NULL;  //Temporary trace descriptor
-    int         rc = 0;         //Return code
-    gpe_fast_core_data_t  * l_temp = NULL;
-    uint32_t    l_pres_hw_cores;
-
-    //poll the pmc deconfig register for newly deconfigured cores
-    l_pres_hw_cores = (~in32(PMC_CORE_DECONFIGURATION_REG)) & HW_CORES_MASK;
-    if(l_pres_hw_cores != G_present_hw_cores)
-    {
-        TRAC_IMP("Present cores changed. old_hw_mask[0x%04x] new_hw_mask[0x%04x]",
-                G_present_hw_cores, l_pres_hw_cores);
-
-        //update our global core presence masks
-        G_present_hw_cores = l_pres_hw_cores;
-        G_present_cores = ((l_pres_hw_cores & LO_CORES_MASK) << 1) |
-                ((l_pres_hw_cores & HI_CORES_MASK) << 3);
-    }
-
-    do
-    {
-        //Check to see if the previous GPE request still running
-        if( !(async_request_is_idle(&G_fast_cores_req.request)) )
-        {
-                //This should not happen unless there's a problem
-                //Trace 1 time
-                if( !G_fast_core_queue_not_idle_traced )
-                {
-                        TRAC_ERR("GPE is still running \n");
-                        G_fast_core_queue_not_idle_traced = TRUE;
-                }
-                break;
-        }
-
-        //Check to see if the previosuly GPE request has been succeeded
-        if( async_request_completed(&G_fast_cores_req.request) )
+        //Initializes high cores data GpeRequest object
+        l_rc = gpe_request_create(&G_high_cores.gpe_req,            // GpeRequest for the task
+                                  &G_async_gpe_queue0,             // Queue
+                                  IPC_ST_CORE_DATA_HIGH_FUNCID,    // Function ID
+                                  &G_high_cores_data_parms,         // Task parameters
+                                  SSX_WAIT_FOREVER,                // Timeout (none)
+                                  NULL,                            // Callback
+                                  NULL,                            // Callback arguments
+                                  0 );                             // Options
+
+        if( l_rc )
         {
-            //If the previous GPE request succeeded then swap the
-            //G_read_fast_core_data_ptr with the G_write_fast_core_data_ptr.
-
-            PROC_DBG("Fast core data GPE request has been succeeded.\n");
+            // If we failed to create the GpeRequest then there is a serious problem.
+            MAIN_TRAC_ERR("Failure creating the high core data GpeRequest. [RC=0x%08x]", l_rc );
 
-            #ifdef  PROC_DEBUG
-                print_fast_core_data();
-            #endif
+            /*
+             * @errortype
+             * @moduleid    PROC_CORE_INIT_MOD
+             * @reasoncode  SSX_GENERIC_FAILURE
+             * @userdata1   gpe_request_create return code
+             * @userdata4   ERC_HIGH_CORE_GPE_REQUEST_CREATE_FAILURE
+             * @devdesc     Failure to create high core GpeRequest object
+             */
+            l_err = createErrl(
+                                PROC_CORE_INIT_MOD,                       //ModId
+                                SSX_GENERIC_FAILURE,                      //Reasoncode
+                                ERC_HIGH_CORE_GPE_REQUEST_CREATE_FAILURE, //Extended reason code
+                                ERRL_SEV_PREDICTIVE,                      //Severity
+                                l_trace,                                  //Trace Buf
+                                DEFAULT_TRACE_SIZE,                       //Trace Size
+                                l_rc,                                       //Userdata1
+                                0                                         //Userdata2
+            );
 
-            l_temp = G_write_fast_core_data_ptr;
-            G_write_fast_core_data_ptr = G_read_fast_core_data_ptr;
-            G_read_fast_core_data_ptr = l_temp;
+            // commit error log
+            REQUEST_RESET(l_err);
+            break;
         }
 
-    //Setup the get fast core data parms
-    G_chip_data_fast_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32);
-    G_chip_data_fast_parms.select = GPE_GET_CORE_DATA_FAST_FREQ_TARGET;
-    G_chip_data_fast_parms.data = (uint32_t) G_write_fast_core_data_ptr;
-
-    //Port flex schedule gpe_get_core_data_fast
-    //Check pore_flex_schedule return code if error
-    //then request OCC reset.
-
-    rc = pore_flex_schedule( &G_fast_cores_req );
-    if( rc != 0 )
-    {
-        //Error in schedule gpe get fast core data
-        TRAC_ERR("Failed PoreFlex schedule fast core data [%x] \n", rc);
-
-        /*
-         * @errortype
-         * @moduleid    PROC_TASK_FAST_CORE_DATA_MOD
-         * @reasoncode  SSX_GENERIC_FAILURE
-         * @userdata1   pore_flex_schedule return code
-         * @userdata4   OCC_NO_EXTENDED_RC
-         * @devdesc     SSX PORE related failure
-         */
-        l_err = createErrl(
-            PROC_TASK_FAST_CORE_DATA_MOD,           //modId
-            SSX_GENERIC_FAILURE,                    //reasoncode
-            OCC_NO_EXTENDED_RC,                     //Extended reason code
-            ERRL_SEV_PREDICTIVE,                    //Severity
-            l_trace, //TODO: create l_trace point   //Trace Buf
-            DEFAULT_TRACE_SIZE,                     //Trace Size
-            rc,                                     //userdata1
-            0 );                                    //userdata2
-
-        // commit error log
-        REQUEST_RESET(l_err);
-        break;
-    }
     } while(0);
 
+    // Initialize the core data control structures at the same time
+// TEMP/TODO: Needs to be re-enabled when the data control task is enabled
+//    proc_core_data_control_init();
+
     return;
 }
 
@@ -701,7 +445,7 @@ void task_fast_core_data( task_t * i_task )
 //              NULL for core ID outside the range of 0 to 11.
 //
 // End Function Specification
-gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id )
+CoreData * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id )
 {
     //The caller needs to send in a valid OCC core id. Since type is uchar
     //so there is no need to check for case less than 0.
@@ -709,32 +453,17 @@ gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id
 
     if( i_occ_core_id <= 11 )
     {
-    //Returns a pointer to the most up-to-date bulk core data.
+        //Returns a pointer to the most up-to-date bulk core data.
         return G_core_data_ptrs[i_occ_core_id];
     }
     else
     {
-    //Core id outside the range
-    TRAC_ERR("Invalid OCC core id [0x%x]", i_occ_core_id);
-    return( NULL );
+        //Core id outside the range
+        TRAC_ERR("Invalid OCC core id [0x%x]", i_occ_core_id);
+        return( NULL );
     }
 }
 
-// Function Specification
-//
-// Name: proc_get_fast_core_data_ptr
-//
-// Description: Returns a pointer to the most up-to-date fast core data
-//
-// End Function Specification
-gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void )
-{
-    //Returns a pointer to the most up-to-date fast core data.
-    //Core data is organized is organized in hardware scheme.
-
-    return G_read_fast_core_data_ptr;
-}
-
 #ifdef PROC_DEBUG
 // Function Specification
 //
@@ -746,7 +475,7 @@ gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void )
 
 void print_core_data_sensors(uint8_t core)
 {
-    gpe_bulk_core_data_t * l_core_data = proc_get_bulk_core_data_ptr(core);
+    CoreData * l_core_data = proc_get_bulk_core_data_ptr(core);
 
     if( l_core_data != NULL )
     {
@@ -777,7 +506,7 @@ void print_core_data_sensors(uint8_t core)
 
 void print_core_status(uint8_t core)
 {
-    gpe_bulk_core_data_t * l_core_data = proc_get_bulk_core_data_ptr(core);
+    CoreData * l_core_data = proc_get_bulk_core_data_ptr(core);
 
     if( l_core_data != NULL )
     {
@@ -804,31 +533,5 @@ void print_core_status(uint8_t core)
     return;
 }
 
-// Function Specification
-//
-// Name: print_fast_core_data
-//
-// Description: Print out fast core data of the chip
-//
-// End Function Specification
-
-void print_fast_core_data(void)
-{
-    gpe_fast_core_data_t * l_fast_core_data = proc_get_fast_core_data_ptr();
-
-    if( l_fast_core_data != NULL )
-    {
-        PROC_DBG("\n---------------------------\n");
-        // TODO: Commented these out b/c they take too long to run in task.
-        //dumpHexString(&l_fast_core_data->tod, sizeof(l_fast_core_data->tod), "Fast Core Data TOD");
-        //dumpHexString(&l_fast_core_data->core_data, sizeof(fast_core_data_t) * MAX_NUM_HW_CORES, "Fast Core Data");
-        PROC_DBG("\n");
-    }
-    else
-    {
-        PROC_DBG("\n G_read_fast_core_data_ptr is NULL. This should not happen.\n");
-    }
-    return;
-}
 #endif
 
diff --git a/src/occ_405/proc/proc_data.h b/src/occ_405/proc/proc_data.h
index 2c7193e..ad404a7 100755
--- a/src/occ_405/proc/proc_data.h
+++ b/src/occ_405/proc/proc_data.h
@@ -29,7 +29,7 @@
 #include <occ_common.h>
 #include <ssx.h>
 #include "rtls.h"
-//#include "gpe_data.h"
+#include "core_data.h"
 
 //Returns 0 if the specified core is not present. Otherwise, returns none-zero.
 #define CORE_PRESENT(occ_core_id) \
@@ -38,35 +38,35 @@
 //Takes an OCC core id and converts it to a core id that
 //can be used by the hardware. The caller needs to send in
 //a valid core id. Since type is uchar so there is no need to check for
-//case less than 0. If core id is invalid then returns unconfigured core 16.
+//case less than 0. If core id is invalid then returns unconfigured core 24.
 #define CORE_OCC2HW(occ_core_id) \
-        ((occ_core_id <= 15) ? G_occ2hw_core_id[occ_core_id] : 16)
+        ((occ_core_id <= 23) ? G_occ2hw_core_id[occ_core_id] : 24)
 
 //Takes a hardware core id and returns a OCC core id.
 //The caller needs to send in a valid core id. Since type is uchar so
 //there is no need to check for case less than 0. If core id
-//is invalid then returns unconfigured core 16.
+//is invalid then returns unconfigured core 24.
 #define CORE_HW2OCC(hw_core_id) \
-    ((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16)
+    ((hw_core_id <= 23) ? G_hw2occ_core_id[hw_core_id] : 24)
 
-#define ALL_CORES_MASK          0xffff0000
+#define ALL_CORES_MASK          0xffffff00
 #define CORE0_PRESENT_MASK      0x80000000ul
 #define CORE0_PRESENT_MASK_GPE  0x8000000000000000ull
 
-#define    MAX_NUM_HW_CORES    16
-#define MAX_NUM_FW_CORES    12
+#define MAX_NUM_HW_CORES    24
+#define MAX_NUM_FW_CORES    24
 
-#define    THREADS_PER_CORE    8
-#define    MAX_MEM_PARTS        4
+#define CORE_MID_POINT (MAX_NUM_FW_CORES / 2)
+
+#define THREADS_PER_CORE    4
 
-#define NUM_FAST_CORE_DATA_BUFF     2
 #define NUM_CORE_DATA_BUFF       7
 #define NUM_CORE_DATA_DOUBLE_BUF 2
 #define NUM_CORE_DATA_EMPTY_BUF  1
 
-#define LO_CORES_MASK       0x7e000000
-#define HI_CORES_MASK       0x007e0000
-#define HW_CORES_MASK       0xffff0000
+#define LO_CORES_MASK       0xfff00000
+#define HI_CORES_MASK       0x000fff00
+#define HW_CORES_MASK       0xffffff00
 
 enum eOccProcCores
 {
@@ -82,44 +82,35 @@ enum eOccProcCores
   CORE_9  = 9,
   CORE_10 = 10,
   CORE_11 = 11,
+  CORE_12 = 12,
+  CORE_13 = 13,
+  CORE_14 = 14,
+  CORE_15 = 15,
+  CORE_16 = 16,
+  CORE_17 = 17,
+  CORE_18 = 18,
+  CORE_19 = 19,
+  CORE_20 = 20,
+  CORE_21 = 21,
+  CORE_22 = 22,
+  CORE_23 = 23,
 };
 
-// TEMP -- CoreData no longer exists
-//typedef CoreData gpe_bulk_core_data_t;
-
 //Processor data collect structures used for task data pointers
 //gpe_req.request.parameter points to GpeGetCoreDataParms
-// TEMP -- CoreData / PoreFlex objects no longer exist
-/*
 struct bulk_core_data_task {
         uint8_t start_core;
         uint8_t current_core;
         uint8_t end_core;
-        gpe_bulk_core_data_t * core_data_ptr;
-        PoreFlex gpe_req;
+        CoreData * core_data_ptr;
+        GpeRequest gpe_req;
 } __attribute__ ((__packed__));
 typedef struct bulk_core_data_task bulk_core_data_task_t;
-*/
-
-//Only PCBS_LOCAL_PSTATE_FREQ_TARGET_STATUS_REG register is being
-//collected at this time. Other register will be added when needed.
-struct fast_core_data {
-    uint64_t    pcbs_lpstate_freq_target_sr;
-} __attribute__ ((__packed__));
-typedef struct fast_core_data fast_core_data_t;
-
-//gpe fast core data structure
-struct gpe_fast_core_data {
-    uint32_t    tod;
-    uint32_t    reserved;
-    fast_core_data_t core_data[MAX_NUM_HW_CORES];
-} __attribute__ ((__packed__));
-typedef struct gpe_fast_core_data gpe_fast_core_data_t;
 
 //Global low and high cores structures used for task data pointers
 // TEMP -- CoreData / PoreFlex objects no longer exist
-//extern bulk_core_data_task_t G_low_cores;
-//extern bulk_core_data_task_t G_high_cores;
+extern bulk_core_data_task_t G_low_cores;
+extern bulk_core_data_task_t G_high_cores;
 
 //Global G_present_cores is bitmask of all OCC core numbering
 extern uint32_t G_present_cores;
@@ -151,20 +142,6 @@ extern uint32_t G_empath_error_core_mask;
 #define CORE_EMPATH_ERROR(occ_core_id) \
         ((CORE0_PRESENT_MASK >> occ_core_id) & G_empath_error_core_mask)
 
-//Takes an OCC core id and converts it to a core id that
-//can be used by the hardware. The caller needs to send in
-//a valid core id. Since type is uchar so there is no need to check for
-//case less than 0. If core id is invalid then returns unconfigured core 16.
-#define CORE_OCC2HW(occ_core_id) \
-        ((occ_core_id <= 15) ? G_occ2hw_core_id[occ_core_id] : 16)
-
-//Takes a hardware core id and returns a OCC core id.
-//The caller needs to send in a valid core id. Since type is uchar so
-//there is no need to check for case less than 0. If core id
-//is invalid then returns unconfigured core 16.
-#define CORE_HW2OCC(hw_core_id) \
-    ((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16)
-
 //Collect bulk core data for all cores in specified range
 void task_core_data( task_t * i_task );
 
@@ -176,11 +153,6 @@ void task_fast_core_data( task_t * i_task );
 
 //Returns a pointer to the most up-to-date bulk core data for the core
 //associated with the specified OCC core id.
-// TEMP -- CoreData / PoreFlex objects no longer exist
-//gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id );
-
-//Returns a pointer to the most up-to-date fast core data
-// TEMP -- CoreData / PoreFlex objects no longer exist
-//gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void );
+CoreData * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id );
 
 #endif //_PROC_DATA_H
diff --git a/src/occ_405/proc/proc_data_control.c b/src/occ_405/proc/proc_data_control.c
index 8e8a3c2..9f55d91 100755
--- a/src/occ_405/proc/proc_data_control.c
+++ b/src/occ_405/proc/proc_data_control.c
@@ -24,7 +24,7 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
 #include "proc_data.h"
-#include "pgp_async.h"
+#include "occhw_async.h"
 #include "threadSch.h"
 #include "pmc_register_addresses.h"
 #include "proc_data_service_codes.h"
@@ -34,7 +34,6 @@
 #include "rtls.h"
 #include "apss.h"
 #include "state.h"
-#include "gpe_control.h"
 #include "occ_sys_config.h"
 
 // Pore flex request for GPE job. The initialization will be done one time
@@ -141,8 +140,8 @@ void proc_core_data_control_init( void )
 
     do
     {
-        //FIXME: Need to move this object to the PGPE (later phase)
-        //Initializes PoreFlex object for fast core data
+        //FIXME: Need to change this to use PGPE queue
+        //Initializes PoreFlex object for pstate control
         rc = pore_flex_create( &G_core_data_control_req,  //gpe_req for the task
                 &G_pore_gpe0_queue,                       //queue
                 gpe_set_pstates,                          //entry point
@@ -192,6 +191,8 @@ void proc_core_data_control_init( void )
 // End Function Specification
 void task_core_data_control( task_t * i_task )
 {
+//TEMP/TODO: proc_core_data_control_init needs to be called from proc_core_init()
+//           when this task is enabled for it to function properly.
     errlHndl_t       l_err   = NULL;     //Error handler
     tracDesc_t       l_trace = NULL;     //Temporary trace descriptor
     int              rc      = 0;        //Return code
diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h
index 91d3e81..7db2e90 100755
--- a/src/occ_405/rtls/rtls.h
+++ b/src/occ_405/rtls/rtls.h
@@ -41,9 +41,9 @@ typedef struct task {
 // These are used as indices into the task table defined below.
 typedef enum {
     TASK_ID_APSS_START = 0x00,
-//    TASK_ID_CORE_DATA_LOW,
+    TASK_ID_CORE_DATA_LOW,
     TASK_ID_APSS_CONT,
-//    TASK_ID_CORE_DATA_HIGH,
+    TASK_ID_CORE_DATA_HIGH,
     TASK_ID_APSS_DONE,
 //    TASK_ID_DCOM_RX_INBX,
 //    TASK_ID_DCOM_TX_INBX,
diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c
index ee48da2..69c6219 100755
--- a/src/occ_405/rtls/rtls_tables.c
+++ b/src/occ_405/rtls/rtls_tables.c
@@ -95,11 +95,9 @@
 task_t G_task_table[TASK_END] = {
     // flags,                      func_ptr,                       data_ptr,// task_id_t
     { FLAGS_APSS_START_MEAS,       task_apss_start_pwr_meas,       NULL },  // TASK_ID_APSS_START
-// TEMP -- PORE ISSUES
-//    { FLAGS_LOW_CORES_DATA,        task_core_data,                 (void *) &G_low_cores},
+    { FLAGS_LOW_CORES_DATA,        task_core_data,                 (void *) &G_low_cores},
     { FLAGS_APSS_CONT_MEAS,        task_apss_continue_pwr_meas,    NULL },  // TASK_ID_APSS_CONT
-// TEMP -- PORE ISSUES
-//    { FLAGS_HIGH_CORES_DATA,       task_core_data,                 (void *) &G_high_cores},
+    { FLAGS_HIGH_CORES_DATA,       task_core_data,                 (void *) &G_high_cores},
     { FLAGS_APSS_DONE_MEAS,        task_apss_complete_pwr_meas,    NULL },  // TASK_ID_APSS_DONE
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_DCOM_RX_SLV_INBX,      task_dcom_rx_slv_inbox,         NULL },  // TASK_ID_DCOM_RX_INBX
@@ -131,10 +129,10 @@ task_t G_task_table[TASK_END] = {
 
 const uint8_t G_tick0_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -151,7 +149,7 @@ const uint8_t G_tick0_seq[] = {
 
 const uint8_t G_tick1_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 TASK_ID_APSS_DONE,
@@ -170,10 +168,10 @@ const uint8_t G_tick1_seq[] = {
 
 const uint8_t G_tick2_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -191,7 +189,7 @@ const uint8_t G_tick3_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
@@ -208,10 +206,10 @@ const uint8_t G_tick3_seq[] = {
 
 const uint8_t G_tick4_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -228,7 +226,7 @@ const uint8_t G_tick4_seq[] = {
 
 const uint8_t G_tick5_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 TASK_ID_APSS_DONE,
@@ -247,10 +245,10 @@ const uint8_t G_tick5_seq[] = {
 
 const uint8_t G_tick6_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -268,7 +266,7 @@ const uint8_t G_tick7_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
@@ -285,10 +283,10 @@ const uint8_t G_tick7_seq[] = {
 
 const uint8_t G_tick8_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -305,7 +303,7 @@ const uint8_t G_tick8_seq[] = {
 
 const uint8_t G_tick9_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 TASK_ID_APSS_DONE,
@@ -324,10 +322,10 @@ const uint8_t G_tick9_seq[] = {
 
 const uint8_t G_tick10_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -345,7 +343,7 @@ const uint8_t G_tick11_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
@@ -362,10 +360,10 @@ const uint8_t G_tick11_seq[] = {
 
 const uint8_t G_tick12_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -382,7 +380,7 @@ const uint8_t G_tick12_seq[] = {
 
 const uint8_t G_tick13_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 TASK_ID_APSS_DONE,
@@ -401,10 +399,10 @@ const uint8_t G_tick13_seq[] = {
 
 const uint8_t G_tick14_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
+                                TASK_ID_CORE_DATA_LOW,
                                 //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
@@ -422,7 +420,7 @@ const uint8_t G_tick15_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index d576110..97e959d 100755
--- a/src/occ_405/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -102,6 +102,7 @@ do {                                                                \
 #define APPCFG_OCC_INSTANCE_ID 4
 
 
+#define PROC_DEBUG 1
 // Common configuration groups for verification. Bypass time-consuming setup
 // or setup done by procedures for simulation environments, and set up special
 // I/O configurations for simulation environments.
diff --git a/src/occ_405/topfiles.mk b/src/occ_405/topfiles.mk
index 5d2dd54..2daa6bc 100644
--- a/src/occ_405/topfiles.mk
+++ b/src/occ_405/topfiles.mk
@@ -52,6 +52,7 @@ TOP-C-SOURCES = amec/amec_data.c \
                 mode.c \
                 occ_sys_config.c \
                 occbuildname.c \
+                proc/proc_data.c \
                 proc/proc_pstate.c \
                 pss/apss.c \
                 reset.c \
diff --git a/src/occ_gpe0/apss_util.c b/src/occ_gpe0/apss_util.c
index 4e9082f..a742be3 100644
--- a/src/occ_gpe0/apss_util.c
+++ b/src/occ_gpe0/apss_util.c
@@ -170,5 +170,27 @@ void busy_wait(uint32_t t_microseconds)
 
     while (current_decrementer_value > end_decrementer_value)     // Wait until end_decrementer_value is reached
         MFDEC(current_decrementer_value);
+}
+
+void ipc_scom_operation(ipc_msg_t* cmd, void* arg)
+{
+    int l_rc;
+    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
+    ipc_scom_op_t *scom_op = (ipc_scom_op_t*) async_cmd->cmd_data;
 
+    if (scom_op->read)
+    {
+        l_rc = getscom_abs(scom_op->addr, &scom_op->data);
+    }
+    else
+    {
+        l_rc = putscom_abs(scom_op->addr, scom_op->data);
+    }
+
+    if(l_rc)
+    {
+        scom_op->rc = l_rc;
+        PK_TRACE("Error doing generic scom! RC: 0x%08X Addr: 0x%08X Read: %d Data: 0x%08X", l_rc,
+                 scom_op->addr, scom_op->read, scom_op->data);
+    }
 }
diff --git a/src/occ_gpe0/apss_util.h b/src/occ_gpe0/apss_util.h
index 9d0a763..2107d40 100644
--- a/src/occ_gpe0/apss_util.h
+++ b/src/occ_gpe0/apss_util.h
@@ -27,6 +27,9 @@
 #define _APSS_UTIL_H
 
 #include <apss_structs.h>
+#include <common_types.h>
+#include <ipc_structs.h>
+#include <ipc_async_cmd.h>
 
 void apss_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint64_t i_ffdc);
 
diff --git a/src/occ_gpe0/img_defs.mk b/src/occ_gpe0/img_defs.mk
index ade3c6b..fe5ea31 100644
--- a/src/occ_gpe0/img_defs.mk
+++ b/src/occ_gpe0/img_defs.mk
@@ -94,6 +94,10 @@ ifndef COMMONLIB_SRCDIR
 export COMMONLIB_SRCDIR = $(abspath ../lib/common)
 endif
 
+ifndef OCC_COMMON_TYPES_DIR
+export OCC_COMMON_TYPES_DIR = $(abspath ../occ_405/incl/)
+endif
+
 ifndef OCCLIB_SRCDIR
 export OCCLIB_SRCDIR = $(abspath ../lib/occlib)
 endif
@@ -177,7 +181,8 @@ DEFS += $(GCC-DEFS)
 INCLUDES += $(IMG_INCLUDES) $(GLOBAL_INCLUDES) \
 	-I$(PK_SRCDIR)/kernel -I$(PK_SRCDIR)/ppe42 -I$(PK_SRCDIR)/trace \
 	-I$(PK_SRCDIR)/$(PPE_TYPE) -I$(PK_SRCDIR)/../../include \
-	-I$(PK_SRCDIR)/../../include/registers -I$(OCCLIB_SRCDIR) -I$(COMMONLIB_SRCDIR)
+	-I$(PK_SRCDIR)/../../include/registers -I$(OCCLIB_SRCDIR) -I$(COMMONLIB_SRCDIR) \
+    -I$(OCC_COMMON_TYPES_DIR)
 
 PIPE-CFLAGS = -pipe -Wa,-m405
 
diff --git a/src/occ_gpe0/ipc_func_tables.c b/src/occ_gpe0/ipc_func_tables.c
index c1ea1e7..4d1e97f 100644
--- a/src/occ_gpe0/ipc_func_tables.c
+++ b/src/occ_gpe0/ipc_func_tables.c
@@ -24,12 +24,14 @@
 /* IBM_PROLOG_END_TAG                                                     */
 #include "ipc_api.h"
 #include "ipc_ping.h"
+#include "apss_util.h"
 
 void apss_init_gpio(ipc_msg_t* cmd, void* arg);
 void apss_init_mode(ipc_msg_t* cmd, void* arg);
 void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg);
 void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg);
 void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg);
+void ipc_scom_operation(ipc_msg_t* cmd, void* arg);
 
 extern ipc_msgq_t G_gpe0_test_msgq0;
 
@@ -59,7 +61,7 @@ IPC_HANDLER(apss_init_mode, 0)               // 2 - IPC_ST_APSS_INIT_MODE_FUNCID
 IPC_HANDLER(apss_start_pwr_meas_read, 0)     // 3 - IPC_ST_APSS_START_PWR_MEAS_READ_FUNCID
 IPC_HANDLER(apss_continue_pwr_meas_read, 0)  // 4 - IPC_ST_APSS_CONTINUE_PWR_MEAS_READ_FUNCID
 IPC_HANDLER(apss_complete_pwr_meas_read, 0)  // 5 - IPC_ST_APSS_COMPLETE_PWR_MEAS_READ_FUNCID
-IPC_HANDLER_DEFAULT                          // 6
+IPC_HANDLER(ipc_scom_operation, 0)           // 6 - IPC_ST_SCOM_OPERATION
 IPC_HANDLER_DEFAULT                          // 7
 IPC_HANDLER_DEFAULT                          // 8
 IPC_HANDLER_DEFAULT                          // 9