new ssx and lib files

Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>

453 files changed, 13746 insertions, 37626 deletions

diff --git a/src/Makefile b/src/Makefile
index d90b2f0..a9dd842 100755
--- a/src/Makefile
+++ b/src/Makefile
@@ -1,3 +1,27 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 
 ifndef ROOTPATH
 ROOTPATH = $(shell pwd)
@@ -7,9 +31,9 @@ endif
 #*******************************************************************************
 # mk variable Declaration
 #*******************************************************************************
-SUBDIRS = tracepp occBootLoader occ occApplet
-COMBINE_IMAGE_SUBDIRS = occBootLoader occ occApplet
-CLEAN_SUBDIRS = occBootLoader occ occApplet ssx/pgp lib
+SUBDIRS = tracepp occBootLoader occ_405 occApplet
+COMBINE_IMAGE_SUBDIRS = occBootLoader occ_405 occApplet
+CLEAN_SUBDIRS = occBootLoader occ_405 occApplet ssx/pgp lib
 CLEANCMD = $(MAKE) clean -C $(dir)
 ALLCMD = $(MAKE) -C $(dir)
 COMBINEIMAGE = $(MAKE) combineImage -C $(dir)
diff --git a/src/lib/Makefile b/src/lib/Makefile
deleted file mode 100755
index 2d257a6..0000000
--- a/src/lib/Makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-# $Id: Makefile,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-#
-#  This Makefile currently builds a single archive, 'libssx.a', from
-#  various library source files. 
-#
-#  Beware that although this library can be built standalone, parts of
-#  its behavior are controlled by options that may be configured in
-#  the optional "ssx_app_cfg.h", so it is best to build the library as
-#  part of the complete application build.
-#
-#  The object files stored in the archive are loaded 'on demand'.
-#  It may be possible to save a little code space therefore by splitting up
-#  the implementation of a header file into multiple files whose
-#  functions are not necessarily called together.
-
-SSX = ../ssx
-PGP = $(SSX)/pgp
-LIB = .
-
-include ./libfiles.mk
-include ./libgpefiles.mk
-INCLUDES =
-
-include $(PGP)/ssx.mk
-
-libssx.a: $(LIBSSX_OBJECTS)
-	$(AR) crs libssx.a $(LIBSSX_OBJECTS)
-
-clean:
-	rm -f *.o *.a *.d *.d.* *.lst *.hooks.cc
-	rm -f $(TEST_EXECUTABLES)
-
-disassemble: libssx.a
-	$(OBJDUMP) -d libssx.a
-
-
-# The targets 'push_updates_to_lab' and 'diff_with_lab' require that an
-# environment variable P8PROCS be defined.  You can also define this on the
-# 'make' command line, for example
-#
-#    make P8PROCS=<... path to your P8 procedures sandbox ...> \
-#        push_updates_to_lab
-
-# LIB-TO-PROCS-FILES are files kept here that need to go there, where 'there'
-# is the top-level procedures directory.
-
-LIB-TO-PROCS-FILES = pgas.h pgas_ppc.h
-
-push_updates_to_lab:
-	if [ -z "$(P8PROCS)" ]; then echo "P8PROCS is not defined"; exit 1; fi
-	cp -u $(LIB-TO-PROCS-FILES) $(P8PROCS)
-
-diff_with_lab:
-	if [ -z "$(P8PROCS)" ]; then echo "P8PROCS is not defined"; exit 1; fi
-
-	for file in $(LIB-TO-PROCS-FILES); do \
-		echo "@@@ $$file"; \
-		diff $$file $(P8PROCS)/$$file; \
-	done; exit 0
-
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(MAKECMDGOALS),push_updates_to_lab)
-ifneq ($(MAKECMDGOALS),diff_with_lab)
-include $(C-SOURCES:.c=.d) 
-include $(S-SOURCES:.S=.d)
-include $(if $(filter -DOCC_FIRMWARE=1,$(DEFS)),$(if $(PGAS_PPC),$(pS-SOURCES:.pS=.d),),$(pS-SOURCES:.pS=.d))
-endif
-endif
-endif
-
diff --git a/src/lib/assert.c b/src/lib/assert.c
deleted file mode 100755
index 36e3caf..0000000
--- a/src/lib/assert.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// $Id: assert.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/assert.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file assert.c
-/// \brief Implementation of library routines implied by <assert.h>
-
-#include "ssx.h"
-#include "ssx_io.h"
-#include "libssx.h"
-
-/// The __assert_fail() function is used to implement the assert() interface
-/// of ISO POSIX (2003). The __assert_fail() function prints the given \a
-/// file filename, \a line line number, \a function function name and a
-/// message on the standard error stream then causes a kernel panic.  If there
-/// is no standard error stream then the error message is printed on the \a
-/// ssxout (printk()) stream.
-/// 
-/// If function is NULL, __assert_fail() omits information about the
-/// function. The aguments \a assertion, \a file, and \a line must be
-/// non-NULL.
-
-void
-__assert_fail(const char *assertion, 
-              const char *file, 
-              unsigned line, 
-              const char *function)
-{
-    FILE *stream;
-
-    stream = stderr;
-    if (stream == 0) {
-        stream = ssxout;
-    }
-
-    fprintf(stream, "%s:%u:%s%s Assertion '%s' failed\n",
-            file, line, 
-            function ? function : "", function ? ":" : "",
-            assertion);
-
-    SSX_PANIC(ASSERTION_FAILURE);
-}
-
diff --git a/src/lib/common/Makefile b/src/lib/common/Makefile
new file mode 100644
index 0000000..5147b59
--- /dev/null
+++ b/src/lib/common/Makefile
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/common/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  This Makefile currently builds a single archive, 'libcommon.a', from
+#  various library source files. 
+#
+#  part of the complete application build.
+#
+
+#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/common
+export SUB_OBJDIR = /commonlib
+
+include img_defs.mk
+include libcommonfiles.mk
+
+OBJS := $(addprefix $(OBJDIR)/, $(LIBCOMMON_OBJECTS))
+
+libcommon.a: local
+	$(AR) crs $(OBJDIR)/libcommon.a $(OBJDIR)/*.o
+
+.PHONY: clean
+
+local: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+#include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/lib/common/README.txt b/src/lib/common/README.txt
new file mode 100644
index 0000000..760da25
--- /dev/null
+++ b/src/lib/common/README.txt
@@ -0,0 +1 @@
+This directory contains code that can run on any PPE or 405 processor.
diff --git a/src/lib/common/kernel.h b/src/lib/common/kernel.h
new file mode 100644
index 0000000..063d35c
--- /dev/null
+++ b/src/lib/common/kernel.h
@@ -0,0 +1,363 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/kernel.h $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __KERNEL_H__
+#define __KERNEL_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file kernel.h
+/// \brief Kernel agnostic macros that allow the same code to work with
+///        different kernels.
+///
+///        Programmers can include this instead of pk.h or ssx.h
+///       
+///
+#ifndef __ASSEMBLER__
+#ifdef __SSX__
+
+/// ----------------------- Use SSX kernel interfaces --------------------------
+
+#include "ssx.h"
+
+//Types
+#define KERN_SEMAPHORE              SsxSemaphore
+#define KERN_SEMAPHORE_COUNT        SsxSemaphoreCount
+#define KERN_DEQUE                  SsxDeque
+#define KERN_THREAD                 SsxThread
+#define KERN_THREAD_PRIORITY        SsxThreadPriority
+#define KERN_THREAD_STATE           SsxThreadState
+#define KERN_THREAD_ROUTINE         SsxThreadRoutine
+#define KERN_THREAD_FLAGS           SsxThreadFlags
+#define KERN_ADDRESS                SsxAddress
+#define KERN_TIMER                  SsxTimer
+#define KERN_TIMER_CALLBACK         SsxTimerCallback
+#define KERN_INTERVAL               SsxInterval
+#define KERN_TIMEBASE               SsxTimebase
+#define KERN_IRQ_ID                 SsxIrqId
+#define KERN_MACHINE_CONTEXT        SsxMachineContext
+
+//Constants
+#define KERN_SEMAPHORE_PEND_TIMED_OUT   SSX_SEMAPHORE_PEND_TIMED_OUT
+#define KERN_SEMAPHORE_PEND_NO_WAIT     SSX_SEMAPHORE_PEND_NO_WAIT
+#define KERN_NONCRITICAL                SSX_NONCRITICAL
+#define KERN_CRITICAL                   SSX_CRITICAL
+#define KERN_SUPERCRITICAL              SSX_SUPERCRITICAL
+#define KERN_ERROR_CHECK_API            SSX_ERROR_CHECK_API
+#define KERN_NO_WAIT                    SSX_NO_WAIT
+#define KERN_WAIT_FOREVER               SSX_WAIT_FOREVER
+
+//Functions
+#define KERN_SECONDS(s)         SSX_SECONDS(s)
+#define KERN_MILLISECONDS(m)    SSX_MILLISECONDS(m) 
+#define KERN_MICROSECONDS(u)    SSX_MICROSECONDS(u)
+#define KERN_NANOSECONDS(n)     SSX_NANOSECONDS(n) 
+
+#define KERN_TIMEBASE_GET()     ssx_timebase_get()
+#define KERN_TIMEBASE_SET(tb)   ssx_timebase_set(tb)
+
+#define KERN_INTERRUPT_PREEMPTION_ENABLE()  ssx_interrupt_preemption_enable()
+#define KERN_INTERRUPT_PREEMPTION_DISABLE() ssx_interrupt_preemption_disable()
+
+#define KERN_TIMER_CREATE(timer, callback, arg) \
+    ssx_timer_create(timer, callback, arg)
+#define KERN_TIMER_CREATE_NONPREEMPTIBLE(timer, callback, arg)  \
+    ssx_timer_create_nonpreemptible(timer, callback, arg)
+#define KERN_TIMER_SCHEDULE_ABSOLUTE(timer, time, period) \
+    ssx_timer_schedule_absolute(timer, time, period)
+#define KERN_TIMER_SCHEDULE(timer, interval, period) \
+    ssx_timer_schedule(timer, interval, period)
+#define KERN_TIMER_CANCEL(timer) \
+    ssx_timer_cancel(timer)
+#define KERN_TIMER_INFO_GET(timer, timeout, active) \
+    ssx_timer_info_get(timer, timeout, active)
+
+#define KERN_THREAD_CREATE(thread, thread_routine, arg, stack, stack_size, priority) \
+    ssx_thread_create(thread, thread_routine, arg, stack, stack_size, priority)
+#define KERN_THREAD_INFO_GET(thread, state, priority, runnable) \
+    ssx_thread_info_get(thread, state, priority, runnable)
+#define KERN_THREAD_PRIORTY_CHANGE(thread, new_priority, old_priority) \
+    ssx_thread_priority_change(thread, new_priority, old_priority)
+#define KERN_THREAD_AT_PRIORITY(priority, thread) \
+    ssx_thread_at_priority(priority, thread)
+#define KERN_THREAD_PRIORITY_SWAP(thread_a, thread_b) \
+    ssx_thread_priority_swap(thread_a, thread_b)
+
+#define KERN_START_THREADS()            ssx_start_threads()
+#define KERN_THREAD_RESUME(thread)      ssx_thread_resume(thread)
+#define KERN_THREAD_SUSPEND(thread)     ssx_thread_suspend(thread)
+#define KERN_THREAD_DELETE(thread)      ssx_thread_delete(thread)
+#define KERN_COMPLETE()                 ssx_complete()
+#define KERN_SLEEP_ABSOLUTE(time)       ssx_sleep_absolute(time)
+#define KERN_SLEEP(interval)            ssx_sleep(interval)
+
+#define KERN_SEMAPHORE_CREATE(semaphore, initial_count, max_count) \
+    ssx_semaphore_create(semaphore, initial_count,max_count)
+#define KERN_SEMAPHORE_STATIC_CREATE(sem, initial_count, max_count) \
+    SSX_SEMAPHORE(sem, initial_count, max_count)
+#define KERN_SEMAPHORE_INITIALIZATION(_initial_count, _max_count) \
+    SSX_SEMAPHORE_INITIALIZATION(_initial_count, _max_count)
+#define KERN_SEMAPHORE_INFO_GET(semaphore, count, pending) \
+    ssx_semaphore_info_get(semaphore, count, pending)
+
+#define KERN_SEMAPHORE_POST(semaphore) \
+    ssx_semaphore_post(semaphore)
+#define KERN_SEMAPHORE_PEND(semaphore, timeout) \
+    ssx_semaphore_pend(semaphore, timeout)
+#define KERN_SEMAPHORE_RELEASE_ALL(semaphore) \
+    ssx_semaphore_release_all(semaphore)
+#define KERN_SEMAPHORE_POST_HANDLER(arg, irq, priority) \
+    ssx_semaphore_post_handler(arg, irq, priority)
+
+
+#define KERN_HALT() \
+    ssx_halt()
+#define KERN_PANIC(code) \
+    SSX_PANIC(code)
+
+#define KERN_DEQUE_SENTINEL_CREATE(deque) \
+    ssx_deque_sentinel_create(deque)
+#define KERN_DEQUE_SENTINEL_STATIC_CREATE(deque) \
+    SSX_DEQUE_SENTINEL_STATIC_CREATE(deque)
+#define KERN_DEQUE_SENTINEL_INIT(dq_addr) \
+    SSX_DEQUE_SENTINEL_INIT(dq_addr)
+#define KERN_DEQUE_ELEMENT_CREATE(element) \
+    ssx_deque_element_create(element)
+#define KERN_DEQUE_ELEMENT_STATIC_CREATE(deque) \
+    SSX_DEQUE_ELEMENT_STATIC_CREATE(deque)
+#define KERN_DEQUE_ELEMENT_INIT() \
+    SSX_DEQUE_ELEMENT_INIT()
+#define KERN_DEQUE_IS_EMPTY(deque) \
+    ssx_deque_is_empty(deque)
+#define KERN_DEQUE_IS_QUEUED(element) \
+    ssx_deque_is_queued(element)
+#define KERN_DEQUE_PUSH_BACK(deque, element) \
+    ssx_deque_push_back(deque, element)
+#define KERN_DEQUE_PUSH_FRONT(deque, element) \
+    ssx_deque_push_front(deque, element)
+#define KERN_DEQUE_POP_FRONT(deque) \
+    ssx_deque_pop_front(deque)
+#define KERN_DEQUE_DELETE(element) \
+    ssx_deque_delete(element)
+
+#define KERN_IRQ_HANDLER(f) \
+    SSX_IRQ_HANDLER(f)
+#define KERN_IRQ_SETUP(irq, polarity, trigger) \
+    ssx_irq_setup(irq, polarity, trigger)
+#define KERN_IRQ_HANDLER_SET(irq, handler, arg, priority) \
+    ssx_irq_handler_set(irq, handler, arg, priority)
+#define KERN_IRQ_ENABLE(irq) \
+    ssx_irq_enable(irq)
+#define KERN_IRQ_DISABLE(irq) \
+    ssx_irq_disable(irq)
+#define KERN_IRQ_STATUS_CLEAR(irq) \
+    ssx_irq_status_clear(irq)
+#define KERN_IRQ_STATUS_SET(irq, value) \
+    ssx_irq_status_set(irq, value)
+#define KERN_IRQ_FAST2FULL(fast_handler, full_handler) \
+    SSX_IRQ_FAST2FULL(fast_handler, full_handler)
+
+#define KERN_CRITICAL_SECTION_ENTER(priority, pctx) \
+    ssx_critical_section_enter(priority, pctx)
+#define KERN_CRITICAL_SECTION_EXIT(pctx) \
+    ssx_critical_section_exit(pctx)
+#define KERN_CONTEXT_CRITICAL_INTERRUPT() \
+    __ssx_kernel_context_critical_interrupt()
+
+#define KERN_ERROR_IF(condition, code) SSX_ERROR_IF(condition, code)
+
+#define KERN_CAST_POINTER(t, p) SSX_CAST_POINTER(t, p)
+
+#define KERN_STATIC_ASSERT(cond) SSX_STATIC_ASSERT(cond)
+
+#elif defined(__PK__)
+
+/// ----------------------- Use PK kernel interfaces --------------------------
+
+#include "pk.h"
+
+//Types
+#define KERN_SEMAPHORE              PkSemaphore
+#define KERN_SEMAPHORE_COUNT        PkSemaphoreCount
+#define KERN_DEQUE                  PkDeque
+#define KERN_THREAD                 PkThread
+#define KERN_THREAD_PRIORITY        PkThreadPriority
+#define KERN_THREAD_STATE           PkThreadState
+#define KERN_THREAD_ROUTINE         PkThreadRoutine
+#define KERN_THREAD_FLAGS           PkThreadFlags
+#define KERN_ADDRESS                PkAddress
+#define KERN_TIMER                  PkTimer
+#define KERN_TIMER_CALLBACK         PkTimerCallback
+#define KERN_INTERVAL               PkInterval
+#define KERN_TIMEBASE               PkTimebase
+#define KERN_IRQ_ID                 PkIrqId
+#define KERN_MACHINE_CONTEXT        PkMachineContext
+
+//Constants
+#define KERN_SEMAPHORE_PEND_TIMED_OUT   PK_SEMAPHORE_PEND_TIMED_OUT
+#define KERN_SEMAPHORE_PEND_NO_WAIT     PK_SEMAPHORE_PEND_NO_WAIT
+#define KERN_NONCRITICAL                0
+#define KERN_CRITICAL                   0
+#define KERN_SUPERCRITICAL              0
+#define KERN_ERROR_CHECK_API            PK_ERROR_CHECK_API
+#define KERN_NO_WAIT                    PK_NO_WAIT
+#define KERN_WAIT_FOREVER               PK_WAIT_FOREVER
+
+//Functions
+#define KERN_SECONDS(s)         PK_SECONDS(s)
+#define KERN_MILLISECONDS(m)    PK_MILLISECONDS(m) 
+#define KERN_MICROSECONDS(u)    PK_MICROSECONDS(u)
+#define KERN_NANOSECONDS(n)     PK_NANOSECONDS(n) 
+
+#define KERN_TIMEBASE_GET()     pk_timebase_get()
+#define KERN_TIMEBASE_SET(tb)   pk_timebase_set(tb)
+
+#define KERN_INTERRUPT_PREEMPTION_ENABLE()  pk_interrupt_preemption_enable()
+#define KERN_INTERRUPT_PREEMPTION_DISABLE() pk_interrupt_preemption_disable()
+
+#define KERN_TIMER_CREATE(timer, callback, arg) \
+    pk_timer_create(timer, callback, arg)
+#define KERN_TIMER_CREATE_NONPREEMPTIBLE(timer, callback, arg)  \
+    pk_timer_create_nonpreemptible(timer, callback, arg)
+#define KERN_TIMER_SCHEDULE_ABSOLUTE(timer, time, period) \
+    pk_timer_schedule_absolute(timer, time, period)
+#define KERN_TIMER_SCHEDULE(timer, interval, period) \
+    pk_timer_schedule(timer, interval, period)
+#define KERN_TIMER_CANCEL(timer) \
+    pk_timer_cancel(timer)
+#define KERN_TIMER_INFO_GET(timer, timeout, active) \
+    pk_timer_info_get(timer, timeout, active)
+
+#define KERN_THREAD_CREATE(thread, thread_routine, arg, stack, stack_size, priority) \
+    pk_thread_create(thread, thread_routine, arg, stack, stack_size, priority)
+#define KERN_THREAD_INFO_GET(thread, state, priority, runnable) \
+    pk_thread_info_get(thread, state, priority, runnable)
+#define KERN_THREAD_PRIORTY_CHANGE(thread, new_priority, old_priority) \
+    pk_thread_priority_change(thread, new_priority, old_priority)
+#define KERN_THREAD_AT_PRIORITY(priority, thread) \
+    pk_thread_at_priority(priority, thread)
+#define KERN_THREAD_PRIORITY_SWAP(thread_a, thread_b) \
+    pk_thread_priority_swap(thread_a, thread_b)
+
+#define KERN_START_THREADS()            pk_start_threads()
+#define KERN_THREAD_RESUME(thread)      pk_thread_resume(thread)
+#define KERN_THREAD_SUSPEND(thread)     pk_thread_suspend(thread)
+#define KERN_THREAD_DELETE(thread)      pk_thread_delete(thread)
+#define KERN_COMPLETE()                 pk_complete()
+#define KERN_SLEEP_ABSOLUTE(time)       pk_sleep_absolute(time)
+#define KERN_SLEEP(interval)            pk_sleep(interval)
+
+#define KERN_SEMAPHORE_CREATE(semaphore, initial_count, max_count) \
+    pk_semaphore_create(semaphore, initial_count,max_count)
+#define KERN_SEMAPHORE_STATIC_CREATE(sem, initial_count, max_count) \
+    PK_SEMAPHORE(sem, initial_count, max_count)
+#define KERN_SEMAPHORE_INITIALIZATION(_initial_count, _max_count) \
+    PK_SEMAPHORE_INITIALIZATION(_initial_count, _max_count)
+#define KERN_SEMAPHORE_INFO_GET(semaphore, count, pending) \
+    pk_semaphore_info_get(semaphore, count, pending)
+
+#define KERN_SEMAPHORE_POST(semaphore) \
+    pk_semaphore_post(semaphore)
+#define KERN_SEMAPHORE_PEND(semaphore, timeout) \
+    pk_semaphore_pend(semaphore, timeout)
+#define KERN_SEMAPHORE_RELEASE_ALL(semaphore) \
+    pk_semaphore_release_all(semaphore)
+#define KERN_SEMAPHORE_POST_HANDLER(arg, irq, priority) \
+    pk_semaphore_post_handler(arg, irq, priority)
+
+
+#define KERN_HALT() \
+    pk_halt()
+#define KERN_PANIC(code) \
+    PK_PANIC(code)
+
+#define KERN_DEQUE_SENTINEL_CREATE(deque) \
+    pk_deque_sentinel_create(deque)
+#define KERN_DEQUE_SENTINEL_STATIC_CREATE(deque) \
+    PK_DEQUE_SENTINEL_STATIC_CREATE(deque)
+#define KERN_DEQUE_SENTINEL_INIT(dq_addr) \
+    PK_DEQUE_SENTINEL_INIT(dq_addr)
+#define KERN_DEQUE_ELEMENT_CREATE(element) \
+    pk_deque_element_create(element)
+#define KERN_DEQUE_ELEMENT_STATIC_CREATE(deque) \
+    PK_DEQUE_ELEMENT_STATIC_CREATE(deque)
+#define KERN_DEQUE_ELEMENT_INIT() \
+    PK_DEQUE_ELEMENT_INIT()
+#define KERN_DEQUE_IS_EMPTY(deque) \
+    pk_deque_is_empty(deque)
+#define KERN_DEQUE_IS_QUEUED(element) \
+    pk_deque_is_queued(element)
+#define KERN_DEQUE_PUSH_BACK(deque, element) \
+    pk_deque_push_back(deque, element)
+#define KERN_DEQUE_PUSH_FRONT(deque, element) \
+    pk_deque_push_front(deque, element)
+#define KERN_DEQUE_POP_FRONT(deque) \
+    pk_deque_pop_front(deque)
+#define KERN_DEQUE_DELETE(element) \
+    pk_deque_delete(element)
+
+#define KERN_IRQ_HANDLER(f) \
+    PK_IRQ_HANDLER(f)
+#define KERN_IRQ_SETUP(irq, polarity, trigger) \
+    pk_irq_setup(irq, polarity, trigger)
+#define KERN_IRQ_HANDLER_SET(irq, handler, arg, priority) \
+    pk_irq_handler_set(irq, handler, arg)
+#define KERN_IRQ_ENABLE(irq) \
+    pk_irq_enable(irq)
+#define KERN_IRQ_DISABLE(irq) \
+    pk_irq_disable(irq)
+#define KERN_IRQ_STATUS_CLEAR(irq) \
+    pk_irq_status_clear(irq)
+#define KERN_IRQ_STATUS_SET(irq, value) \
+    pk_irq_status_set(irq, value)
+#define KERN_IRQ_FAST2FULL(fast_handler, full_handler) \
+    PK_IRQ_FAST2FULL(fast_handler, full_handler)
+
+#define KERN_CRITICAL_SECTION_ENTER(priority, pctx) \
+    pk_critical_section_enter(pctx)
+#define KERN_CRITICAL_SECTION_EXIT(pctx) \
+    pk_critical_section_exit(pctx)
+#define KERN_CONTEXT_CRITICAL_INTERRUPT() \
+    (0)
+
+#define KERN_ERROR_IF(condition, code) PK_ERROR_IF(condition, code)
+
+#define KERN_CAST_POINTER(t, p) PK_CAST_POINTER(t, p)
+
+#define KERN_STATIC_ASSERT(cond) PK_STATIC_ASSERT(cond)
+
+#else
+
+/// ----------------------- Kernel type not defined --------------------------
+
+#error "Kernel type must be defined in img_defs.mk"
+
+#endif /*__SSX__*/
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* __KERNEL_H__ */
diff --git a/src/lib/common/libcommonfiles.mk b/src/lib/common/libcommonfiles.mk
new file mode 100644
index 0000000..9fe7592
--- /dev/null
+++ b/src/lib/common/libcommonfiles.mk
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/common/libcommonfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file libcommonfiles.mk
+#
+#  @brief mk for libcommon.a object files
+#
+#  @page ChangeLogs Change Logs
+#  @section ofiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# INCLUDES
+##########################################################################
+
+C-SOURCES = \
+    memcpy.c \
+	memset.c \
+	rand32.c \
+	string.c \
+	sync.c
+
+
+S-SOURCES =  
+
+LIBCOMMON_OBJECTS = $(C-SOURCES:.c=.o) $(S-SOURCES:.S=.o)
diff --git a/src/lib/memcpy.c b/src/lib/common/memcpy.c
index ab508ea..77827dc 100755..100644
--- a/src/lib/memcpy.c
+++ b/src/lib/common/memcpy.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/memcpy.c $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: memcpy.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/memcpy.c,v $
 //-----------------------------------------------------------------------------
@@ -9,7 +33,7 @@
 /// \file memcpy.c
 /// \brief The memcpy() function
 
-#include "ssx.h"
+#include "kernel.h"
 
 /// The memcpy() function copies \a n bytes from memory area \a src to memory
 /// area \a dest.  The memory areas should not overlap.  Use memmove(3) if the
diff --git a/src/lib/memset.c b/src/lib/common/memset.c
index 98fdda2..1d98677 100755..100644
--- a/src/lib/memset.c
+++ b/src/lib/common/memset.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/memset.c $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: memset.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/memset.c,v $
 //-----------------------------------------------------------------------------
@@ -9,7 +33,7 @@
 /// \file memset.c
 /// \brief The memset() function
 
-#include "ssx.h"
+#include "kernel.h"
 
 /// The memset() function fills the first \a n bytes of the memory area
 /// pointed to by \a s with the constant byte \a c.  The memset() function
diff --git a/src/lib/common/rand.h b/src/lib/common/rand.h
new file mode 100644
index 0000000..369b8fd
--- /dev/null
+++ b/src/lib/common/rand.h
@@ -0,0 +1,124 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/rand.h $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __RAND_H__
+#define __RAND_H__
+
+// $Id$
+
+/// \file rand.h
+/// \brief Random number generation
+
+#include <stdint.h>
+
+// Error/Panic codes
+
+#define RAND64_UNIMPLEMENTED 0x00726301
+
+
+/// RAND32_ALL is used as the \a limit argument to rand32() and _rand32() to
+/// request the return of a full 32-bit random unsigned integer.
+
+#define RAND32_ALL 0
+
+extern uint32_t _seed32;
+
+uint32_t 
+_rand32(uint32_t *seed, uint32_t limit);
+
+uint32_t
+rand32(uint32_t limit);
+
+void
+srand32(uint32_t seed);
+
+
+/// RAND64_ALL is used as the \a limit argument to rand64() and _rand64() to
+/// request the return of a full 64-bit random unsigned integer.
+
+#define RAND64_ALL 0
+
+extern uint64_t _seed64;
+
+//void
+//davidmult64to128(uint64_t u, uint64_t v, uint64_t &h, uint64_t &l);
+
+uint64_t 
+_rand64(uint64_t *seed, uint64_t limit);
+
+uint64_t
+rand64(uint64_t limit);
+
+void
+srand64(uint64_t seed);
+
+
+/// A random weighting map for integer selections
+///
+/// See rand_map_int() for details.
+
+typedef struct {
+
+    /// The relative weight of this selection
+    ///
+    /// The final weight of the map array \e must be 0 to terminate the map.
+    unsigned weight;
+
+    /// The selection
+    int selection;
+
+} RandMapInt;
+
+
+/// A random weighting map for pointer selections
+///
+/// See rand_map_ptr() for details.
+
+typedef struct {
+
+    /// The relative weight of this selection
+    ///
+    /// The final weight of the map array \e must be 0 to terminate the map.
+    unsigned weight;
+
+    /// The selection
+    void *selection;
+
+} RandMapPtr;
+
+
+int
+_rand_map_int(uint32_t *seed, RandMapInt *map, int *index);
+
+int
+rand_map_int(RandMapInt *map);
+
+void *
+_rand_map_ptr(uint32_t *seed, RandMapPtr *map, int *index);
+
+void *
+rand_map_ptr(RandMapPtr *map);
+
+
+#endif	/* __RAND_H__ */
diff --git a/src/lib/common/rand32.c b/src/lib/common/rand32.c
new file mode 100644
index 0000000..c75fc76
--- /dev/null
+++ b/src/lib/common/rand32.c
@@ -0,0 +1,384 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/rand32.c $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file rand32.c
+/// \brief 32-bit unsigned pseudo-random number generation
+
+#include "rand.h"
+
+/// The default seed for rand32()
+
+uint32_t _seed32 = 405405405;
+
+
+/// Generate a random 32-bit unsigned integer from an explicit seed
+///
+/// \param seed A pointer to the random seed (updated by this routine).
+///
+/// \param limit The (exclusive) upper bound of the range of generated random
+/// integers.  The (inclusive) lower bound is always 0.
+///
+/// \retval A pseudo-random unsigned 32-bit integer uniformly selected from
+/// the range 0 to \a limit - 1 (inclusive). However if the \a limit parameter
+/// is \c RAND32_ALL (0), then the return value is a full 32-bit random bit
+/// vector. 
+///
+/// This is a 32-bit linear congruential generator, taken from the 'ranqd1'
+/// generator from "Numerical Recipes in C".  The authors' only praise for
+/// this generator is that it is "\e very fast"; the quality of random numbers
+/// is deemed "entirely adequate for many uses".
+///
+/// The initial 32 pseudo-random result is treated as a 32-bit binary fraction
+/// that is multipled by the limit to yield the final random 32-bit
+/// integer. If the limit is 0, then the full 32-bit result is returned. As
+/// with all LCG, do not count on the low-order bits to be particularly
+/// random.
+
+uint32_t
+_rand32(uint32_t *seed, uint32_t limit)
+{
+    uint64_t x;
+
+    *seed = (*seed * 1664525) + 1013904223;
+    if (limit == RAND32_ALL) {
+	return *seed;
+    } else {
+	x = (uint64_t)(*seed) * limit;
+	return x >> 32;
+    }
+}
+
+
+/// Generate a random 32-bit unsigned integer from a system-wide seed
+///
+/// \param limit The (exclusive) upper bound of the range of generated random
+/// integers. The (inclusive) lower bound is always 0.
+///
+/// \retval A pseudo-random unsigned 32-bit integer uniformly selected from
+/// the range 0 to \a limit - 1 (inclusive). However if the \a limit parameter
+/// is \c RAND32_ALL (0), then the return value is a full 32-bit random bit
+/// vector. 
+///
+/// rand32() is not thread safe.  There is a small possibility that multiple
+/// threads may observe the same random numbers, and it is also possible that
+/// the random sequence may appear to repeat due to thread interactions.  If
+/// these are concerns then the application should either call rand32() from
+/// within a critical section, or provide a unique seed to each thread or
+/// process and use the underlying _rand32() API explicitly.
+
+uint32_t
+rand32(uint32_t limit)
+{
+    return _rand32(&_seed32, limit);
+}
+
+
+/// Set the global random seed for rand32()
+
+void
+srand32(uint32_t seed)
+{
+    _seed32 = seed;
+}
+
+
+/// Select an integer from a weighted distribution using a specific seed
+///
+/// \param seed A 32-bit unsigned random seed (accumulator)
+///
+/// \param map An array of RandMapInt structures, the final element of which
+/// must have the \a weight field = 0.  This array will typically be allocated
+/// statically. 
+///
+/// \param index An optional pointer to an integer which will recieve the
+/// index of the item selected.  NULL \a index are ignored. This is provided
+/// for appplications that require statistics on selections.
+///
+/// \retval One of the \a selection from the array with a non-0 \a weight.  If
+/// the weight array is NULL (= {{0, \<dont care\>}}), then by convention the
+/// return value is 0, and the return index is -1.
+///
+/// This routine selects items from the \a map randomly, given the weighting
+/// implied by (map[i].weight / SUM(i = 0,...,N, map[i].weight)).  For
+/// example, the following two maps are equivalent in that they select 'a' and
+/// 'c' with 25% probability, and 'b' with 50% probability:
+///
+/// RandMapInt map0[] = {{1, 'a'}, {2, 'b'}, {1, 'c'}, {0, 0}};
+///
+/// RandMapInt map1[] = {{25, 'a'}, {50, 'b'}, {25, 'c'}, {0, 0}};
+///
+/// Note that several errors including negative weights, or the overflow of
+/// the sum of weights as an \a unsigned number are neither detected nor
+/// reported.
+///
+/// \todo We could probably merge the code for the integer and pointer versions
+/// somewhat.  This is a great example of where C++ would be nice, as we could
+/// easily cache the sum of weights when the map was constructed.
+
+int
+_rand_map_int(uint32_t *seed, RandMapInt *map, int *index)
+{
+    unsigned weight, sum;
+    RandMapInt *p;
+    uint32_t rand;
+    int i = -1;
+    int selection = 0;
+
+    sum = 0;
+    p = map;
+    while (p->weight != 0) {
+	sum += p->weight;
+	p++;
+    }
+
+    if (sum != 0) {
+
+	rand = _rand32(seed, sum);
+
+	weight = 0;
+	p = map;
+	i = 0;
+	while (p->weight != 0) {
+	    weight += p->weight;
+	    if (rand < weight) {
+		selection = p->selection;
+		break;
+	    }
+	    p++;
+	    i++;
+	}
+    }
+
+    if (index != 0) {
+	*index = i;
+    }
+
+    return selection;
+}
+
+    
+/// Select an integer from a weighted distribution using the system-side seed
+/// \a _seed32
+///
+/// See _rand_map_int() for documentation
+
+int
+rand_map_int(RandMapInt *map)
+{
+    return _rand_map_int(&_seed32, map, 0);
+}
+
+
+/// Select a pointer from a weighted distribution using a specific seed
+///
+/// \param seed A 32-bit unsigned random seed (accumulator)
+///
+/// \param map An array of RandMapPtr structures, the final element of which
+/// must have the \a weight field = 0.  This array will typically be allocated
+/// statically. 
+///
+/// \param index An optional pointer to an integer which will recieve the
+/// index of the item selected.  NULL \a index are ignored. This is provided
+/// for appplications that require statistics on selections.
+///
+/// \retval One of the \a selection from the array with a non-0 \a weight.  If
+/// the weight array is NULL (= {{0, \<dont care\>}}), then by convention the
+/// return value is 0, and the return index is -1;
+///
+/// This routine selects items from the \a map randomly, given the weighting
+/// implied by (map[i].weight / SUM(i = 0,...,N, map[i].weight)).  For
+/// example, the following two maps are equivalent in that they select &a and
+/// &c with 25% probability, and &b with 50% probability:
+///
+/// RandMapPtr map0[] = {{1, &a}, {2, &b}, {1, &c}, {0, 0}};
+///
+/// RandMapPtr map1[] = {{25, &a}, {50, &b}, {25, &c}, {0, 0}};
+///
+/// Note that several errors including negative weights, or the overflow of
+/// the sum of weights as an \a unsigned number are neither detected nor
+/// reported.
+
+
+void *
+_rand_map_ptr(uint32_t *seed, RandMapPtr *map, int *index)
+{
+    unsigned weight, sum;
+    RandMapPtr *p;
+    uint32_t rand;
+    int i = -1;
+    void *selection = 0;
+
+    sum = 0;
+    p = map;
+    while (p->weight != 0) {
+	sum += p->weight;
+	p++;
+    }
+
+    if (sum != 0) {
+
+	rand = _rand32(seed, sum);
+
+	weight = 0;
+	p = map;
+	i = 0;
+	while (p->weight != 0) {
+	    weight += p->weight;
+	    if (rand < weight) {
+		selection = p->selection;
+		break;
+	    }
+	    p++;
+	    i++;
+	}
+    }
+    
+    if (index != 0) {
+	*index = i;
+    }
+
+    return selection;
+}
+
+    
+/// Select a pointer from a weighted distribution using the system-side seed
+/// \a _seed32
+///
+/// See _rand_map_ptr() for documentation
+
+void *
+rand_map_ptr(RandMapPtr *map)
+{
+    return _rand_map_ptr(&_seed32, map, 0);
+}
+
+
+////////////////////////////////////////////////////////////////////////////
+
+#ifdef __TEST_RAND_C__
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#ifdef RANDOM_MAP
+
+// Weighted distribution testing
+
+int a, b, c;
+int aa, bb, cc;
+
+int x[3];
+
+RandMapPtr map0[] = {{1, &a}, {2, &b}, {1, &c}, {0, 0}};
+RandMapPtr map1[] = {{25, &aa}, {50, &bb}, {25, &cc}, {0, 0}};
+
+RandMapInt map2[] = {{25, 0}, {50, 1}, {25, 2}, {0, 0}};
+
+int
+main()
+{
+    int i, j;
+    int *p;
+
+    for (i = 0; i < 1000000; i++) {
+	p = (int *)(rand_map_ptr(map0));
+	*p = *p + 1;
+	p = (int *)(rand_map_ptr(map1));
+	*p = *p + 1;
+	j = rand_map_int(map2);
+	x[j]++;
+    }
+    
+    printf("%d %d %d\n", a, b, c);
+    printf("%d %d %d\n", aa, bb, cc);
+    printf("%d %d %d\n", x[0], x[1], x[2]);
+
+    return 0;
+}
+
+#endif	/* RANDOM_MAP */
+
+
+#ifdef BASIC_TEST
+
+// Simple self-checking uniform distrubution tests for rand32.
+
+void
+test(int *a, int size, int count, double max_error)
+{
+    int i;
+    double error;
+
+    for (i = 0; i < size; i++) {
+	a[i] = 0;
+    }
+
+    for (i = 0; i < size * count; i++) {
+	a[rand32(size)]++;
+    }
+
+    for (i = 0; i < size; i++) {
+	error = (a[i] / (double)count) - 1.0;
+	printf("a[%4d] : %10d %.5f\n", i, a[i], error);
+	if (abs(error) > max_error) {
+	    printf("Too much error\n");
+	    exit(1);
+	}
+    }
+}
+    
+#define MAX_SIZE 128
+
+int
+main()
+{
+    int a[MAX_SIZE];
+    int count = 1000000;
+    double max_error = .005;
+    int i;
+
+    for (i = 2; i <= MAX_SIZE; i *= 2) {
+	printf("\nTest %d\n\n", i);
+	test(a, i, count, max_error);
+    }
+
+    srand32(0);
+    for (i = 2; i <= MAX_SIZE; i *= 2) {
+	printf("\nTest %d\n\n", i);
+	test(a, i, count, max_error);
+    }
+
+    srand32(0xdeadbeef);
+    for (i = 2; i <= MAX_SIZE; i *= 2) {
+	printf("\nTest %d\n\n", i);
+	test(a, i, count, max_error);
+    }
+}
+    
+#endif	/* BASIC_TEST */
+
+#endif	/* __TEST_RAND_C__ */
+
diff --git a/src/lib/string.c b/src/lib/common/string.c
index 81d1778..7c82653 100755..100644
--- a/src/lib/string.c
+++ b/src/lib/common/string.c
@@ -1,5 +1,27 @@
-// $Id: string.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/string.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/string.c $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2013
 // *! All Rights Reserved -- Property of IBM
@@ -9,7 +31,6 @@
 /// \file string.c
 /// \brief strlen(), strcmp() etc. functions
 
-#include "ssx.h"
 #include "string.h"
 
 /// Compute the length of a string
diff --git a/src/ssx/pgp/registers/mcs_register_addresses.h b/src/lib/common/string.h
index 197ecfb..5cfa470 100755..100644
--- a/src/ssx/pgp/registers/mcs_register_addresses.h
+++ b/src/lib/common/string.h
@@ -1,11 +1,11 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/ssx/pgp/registers/mcs_register_addresses.h $              */
+/* $Source: src/lib/common/string.h $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,57 +22,67 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-#ifndef __MCS_REGISTER_ADDRESSES_H__
-#define __MCS_REGISTER_ADDRESSES_H__
+#ifndef __STRING_H__
+#define __STRING_H__
 
-// $Id: mcs_register_addresses.h,v 1.4 2015/01/27 17:56:30 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_register_addresses.h,v $
+// $Id: string.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/string.h,v $
 //-----------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2013
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file mcs_register_addresses.h
-/// \brief Symbolic addresses for the MCS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define MCS0_PIB_BASE 0x02011800
-#define MCS1_PIB_BASE 0x02011880
-#define MCS2_PIB_BASE 0x02011900
-#define MCS3_PIB_BASE 0x02011980
-#define MCS4_PIB_BASE 0x02011C00
-#define MCS5_PIB_BASE 0x02011C80
-#define MCS6_PIB_BASE 0x02011D00
-#define MCS7_PIB_BASE 0x02011D80
-#define MCFGPR_OFFSET 0x00000002
-#define MCS0_MCFGPR 0x02011802
-#define MCS1_MCFGPR 0x02011882
-#define MCS2_MCFGPR 0x02011902
-#define MCS3_MCFGPR 0x02011982
-#define MCS4_MCFGPR 0x02011c02
-#define MCS5_MCFGPR 0x02011c82
-#define MCS6_MCFGPR 0x02011d02
-#define MCS7_MCFGPR 0x02011d82
-#define MCSMODE0_OFFSET 0x00000007
-#define MCS0_MCSMODE0 0x02011807
-#define MCS1_MCSMODE0 0x02011887
-#define MCS2_MCSMODE0 0x02011907
-#define MCS3_MCSMODE0 0x02011987
-#define MCS4_MCSMODE0 0x02011c07
-#define MCS5_MCSMODE0 0x02011c87
-#define MCS6_MCSMODE0 0x02011d07
-#define MCS7_MCSMODE0 0x02011d87
-#define MCS0_MCIFIR 0x02011840
-#define MCS1_MCIFIR 0x020118C0
-#define MCS2_MCIFIR 0x02011940
-#define MCS3_MCIFIR 0x020119C0
-#define MCS4_MCIFIR 0x02011C40
-#define MCS5_MCIFIR 0x02011CC0
-#define MCS6_MCIFIR 0x02011D40
-#define MCS7_MCIFIR 0x02011DC0
-
-#endif // __MCS_REGISTER_ADDRESSES_H__
+/// \file string.h
+/// \brief Replacement for <string.h>
+///
+/// The SSX library does not implement the entire <string.h> function.
+/// However the real reason for this header was the finding that under certain
+/// optimization modes, we were geting errors from the default <string.h>
+/// supplied with the MPC environment.  So we created this replacement that
+/// only calls out what is implemented, exactly as it is implemented for SSX.
 
+#ifndef __ASSEMBLER__
+
+#include <stddef.h>
+
+// APIs inmplemented by string.c
+
+size_t 
+strlen(const char *s);
+
+int
+strcmp(const char* s1, const char* s2);
+
+int 
+strncmp(const char* s1, const char* s2, size_t n);
+
+int
+strcasecmp(const char* s1, const char* s2);
+
+int 
+strncasecmp(const char* s1, const char* s2, size_t n);
+
+char *
+strcpy(char *dest, const char *src);
+
+char *
+strncpy(char *dest, const char *src, size_t n);
+
+void *
+memcpy(void *dest, const void *src, size_t n);
+
+void *
+memset(void *s, int c, size_t n);
+
+int
+memcmp(const void* s1, const void* s2, size_t n);
+
+// APIs implemented by strdup.c
+
+char *
+strdup(const char* s);
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __STRING_H__ */
diff --git a/src/lib/common/sync.c b/src/lib/common/sync.c
new file mode 100644
index 0000000..a489be8
--- /dev/null
+++ b/src/lib/common/sync.c
@@ -0,0 +1,294 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/sync.c $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file sync.c
+/// \brief A library of higher-level synchronization primitives based on
+/// low-level kernel services.
+///
+/// The APIs provided here are currently based on kernel services, but the
+/// specifications should allow applications to be ported to other
+/// environments if required.  Note that like  kernel services, data
+/// structures manipulated by this code are protected in KERN_NONCRITICAL
+/// critical sections. 
+
+#include "kernel.h"
+#include "sync.h"
+
+/// Create a Barrier
+///
+/// \param barrier A pointer to an uninitialized or currently unused Barrier
+///
+/// \param count The number of threads required to pend at the barrier before
+/// all threads are released again for execution.  Note that \a count values
+/// of 0 and 1 are treated as equivalent - threads will not pend at all in
+/// these cases.  Also note that if a watchdog thread is being used, the
+/// watchdog thread should not be included in the count.
+///
+/// \retval 0 Success
+///
+/// \retval -SYNC_INVALID_OBJECT The \a barrier is NULL (0)
+
+int
+barrier_create(Barrier *barrier, KERN_SEMAPHORE_COUNT count)
+{
+    if (KERN_ERROR_CHECK_API) {
+	KERN_ERROR_IF(barrier == 0, SYNC_INVALID_OBJECT);
+    }
+
+    barrier->entry_sem = &(barrier->sem[0]);
+    barrier->exit_sem = &(barrier->sem[1]);
+
+    KERN_SEMAPHORE_CREATE((KERN_SEMAPHORE *)(barrier->entry_sem), 0, 0);
+    KERN_SEMAPHORE_CREATE((KERN_SEMAPHORE *)(barrier->exit_sem), 0, 0);
+
+    barrier->entry_count = 0;
+    barrier->exit_count = 0;
+    barrier->target_count = count;
+
+    barrier->watchdog_pending = 0;
+    barrier->watchdog_entries = 0;
+
+    barrier->callback = 0;
+    barrier->arg = 0;
+    barrier->run_callback = 0;
+
+    return 0;
+}
+
+
+/// Install a barrier callback
+///
+/// \param barrier A pointer to an initialized Barrier object
+///
+/// \param callback A function taking a single (void *) argument, to be
+/// executed in the context of the first thread to exit the barrier when the
+/// barrier condition is met.
+///
+/// \param arg The argument of the \a callback.
+///
+/// The Barrier object supports an optional callback function.  The callback
+/// (with the customary single (void *) parameter) is made when the barrier
+/// condition is met, in the thread context of the first (highest priority)
+/// thread to exit the barrier. The callback is made inside the barrier_pend()
+/// call, but outside of a critical section. The specification of the callback
+/// is not part of the barrier_create() call, but is provided later by this
+/// API. Setting a NULL (0) callback disables the callback mechanism.
+///
+/// \retval 0 Success
+///
+/// \retval -SYNC_INVALID_OBJECT The \a barrier is NULL (0)
+
+int
+barrier_callback_set(Barrier *barrier, 
+		     BarrierCallback callback,
+		     void *arg)
+{
+    KERN_MACHINE_CONTEXT ctx;
+
+    if (KERN_ERROR_CHECK_API) {
+	KERN_ERROR_IF(barrier == 0, SYNC_INVALID_OBJECT);
+    }
+
+    KERN_CRITICAL_SECTION_ENTER(KERN_NONCRITICAL, &ctx);
+
+    barrier->callback = callback;
+    barrier->arg = arg;
+
+    KERN_CRITICAL_SECTION_EXIT(&ctx);
+
+    return 0;
+}
+    
+
+static int
+_barrier_pend(Barrier *barrier, int watchdog)
+{
+    KERN_MACHINE_CONTEXT ctx;
+    int rc = 0;
+    KERN_SEMAPHORE *temp_sem;
+    BarrierCallback callback = 0; /* Make GCC Happy */
+    void *arg = 0;		/* Make GCC Happy */
+    int run_callback;
+
+    if (KERN_ERROR_CHECK_API) {
+	KERN_ERROR_IF(barrier == 0, SYNC_INVALID_OBJECT);
+    }
+
+    KERN_CRITICAL_SECTION_ENTER(KERN_NONCRITICAL, &ctx);
+
+    // A normal thread will pend at the entry unless 1) the thread satisfies
+    // the barrier condition, or 2) a watchdog thread is pending here.  A
+    // watchdog thread only pends if no other threads are pending.
+
+    if (watchdog) {
+	barrier->watchdog_entries++;
+    }
+
+    barrier->entry_count++;
+    if (!barrier->watchdog_pending &&
+	((watchdog && (barrier->entry_count == 1)) ||
+	 (!watchdog && (barrier->entry_count < barrier->target_count)))) {
+
+	if (watchdog) {
+	    barrier->watchdog_pending = 1;
+	}
+
+	// The thread must pend here
+
+	rc = KERN_SEMAPHORE_PEND((KERN_SEMAPHORE *)(barrier->entry_sem), 
+				KERN_WAIT_FOREVER);
+	if (rc) {
+	    goto exit_critical;
+	}
+
+    } else {
+
+	// The barrier condition is met - or the watchdog thread is blocked
+	// here.  The entry and exit semaphores and counts are swapped. The
+	// callback is marked to be called.
+
+	// If the barrier is used incorrectly, or threads are deleted without
+	// adjusting the barrier target count then the following condition
+	// could become true, which could lead to bad behavior.
+
+	if (barrier->exit_count != 0) {
+	    KERN_PANIC(SYNC_BARRIER_INVARIANT);
+	}
+
+	barrier->entry_count--;	// Undo preincrement above
+	barrier->watchdog_pending = 0;
+
+	temp_sem = (KERN_SEMAPHORE *)(barrier->exit_sem);
+	barrier->exit_sem = barrier->entry_sem;
+	barrier->entry_sem = temp_sem;
+
+	barrier->exit_count = barrier->entry_count;
+	barrier->entry_count = 0;
+
+	barrier->run_callback = 1;
+    }
+
+    // This thread either continues to run or just woke up after having
+    // blocked at the barrier.  The current thread makes the next thread (if
+    // any) runnable as well.  Normally the current thread will be of a higher
+    // priority than any blocked threads, so no context switch will occur. The
+    // thread that satisfies the barrier condition \e will cause a context
+    // switch here, unless it just happens to be the highest priority thread
+    // in the barrier group.
+
+    if (barrier->exit_count != 0) {
+	barrier->exit_count--;
+	rc = KERN_SEMAPHORE_POST((KERN_SEMAPHORE *)(barrier->exit_sem));
+    }
+    
+exit_critical:
+
+    if (rc) {
+	KERN_CRITICAL_SECTION_EXIT(&ctx);
+	return rc;
+    }
+
+    // In the case of a satisfied barrier condition, the first thread to exit
+    // the critical section will be the higest priority thread blocked at the
+    // barrier.  This thread is tasked with executing the callback, outside of
+    // the critical section.
+
+    run_callback = barrier->run_callback;
+    barrier->run_callback = 0;
+    if (run_callback) {
+	callback = barrier->callback;
+	arg = (void *)(barrier->arg); /* Cast away 'volatile' */
+    }
+
+    KERN_CRITICAL_SECTION_EXIT(&ctx);
+
+    if (run_callback && callback) {
+	callback(arg);
+    }
+
+    return 0;
+}
+
+
+/// Pend at a Barrier
+///
+/// \param barrier An initialized barrier object
+///
+/// A thread will pend at a barrier until \a count number of threads (supplied
+/// in the call of barrier_create()) are pending.  If \a count is 0 or 1, the
+/// API always returns immediately. 
+///
+/// If barrier watchdog thread is being used (correctly), then the watchdog
+/// will cause thread pending on the barrier to be released whenever all
+/// threads in the group are blocked, regardless of whether some of the
+/// group's threads are blocked elesewhere.
+///
+/// \retval 0 Success
+///
+/// \retval -SYNC_INVALID_OBJECT The \a barrier is NULL (0)
+///
+/// Other errors may be returned by the embedded call of ssx_semephore_pend().
+/// In particular this API will fail if called outside of a thread context
+/// since it requires blocking indefinitely on a semaphore.
+///
+/// \bug The semaphore should be able to provide the number of pending threads
+/// - which we should really be using here instead of the barrier counts.  The
+/// current implementation can produce some strange behavior if threads are
+/// deleted.
+
+int
+barrier_pend(Barrier *barrier)
+{
+    return _barrier_pend(barrier, 0);
+}
+
+
+/// Barrier watchdog thread
+///
+/// \param arg A pointer to the Barrier object this thread should manage.
+///
+/// A barrier_watchdog() thread is attached to a Barrier object, and forces
+/// the barrier condition to be met whenever it runs.  This thread is designed
+/// to be mapped at a priority immediately below the priorities of a group of
+/// threads that pend on the barrier.  
+///
+/// In this way, should every thread in the group become blocked, the watchdog
+/// will allow any threads that are blocked on the barrier to run. If all the
+/// threads are blocked elsewhere, then the watchdog blocks on the barrier,
+/// and as soon as any thread pends again at the barrier the thread remains
+/// runnable and the watchdog becomes runnable.
+///
+/// The barrier_watchdog() thread is not required.  Without the watchdog,
+/// otherwise runnable threads in the barrier group will remain blocked on the
+/// barrier as long as any of their cohorts remain blocked elsewhere.
+
+void
+barrier_watchdog(void *arg)
+{
+    do {
+	_barrier_pend((Barrier *)arg, 1);
+    } while (1);
+}
diff --git a/src/lib/common/sync.h b/src/lib/common/sync.h
new file mode 100644
index 0000000..5657c78
--- /dev/null
+++ b/src/lib/common/sync.h
@@ -0,0 +1,167 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/common/sync.h $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SYNC_H__
+#define __SYNC_H__
+
+// $Id$
+
+/// \file sync.h
+/// \brief A library of higher-level synchronization primitives based on
+/// low-level kernel services.
+///
+/// The APIs provided here are currently based on SSX services, but the
+/// specifications should allow applications to be fairly easily ported to
+/// other environments if required.
+///
+/// \todo Consider implementing a subset of the POSIX pthreads standards
+/// instead of these non-standard synchronization primitives. Ideally all
+/// synchronization primitives would be part of the SSX kernel so that they
+/// would correctly handle thread suspension and deletion while pending.
+
+#include "kernel.h"
+
+// Error/panic codes
+
+#define SYNC_INVALID_OBJECT         0x00896201
+#define SYNC_INVALID_ARGUMENT       0x00896202
+#define SYNC_BARRIER_PEND_TIMED_OUT 0x00896203
+#define SYNC_BARRIER_OVERFLOW       0x00896204
+#define SYNC_BARRIER_UNDERFLOW      0x00896205
+#define SYNC_BARRIER_INVARIANT      0x00896206
+#define SYNC_SHARED_UNDERFLOW       0x00896207
+
+////////////////////////////////////////////////////////////////////////////
+// Barrier
+////////////////////////////////////////////////////////////////////////////
+
+typedef void (*BarrierCallback)(void *);
+
+/// A thread barrier object 
+///
+/// A Barrier allows multiple threads to pend until a group of threads are all
+/// pending at the barrier.  Once all threads are pending at the barrier, all
+/// threads are released again for execution.  The barrier guarantees that
+/// once released, lower-priority threads will have the chance to execute
+/// before the barrier condition is satisfied again.  Thus the Barrier can be
+/// used as a form of fair scheduling for a group of threads that execute in a
+/// loop of doing work followed by pending at the barrier.
+///
+/// Although the barrier guarantees fairness, it can not by itself guarantee
+/// progress. If several threads in a barrier group are
+/// pending at the barrier while other threads in the group are blocked away
+/// from the barrier, the threads at the barrier should be running (if allowed
+/// by the priority mappings etc.).  The only way to guarantee constant
+/// progress by any unblocked thread in a group is to created another,
+/// 'watchdog' thread that has lower priority than the other threads in the
+/// group.  The watchdog thread only executes when all threads in the group
+/// are blocked, and ensures progress.  This implementation provides a
+/// watchdog thread routine as barrier_watchdog().
+///
+/// Normally the threads in a barrier group will be assigned consecutive
+/// priorities - otherwise various forms of priority inversion can arise.  The
+/// watchdog thread, if any, will normally be assigned the priority
+/// immediately lower than the lowest priority thread in the group.
+///
+/// The Barrier object supports an optional callback function.  The callback
+/// (with the customary single (void *) parameter) is made when the barrier
+/// condition is met, in the thread context of the first (highest priority)
+/// thread to exit the barrier. The callback is made inside the barrier_pend()
+/// call, but outside of a critical section. The specification of the callback
+/// is not part of the barrier_create() call, but is provided later by the
+/// barrier_callback_set() call. A NULL (0) callback (the default) is ignored.
+///
+/// NB: All barrier APIs (other than barrier_create()) must be made from
+/// thread mode - they will fail if called from interrupt handlers or before
+/// threads have started.
+
+typedef struct Barrier {
+
+    /// Semaphore array; see \a entry_sem and \a exit_sem;
+    KERN_SEMAPHORE sem[2];
+
+    /// The entry semaphore.
+    ///
+    /// Threads pending at the barrier initially block here.  Once all of the
+    /// threads in the group are pending here, the entry and exit semaphores
+    /// are swapped and threads are released (in priority order) from the new
+    /// exit semaphore.
+    volatile KERN_SEMAPHORE *entry_sem;
+
+    /// The exit semaphore.
+    volatile KERN_SEMAPHORE *exit_sem;
+
+    /// The current count of threads pending at \a entry_sem.
+    volatile KERN_SEMAPHORE_COUNT entry_count;
+
+    /// The current count of threads pending at \a exit_sem.
+    volatile KERN_SEMAPHORE_COUNT exit_count;
+
+    /// The target number of threads required to release the barrier
+    volatile KERN_SEMAPHORE_COUNT target_count;
+
+    /// A flag - Is the watchdog thread pending at the barrier?
+    volatile int watchdog_pending;
+
+    /// Statistics - The number of times the watchdog has entered the barrier.
+    volatile uint32_t watchdog_entries;
+    
+    /// The barrier condition callback function 
+    volatile BarrierCallback callback;
+
+    /// The argument of the callback function
+    volatile void *arg;
+
+    /// This flag is set to tell the first thread to exit the barrier to
+    /// execute the callback (if any).
+    volatile int run_callback;
+
+} Barrier;
+
+int
+barrier_create(Barrier *barrier, KERN_SEMAPHORE_COUNT count);
+
+int
+barrier_callback_set(Barrier *barrier, 
+		     BarrierCallback callback,
+		     void *arg);
+
+int
+barrier_pend(Barrier *barrier);
+
+void
+barrier_watchdog(void *arg);
+
+
+#endif // __SYNC_H__
+
+
+
+
+
+
+
+
+    
+ 
diff --git a/src/lib/ctype.c b/src/lib/ctype.c
deleted file mode 100755
index 5b10635..0000000
--- a/src/lib/ctype.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// $Id: ctype.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/ctype.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file ctype.c
-/// \brief Replacement for <ctype.h> functions
-///
-/// This file contains entry point equivalents for the "ctype.h" macros.
-/// These would only ever be used by assembler programs, therefore it's likely
-/// that the object file will never be linked into an image.
-
-#define __CTYPE_C__
-#include "ctype.h"
-#undef  __CTYPE_C__
-
-
-
-
diff --git a/src/lib/errno.h b/src/lib/errno.h
deleted file mode 100755
index a45bb84..0000000
--- a/src/lib/errno.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ERRNO_H__
-#define __ERRNO_H__
-
-// $Id: errno.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/errno.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file errno.h
-/// \brief Replacement for <errno.h>
-///
-/// SSX does not support a per-thread or global 'errno'.  The standard Unix
-/// errno values returned by library functions are defined here. The prefix
-/// code is the 'telephone code' for "errn".
-
-#define EINVAL 0x00377601
-#define EBADF  0x00377602
-#define EAGAIN 0x00377603
-#define ENXIO  0x00377604
-#define ENOMEM 0x00377605
-
-#endif  /* __ERRNO_H__ */
diff --git a/src/lib/gpe.h b/src/lib/gpe.h
deleted file mode 100755
index e759c7d..0000000
--- a/src/lib/gpe.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef __GPE_H__
-#define __GPE_H__
-
-// $Id: gpe.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe.h
-/// \brief Useful PGAS macros for PORE-GPE procedures
-
-#include "pgas.h"
-
-#ifdef __ASSEMBLER__
-#ifdef __PGAS__
-
-// Required to guarantee that the .purgem below always works.  .purgem on
-// undefined macros causes an error; There appears to be no way to determine
-// if a macro is defined.
-#include "ppc32_asm.h"
-
-
-         // All GPE code should be assembled in the .text.pore section, and
-         // all GPE data should be assembled in the .data.pore section.
-
-        .macro  .text.pore
-        .section .text.pore, "ax", @progbits
-        .balign 4
-        .endm
-
-
-        .macro  .data.pore
-        .section .data.pore, "a", @progbits
-        .balign 8
-        .endm    
-
-        .purgem .function
-        .macro  .function symbol
-        .text.pore
-        .align  2
-        .endm
-
-        .purgem .global_function
-        .macro  .global_function symbol
-        .text.pore
-        .align  2
-        .global \symbol
-        .endm
-
-
-        // Get the CFAM Id right-justified in a Dx register, scratching a Px
-        // register in the process.
-
-        .macro  cfam_id, Dx:req, Px:req
-        ..data  (\Dx)
-        ..pervasive_chiplet_id (\Px)
-        lpcs    (\Px), 0x000f000f
-        ldandi  (\Dx), 0x000f000f, (\Px), 0xffffffff00000000
-        rols    (\Dx), (\Dx), 32
-        .endm
-
-
-        // This macro defines structure offsets for PORE assembler-versions of
-        // structures.
-
-        .macro  .gpeStructField, field:req, size=8
-\field\():
-        .struct \field + (\size)
-        .endm
-
-
-#endif  // __PGAS__ 
-#endif  // __ASSEMBLER__
-
-#endif  // __GPE_H__ 
diff --git a/src/lib/gpe_control.h b/src/lib/gpe_control.h
deleted file mode 100755
index 355330f..0000000
--- a/src/lib/gpe_control.h
+++ /dev/null
@@ -1,171 +0,0 @@
-#ifndef __GPE_CONTROL_H__
-#define __GPE_CONTROL_H__
-
-// $Id: gpe_control.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_control.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe_control.h
-/// \brief GPE procedures for control
-
-#include "pstates.h"
-#include "pgp_config.h"
-
-////////////////////////////////////////////////////////////////////////////
-// PcbsPstateRegs
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// Per-core Pstate control registers
-///
-/// Firmware maintains a vector of PcbsPstateRegs structures - one for
-/// each core on the chip - and updates the register fields in place.  The GPE
-/// procedure gpe_set_pstates() is run periodically to update the core
-/// chiplets from this data structure.  The array can (should) be cleared
-/// initially.
-
-typedef struct {
-
-    /// The clipping register
-    pcbs_power_management_bounds_reg_t pmbr;
-
-    /// The idle control register
-    pcbs_power_management_idle_control_reg_t pmicr;
-
-    /// The Pstate control register
-    pcbs_power_management_control_reg_t pmcr;
-
-} PcbsPstateRegs;
-
-#endif  /* __ASSEMBLER__ */
-
-//  Offsets into PcbsPstateRegs
-
-#define PCBSPSTATEREGS_PMBR  0x00  
-#define PCBSPSTATEREGS_PMICR 0x08 
-#define PCBSPSTATEREGS_PMCR  0x10 
-
-#define SIZEOF_PCBSPSTATEREGS 0x18
-
-
-#ifndef __ASSEMBLER__
-
-/// Set a chiplet Pmax clipping Pstate
-static inline void
-set_chiplet_pmax(PcbsPstateRegs *regs, int chiplet, Pstate pmax)
-{
-    regs[chiplet].pmbr.fields.pmax_clip = pmax;
-}
-
-/// Set a chiplet Pmin clipping Pstate
-static inline void
-set_chiplet_pmin(PcbsPstateRegs *regs, int chiplet, Pstate pmin)
-{
-    regs[chiplet].pmbr.fields.pmin_clip = pmin;
-}
-
-/// Set chiplet Global and Local Pstate requests
-static inline void
-set_chiplet_pstate(PcbsPstateRegs *regs, int chiplet, 
-                   Pstate global, Pstate local)
-{
-    regs[chiplet].pmcr.fields.global_pstate_req = global;
-    regs[chiplet].pmcr.fields.local_pstate_req = local;
-}
-
-/// Enable/Disable/Configure chiplet Nap Pstates
-static inline void
-set_chiplet_nap_pstate(PcbsPstateRegs *regs, int chiplet,
-                       Pstate pstate, int enable, int global, int latency)
-{
-    regs[chiplet].pmicr.fields.nap_pstate_req = pstate;
-    regs[chiplet].pmicr.fields.nap_pstate_en  = (enable != 0);
-    regs[chiplet].pmicr.fields.nap_global_en  = (global != 0);
-    regs[chiplet].pmicr.fields.nap_latency    = latency;
-}
-
-/// Enable/Disable/Configure chiplet Sleep Pstates
-static inline void
-set_chiplet_sleep_pstate(PcbsPstateRegs *regs, int chiplet,
-                         Pstate pstate, int enable, int global, int latency)
-{
-    regs[chiplet].pmicr.fields.sleep_pstate_req = pstate;
-    regs[chiplet].pmicr.fields.sleep_pstate_en  = (enable != 0);
-    regs[chiplet].pmicr.fields.sleep_global_en  = (global != 0);
-    regs[chiplet].pmicr.fields.sleep_latency    = latency;
-}
-
-/// Enable/Disable/Configure chiplet Winkle Pstates
-static inline void
-set_chiplet_winkle_pstate(PcbsPstateRegs *regs, int chiplet,
-                          Pstate pstate, int enable, int global, int latency)
-{
-    regs[chiplet].pmicr.fields.winkle_pstate_req = pstate;
-    regs[chiplet].pmicr.fields.winkle_pstate_en  = (enable != 0);
-    regs[chiplet].pmicr.fields.winkle_global_en  = (global != 0);
-    regs[chiplet].pmicr.fields.winkle_latency    = latency;
-}
-
-#endif /* __ASSEMBLER__ */
-
-/// \bug These need to be defined and documented
-
-#define SLEEP_LATENCY_DISABLED    0
-#define SLEEP_LATENCY_CLOCKS_OFF  1
-#define SLEEP_LATENCY_FAST        2
-#define SLEEP_LATENCY_DEEP        3
-
-#define WINKLE_LATENCY_DISABLED    0
-#define WINKLE_LATENCY_CLOCKS_OFF  1
-#define WINKLE_LATENCY_FAST        2
-#define WINKLE_LATENCY_DEEP        3
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_set_pstates()
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-///  Parameters for the GPE procedure gpe_set_pstates()
-
-typedef struct {
-
-    // The chip configuration (for actuation purposes).  Only those core
-    // chiplets with bits set in the mask will be actuated.
-    ChipConfig config;
-
-    /// This mask, comprised of a logical OR of the GPE_SET_PSTATE_*
-    /// macros, controls which register(s) is(are) actuated for each core.
-    uint64_t select;
-
-    /// The 32-bit pointer to the array of PcbsPstateRegs holding the register
-    /// data, coerced to a 64-bit unsigned.  The real 32-bit pointer must be
-    /// the low-order 32 bits of this value.
-    uint64_t regs;
-
-} GpeSetPstatesParms;
-
-PoreEntryPoint gpe_set_pstates;
-
-#endif /* __ASSEMBLER__ */
-
-// Parameter offsets for gpe_set_pstates()
-
-#define GPESETPSTATESPARMS_CONFIG                    0x00
-#define GPESETPSTATESPARMS_SELECT                    0x08
-#define GPESETPSTATESPARMS_REGS                      0x10
-
-// Register/Function select masks for gpe_set_pstates()
-
-#define GPE_SET_PSTATES_PMBR  0x01
-#define GPE_SET_PSTATES_PMICR 0x02
-#define GPE_SET_PSTATES_PMCR  0x04
-#define GPE_SET_PSTATES_SYNC  0x08
-
-#endif  /* __GPE_CONTROL_H__ */
diff --git a/src/lib/gpe_control.pS b/src/lib/gpe_control.pS
deleted file mode 100755
index 3f3c790..0000000
--- a/src/lib/gpe_control.pS
+++ /dev/null
@@ -1,160 +0,0 @@
-// $Id: gpe_control.pS,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_control.pS,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-        
-/// \file gpe_control.S
-/// \brief GPE procedures for control
-
-        .nolist
-
-#include "ssx.h"
-#include "pgas.h"
-#include "gpe.h"
-#include "gpe_control.h"
-
-        .list
-
-        .oci
-        .text.pore
-
-/// \fn gpe_set_pstates(GpeSetPstatesParms *parms)
-/// \brief Set core chiplet Pstate registers
-///
-/// This routine loops through an array of PcbsPstateRegs structures
-/// holding the register images to be actuated.  A pointer to the array is
-/// provided as the \a registers parameter. For every core chiplet
-/// appearing in the \a cfg parameter, those registers marked in the \a select
-/// parameter are updated.
-///  
-/// When the PMBR is being updated, an option is provided to
-/// set PCBS_PCBSPM_MODE_REG[enable_pmax_sync_interrupt] around the
-/// update of PMBR.  This will cause a SYNC interrupt from each
-/// core. This mode currently does not set up the sync protocol in the PMC -
-/// the caller must do that.
-///
-/// Note that actuating the PMCR and PMICR using this method requires that the
-/// PCB Slave bit PMGP0_REG.pm_spr_override_en is set.
-#ifdef DOXYGEN_ONLY
-void gpe_set_pstates(GpeSetPstatesParms *parms);
-#endif
-/// \cond
-        
-        // Register usage:
-        //
-        // A1 :  Holds the (constant) pointer to the paramaters
-        // A0 :  Holds the (varying) pointer to the next register block
-        // D1 :  Holds the (varying) ChipConfig mask
-        // D0 :  Scratch
-        // P0 :  Holds the (varying) chiplet id
-
-        .global gpe_set_pstates
-
-gpe_set_pstates:
-                
-        // Set up registers.  The chiplet part of the ChipConfig is left
-        // justified in D1, which will be rotated on each loop.
-        
-        mr      A1, ETR
-        ld      D0, GPESETPSTATESPARMS_REGS, A1
-        mr      A0, D0
-        ld      D0, GPESETPSTATESPARMS_CONFIG, A1
-        mr      D1, D0
-        left_justify_core_config D1
-        lpcs    P0, 0x10000000  # Load P0 with core chiplet 0 address
-        ls      CTR, PGP_NCORES
-        bra     start_loop
-
-set_pstates_loop:
-        // If the chiplet is not configured, simply continue
-        
-        andi    D0, D1, 0x8000000000000000
-        braz    D0, set_pstates_continue
-
-        // Test/actuate each register in order
-
-        ldandi  D0, GPESETPSTATESPARMS_SELECT, A1, GPE_SET_PSTATES_PMBR
-        braz    D0, pmicr
-
-        // PMBR.  
-        
-        // If SYNCing, the register write is wrapped by a read-modify-write of
-        // the PCBS_PCBSPM_MODE_REG which enables the PMAX Sync
-        // acknowledge. Note that the original PCBSPM mode reg is saved and
-        // restored.
-pmbr:   
-        ldandi  D0, GPESETPSTATESPARMS_SELECT, A1, GPE_SET_PSTATES_SYNC
-        braz    D0, nosync
-
-sync:
-        ld      D0, PCBS_PCBSPM_MODE_REG, P0
-        la      A1, gsp_pcbs_pcbspm_mode_reg
-        std     D0, 0, A1
-        ori     D0, D0, PCBS_PCBSPM_MODE_REG_ENABLE_PMC_PMAX_SYNC_NOTIFICATION
-        std     D0, PCBS_PCBSPM_MODE_REG, P0
-
-        ld      D0, PCBSPSTATEREGS_PMBR, A0
-        std     D0, PCBS_POWER_MANAGEMENT_BOUNDS_REG, P0
-
-        ld      D0, 0, A1
-        std     D0, PCBS_PCBSPM_MODE_REG, P0
-        // restore A1
-        mr      A1, ETR
-        bra     pmicr   
-
-nosync: 
-        ld      D0, PCBSPSTATEREGS_PMBR, A0
-        std     D0, PCBS_POWER_MANAGEMENT_BOUNDS_REG, P0
-
-        // PMICR
-pmicr:
-        ldandi  D0, GPESETPSTATESPARMS_SELECT, A1, GPE_SET_PSTATES_PMICR
-        braz    D0, pmcr
-        ld      D0, PCBSPSTATEREGS_PMICR, A0
-        std     D0, PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG, P0
-
-        // PMCR
-pmcr:   
-        ldandi  D0, GPESETPSTATESPARMS_SELECT, A1, GPE_SET_PSTATES_PMCR
-        braz    D0, set_pstates_continue
-        ld      D0, PCBSPSTATEREGS_PMCR, A0
-        std     D0, PCBS_POWER_MANAGEMENT_CONTROL_REG, P0
-
-set_pstates_continue:   
-
-        // Increment the chiplet index and data pointer, then loop or halt. 
-
-        adds    P0, P0, 1
-        adds    A0, A0, SIZEOF_PCBSPSTATEREGS
-        rotldi  D1, D1, 1
-start_loop:             
-        loop    set_pstates_loop
-
-        halt
-
-        .epilogue gpe_set_pstates
-
-/// \endcond
-
-/// Data storage for procedures.
-/// Placing data in the .rodata section to prevent the 405 from stomping them.
-        .section .rodata
-        .balign 8
-/// data for gpe_set_pstates
-
-
-
-
-
-
-
-
-
-/// \cond
-
-gsp_pcbs_pcbspm_mode_reg:
-        .quad   0
-/// \endcond
diff --git a/src/lib/gpe_data.h b/src/lib/gpe_data.h
deleted file mode 100755
index 790d82b..0000000
--- a/src/lib/gpe_data.h
+++ /dev/null
@@ -1,672 +0,0 @@
-#ifndef __GPE_DATA_H__
-#define __GPE_DATA_H__
-
-// $Id: gpe_data.h,v 820.1 2014/08/22 16:33:56 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/fw820/procedures/lib/gpe_data.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe_data.h
-/// \brief Data structures for the GPE programs that collect raw data defined
-/// in gpe_data.S.  The data structure layouts are also documented in the
-/// spreadsheet "Pgp Procedures.ods" in lib/doc.
-///
-/// \todo Add SPURR Fraction update as an option
-
-#include "ssx.h"
-#include "gpe.h"
-#include "pgp_config.h"
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_core_data()
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// Paramaters for gpe_get_core_data() & gpe_get_per_core_data()
-
-typedef struct {
-
-    /// gpe_get_core_data() and gpe_get_per_core_data() only collects data for
-    /// core chiplets configured in this mask.
-    ChipConfig config;
-
-    /// This mask, comprised of a logical OR of the GPE_GET_CORE_DATA_*
-    /// macros, controls which data groups are collected.
-    uint64_t select;
-
-    /// This is the 32-bit pointer (cast to a uint64_t) to the core chiplet
-    /// raw data area to be filled by this invocation of gpe_get_core_data().
-    ///
-    /// For gpe_get_core_data() (used by the lab thread coreData) this is a
-    /// pointer to an array of CoreData structures, with one structure
-    /// allocated for each possible core supported by the architecture.
-    ///
-    /// For gpe_get_per_core_data() (used by OCC FW) this is a pointer to a
-    /// single CoreData structure to be filled in by the routine.
-    uint64_t data;
-
-} GpeGetCoreDataParms;
-
-// Get data for all cores, placing data at an index into 
-// GpeGetCoreDataParms->data pointer, depending on the core which got data.
-PoreEntryPoint gpe_get_core_data;      
-
-// Get data for first core in GpeGetCoreDataParms->config, placing data 
-// directly into GpeGetCoreDataParms->data pointer
-PoreEntryPoint gpe_get_per_core_data;
-
-#endif  /* __ASSEMBLER__ */
-
-// Parameter offsets for gpe_get_core_data()
-
-#define GPEGETCOREDATAPARMS_CONFIG      0x00
-#define GPEGETCOREDATAPARMS_SELECT      0x08
-#define GPEGETCOREDATAPARMS_DATA        0x10
-
-// Data group select masks for gpe_get_core_data()
-
-#define GPE_GET_CORE_DATA_EMPATH            0x0001
-#define GPE_GET_CORE_DATA_MEMORY            0x0002
-#define GPE_GET_CORE_DATA_THROTTLE          0x0004
-#define GPE_GET_CORE_DATA_THREAD            0x0008
-#define GPE_GET_CORE_DATA_DTS_CPM           0x0010
-#define GPE_GET_CORE_DATA_PCB_SLAVE         0x0020
-
-#define GPE_GET_CORE_DATA_ALL 0x003f
-
-// Per-core data area offsets
-
-#define CORE_DATA_EMPATH_BASE 0
-#define CORE_DATA_EMPATH_SIZE 40
-
-#define CORE_DATA_MEMORY_BASE                           \
-    (CORE_DATA_EMPATH_BASE + CORE_DATA_EMPATH_SIZE)
-#define CORE_DATA_MEMORY_SIZE 24
-
-#define CORE_DATA_THROTTLE_BASE \
-    (CORE_DATA_MEMORY_BASE + CORE_DATA_MEMORY_SIZE)
-#define CORE_DATA_THROTTLE_SIZE 24
-
-#define CORE_DATA_THREAD_BASE(t)                                        \
-    (CORE_DATA_THROTTLE_BASE + CORE_DATA_THROTTLE_SIZE + (24 * (t)))
-#define CORE_DATA_THREAD_SIZE (24 * 8)
-
-#define CORE_DATA_DTS_CPM_BASE                          \
-    (CORE_DATA_THREAD_BASE(0) + CORE_DATA_THREAD_SIZE)
-#define CORE_DATA_DTS_CPM_SIZE 40
-
-#define CORE_DATA_PCB_SLAVE_BASE                        \
-    (CORE_DATA_DTS_CPM_BASE + CORE_DATA_DTS_CPM_SIZE)
-#define CORE_DATA_PCB_SLAVE_SIZE 32
-
-#define CORE_DATA_OHA_BASE \
-    (CORE_DATA_PCB_SLAVE_BASE + CORE_DATA_PCB_SLAVE_SIZE)
-#define CORE_DATA_OHA_SIZE 8
-
-#define CORE_DATA_SIZE (CORE_DATA_OHA_BASE + CORE_DATA_OHA_SIZE)
-
-// Data area components.  Each data group is marked with the TOD captured just
-// before each data group capture.  Data groups that may have some relation to
-// frequency are also tagged with the current raw cycles reading.  The offsets
-// are _byte_ offsets into a byte array.  The user needs to be aware of
-// whether each datum represents a 32- or 64-bit integer.
-
-#define CORE_DATA_EMPATH_UNUSED        (CORE_DATA_EMPATH_BASE + 0x00)
-#define CORE_DATA_EMPATH_TOD           (CORE_DATA_EMPATH_BASE + 0x04)
-#define CORE_DATA_DISPATCH             (CORE_DATA_EMPATH_BASE + 0x08)
-#define CORE_DATA_COMPLETION           (CORE_DATA_EMPATH_BASE + 0x0c)
-#define CORE_DATA_FREQ_SENS_BUSY       (CORE_DATA_EMPATH_BASE + 0x10)
-#define CORE_DATA_FREQ_SENS_FINISH     (CORE_DATA_EMPATH_BASE + 0x14)
-#define CORE_DATA_RUN_CYCLES           (CORE_DATA_EMPATH_BASE + 0x18)
-#define CORE_DATA_RAW_CYCLES           (CORE_DATA_EMPATH_BASE + 0x1c)
-#define CORE_DATA_MEM_A                (CORE_DATA_EMPATH_BASE + 0x20)
-#define CORE_DATA_MEM_B                (CORE_DATA_EMPATH_BASE + 0x24)
-
-#define CORE_DATA_MEMORY_RAW_CYCLES    (CORE_DATA_MEMORY_BASE + 0x00)
-#define CORE_DATA_MEMORY_TOD           (CORE_DATA_MEMORY_BASE + 0x04)
-#define CORE_DATA_MEMORY_COUNT(p)      (CORE_DATA_MEMORY_BASE + 0x08 + ((p) * 4))
-
-#define CORE_DATA_THROTTLE_RAW_CYCLES   (CORE_DATA_THROTTLE_BASE + 0x00)
-#define CORE_DATA_THROTTLE_TOD          (CORE_DATA_THROTTLE_BASE + 0x04)
-#define CORE_DATA_THROTTLE_IFU_THROTTLE (CORE_DATA_THROTTLE_BASE + 0x08)
-#define CORE_DATA_THROTTLE_ISU_THROTTLE (CORE_DATA_THROTTLE_BASE + 0x10)
-#define CORE_DATA_THROTTLE_IFU_ACTIVE   (CORE_DATA_THROTTLE_BASE + 0x18)
-
-#define CORE_DATA_THREAD_RAW_CYCLES(t) (CORE_DATA_THREAD_BASE(t) + 0x00)
-#define CORE_DATA_THREAD_TOD(t)        (CORE_DATA_THREAD_BASE(t) + 0x04)
-#define CORE_DATA_THREAD_RUN_CYCLES(t) (CORE_DATA_THREAD_BASE(t) + 0x08)
-#define CORE_DATA_THREAD_COMPLETION(t) (CORE_DATA_THREAD_BASE(t) + 0x0c)
-#define CORE_DATA_THREAD_MEM_A(t)      (CORE_DATA_THREAD_BASE(t) + 0x10)
-#define CORE_DATA_THREAD_MEM_B(t)      (CORE_DATA_THREAD_BASE(t) + 0x14)
-
-#define CORE_DATA_DTS_CPM_UNUSED       (CORE_DATA_DTS_CPM_BASE + 0x00)
-#define CORE_DATA_DTS_CPM_TOD          (CORE_DATA_DTS_CPM_BASE + 0x04)
-#define CORE_DATA_SENSOR_V0            (CORE_DATA_DTS_CPM_BASE + 0x08)
-#define CORE_DATA_SENSOR_V1            (CORE_DATA_DTS_CPM_BASE + 0x10)
-#define CORE_DATA_SENSOR_V8            (CORE_DATA_DTS_CPM_BASE + 0x18)
-#define CORE_DATA_SENSOR_V9            (CORE_DATA_DTS_CPM_BASE + 0x20)
-
-#define CORE_DATA_PCB_SLAVE_UNUSED     (CORE_DATA_PCB_SLAVE_BASE + 0x00)
-#define CORE_DATA_PCB_SLAVE_TOD        (CORE_DATA_PCB_SLAVE_BASE + 0x04)
-#define CORE_DATA_PMCR                 (CORE_DATA_PCB_SLAVE_BASE + 0x08)
-#define CORE_DATA_PMSR                 (CORE_DATA_PCB_SLAVE_BASE + 0x10)
-#define CORE_DATA_PM_HISTORY           (CORE_DATA_PCB_SLAVE_BASE + 0x18)
-
-#define CORE_DATA_OHA_RO_STATUS_REG    (CORE_DATA_OHA_BASE + 0x00)
-
-
-#ifndef __ASSEMBLER__
-
-// The GPE routine requires that the structure of core data collected by
-// gpe_get_core_data() be represented as the offsets defined above.  This set
-// of structures represents the equivalent C-structure form of the data.  Note
-// that the procedure formats the TOD as a 32-bit, 2 MHz timebase.
-
-typedef struct {
-    uint32_t unused;
-    uint32_t tod_2mhz;
-    uint32_t dispatch;
-    uint32_t completion;
-    uint32_t freq_sens_busy;
-    uint32_t freq_sens_finish;
-    uint32_t run_cycles;
-    uint32_t raw_cycles;
-    uint32_t mem_a;
-    uint32_t mem_b;
-} CoreDataEmpath;
-
-typedef struct {
-    uint32_t raw_cycles;
-    uint32_t tod_2mhz;
-    uint32_t count[4];
-} CoreDataPerPartitionMemory;
-
-typedef struct {
-    uint32_t raw_cycles;
-    uint32_t tod_2mhz;
-    uint32_t ifu_throttle;
-    uint32_t isu_throttle;
-    uint32_t ifu_active;
-    uint32_t undefined;
-} CoreDataThrottle;
-
-typedef struct {
-    uint32_t raw_cycles;
-    uint32_t tod_2mhz;
-    uint32_t run_cycles;
-    uint32_t completion;
-    uint32_t mem_a;
-    uint32_t mem_b;
-} CoreDataPerThread;
-
-typedef struct {
-    uint32_t unused;
-    uint32_t tod_2mhz;
-    sensors_v0_t sensors_v0;
-    sensors_v1_t sensors_v1;
-    sensors_v8_t sensors_v8;
-    sensors_v9_t sensors_v9;
-} CoreDataDtsCpm;
-    
-typedef struct {
-    uint32_t unused;
-    uint32_t tod_2mhz;
-    pcbs_power_management_control_reg_t pmcr;
-    pcbs_power_management_status_reg_t pmsr;
-    pcbs_pmstatehistocc_reg_t pm_history;
-} CoreDataPcbSlave;
-
-typedef struct {
-    oha_ro_status_reg_t oha_ro_status_reg;
-} CoreDataOha;
-    
-typedef struct {
-    CoreDataEmpath             empath;
-    CoreDataPerPartitionMemory per_partition_memory;
-    CoreDataThrottle           throttle;
-    CoreDataPerThread          per_thread[8];
-    CoreDataDtsCpm             dts_cpm;
-    CoreDataPcbSlave           pcb_slave;
-    CoreDataOha                oha;
-} CoreData;
-
-#endif // __ASSEMBLER__
-
-
-/// \defgroup core_data_status_bits Core Data Status Bits
-///
-/// These bits are set (if appropriate) in the low-order reserved area of the
-/// OHA_RO_STATUS_REG image stored in the CoreData structure.
-///
-/// @{
-
-/// This bit is set if SCOM access to the OHA returns a non-0 PIB return code
-/// when trying to write the OHA_CPM_HIST_RESET_REG to set up PC-only special
-/// wakeup.
-#define CORE_DATA_CPM_HIST_RESET_ACCESS_FAILED 0x01
-
-/// This bit is set if access to the OHA returns a non-0 PIB return code when
-/// trying to read the OHA_RO_STATUS_REG to determine core status.
-#define CORE_DATA_OHA_RO_STATUS_ACCESS_FAILED 0x02
-
-/// This bit is set if EMPATH data was requested to be collected and was
-/// collected. If this bit is not set then any EMPATH data requested to be
-/// collected will be 0. 
-///
-/// If EMPATH data was requested but was not collected, then one of the bits
-/// CORE_DATA_EXPECTED_EMPATH_ERROR or CORE_DATA_UNEXPECTED_EMPATH_ERROR will
-/// be set, and the error code is stored in the OHA_RO_STATUS register image.
-#define CORE_DATA_EMPATH_COLLECTED 0x04
-
-/// This bit is set if core sensor data (DTS/CPM) was collected. If this bit
-/// is not set then core DTS/CPM data will be 0.
-#define CORE_DATA_CORE_SENSORS_COLLECTED 0x08
-
-/// This bit is set if L3 sensor data (DTS/CPM) was collected. If this bit is
-/// not set then L3 DTS/CPM data will be 0.
-#define CORE_DATA_L3_SENSORS_COLLECTED 0x10
-
-/// If this bit is set, then an "expected" error was encountered while
-/// collecting EMPATH data. Given that the procedure has gone through the
-/// PC-only special wakeup protocol, the only "expected" error is the
-/// intermittant PCB error code #4 due to HW280375.
-#define CORE_DATA_EXPECTED_EMPATH_ERROR 0x20
-
-/// If this bit is set, then an "unexpected" error was encountered while
-/// collecting EMPATH data. Given that the procedure has gone through the
-/// PC-only special wakeup protocol, the only "expected" error is the
-/// intermittant PCB error code #4 due to HW280375. If this bit is set it
-/// indicates a serious problem.
-#define CORE_DATA_UNEXPECTED_EMPATH_ERROR 0x40
-
-/// The first bit of the 4-bit PCB parity + error code, in the event a PCB
-/// error is encountered during EMPATH processing.
-#define CORE_DATA_EMPATH_ERROR_LOCATION 52
-
-#define CORE_DATA_EMPATH_ERROR_BITS 4
-
-/// @}
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_core_data_fast()
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// Paramaters for gpe_get_chip_data_fast()
-
-typedef struct {
-
-    /// gpe_get_core_data_fast() only collects data for chiplets configured in
-    /// this mask.
-    ChipConfig config;
-
-    /// This mask, comprised of a logical OR of the GPE_GET_CORE_DATA_FAST_*
-    /// macros, controls which data groups are collected.
-    uint64_t select;
-
-    /// This is the 32-bit pointer (cast to a uint64_t) to the chiplet raw
-    /// data area to be filled by this invocation of gpe_get_core_data_fast().
-    uint64_t data;
-
-} GpeGetChipDataFastParms;
-
-PoreEntryPoint gpe_get_core_data_fast;
-
-#endif  /* __ASSEMBLER__ */
-
-// Parameter offsets for gpe_get_core_data()
-
-#define GPEGETCOREDATAFASTPARMS_CONFIG  0x00
-#define GPEGETCOREDATAFASTPARMS_SELECT  0x08
-#define GPEGETCOREDATAFASTPARMS_DATA    0x10
-
-// Data group select masks for gpe_get_core_data_fast()
-
-#define GPE_GET_CORE_DATA_FAST_FREQ_TARGET 0x0001
-
-#define CORE_DATA_FAST_FREQ_TARGET_BASE 0x0
-#define CORE_DATA_FAST_FREQ_TARGET_SIZE (8 + (PGP_NCORES * 8))
-
-#define CORE_DATA_FAST_SIZE \
-    (CORE_DATA_FAST_FREQ_TARGET_BASE + CORE_DATA_FAST_FREQ_TARGET_SIZE)
-
-#define CORE_DATA_FAST_FREQ_TARGET_UNUSED    (CORE_DATA_FAST_FREQ_TARGET_BASE + 0)
-#define CORE_DATA_FAST_FREQ_TARGET_TOD       (CORE_DATA_FAST_FREQ_TARGET_BASE + 4)
-#define CORE_DATA_FAST_FREQ_TARGET_LPFTSR(n) (CORE_DATA_FAST_FREQ_TARGET_BASE + 8 + ((n) * 8))
-
-#ifndef __ASSEMBLER__
-
-typedef struct {
-    uint32_t unused;
-    uint32_t tod_2mhz;
-    pcbs_local_pstate_frequency_target_status_reg_t lpftsr[PGP_NCORES];
-} CoreDataFast;
-
-#endif // __ASSEMBLER__
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_chip_data()
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// Paramaters for gpe_get_chip_data()
-
-typedef struct {
-
-    /// This mask, comprised of a logical OR of the GPE_GET_CHIP_DATA_*
-    /// macros, controls which data groups are collected.
-    uint64_t select;
-
-    /// This is the 32-bit pointer (cast to a uint64_t) to the chiplet raw
-    /// data area to be filled by this invocation of gpe_get_chip_data().
-    uint64_t data;
-
-} GpeGetChipDataParms;
-
-PoreEntryPoint gpe_get_chip_data;
-
-#endif  /* __ASSEMBLER__ */
-
-// Parameter offsets for gpe_get_chip_data()
-
-#define GPEGETCHIPDATAPARMS_SELECT 0x00
-#define GPEGETCHIPDATAPARMS_DATA   0x08
-
-// Data group select masks for gpe_get_chip_data()
-
-#define GPE_GET_CHIP_DATA_OVERCOMMIT 0x0001
-
-#define CHIP_DATA_OVERCOMMIT_BASE 0
-#define CHIP_DATA_OVERCOMMIT_SIZE 56
-
-#define CHIP_DATA_SIZE (CHIP_DATA_OVERCOMMIT_BASE + CHIP_DATA_OVERCOMMIT_SIZE)
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_mem_data()
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// Paramaters for gpe_get_mem_data()
-
-typedef struct {
-
-    /// The index (0 .. PGP_NCENTAUR - 1) of the Centaur whose sensor cache
-    /// data to collect, or -1 to bypass collection.
-    uint64_t collect;
-
-    /// The index (0 .. PGP_NCENTAUR - 1) of the Centaur to "poke" to cause it
-    /// to begin collecting the next round of data into its sensor cache, or
-    /// -1 to bypass updating.
-    uint64_t update;
-
-    /// This is the 32-bit pointer (cast to a uint64_t) to the chiplet raw
-    /// data area to be filled by this invocation of gpe_get_mem_data(). This
-    /// pointer need not be valid if the \a collect field of the structure is
-    /// -1.
-    uint64_t data;
-
-    /// The return code returned by the last invocation of the procedure; See
-    /// \ref gpe_get_mem_date_rc.
-    uint64_t rc;
-    
-    /// The 'update' timestamp
-    ///
-    /// This is the value of the chip TOD at the time the 'update' phase of
-    /// the procedure is run, as close as possible to the "poke" of the
-    /// Centaur. This timestamp indicates the time that the Centaur sensor
-    /// cache line collection was kicked off. The timestamp is collected even
-    /// if the \a update field of the structure is -1. Consistent with
-    /// gpe_get_core_data() the timestamp is reduced to a 32-bit, 2MHz
-    /// timestamp, and stored in the low-order half of a doubleword.
-    uint32_t pad;
-    uint32_t tod_2mhz;
-
-} GpeGetMemDataParms;
-
-PoreEntryPoint gpe_get_mem_data;
-
-#endif  /* __ASSEMBLER__ */
-
-// Parameter offsets for gpe_get_mem_data()
-
-#define GPEGETMEMDATAPARMS_COLLECT 0x00
-#define GPEGETMEMDATAPARMS_UPDATE  0x08
-#define GPEGETMEMDATAPARMS_DATA    0x10
-#define GPEGETMEMDATAPARMS_RC      0x18
-#define GPEGETMEMDATAPARMS_PAD_TOD 0x20
-#define SIZEOF_GPEGETMEMDATAPARMS  0x28
-
-
-/// \defgroup gpe_mem_data_rc gpe_get_mem_data() Error Return Codes
-///
-/// The gpe_get_mem_data() procedure deposits a non-0 return code into the \a
-/// rc field of its parameter structure in the event of failure. Note that the
-/// procedure stops on the first failure, and in particular the TOD timestamp
-/// is not valid in the event of failure.
-///
-/// @{
-
-/// The procedure died, but no other information is available. This would have
-/// signalled an error interrupt and the PORE flex request will contain FFDC
-/// about the failure.
-#define GPE_GET_MEM_DATA_DIED 1
-
-/// The \a collect parameter was invalid, i.e. it either was an illegal index
-/// or the index of an unconfigured MCS or Centaur.
-#define GPE_GET_MEM_DATA_COLLECT_INVALID 2
-
-/// The \a update parameter was invalid, i.e. it either was an illegal index
-/// or the index of an unconfigured MCS or Centaur.
-#define GPE_GET_MEM_DATA_UPDATE_INVALID 3
-
-/// The global G_centaurConfiguration is not valid
-#define GPE_GET_MEM_DATA_NOT_CONFIGURED 4
-
-/// The workaround for HW256773 failed.  To diagnose the failure look at the
-/// 'rc' field of the global variable G_hw256773.
-#define GPE_GET_MEM_DATA_HW256773_FAILED 5
-
-/// This code is established in the RC field prior to collecting the Centaur
-/// sensor cache data. If this RC is observed on a hard failure it most likely
-/// indicates an error assiciated with the Centaur whose data was being
-/// collected.
-#define GPE_GET_MEM_DATA_SENSOR_CACHE_FAILED 6
-
-/// This code is established in the RC field prior to "poking" the Centaur (if
-/// any) that is being updated this pass. If this RC is observed on a hard
-/// failure it most likely indicates an error associated with the Centaur
-/// being updated.
-#define GPE_GET_MEM_DATA_UPDATE_FAILED 7
-
-/// @}        
-
-
-#ifndef __ASSEMBLER__
-
-// The GPE routine requires that the structure of centaur data collected by
-// gpe_get_mem_data() be represented as the offsets defined above.  This set
-// of structures represent the equivalent C-structure form of the data.  Note
-// that the procedure formats the TOD as a 32-bit, 2 MHz timebase.
-
-/// Layout of data collected from MCS
-///
-/// This is currently empty, however to avoid code rewrites if any data is
-/// ever collected here the structure is declared and placed in the larger
-/// MemData structure.  The fact that the structure is empty does not seem to
-/// cause problems. 
-
-typedef struct {
-} MemDataMcs;
-
-/// The layout of a Centaur chip thermal sensor
-///
-/// \todo Centaur spec. has no doc. on layout of these bits; Waiting for more
-/// info from Centaur team.
-
-typedef union {
-    uint16_t value;
-    struct {
-        uint16_t value;
-    } fields;
-} centaur_sensor_t;
-
-/// The layout of a Centaur DIMM sensor
-///
-/// Mnemonic macros for the 2-bit status codes (DIMM_SENSOR_STATUS_*) are
-/// currently defined in ssx/pgp/pgp_common.h
-///
-/// \todo Waiting for more info from Centaur team on how to interpret
-
-typedef union {
-    uint16_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint16_t crit_trip : 1;
-    uint16_t alarm_trip : 1;
-    uint16_t below_trip : 1;
-    uint16_t sign_bit : 1;
-    uint16_t temperature : 8;
-    uint16_t temp_fraction : 2;
-    uint16_t status : 2;
-#else
-    uint16_t status : 2;
-    uint16_t temp_fraction : 2;
-    uint16_t temperature : 8;
-    uint16_t sign_bit : 1;
-    uint16_t below_trip : 1;
-    uint16_t alarm_trip : 1;
-    uint16_t crit_trip : 1;
-#endif
-    } fields;
-} centaur_dimm_sensor_t;
-
-/// The layout of the status bits of the sensor cache line
-///
-/// The sensor cache-line aggregator gets each element of the sensor cache
-/// line by an internal SCOM.  The individual PCB return codes for each SCOM
-/// are collected here (3 bits each) - note that many of the 32-bit registers
-/// come back in a single 64-bit internal SCOM. Normally this register will
-/// always read as 0 indicating all data was collected successfully.  The PCB
-/// error codes (PCB_ERROR_*) are currently defined in ssx/pgp/pgp_common.h.
-
-typedef union {
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t mba01_rw : 3;         /// mba01_rd[+ wr]
-        uint64_t mba01_ap : 3;         /// mba01_act[+ powerups]
-        uint64_t mba23_rw : 3;         /// mba23_rd[+ wr]
-        uint64_t mba23_ap : 3;         /// mba23_act[+ powerups]
-        uint64_t mba_sc : 3;           /// mba01[+ 23]_spec_cancels
-        uint64_t lp2_exits : 3;        /// lp2_exits
-        uint64_t frame_count : 3;      /// frame_count
-        uint64_t mba01_chrw : 3;       /// mba01_cache_hits_rd[+ wr]
-        uint64_t mba23_chrw : 3;       /// mba23_cache_hits_rd[+ wr]
-        uint64_t mba01_iac_bl : 3;     /// mba01_intreq_arr_cnt_base[+ low]
-        uint64_t mba01_iac_mh : 3;     /// mba01_intreq_arr_cnt_med[+ high]
-        uint64_t mba23_iac_bl : 3;     /// mba23_intreq_arr_cnt_base[+ low]
-        uint64_t mba23_iac_mh : 3;     /// mba23_intreq_arr_cnt_med[+ high]
-        uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
-        uint64_t centaur01 : 3;        /// centaur_thermal_sensor[0 - 1]
-        uint64_t dimm03 : 3;           /// dimm_thermal_sensor[0 - 3]
-        uint64_t dimm47 : 3;           /// dimm_thermal_sensor[4 - 7]
-        uint64_t reserved : 13;
-#else
-        uint64_t reserved : 13;
-        uint64_t dimm47 : 3;           /// dimm_thermal_sensor[4 - 7]
-        uint64_t dimm03 : 3;           /// dimm_thermal_sensor[0 - 3]
-        uint64_t centaur01 : 3;        /// centaur_thermal_sensor[0 - 1]
-        uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
-        uint64_t mba23_iac_mh : 3;     /// mba23_intreq_arr_cnt_med[+ high]
-        uint64_t mba23_iac_bl : 3;     /// mba23_intreq_arr_cnt_base[+ low]
-        uint64_t mba01_iac_mh : 3;     /// mba01_intreq_arr_cnt_med[+ high]
-        uint64_t mba01_iac_bl : 3;     /// mba01_intreq_arr_cnt_base[+ low]
-        uint64_t mba23_chrw : 3;       /// mba23_cache_hits_rd[+ wr]
-        uint64_t mba01_chrw : 3;       /// mba01_cache_hits_rd[+ wr]
-        uint64_t frame_count : 3;      /// frame_count
-        uint64_t lp2_exits : 3;        /// lp2_exits
-        uint64_t mba_sc : 3;           /// mba01[+ 23]_spec_cancels
-        uint64_t mba23_ap : 3;         /// mba23_act[+ powerups]
-        uint64_t mba23_rw : 3;         /// mba23_rd[+ wr]
-        uint64_t mba01_ap : 3;         /// mba01_act[+ powerups]
-        uint64_t mba01_rw : 3;         /// mba01_rd[+ wr]
-#endif
-    } fields;
-} centaur_scom_status_t;
-
-/// The layout of the Centaur sensor cache line
-
-typedef struct {
-    uint32_t mba01_rd;                      // PP1/MBA01 Reads 
-    uint32_t mba01_wr;                      // PP1/MBA01 Writes
-    uint32_t mba01_act;                     // PP1/MBA01 Activations
-    uint32_t mba01_powerups;                // PP1/MBA01 PowerUps
-    
-    uint32_t mba23_rd;                      // PP2/MBA23 Reads 
-    uint32_t mba23_wr;                      // PP2/MBA23 Writes
-    uint32_t mba23_act;                     // PP2/MBA23 Activations
-    uint32_t mba23_powerups;                // PP2/MBA23 PowerUps
-
-    uint32_t mba01_spec_cancels;            // PP1/MBA01 Speculative Cancels
-    uint32_t mba23_spec_cancels;            // PP2/MBA23 Speculative Cancels
-#ifdef _BIG_ENDIAN
-    uint32_t eventn     :4;                 // EVENTN
-    uint32_t reserved_0 :20;                // Reserved
-    uint32_t lp2_exits  :8;                 // LP2 Exits
-#else
-    uint32_t lp2_exits  :8;                 // LP2 Exits
-    uint32_t reserved_0 :20;                // Reserved
-    uint32_t eventn     :4;                 // EVENTN
-#endif
-    uint32_t frame_count;                   // Frame Count (timestamp)
-
-    uint32_t mba01_cache_hits_rd;           // PP1/MBA01 Cache Hits Reads
-    uint32_t mba01_cache_hits_wr;           // PP1/MBA01 Cache Hits Writes
-    uint32_t mba23_cache_hits_rd;           // PP2/MBA23 Cache Hits Reads
-    uint32_t mba23_cache_hits_wr;           // PP2/MBA23 Cache Hits Writes
-    
-    uint32_t mba01_intreq_arr_cnt_base;     // PP1/MBA01 Inter-Req Arrival Count Base
-    uint32_t mba01_intreq_arr_cnt_low;      // PP1/MBA01 Inter-Req Arrival Count Low
-    uint32_t mba01_intreq_arr_cnt_med;      // PP1/MBA01 Inter-Req Arrival Count Med 
-    uint32_t mba01_intreq_arr_cnt_high;     // PP1/MBA01 Inter-Req Arrival Count High
-
-    uint32_t mba23_intreq_arr_cnt_base;     // PP2/MBA23 Inter-Req Arrival Count Base
-    uint32_t mba23_intreq_arr_cnt_low;      // PP2/MBA23 Inter-Req Arrival Count Low
-    uint32_t mba23_intreq_arr_cnt_med;      // PP2/MBA23 Inter-Req Arrival Count Med 
-    uint32_t mba23_intreq_arr_cnt_high;     // PP2/MBA23 Inter-Req Arrival Count High
-
-    uint32_t intreq_arr_cnt_high_latency;   // Inter-Req Arrival Count High Latency
-    centaur_sensor_t centaur_thermal_sensor[2];   // Centaur Thermal Sensors 0-1
-    centaur_dimm_sensor_t dimm_thermal_sensor[8]; // DIMM Thermal Sensors 0-7
-    centaur_scom_status_t status;           // Aggregated internal SCOM status
-} MemDataSensorCache;
-
-typedef struct {
-    MemDataMcs         mcs;                 // TODO:  Not collected yet
-    MemDataSensorCache scache;              // OCC Centaur Sensor Cache Line (128 bytes)
-} MemData;
-
-#endif // __ASSEMBLER__
-
-
-// Data offsets for gpe_get_mem_data()
-
-#define MEM_DATA_MCS_BASE 0
-#define MEM_DATA_MCS_SIZE 0
-
-#define MEM_DATA_CENTAUR_BASE (MEM_DATA_MCS_BASE + MEM_DATA_MCS_SIZE)
-#define MEM_DATA_CENTAUR_SIZE 128
-
-#define MEM_DATA_SIZE (MEM_DATA_MCS_SIZE + MEM_DATA_CENTAUR_SIZE)
-
-#endif  /* __GPE_DATA_H__ */
diff --git a/src/lib/gpe_data.pS b/src/lib/gpe_data.pS
deleted file mode 100755
index 2338276..0000000
--- a/src/lib/gpe_data.pS
+++ /dev/null
@@ -1,1585 +0,0 @@
-// $Id: gpe_data.pS,v 820.1 2014/08/22 16:33:56 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/fw820/procedures/lib/gpe_data.pS,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-        
-/// \file gpe_data.S
-/// \brief GPE procedures for raw data collection
-
-        .nolist
-
-#include "ssx.h"
-#include "pgas.h"
-#include "pgp_config.h"
-#include "gpe.h"
-#include "gpe_pba.h"
-#include "gpe_data.h"
-#include "gpe_scom.h"
-
-        .list
-
-        .oci
-        .text.pore
-
-        .revision_string G_gpe_data_pS_revision, "$Revision: 820.1 $"
-
-/// \cond
-
-////////////////////////////////////////////////////////////////////////////
-// Common Macros
-////////////////////////////////////////////////////////////////////////////            
-
-        // Get a full 64-bit SCOM and write to OCI space.  Clobbers a Data
-        // register. 
-
-        .macro get_scom, dx, scom, chiplet_base, oci_offset, oci_base
-
-        ld      (\dx), (\scom), (\chiplet_base)
-        std     (\dx), (\oci_offset), (\oci_base)
-
-        .endm
-
-
-        // Tag a data group with TOD[24..56]. This macro clobbers a data
-        // register. 
-
-        .macro tag_data_group, base, dx, oci_base, tod_chiplet
-
-        ld      (\dx), TOD_VALUE_REG, (\tod_chiplet)
-        extrdi  (\dx), (\dx), 32, 24  
-        std     (\dx), (\base), (\oci_base)
-
-        .endm
-
-
-        // An OCI - OCI copy.  Dx gets clobbered
-
-        .macro  ocicopy, dx, src_offset, src_base, dst_offset, dst_base
-
-        ld      (\dx), (\src_offset), (\src_base)
-        std     (\dx), (\dst_offset), (\dst_base)
-
-        .endm
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_core_data()
-////////////////////////////////////////////////////////////////////////////            
-
-        // Macros for gpe_get_core_data().
-
-        // Tag a core data group with TOD[24..56], and optionally with the raw
-        // cycle count. Always clobbers D0 and D1.  If called with store=0, the
-        // tag ends up in D0.
-
-        .macro tag_core_data_group, base, oci_base, pc_chiplet, tod_chiplet, \
-                raw=1, store=1
-
-        ld      D0, TOD_VALUE_REG, (\tod_chiplet)
-        extrdi  D0, D0, 32, 24
-        .if     (\raw)
-                sti     PC_OCC_SPRC, (\pc_chiplet), SPRN_CORE_RAW_CYCLE
-                ld      D1, PC_OCC_SPRD, (\pc_chiplet)
-                rotldi  D1, D1, 32
-                or      D0, D0, D1
-        .endif
-        .if     (\store)
-                std     D0, (\base), (\oci_base)
-        .endif
-        .endm
-
-
-        // Get a pair of SCOMs from PC, packing them into a single 64-bit value
-        // and writing them to OCI space.  Clobbers D0 and D1.  Assumes that
-        // PC_OCC_SPRC is set up for autoincrement access as well.
-        //
-        // This macro takes advantage of the fact that PC-unit SCOMs only
-        // define the lower 32 bits, and the high-32 are 0.
-
-        .macro  get_pc_pair, offset, oci_base, chiplet_base
-
-        ld      D0, PC_OCC_SPRD, (\chiplet_base)
-        ld      D1, PC_OCC_SPRD, (\chiplet_base)
-        rotldi  D0, D0, 32
-        or      D0, D0, D1
-        std     D0, (\offset), (\oci_base)
-
-        .endm
-/// \endcond
-
-
-
-
-/// \fn gpe_get_core_data(GpeGetCoreDataParms *parms);
-/// \brief Get core chiplet raw data on performance/thermal timescale
-///
-/// This routine uses get_per_core_raw_data() to collect raw data for one or
-/// more cores.  The \a data field of the GpeGetCoreDataParms parameter
-/// contains a pointer to an array of CoreData* pointers.  Data for every core
-/// configured in the configuration mask is collected - it is assumed that the
-/// data area for the data exists.
-///
-/// This entry point is used by the lab thread 'coreData'.
-#ifdef DOXYGEN_ONLY
-void gpe_get_core_data(GpeGetCoreDataParms *parms);
-#endif
-/// \cond
-        
-        // Register usage:
-        //
-        // ETR   :  At entry, holds the parameter pointer.
-        // A1    :  Holds the pointer to the paramaters
-        // A0    :  Holds the (varying) pointer to the data area for the
-        //          current core.
-        // P1    :  Holds the (constant) chiplet id of the TOD
-        // P0    :  Holds the (varying) chiplet id of the current core
-        // SPRG0 :  Temporary storage of the chiplet mask as it rotates.
-        // CTR   :  Loops through core chiplets indices
-        // D1    :  Scratch
-        // D0    :  Scratch
-
-        .global gpe_get_core_data
-
-gpe_get_core_data:
-                
-        // Set up registers.  The chiplet part of the ChipConfig is left
-        // justified then stored in SPRG0, where it will be maintained as we
-        // rotate through it.  Note that SPRG0 is 32 bits, so it needs to be
-        // manipulated from the low-order portion of a data register.
-        
-        mr      D0, ETR
-        la      A1, core_data_parms
-        std     D0, 0, A1
-        mr      A1, D0
-
-        ld      D0, GPEGETCOREDATAPARMS_DATA, A1
-        mr      A0, D0
-        
-        ld      D0, GPEGETCOREDATAPARMS_CONFIG, A1
-        left_justify_core_config D0
-        rotldi  D0, D0, 32
-        mr      SPRG0, D0
-
-        lpcs    P1, TOD_VALUE_REG
-        ls      P0, 0x10
-        ls      CTR, (PGP_NCORES - 1) # PORE does test, then decr. and branch
-
-core_data_loop:
-        
-        // Load/test the chiplet mask, and store the rotated mask back to
-        // SPRG0. If the chiplet is not configured, simply continue.
-        
-        mr      D0, SPRG0
-        andi    D1, D0, 0x80000000
-        rotldi  D0, D0, 1
-        mr      SPRG0, D0
-        braz    D1, core_data_continue
-
-        // Collect Raw Data for Core specified by P0, stored at A0
-        
-        bsr     get_per_core_raw_data
-
-core_data_continue:     
-
-        // Increment the core chiplet index and data pointer, then loop or
-        // halt.
-
-        adds    P0, P0, 1
-        adds    A0, A0, CORE_DATA_SIZE
-        loop    core_data_loop
-
-        halt
-
-        .epilogue gpe_get_core_data
-
-/// \endcond
-
-
-
-/// \fn gpe_get_per_core_data(GpeGetCoreDataParms *parms);
-/// \brief Get core chiplet raw data for a single core
-///
-/// This routine uses get_per_core_raw_data() to collect raw data for a single
-/// core.  Regardless of the configuration mask setting, this routine exits
-/// after collecting data for a single core. The \a data field of the
-/// GpeGetCoreDataParms contains a pointer to a single CoreData object.
-///
-/// This entry point is used by OCC product firmware.
-#ifdef DOXYGEN_ONLY
-void gpe_get_per_core_data(GpeGetCoreDataParms *parms);
-#endif
-/// \cond
-        
-        // Register usage:
-        //
-        // A1    :  Holds the pointer to the paramaters
-        // A0    :  Holds the (varying) pointer to the data area for the
-        //          current core, as well as the data pointer-pointer while
-        //          searching for a configured core.
-        // P1    :  Holds the (constant) chiplet id of the TOD
-        // P0    :  Holds the (varying) chiplet id of the current core
-        // SPRG0 :  Temporary storage of the chiplet mask as it rotates.
-        // CTR   :  Loops through core chiplets indices
-        // D1    :  Scratch
-        // D0    :  Scratch
-
-        .global gpe_get_per_core_data
-
-gpe_get_per_core_data:
-                
-        // Set up registers.  A1 gets the parameters (which must also be
-        // stored in memory), the the ETR is replaced by the data
-        // pointer-pointer. The chiplet part of the ChipConfig is left
-        // justified then stored in SPRG0, where it will be maintained as we
-        // rotate through it.  Note that SPRG0 is 32 bits, so it needs to be
-        // manipulated from the low-order portion of a data register.
-        
-        mr      D0, ETR
-        la      A1, core_data_parms
-        std     D0, 0, A1
-        mr      A1, D0
-        
-        ld      D0, GPEGETCOREDATAPARMS_DATA, A1
-        mr      A0, D0
-        
-        ld      D0, GPEGETCOREDATAPARMS_CONFIG, A1
-        left_justify_core_config D0
-        rotldi  D0, D0, 32
-        mr      SPRG0, D0
-        
-        lpcs    P1, TOD_VALUE_REG
-        ls      P0, 0x10
-        ls      CTR, (PGP_NCORES - 1) # PORE does test, then decr. and branch
-
-per_core_data_loop:
-        
-        // Load/test the chiplet mask, and store the rotated mask back to
-        // SPRG0. If the chiplet is not configured, simply continue.
-        
-        mr      D0, SPRG0
-        andi    D1, D0, 0x80000000
-        rotldi  D0, D0, 1
-        mr      SPRG0, D0
-        braz    D1, per_core_data_continue
-
-        // Collect Raw Data for Core specified by P0, stored at A0
-        
-        bsr     get_per_core_raw_data
-
-        // Exit GPE after gathering data for one core 
-        bra per_core_data_complete
-
-per_core_data_continue:     
-
-        // Increment the core chiplet index and data pointer, then loop or
-        // halt.
-        adds    P0, P0, 1
-        loop    per_core_data_loop
-
-per_core_data_complete:
-        halt
-
-        .epilogue gpe_get_per_core_data
-
-/// \endcond
-
-/// \fn gpe_get_per_core_raw_data();
-/// \brief Get core chiplet raw data for one core
-///
-/// This routine collects raw data from the core designated by P0. Data is
-/// grouped into logical groups, and the collection of any group is enabled by
-/// a group select mask. All data and thread groups (except the PCB Slave
-/// group) are tagged with the TOD and raw cycle counts sampled immediately
-/// before the group data are sampled.
-///
-/// The final PCB Slave data group should always be selected (but \e is
-/// configurable) as it contains the PCB Slave Power Management history
-/// register.  This register value is required to determine how to interpret
-/// the other data items.
-///
-/// The PC counters are collected using the SPRC/SPRD autoincrement
-/// mechanism. Be very cautious about changing this code or the data layout
-/// because the counter order is fixed by hardware and the data layout
-/// reflects the most natural way to collect the data based on the
-/// hardware. Note that SPRC/SPRD autoincrement IS NOT OPTIONAL for the OCC
-/// registers, regardless of how it may be documented in the PC workbook, or
-/// the fact that the procedure redundantly sets up auto-increment.  That is,
-/// the hardware always does auto-increment for these SPRC/SPRD reads.
-///
-/// The data structure includes a TOD/Raw cycles word for each set of counters
-/// for each thread.  Due to the amount of time it may take to collect
-/// per-thread data for 8 threads, errors of 1% or more could accrue at thread
-/// 7 if each thread group were not individually tagged. To avoid having to
-/// SCOM the TOD plus a SCOMC/SCOMD pair to create each thread group header
-/// however, we instead tag thread0 with actual data, then tag the remaining
-/// thread groups with interpolated TOD/Raw cycle values computed by obtaining
-/// a tag at the end of all threads.  This takes only a little more time than
-/// the simpler expedient of copying the Tod/Raw Cycles count from thread0 to
-/// threads 1-7.
-///
-/// At the entry point of the routine, the code must go through the PC-ONLY
-/// special wakeup procedure to ensure that we can SCOM a napping core. This
-/// has to be done carefully as it's possible that SCOM access to the OHA will
-/// result in a 0x1 PIB response if the core is coming out of deep
-/// sleep/winkle. This PIB response would discombobulate the PORE engine so we
-/// have to run these SCOMs with error handling done manually.  If a core is
-/// inaccessible due to an idle state we clear all of the configured EMPATH
-/// counts, per-thread counts and DTS and CPM for the core. If the core is
-/// only asleep (not winkled) then we attempt to read the DTS and CPM for the
-/// L3.  Note that TOD timestamps are always collected, even if the data is
-/// simply zeroed.
-///
-/// A modified copy of the OHA_RO_STATUS_REG read during the PC-only SPWU
-/// protocol is stored with the data. Several low-order reserved bits of the
-/// register image are programmed with the following masks.  See the
-/// documentation for these bits for full details.
-///
-/// - CORE_DATA_CPM_HIST_RESET_ACCESS_FAILED
-/// - CORE_DATA_OHA_RO_STATUS_ACCESS_FAILED 
-/// - CORE_DATA_EMPATH_COLLECTED
-/// - CORE_DATA_CORE_SENSORS_COLLECTED
-/// - CORE_DATA_L3_SENSORS_COLLECTED
-/// - CORE_DATA_EXPECTED_EMPATH_ERROR
-/// - CORE_DATA_UNEXPECTED_EMPATH_ERROR
-///
-/// In the event of expected or unexpected errors during EMPATH data
-/// collection the 3-bit PCB error code will also be stored at bit
-/// CORE_DATA_EMPATH_ERROR_LOCATION.
-///
-/// This is the PC-ONLY Special Wakeup + processing Sequence
-///
-/// 1. Switch to manual error handling mode and disable PIB errors.
-///
-/// 2. Write OHA_CPM_HIST_RESET_REG.pconly_special_wakeup = 1.  If the write
-/// fails, note the failure and go to the bypass routine.
-///
-/// 3. Read OHA_RO_STATUS_REG. If the SCOM fails, access is impossible and
-/// noted. If the special wakeup complete is not immediately set that error is
-/// also noted. If either test fails then go to the bypass routine. Otherwise
-/// note success and continue. 
-///
-/// 4. Attempt to collect sensor (DTS/CPM) data for the core and L3. This must
-/// be done with manual error handling as these SCOMs are not protected by
-/// PC-only SPWU.
-///
-/// 5. Switch to a private error handling table setup that allows the
-/// procedure to catch PCB data errors during EMPATH processing. This is
-/// required as a workaround for HW280375.
-///
-/// 6. Collect EMPATH data.
-///
-/// 7. Restore error handling; Clear the PC-only SPWU bit.
-///
-/// 8. Collect PCB Slave data.
-///
-/// When the core is inaccessible a similar "bypass" sequence to the data
-/// collection sequence is run, however all data other than timestamps and the
-/// PCB Slave data are stored as 0, and the PC-Only SPWU bit is cleared before
-/// error handling is re-enabled.  The bypass routine will also take care of
-/// attempting to collect L3 DTS/CPM data for sleeping cores.
-///
-/// Note that the PCB slave data must be collected after the removal of
-/// PC-only special wakeup, otherwise a napping core will always appear to be
-/// in the run state.
-///
-/// Several global variables are required. Thus this procedure and its callers
-/// are not reentrant.
-#ifdef DOXYGEN_ONLY
-        void get_per_core_raw_data();
-#endif
-/// \cond
-
-get_per_core_raw_data:
-
-        // At entry:
-        //
-        // P0    : The chiplet to access (invariant)
-        // A0    : Pointer to the data area for the core (invariant)
-        // SPRG0 : Reserved to the caller (invariant)
-        // CTR   : Reserved to the caller (invariant)
-        //                
-        // core_data_parms: Holds the pointer to the parameters
-        //
-        // At exit:
-        //
-        // All other registers are scratched by this routine
-        
-        // (1) Switch to manual error handling mode and disable PIB errors.
-
-        mr      D0, EMR
-        la      A1, saved_emr
-        std     D0, 0, A1
-        
-        andi    D0, D0, ~(PORE_ERROR_MASK_ENABLE_ERR_HANDLER0 | \
-                          PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 | \
-                          PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 | \
-                          PORE_ERROR_MASK_STOP_EXE_ON_ERROR0)
-        mr      EMR, D0
-        la      A1, manual_emr
-        std     D0, 0, A1        
-                
-
-        // (2) Write OHA_CPM_HIST_RESET_REG.pconly_special_wakeup = 1. If the
-        // write fails, note the failure and go to the bypass routine.
-              
-        sti     OHA_CPM_HIST_RESET_REG, P0, \
-                OHA_CPM_HIST_RESET_REG_PCONLY_SPECIAL_WAKEUP
-        tprcbz  D0, 3f
-
-        sti     CORE_DATA_OHA_RO_STATUS_REG, A0, \
-                CORE_DATA_CPM_HIST_RESET_ACCESS_FAILED
-        bra     bypass_core_data
-
-
-        // 3. Read OHA_RO_STATUS_REG. If the SCOM fails, access is impossible
-        // and noted. If the special wakeup complete is not immediately set
-        // that error is also noted. If either test fails then go to the
-        // bypass routine. Otherwise note success and continue.
-        
-3:      
-        ld      D0, OHA_RO_STATUS_REG, P0
-        tprcbz  D1, 31f
-        
-        sti     CORE_DATA_OHA_RO_STATUS_REG, A0, \
-                CORE_DATA_OHA_RO_STATUS_ACCESS_FAILED
-        bra     bypass_core_data
-
-31:      
-        std     D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-                
-        // If either access is impossible we go to bypass.  The bypass code
-        // will read the L3 DTS/CPM data if it is possible.
-
-        andi    D1, D0, (OHA_RO_STATUS_REG_CORE_ACCESS_IMPOSSIBLE | \
-                         OHA_RO_STATUS_REG_ECO_ACCESS_IMPOSSIBLE)
-        branz   D1, bypass_core_data
-        
-        andi    D1, D0, OHA_RO_STATUS_REG_SPECIAL_WAKEUP_COMPLETED
-        braz    D1, bypass_core_data
-
-
-        // 4. Attempt to collect sensor (DTS/CPM) data. This must be done with
-        // manual error handling (in effect here) as these SCOMs are not
-        // protected by a PC-only SPWU. 
-
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0
-
-        bsr     getSensors
-
-
-        // 5. Switch to a private error handling table setup that allows the
-        // procedure to catch PCB errors during EMPATH processing.
-
-        // NB: We know that this is being run as a PoreFlex job from OCC FW on
-        // either GPE0 or GPE1. We also know that the default error mask does
-        // not handle any errors with a table.
-
-        tebngpe0 D0, 1f
-                la      A1, PORE_GPE0_TABLE_BASE_ADDR
-                bra     2f
-1:
-                la      A1, PORE_GPE1_TABLE_BASE_ADDR
-2:
-        la      D0, empathErrorHandlers
-        std     D0, 0, A1
-        
-        la      A1, saved_emr
-        ld      D0, 0, A1
-        ori     D0, D0, PORE_ERROR_MASK_ENABLE_ERR_HANDLER0
-        andi    D0, D0, ~(PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 | \
-                          PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 | \
-                          PORE_ERROR_MASK_STOP_EXE_ON_ERROR0)
-        mr      EMR, D0
-
-#if INJECT_HW280375_ERRORS
-
-        // This code is used to test the workaround for HW280375. The
-        // undiagnosed hardware bug causes PCB error 4 to occur intermittantly
-        // when accessing EMPATH registers. The appearance of the defect is
-        // actually quite rare in practice, therefore this code remains in
-        // case future development and testing of this procedure is necessary.
-
-        // The test generates PCB error 4 by reading a non-existant OHA
-        // register of the current core, once every 1024 samples on
-        // average. The LFSR modifies A0 so we need to shuffle A0 <->
-        // A1. (Note the LFSR code is not delivered to OCC FW).
-
-        mr      A1, A0
-        
-        la      A0, testHw280375Lfsr
-        ld      D0, 0, A0
-        bsr     pore_rand64
-        la      A0, testHw280375Lfsr
-        std     D0, 0, A0
-
-        mr      A0, A1
-
-        andi    D0, D0, 0x3ff
-        branz   D0, 1f
-                ld      D0, 0x200ff, P0 # Force PCB error 4
-1:      
-
-#endif
-
-        // 6. Collect EMPATH data
-
-        // Test/collect each data group in order.  First reload the parameter
-        // pointer into A1.
-
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0
-
-        // EMPATH
-empath:
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_EMPATH
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_EMPATH_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-
-        sti     PC_OCC_SPRC, P0, \
-                (SPRN_CORE_INSTRUCTION_DISPATCH | SPRN_PC_AUTOINCREMENT)
-
-        get_pc_pair (_BASE + 0x08), A0, P0
-        get_pc_pair (_BASE + 0x10), A0, P0
-        get_pc_pair (_BASE + 0x18), A0, P0
-        get_pc_pair (_BASE + 0x20), A0, P0
-
-        // Per-Core (partition) Memory Counters
-per_core_memory:
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_MEMORY
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_MEMORY_BASE
-        tag_core_data_group _BASE, A0, P0, P1
-
-        sti     PC_OCC_SPRC, P0, \
-                (SPRN_CORE_MEM_C_LPAR(0) | SPRN_PC_AUTOINCREMENT)
-
-        get_pc_pair (_BASE + 0x08), A0, P0
-        get_pc_pair (_BASE + 0x10), A0, P0
-
-        // Throttling Counters
-throttling:
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_THROTTLE
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_THROTTLE_BASE
-        tag_core_data_group _BASE, A0, P0, P1
-
-        sti     PC_OCC_SPRC, P0, \
-                (SPRN_IFU_THROTTLE_COUNTER | SPRN_PC_AUTOINCREMENT)
-
-        get_pc_pair (_BASE + 0x08), A0, P0
-        get_pc_pair (_BASE + 0x10), A0, P0
-
-        // Per-Thread Counters
-per_thread:
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_THREAD
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_THREAD_BASE(0)
-        tag_core_data_group _BASE, A0, P0, P1
-
-        sti     PC_OCC_SPRC, P0, \
-                (SPRN_THREAD_RUN_CYCLES(0) | SPRN_PC_AUTOINCREMENT)
-
-        get_pc_pair (_BASE + 0x08), A0, P0   # Run/Completion T0
-        get_pc_pair (_BASE + 0x10), A0, P0   # Mem A/B        T0
-        //          (_BASE + 0x18), A0, P0   # Tag            T1
-        get_pc_pair (_BASE + 0x20), A0, P0   # Run/Completion T1
-        get_pc_pair (_BASE + 0x28), A0, P0   # Mem A/B        T1
-        //          (_BASE + 0x30), A0, P0   # Tag            T2
-        get_pc_pair (_BASE + 0x38), A0, P0   # Run/Completion T2
-        get_pc_pair (_BASE + 0x40), A0, P0   # Mem A/B        T2
-        //          (_BASE + 0x48), A0, P0   # Tag            T3
-        get_pc_pair (_BASE + 0x50), A0, P0   # Run/Completion T3
-        get_pc_pair (_BASE + 0x58), A0, P0   # Mem A/B        T3
-        //          (_BASE + 0x60), A0, P0   # Tag            T4
-        get_pc_pair (_BASE + 0x68), A0, P0   # Run/Completion T4
-        get_pc_pair (_BASE + 0x70), A0, P0   # Mem A/B        T4
-        //          (_BASE + 0x78), A0, P0   # Tag            T5
-        get_pc_pair (_BASE + 0x80), A0, P0   # Run/Completion T5
-        get_pc_pair (_BASE + 0x88), A0, P0   # Mem A/B        T5
-        //          (_BASE + 0x90), A0, P0   # Tag            T6
-        get_pc_pair (_BASE + 0x98), A0, P0   # Run/Completion T6
-        get_pc_pair (_BASE + 0xa0), A0, P0   # Mem A/B        T6
-        //          (_BASE + 0xa8), A0, P0   # Tag            T7
-        get_pc_pair (_BASE + 0xb0), A0, P0   # Run/Completion T7
-        get_pc_pair (_BASE + 0xb8), A0, P0   # Mem A/B        T7
-
-
-        // Interpolation of TOD and Raw Cycles over 8 threads.  First collect
-        // a new tag, then compute the difference with the thread0 tag.  The
-        // differences are then divided by 8 to form the interpolation
-        // increment, and interpolation takes places in an unrolled loop.
-        //
-        // Note that we're doing parallel arithmetic here, and ignoring the
-        // fact that there may be a carry/borrow from the low-order TOD into
-        // the high-order cycle count.  A single LSB is noise for the cycle
-        // count, but would be significant for the TOD, which is why the
-        // TOD is placed in the low-order part of the doubleword. Given that
-        // a single LSB is noise for the cycle count there is no reason to
-        // expend the time/code space to do the arithmetic 'correctly'.
-
-interpolate: 
-        tag_core_data_group 0, 0, P0, P1, store=0 # D0 contains the _NOW_ tag
-        
-        ld      D1, CORE_DATA_THREAD_BASE(0), A0 # D1 will be used for interp.
-        sub     D0, D0, D1
-        andi    D0, D0, 0xfffffff8fffffff8 # Mask off bad bits and div. by 8.
-        rotrdi  D0, D0, 3
-
-        .macro  interpolate, thread
-        add     D1, D0, D1
-        std     D1, CORE_DATA_THREAD_BASE(\thread), A0
-        .endm
-
-        interpolate 1
-        interpolate 2
-        interpolate 3
-        interpolate 4
-        interpolate 5
-        interpolate 6
-        interpolate 7
-
-
-        // If we made it here there were no errors - Yippee! If we were asked
-        // to collect any EMPATH data then acknowledge that we did.
-1:              
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, \
-                (GPE_GET_CORE_DATA_EMPATH   | \
-                 GPE_GET_CORE_DATA_MEMORY   | \
-                 GPE_GET_CORE_DATA_THROTTLE | \
-                 GPE_GET_CORE_DATA_THREAD)
-        braz    D0, 1f
-
-        ld      D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-        ori     D0, D0, CORE_DATA_EMPATH_COLLECTED
-        std     D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-
-
-        // 7. Restore error handling; Clear the PC-Only SPWU bit
-1:      
-        la      A1, saved_emr
-        ld      D0, 0, A1
-        mr      EMR, D0
-        
-        sti     OHA_CPM_HIST_RESET_REG, P0, 0
-
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0
-
-
-        // 8. Collect PCB-Slave data
-pcb_slave:      
-
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_PCB_SLAVE
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_PCB_SLAVE_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-        
-        get_scom D0, PCBS_POWER_MANAGEMENT_CONTROL_REG, P0, CORE_DATA_PMCR, A0
-        get_scom D0, PCBS_POWER_MANAGEMENT_STATUS_REG, P0, CORE_DATA_PMSR, A0
-        get_scom D0, PCBS_PMSTATEHISTOCC_REG, P0, CORE_DATA_PM_HISTORY, A0
-                   
-1:      
-        ret
-
-
-        //////////////////////////////////////////////////////////////////////
-        // getSensors
-        //////////////////////////////////////////////////////////////////////
-        //
-        // Try to get core and L3 sensor (DTS/CPM) data
-        //
-        // At Entry:
-        //
-        // We are in manual PIB error handling mode
-        // A0 : Base address of core data area
-        // A1 : Address of the parameter block
-        // P0 : Chiplet
-        //
-        // At exit:
-        //
-        // A0, P0 unchanged
-        // D0, D1 scratched
-        //
-        // Note that due to HW279433, we can not read the CPM sensors without
-        // the possiblity of a FIR bit being set due to a PCB timeout. Since
-        // the CPMs are currently not in plan for P8, these fields of the data
-        // structure are simply zeroed.
-
-getSensors:
-
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_DTS_CPM
-        braz    D0, getSensorsDone
-        
-        // HW279433, see above
-        ls      D0, 0
-        std     D0, CORE_DATA_SENSOR_V8, A0
-        std     D0, CORE_DATA_SENSOR_V9, A0
-
-        .set    _BASE, CORE_DATA_DTS_CPM_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-        
-        // First try the core
-
-        ld      D0, SENSORS_CORE_V0, P0
-        tprcbnz D1, coreSensorsFailed
-        std     D0, CORE_DATA_SENSOR_V0, A0
-
-        ld      D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-        ori     D0, D0, CORE_DATA_CORE_SENSORS_COLLECTED
-        std     D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-
-        bra     tryL3
-
-coreSensorsFailed:
-
-        la      A1, G_ggcd_coreSensorFail
-        std     D1, 0, A1
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0
-
-        ls      D0, 0
-        std     D0, CORE_DATA_SENSOR_V0, A0
-        
-        // Now try the L3
-tryL3:
-        ld      D0, SENSORS_CORE_V1, P0
-        tprcbnz D1, l3SensorsFailed
-        std     D0, CORE_DATA_SENSOR_V1, A0
-
-        ld      D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-        ori     D0, D0, CORE_DATA_L3_SENSORS_COLLECTED
-        std     D0, CORE_DATA_OHA_RO_STATUS_REG, A0
-
-        bra     getSensorsDone
-
-l3SensorsFailed:
-
-        la      A1, G_ggcd_l3SensorFail
-        std     D1, 0, A1
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0
-
-        ls      D0, 0
-        std     D0, CORE_DATA_SENSOR_V1, A0
-
-getSensorsDone:
-        ret
-                
-
-        //////////////////////////////////////////////////////////////////////
-        // gpcrdError0
-        //
-        // Trap error 0 during EMPATH processing, and set a bit indicating if
-        // this is an "expected" or "unexpected" error. The only expected
-        // error is a PCB error #4 due to HW280375.
-        //
-        // Note that PORE treats error branches as subroutine calls. We need
-        // to pop the HW stack before continuing. We assume we are running on
-        // either GPE0 or GPE1.
-        ////////////////////////////////////////////////////////////////////////////
-
-        .global empathErrorHandlers
-empathErrorHandlers:
-        bra     gpcrdError0
-        
-gpcrdError0:
-
-        // Set A1 for current engine
-
-        tebngpe0 D0, 1f
-                la      A1, PORE_GPE0_OCI_BASE
-                bra     2f
-1:
-                la      A1, PORE_GPE1_OCI_BASE
-2:
-                        
-        // Extract PCB parity error + 3-bit code and compare. Apparently the
-        // PCB error code is not set in the IFR when we take the error branch,
-        // so we have to get it from the debug register. The error code is
-        // used to decide if the error is "expected" or "unexpected".
-
-        ld      D0, PORE_DBG0_OFFSET, A1
-        extrdi  D0, D0, 4, 32
-
-        ld      D1, CORE_DATA_OHA_RO_STATUS_REG, A0
-        cmpibraeq D0, 1f, 4
-
-                // This error is "unexpected"
-
-                ori     D1, D1, CORE_DATA_UNEXPECTED_EMPATH_ERROR
-                bra     2f
-
-                // This error (#4) is "expected"
-1:                 
-                ori     D1, D1, CORE_DATA_EXPECTED_EMPATH_ERROR
-
-        // Insert the error code into the OHA_RO_STATUS image
-2:      
-        insrdi  D1, D0, \
-                CORE_DATA_EMPATH_ERROR_BITS, CORE_DATA_EMPATH_ERROR_LOCATION
-        std     D1, CORE_DATA_OHA_RO_STATUS_REG, A0
-
-        
-        // Pop the hardware stack. The easiest way to do this is to modify the
-        // current stack pointer and "return" to a local label.
-
-        la      D0, 1f
-        sldi    D0, D0, 16
-        std     D0, PORE_PC_STACK0_OFFSET, A1
-        ret
-1:
-
-        // Clear the debug registers.
-
-        ls      D0, 0
-        std     D0, PORE_DBG0_OFFSET, A1
-        std     D0, PORE_DBG1_OFFSET, A1
-
-        // Bypass EMPATH data (that routine will restore the default error
-        // handling and re-establish A1)
-        
-        bra     bypass_core_data
-
-
-        //////////////////////////////////////////////////////////////////////
-        // bypass_core_data
-        //////////////////////////////////////////////////////////////////////
-        //
-        // This entry point is used when the core is inaccessible due to idle
-        // modes or other conditions. At entry we are in manual SCOM error
-        // handling mode. The routine will first attempt to collect the 
-        // core and L3 DTS/CPM for Sleeping cores, then restore error
-        // handling and zero out the EMPATH data before collecting PCBS data.
-
-        // HW243646: We never read EMPATH counters here.  The
-        // counters are all zeroed and all calls of tag_core_data_group
-        // specify raw=0.
-
-bypass_core_data:
-
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0        
-        
-        bsr     getSensors
-
-        // Clear the PC-Only SPWU bit and restore SCOM error handling.  Then
-        // reload the parameter pointer into A1.
-        
-        sti     OHA_CPM_HIST_RESET_REG, P0, 0
-
-        la      A1, saved_emr
-        ld      D0, 0, A1
-        mr      EMR, D0
-
-        la      A1, core_data_parms
-        ld      D0, 0, A1
-        mr      A1, D0        
-        
-        // Bypass core data
-        
-        // EMPATH
-
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_EMPATH
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_EMPATH_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-
-        ls      D0, 0
-        std     D0, (_BASE + 0x08), A0
-        std     D0, (_BASE + 0x10), A0
-        std     D0, (_BASE + 0x18), A0
-        std     D0, (_BASE + 0x20), A0
-
-
-        // Per-Core Memory Counters
-
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_MEMORY
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_MEMORY_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-
-        ls      D0, 0        
-        std     D0, (_BASE + 0x08), A0
-        std     D0, (_BASE + 0x10), A0
-
-
-        // Throttling Counters
-
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_THROTTLE
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_THROTTLE_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-
-        ls      D0, 0        
-        std     D0, (_BASE + 0x08), A0
-        std     D0, (_BASE + 0x10), A0
-
-
-        // Per-Thread Counters
-        
-1:      
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_THREAD
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_THREAD_BASE(0)
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-
-        ls      D0, 0
-        std     D0, (_BASE + 0x08), A0   # Run/Completion T0
-        std     D0, (_BASE + 0x10), A0   # Mem A/B        T0
-        //          (_BASE + 0x18), A0   # Tag            T1
-        std     D0, (_BASE + 0x20), A0   # Run/Completion T1
-        std     D0, (_BASE + 0x28), A0   # Mem A/B        T1
-        //          (_BASE + 0x30), A0   # Tag            T2
-        std     D0, (_BASE + 0x38), A0   # Run/Completion T2
-        std     D0, (_BASE + 0x40), A0   # Mem A/B        T2
-        //          (_BASE + 0x48), A0   # Tag            T3
-        std     D0, (_BASE + 0x50), A0   # Run/Completion T3
-        std     D0, (_BASE + 0x58), A0   # Mem A/B        T3
-        //          (_BASE + 0x60), A0   # Tag            T4
-        std     D0, (_BASE + 0x68), A0   # Run/Completion T4
-        std     D0, (_BASE + 0x70), A0   # Mem A/B        T4
-        //          (_BASE + 0x78), A0   # Tag            T5
-        std     D0, (_BASE + 0x80), A0   # Run/Completion T5
-        std     D0, (_BASE + 0x88), A0   # Mem A/B        T5
-        //          (_BASE + 0x90), A0   # Tag            T6
-        std     D0, (_BASE + 0x98), A0   # Run/Completion T6
-        std     D0, (_BASE + 0xa0), A0   # Mem A/B        T6
-        //          (_BASE + 0xa8), A0   # Tag            T7
-        std     D0, (_BASE + 0xb0), A0   # Run/Completion T7
-        std     D0, (_BASE + 0xb8), A0   # Mem A/B        T7
-
-
-        // Interpolation of TOD and Raw Cycles over 8 threads.  First collect
-        // a new tag, then compute the difference with the thread0 tag.  The
-        // differences are then divided by 8 to form the interpolation
-        // increment, and interpolation takes places in an unrolled loop.
-        //
-        // Note that we're doing parallel arithmetic here, and ignoring the
-        // fact that there may be a carry/borrow from the low-order TOD into
-        // the high-order cycle count.  A single LSB is noise for the cycle
-        // count, but would be significant for the TOD, which is why the
-        // TOD is placed in the low-order part of the doubleword. Given that
-        // a single LSB is noise for the cycle count there is no reason to
-        // expend the time/code space to do the arithmetic 'correctly'.
-
-        tag_core_data_group 0, 0, P0, P1, raw=0, store=0 # D0 contains _NOW_ tag
-        
-        ld      D1, CORE_DATA_THREAD_BASE(0), A0 # D1 will be used for interp.
-        sub     D0, D0, D1
-        andi    D0, D0, 0xfffffff8fffffff8 # Mask off bad bits and div. by 8.
-        rotrdi  D0, D0, 3
-
-        interpolate 1
-        interpolate 2
-        interpolate 3
-        interpolate 4
-        interpolate 5
-        interpolate 6
-        interpolate 7
-
-
-        // Per-Core PCB Slave Registers
-get_pcbs_data:
-
-        ldandi  D0, GPEGETCOREDATAPARMS_SELECT, A1, GPE_GET_CORE_DATA_PCB_SLAVE
-        braz    D0, 1f
-
-        .set    _BASE, CORE_DATA_PCB_SLAVE_BASE
-        tag_core_data_group _BASE, A0, P0, P1, raw=0
-        
-        get_scom D0, PCBS_POWER_MANAGEMENT_CONTROL_REG, P0, CORE_DATA_PMCR, A0
-        get_scom D0, PCBS_POWER_MANAGEMENT_STATUS_REG, P0, CORE_DATA_PMSR, A0
-        get_scom D0, PCBS_PMSTATEHISTOCC_REG, P0, CORE_DATA_PM_HISTORY, A0
-
-1:
-        ret    
-        
-/// \endcond
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_core_data_fast()
-////////////////////////////////////////////////////////////////////////////            
-
-/// \fn gpe_get_core_data_fast(GpeGetChipDataFastParms *parms);
-/// \brief Get chip raw data on fastest possible timescale
-///
-/// This routine collects raw data for the entire chip on the fastest possible
-/// timescale. Where chiplet data is collected, the configured chiplets are 
-/// specified in the configuration mask parameter. Data is grouped
-/// into logical groups, and the collection of any group is enabled by a group
-/// select mask. All data groups are tagged with the TOD.
-#ifdef DOXYGEN_ONLY
-void gpe_get_core_data_fast(GpeGetChipDataFastParms *parms);
-#endif
-/// \cond
-
-        // Register usage:
-        //
-        // A1 :  Holds the (constant) pointer to the paramaters
-        // A0 :  Holds the (varying) pointer to the data area for the current
-        //       data group or datum. 
-        // P1 :  Holds the (constant) chiplet id of the TOD
-        // P0 :  Holds the (varying) chiplet id of interest
-        // CTR :  Loops through chiplet indices
-        // D1 :  Holds/rotates configuration mask
-        // D0 :  Scratch
-
-        .global gpe_get_core_data_fast
-
-gpe_get_core_data_fast:
-
-        // Set up registers. A0 must follow the target OCI address as each core
-        // chiplet is considered. Since we're only doing a single
-        // getscom/putOCI, we can keep the chiplet mask in D1. The data group
-        // is tagged with the TOD.
-        
-        mr      A1, ETR
-        ld      D0, GPEGETCOREDATAFASTPARMS_CONFIG, A1
-        left_justify_core_config D0
-        mr      D1, D0
-        lpcs    P1, TOD_VALUE_REG
-        ld      D0, GPEGETCOREDATAFASTPARMS_DATA, A1
-        mr      A0, D0
-
-        tag_data_group CORE_DATA_FAST_FREQ_TARGET_BASE, D0, A0, P1
-        adds    A0, A0, 8
-
-        ls      P0, 0x10
-        ls      CTR, (PGP_NCORES - 1) # PORE does test, then decr. and branch
-        
-freq_target_loop:
-
-        // Test the chiplet mask. If the chiplet is not configured, simply
-        // continue.
-        
-        andi    D0, D1, 0x8000000000000000
-        rotldi  D1, D1, 1
-        braz    D0, freq_target_continue
-
-        get_scom D0, PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_STATUS_REG, P0, \
-                0x00, A0
-
-freq_target_continue:   
-
-        // Increment the core chiplet index and data pointer, then loop or
-        // carry on.
-
-        adds    P0, P0, 1
-        adds    A0, A0, 8
-        loop    freq_target_loop
-        
-1:
-        halt
-
-/// \endcond
-        
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_chip_data()
-////////////////////////////////////////////////////////////////////////////            
-
-/// \fn gpe_get_chip_data(GpeGetChipDataParms *parms);
-/// \brief Get chip-level raw data
-///
-/// This routine collects chip-level raw data.  Data is grouped into logical
-/// groups, and the collection of any group is enabled by a group select
-/// mask. All data groups are tagged with the TOD.
-#ifdef DOXYGEN_ONLY
-void gpe_get_chip_data(GpeGetChipDataParms *parms);
-#endif
-/// \cond
-
-        // Register usage:
-        //
-        // A0 :  Holds the (varying) pointer to the data area for the current
-        //       data group or datum. 
-        // P1 :  Holds the (constant) chiplet id of the TOD
-        // D1 :  Holds the (constant) select mask
-
-        .global gpe_get_chip_data
-
-gpe_get_chip_data:
-
-        // Set up registers.
-        
-        mr      A1, ETR
-        ld      D0, GPEGETCHIPDATAPARMS_SELECT, A1
-        mr      D1, D0
-        lpcs    P1, TOD_VALUE_REG
-        ld      D0, GPEGETCHIPDATAPARMS_DATA, A1
-        mr      A0, D0
-
-        // Overcommit data.
-
-        andi    D0, D1, GPE_GET_CHIP_DATA_OVERCOMMIT
-        braz    D0, 1f
-        tag_data_group CHIP_DATA_OVERCOMMIT_BASE, D0, A0, P1
-        
-        // Overcommit data consists of PBA_PBOCR(0)...PBA_PBOCR(5), all stored
-        // at 8-byte offsets
-        
-        la   A1, PBA_PBOCRN(0)
-        ocicopy D0, 0x00, A1, 0x08, A0
-        ocicopy D0, 0x08, A1, 0x10, A0
-        ocicopy D0, 0x10, A1, 0x18, A0
-        ocicopy D0, 0x18, A1, 0x20, A0
-        ocicopy D0, 0x20, A1, 0x28, A0
-        ocicopy D0, 0x28, A1, 0x30, A0
-        
-1:
-        halt
-
-        .epilogue gpe_get_chip_data
-
-/// \endcond
-
-
-////////////////////////////////////////////////////////////////////////////
-// gpe_get_mem_data()
-////////////////////////////////////////////////////////////////////////////            
-
-/// \fn gpe_get_mem_data(GpeGetMemDataParms *parms);
-/// \brief Get memory (MCS/Centaur) data for a particular MCS/Centaur
-///
-/// This routine collects data for the MCS/Centaur named (by instance ID,
-/// (0...PGP_NCENTAUR -1)) in the \a collect field of the \a parms parameter,
-/// unless \a collect is -1 in which case the data collection is bypassed.
-/// Once data has been collected, if the \a update field of the a \parms is
-/// not -1 then that numbered Centaur will be "poked" to start the sensor
-/// cache update. Once data collection (if any) and "poking" (if any) are
-/// finished the parameter block is timestamped with the TOD (at the standard
-/// 2MHz). This means that the TOD timestamp marks the "poke" time (when data
-/// collection starts), not the data collection time.
-///
-/// This procedure requires that the global G_centaurConfiguration structure
-/// must be present and have been properly initialized by
-/// centaur_configuration_create(). The procedure returns a return code -
-/// Either 0 for success, or a non zero value for failure.  The failure codes
-/// are documented here: \ref gpe_get_mem_data_rc. Since the parameter block
-/// is read and written by GPE code it is strongly recommended to allocate
-/// instances of this structure in non-cacheable data sections, with the
-/// caveat that data structures assigned to non-default data sections must
-/// always be initialized. For example:
-///
-/// \code
-///
-/// static GpeGetMemDataParms S_parms SECTION_ATTRIBUTE(".noncacheable") = {0};
-///
-/// \endcode
-///
-/// NB: SW273814 documents a request to be able to differentiate which of the 2
-/// Centaurs is responsible for a hard failure. That's why we take pains to
-/// set up the RC prior to collection/poking to enable recovery code to make
-/// this determination.
-#ifdef DOXYGEN_ONLY
-void gpe_get_mem_data(GpeGetMemDataParms *parms);
-#endif
-/// \cond
-
-        .global gpe_get_mem_data
-gpe_get_mem_data:
-
-        // At entry:    
-        //
-        // ETR : parms
-        //
-        // Invariants:
-        //
-        // ETR : parms
-        // A1  : parms (except when scratched by subroutines, always restored)
-
-        // Begin by marking the procedure as having died
-
-        mr      A1, ETR
-        sti     GPEGETMEMDATAPARMS_RC, A1, GPE_GET_MEM_DATA_DIED
-        
-        // Next check to make sure the G_centaurConfiguration is properly
-        // initialized (.configRc == 0).
-        //
-        // A1 :  parms
-
-        la      A0, G_centaurConfiguration
-        ld      D0, CENTAUR_CONFIGURATION_CONFIG_RC, A0
-        braz    D0, 1f
-
-                ls      D0, GPE_GET_MEM_DATA_NOT_CONFIGURED
-                bra     ggmdExit
-        
-1:
-        // Set up the PBA for Centaur sensor cache access
-        //
-        // A1 : parms
-        // A0 : &G_centaurConfiguration ==> &G_centaurConfiguration.dataParms;
-
-        adds    A0, A0, CENTAUR_CONFIGURATION_DATA_PARMS
-        bsr     gpe_pba_reset
-        bsr     gpe_pba_setup
-        mr      A1, ETR         # Re-establish invariant
-                        
-
-        // See if we're collecting data this pass. If so validate that the
-        // MCS/Centaur index is valid according to G_centaurConfiguration.
-        //
-        // A1 : parms
-
-        ld      D0, GPEGETMEMDATAPARMS_COLLECT, A1
-        cmpibraeq D0, ggmdUpdate, -1
-
-        bsr     ggmdDataSetup
-        mr      A1, ETR         # Re-establish invariant
-        braz    D0, 1f
-
-                ls      D0, GPE_GET_MEM_DATA_COLLECT_INVALID
-                bra     ggmdExit
-        
-1:
-        // A0 has the base address of the sensor cache as a PowerBus
-        // mapping. Load A1 with the user data pointer and collect the data.
-        //
-        // A1 : parms ==> &MemData
-
-        sti     GPEGETMEMDATAPARMS_RC, A1, GPE_GET_MEM_DATA_SENSOR_CACHE_FAILED
-
-        ld      D0, GPEGETMEMDATAPARMS_DATA, A1
-        mr      A1, D0
-        
-        ocicopy D0, 0x00, A0, 0x00, A1
-        ocicopy D0, 0x08, A0, 0x08, A1
-        ocicopy D0, 0x10, A0, 0x10, A1
-        ocicopy D0, 0x18, A0, 0x18, A1
-        ocicopy D0, 0x20, A0, 0x20, A1
-        ocicopy D0, 0x28, A0, 0x28, A1
-        ocicopy D0, 0x30, A0, 0x30, A1
-        ocicopy D0, 0x38, A0, 0x38, A1
-        ocicopy D0, 0x40, A0, 0x40, A1
-        ocicopy D0, 0x48, A0, 0x48, A1
-        ocicopy D0, 0x50, A0, 0x50, A1
-        ocicopy D0, 0x58, A0, 0x58, A1
-        ocicopy D0, 0x60, A0, 0x60, A1
-        ocicopy D0, 0x68, A0, 0x68, A1
-        ocicopy D0, 0x70, A0, 0x70, A1
-        ocicopy D0, 0x78, A0, 0x78, A1
-
-        mr      A1, ETR         # Re-establish invariant
-
-        sti     GPEGETMEMDATAPARMS_RC, A1, GPE_GET_MEM_DATA_DIED
-
-        // See if we're poking Centaur this pass. If so validate that the
-        // MCS/Centaur index is valid according to G_centaurConfiguration.
-        //
-        // A1 : parms
-ggmdUpdate:     
-
-        ld      D0, GPEGETMEMDATAPARMS_UPDATE, A1
-        cmpibraeq D0, ggmdTimestamp, -1
-
-        bsr     ggmdDataSetup
-        mr      A1, ETR         # Re-establish invariant
-        braz    D0, 1f
-
-                ls      D0, GPE_GET_MEM_DATA_UPDATE_INVALID
-                bra     ggmdExit
-                  
-1:
-        // Poke it
-
-        sti     GPEGETMEMDATAPARMS_RC, A1, GPE_GET_MEM_DATA_UPDATE_FAILED
-
-        ls      D0, 0
-        std     D0, 0, A0
-        
-        sti     GPEGETMEMDATAPARMS_RC, A1, GPE_GET_MEM_DATA_DIED
-
-        // Collect the timestamp and reduce the 64-bit 512MHz timestamp to a
-        // 32-bit 2MHz timestamp. Then we're out...
-        //
-        // A1 : parms
-ggmdTimestamp:
-
-        lpcs    P0, TOD_VALUE_REG
-        ld      D0, TOD_VALUE_REG, P0
-        extrdi  D0, D0, 32, 24
-        std     D0, GPEGETMEMDATAPARMS_PAD_TOD, A1
-
-
-        ////////////////////////////////////////////////////////////////////
-        // Not so fast... If this is Centaur DD1 then we did not actually
-        // collect the Centaur internal temperatures due to HW256773. So we
-        // will go collect them now "manually" by calling _gpe_scom_centaur
-        // with a hard-coded setup to collect SCOM 0x02050000.  We then
-        // splice this result into the accumulated cache-line data.
-        //
-        // A1 :  Parms
-        ////////////////////////////////////////////////////////////////////
-
-        // Nothing to do if we're not collecting data. Otherwise pull out the
-        // CFAM ID and compare for Centaur DD1
-
-        ld      D0, GPEGETMEMDATAPARMS_COLLECT, A1
-        cmpibraeq D0, ggmdCleanExit, -1
-
-        sldi    D0, D0, 3       # Multiply by 8 for a byte offset
-
-        la      D1, G_centaurConfiguration
-        adds    D1, D1, CENTAUR_CONFIGURATION_DEVICE_ID
-        add     D0, D0, D1
-        mr      A0, D0
-        ld      D0, 0, A0
-        extrdi  D0, D0, 32, 0
-        
-        cmpibrane D0, ggmdCleanExit, CFAM_CHIP_ID_CENTAUR_10
-
-        // This is DD1.  Set up the parameters and call _gpe_scom_centaur.
-        // Since we can only do 8-byte stores we read-modify-write the first
-        // entry of the scomList_t.  Then call for the SCOM. If it failed set
-        // the failure code. All registers must be restored after the
-        // subroutine call.
-        
-        la      A0, G_ggmdHw256773
-        ld      D0, SCOM_LIST_COMMAND, A0
-        ld      D1, GPEGETMEMDATAPARMS_COLLECT, A1
-        scom_list_set_instance_number D0, D1
-        std     D0, SCOM_LIST_COMMAND, A0
-
-        la      A0, G_hw256773
-        bsr     _gpe_scom_centaur
-
-        la      A0, G_hw256773
-        mr      A1, ETR
-
-        ld      D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-        gpe_scom_parms_get_rc D0, D0
-        braz    D0, 1f
-
-                ls      D0, GPE_GET_MEM_DATA_HW256773_FAILED
-                bra     ggmdExit
-
-1:
-        // The SCOM succeeded.  The data needs to be moved from the
-        // gpe_scom_centaur data into the sensor-cache data area. Since there
-        // are only 32 bits we need to read-modify-write the SRAM. This is
-        // doubleword 12 of the sensor cache.  The 32 bits of the SCOM we need
-        // are the high-order bits, copied into the low-order bits of the
-        // sensor-cache doubleword. Finally fall through to the clean exit.
-
-        la      A0, G_ggmdHw256773
-        ld      D0, SCOM_LIST_DATA, A0
-        
-        ld      D1, GPEGETMEMDATAPARMS_DATA, A1
-        mr      A0, D1
-        ld      D1, 0x60, A0
-        rldimi  D1, D0, 32, 32, 63
-        std     D1, 0x60, A0
-
-
-ggmdCleanExit:
-        ls      D0, 0
-ggmdExit:               
-        std     D0, GPEGETMEMDATAPARMS_RC, A1
-        halt
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // ggmdDataSetup
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // At entry:    
-        //
-        //     D0 : The Centaur instance number to set up
-        //
-        // At exit:     
-        //
-        //     A0  : On success, the OCI base address to use to access the
-        //           sensor cache.
-        //     D0  : 0 = Success; 1 = Failure - the caller will supply the
-        //           correct error code back to the user.
-        //     
-        // This routine checks the Centaur instance number for validity.  If
-        // the instance number is valid then the PBA is programmed to access
-        // the sensor cache address.  This requires reprogramming the PBA
-        // because part of the data address, which varies by Centaur, must be
-        // stored as the extended address field of the PBA slave control
-        // register. It is not necessary to reset the PBA slave for each data
-        // operation.
-ggmdDataSetup: 
-
-        // Check the Centaur instance number (D0) for validity.
-
-        ls      D1, PGP_NCENTAUR
-        sub     D1, D0, D1
-        tfbult  D1, 1f
-
-        ls      D0, 1
-        ret                     # Centaur instance too big
-
-1:
-        // Check to make sure the Centaur is configured by testing the base
-        // address for 0. The instance number is first multiplied by 8 to
-        // create an array offset.
-
-        sldi    D0, D0, 3
-        la      D1, G_centaurConfiguration
-        adds    D1, D1, CENTAUR_CONFIGURATION_BASE_ADDRESS
-        add     D0, D0, D1
-        mr      A0, D0
-        ld      D0, 0, A0
-        branz   D0, 1f
-
-        ls      D0, 1
-        ret                     # Base address is 0
-
-1:
-        // We have the Centaur base address in D0, and convert it to the full
-        // PowerBus address for the inband sensor cache access. Bit 27 is set
-        // to indicate OCC (vs. FSP) access. Bit 28 is set to indicate a
-        // sensor cache access. 
-
-        ori     D0, D0, 0x0000001800000000
-
-#if 1
-        la      A0, G_ggmd_lastDataAddress # Debug
-        std     D0, 0, A0
-#endif
-
-        // The OCI address is always 0, decorated with the PBA BAR number.
-
-        la      A0, (PBA_BAR_CENTAUR << 28)             
-
-        // Bits 23:36 of the address go into the extended address field (35:
-        // 48) of the PBA slave control register by a read-modify-write
-        // operation. Note: We're using rldimi explicitly here - not an
-        // extended mnemonic - to save having to justify the data.
-
-        la      A1, G_centaurConfiguration
-        ld      D1, \
-               (CENTAUR_CONFIGURATION_DATA_PARMS + \
-                 GPEPBAPARMS_SLVCTL_ADDRESS), \
-                 A1
-        mr      A1, D1
-        ld      D1, 0, A1
-        rldimi  D1, D0, 64 - (35 - 23), 35, 48
-        std     D1, 0, A1
-
-#if 1
-        la      A1, G_ggmd_lastSlaveControl # Debug
-        std     D1, 0, A1
-        mr      D1, A0
-        la      A1, G_ggmd_lastOciAddress
-        std     D1, 0, A1
-#endif
-        
-        // Clear D0 to signal success and we're out
-
-        ls      D0, 0
-        ret
-        .epilogue gpe_get_mem_data
-        
-/// \endcond
-
-
-////////////////////////////////////////////////////////////////////////////
-// Global Data
-////////////////////////////////////////////////////////////////////////////            
-
-        
-
-/// \cond
-
-        .data.pore
-
-        // Data storage for gpe_get_core_data()
-
-core_data_parms:
-        .quad   0
-saved_emr: 
-        .quad   0
-manual_emr:     
-        .quad   0
-hw243646:
-#if 0
-        .quad   0x3             # Determined + Required
-#else
-        .quad   0x2             # Determined + Not Required
-#endif  
-
-        // Used to debug the workaround for HW280375
-
-testHw280375Lfsr:               
-        .quad   0xdeadbeef      # Initial state of LFSR
-
-        // Debug/Info: Failure codes when sensor reads fail
-
-        .global G_ggcd_coreSensorFail
-G_ggcd_coreSensorFail:
-        .quad   0
-
-        .global G_ggcd_l3SensorFail
-G_ggcd_l3SensorFail:    
-        .quad   0
-
-
-        // Debug only, the last values computed by ggmdDataSetup.
-        
-        .global G_ggmd_lastDataAddress
-G_ggmd_lastDataAddress:
-        .quad   0
-
-        .global G_ggmd_lastSlaveControl
-G_ggmd_lastSlaveControl:
-        .quad   0
-
-        .global G_ggmd_lastOciAddress
-G_ggmd_lastOciAddress:
-        .quad   0
-
-
-        // Required for Centaur DD1.  This is an assembler layout of a
-        // GpeScomParms structure pointing to a scomList_t structure to read
-        // Centaur SCOM 0x02050000.  See the code comments for more details.
-
-        .global G_ggmdHw25773
-G_ggmdHw256773:
-        .long   0x02050000      # SCOM
-        .byte   0               # Reserved
-        .byte   0               # Error flags (output)
-        .byte   0               # Instance Number (input)
-        .byte   GPE_SCOM_READ   # Command
-        .quad   0               # Mask (unused)
-        .quad   0               # Data (output)
-
-        .global G_hw256773
-G_hw256773:
-        .long   0               # (32-bit addresses)
-        .long   G_ggmdHw256773  # scomList
-        .long   1               # Entries in the scomList
-        .long   0               # Options
-        .long   0               # rc (output)
-        .long   0               # errorIndex (output)
-        
-/// \endcond
diff --git a/src/lib/gpe_pba.c b/src/lib/gpe_pba.c
deleted file mode 100755
index c3b0a00..0000000
--- a/src/lib/gpe_pba.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// $Id: gpe_pba.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_pba.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe.c
-/// \brief Generic PORE-GPE support procesures (outside of the kernel
-/// drivers).
-
-#include "ssx.h"
-#include "gpe.h"
-#include "gpe_pba.h"
-
-/// Create/initialize a GpePbaParms structure
-///
-/// \param parms A unused or uninitialized GpePbaParms structure
-///
-/// \param slave The PBA slave port to program.  For production code this will
-/// normally be PBA_SLAVE_PORE_GPE, however for test/verification code it
-/// could be any PBA slave.
-///
-/// \param write_ttype One of PBA_WRITE_TTYPE_* (see pgp_pba.h).  Use
-/// PBA_WRITE_TTYPE_DC (don't care) if the GPE application does not do writes.
-///
-/// \param write_tsize One of PBA_WRITE_TSIZE_* (see pgp_pba.h).  The \a
-/// write_tsize is only relevant for \a write_ttype == PBA_WRITE_TTYPE_LCO_M,
-/// where the macro PBA_WRITE_TSIZE_CHIPLET() is used to specify the target
-/// chiplet, and \a write_ttype == PBA_WRITE_TTYPE_ATOMIC_RMW, where the \a
-/// write_tsize specifies the atomic operation. Otherwise use
-/// PBA_WRITE_TTYPE_DC (don't care).
-///
-/// \param read_ttype One of PBA_READ_TTYPE_* (see pgp_pba.h).  Normally this
-/// will be PBA_READ_TTYPE_CL_READ_NC (or PBA_READ_TTYPE_DC if you don't
-/// care.) 
-///
-/// \param flags Two flags are provided that override default
-/// behavior. GPE_PBA_PARMS_READ_INVALIDATE specifies read buffer invalidation
-/// after every read.  This is always selected when the read Ttype is a
-/// cache-inhibited partial read, but may be optionally specified for test
-/// purposes. 
-///
-/// Similarly, GPE_PBA_PARMS_DISABLE_WRITE_GATHER specifies that write
-/// gathering for write Ttype DMA partial write is disabled. Note that
-/// GPE_PBA_PARMS_DISABLE_WRITE_GATHER disables write gathering in the sense
-/// that writes pass through the PBA immediately without being buffered. This
-/// is different from using the PBA_WRITE_GATHER_TIMEOUT_DISABLE option to \a
-/// write_gather_timeout, which specifies that writes are gathered until an
-/// entire line is filled.
-///
-/// This API initializes the GpePbaParms structure used by every GPE program
-/// that accesses mainstore via PBA. It creates an image of a PBA_SLVCTL
-/// register to be applied under a mask.  
-///
-/// \note Read buffer invalidation is always enforced for cache-inhibited
-/// partial reads. This also forces prefetching to be disabled for the
-/// slave. Our procedures currently do not support save/restore of prefetch
-/// controls as different tasks reprogram the PBA Slave.  Thus any access of a
-/// shared slave that is also used to do CI_PR_RD will have prefetching
-/// disabled. 
-///
-/// \retval 0 Success
-///
-/// \retval -GPE_INVALID_OBJECT The \a parms pointer is NULL (0) or othewise
-/// invalid. 
-///
-/// \retval -GPE_INVALID_ARGUMENT One of the arguments is invalid in some way.
-
-int
-gpe_pba_parms_create(GpePbaParms *parms,
-                     int slave,
-                     int write_ttype,
-                     int write_tsize,
-                     int read_ttype)
-{
-    pba_slvctln_t *slvctl, *mask;
-    pba_slvrst_t* slvrst;
-    pba_slvrst_t* slvrst_in_progress;
-    uint64_t all1 = 0xffffffffffffffffull;
-
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((parms == 0), GPE_INVALID_OBJECT);
-        SSX_ERROR_IF((slave < 0) ||
-                     (slave >= PBA_SLAVES),
-                     GPE_INVALID_ARGUMENT);
-    }
-
-    parms->slave_id = slave;
-
-    slvctl = &(parms->slvctl);
-    mask = &(parms->mask);
-    slvrst = &(parms->slvrst);
-    slvrst_in_progress = &(parms->slvrst_in_progress);
-
-    parms->slvctl_address = PBA_SLVCTLN(slave);
-
-    slvrst->value = 0;
-    slvrst->fields.set = PBA_SLVRST_SET(slave);
-
-    slvrst_in_progress->value = 0;
-    slvrst_in_progress->fields.in_prog = PBA_SLVRST_IN_PROG(slave);
-
-    slvctl->value = 0;
-    mask->value = 0;
-
-    slvctl->fields.enable = 1;
-    mask->fields.enable = all1;
-
-    slvctl->fields.write_ttype = write_ttype;
-    mask->fields.write_ttype = all1;
-    
-    slvctl->fields.write_tsize = write_tsize;
-    mask->fields.write_tsize = all1;
-
-    slvctl->fields.read_ttype = read_ttype;
-    mask->fields.read_ttype = all1;
-
-    if (read_ttype == PBA_READ_TTYPE_CI_PR_RD) {
-
-        slvctl->fields.buf_invalidate_ctl = 1;
-        mask->fields.buf_invalidate_ctl = all1;
-
-        slvctl->fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
-        mask->fields.read_prefetch_ctl = all1;
-
-    } else {
-
-        slvctl->fields.buf_invalidate_ctl = 0;
-        mask->fields.buf_invalidate_ctl = all1;
-    }
-
-    mask->value = ~(mask->value);
-
-    return 0;
-}
-        
-    
-    
-          
-    
-
-    
-                     
-    
-                     
diff --git a/src/lib/gpe_pba.h b/src/lib/gpe_pba.h
deleted file mode 100644
index 5f8ea2c..0000000
--- a/src/lib/gpe_pba.h
+++ /dev/null
@@ -1,116 +0,0 @@
-#ifndef __GPE_PBA_H__
-#define __GPE_PBA_H__
-
-// $Id: gpe_pba.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_pba.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe_pba.h
-/// \brief PBA subroutines for PORE-GPE procedures
-
-// Error/Panic codes
-
-#define GPE_INVALID_OBJECT   0x00473001
-#define GPE_INVALID_ARGUMENT 0x00473002
-
-
-#ifndef __ASSEMBLER__
-
-/// Encapsulated PBA setup for GPE programs
-///
-/// All GPE programs that access mainstore via PBA utilize a common parameter
-/// structure that encapsulates the required setup.  This is required due to
-/// the unusual architecture of the PBA which interprets OCI addresses and the
-/// associated PowerBus transaction type based on which OCI \e master issued
-/// the OCI transaction, not based on the OCI \a address (or PowerBus
-/// address).  The final complication is that each OCI master is assigned a
-/// unique PBA "slave port", so any reprogramming must be done on the PBA
-/// registers associated with the particular port assigned to the particular
-/// PORE engine.
-///
-/// In product code the PBA slave port assignment for the PORE-GPE engines
-/// will be fixed; however this structure assumes the most general case and
-/// allows for an arbitraray and dynamic assignment, and even allows mainstore
-/// programs to run on the PORE-SLW. However the procedure that creates this
-/// structure (gpe_pba_parms_create()) must know which engine/port will run
-/// the program in order to set up the parameters.
-///
-/// The PBA software interface is not friendly for dynamic programming of the
-/// PBA slave setup, especially from the PORE. The slave setup is modifed by a
-/// read-modify-write under mask. gpa_pba_parms_create() does not allow
-/// specification of which read buffers, prefetch modes or write timeouts to
-/// use as these have global implications. Only the values that affect the
-/// particular mode can be programmed there (but of course can be later
-/// overridden if required).
-///
-/// Note that there is an assumption that PORE engines have exclusive access
-/// to their PBA ports.  All GPE procedures that access the PowerBus follow a
-/// protocol that makes no assumptions about how the PBA is set up - they set
-/// up the PBA for their own use, then leave it to subsequent procedures to
-/// re-setup the PBA as necessary for subsequent use. Also note that only one
-/// GPE thread can be designated to run programs that access the PBA,
-/// as they share an OCI master ID, and hence a PBA slave port.
-///
-/// Another - perhaps obvious - complication has to do with PBA slave reset. A
-/// PORE engine executing from main memory can not modify the PBA slave read
-/// parameter setup, as this would corrupt the instruction stream.  Currently
-/// GPE procedures that need to modify the PBA read parameter setup execute
-/// from SRAM, and the SLW executing from main memeory never changes its read
-/// setup.
-///
-/// This structure is read-only to the GPE routines that access it.
-
-typedef struct {
-
-    /// The 32-bit OCI address of the PBA_SLVCTLn register to set up
-    uint64_t slvctl_address;
-
-    /// An image of the relevant parts of the PBA_SLVCTLn register in effect
-    /// for this procedure
-    pba_slvctln_t slvctl;
-
-    /// The mask in effect for this update of the PBA_SLVCTL
-    pba_slvctln_t mask;
-
-    /// The value to write to the PBA_SLVRST register to reset the slave
-    pba_slvrst_t slvrst;
-
-    /// The bit to AND-poll to check for slave reset in progress
-    pba_slvrst_t slvrst_in_progress;
-
-    /// The slave id (0 - 3)
-    uint64_t slave_id;
-
-} GpePbaParms;
-
-int
-gpe_pba_parms_create(GpePbaParms *parms,
-                     int slave,
-                     int write_ttype,
-                     int write_tsize,
-                     int read_ttype);
-
-#endif /* __ASSEMBLER__ */
-
-// Parameter offset for GpePbaParms
-
-#define GPEPBAPARMS_SLVCTL_ADDRESS     0x00
-#define GPEPBAPARMS_SLVCTL             0x08
-#define GPEPBAPARMS_MASK               0x10
-#define GPEPBAPARMS_SLVRST             0x18
-#define GPEPBAPARMS_SLVRST_IN_PROGRESS 0x20
-#define GPEPBAPARMS_SLAVE_ID           0x28        
-
-#define SIZEOF_GPEPBAPARMS 0x30
-
-
-// Flags for gpe_pba_parms_setup()
-
-#define GPE_PBA_PARMS_READ_INVALIDATE      0x01
-#define GPE_PBA_PARMS_DISABLE_WRITE_GATHER 0x02
-
-#endif  /* __GPE_H__ */
diff --git a/src/lib/gpe_pba_pgas.pS b/src/lib/gpe_pba_pgas.pS
deleted file mode 100755
index 346234d..0000000
--- a/src/lib/gpe_pba_pgas.pS
+++ /dev/null
@@ -1,110 +0,0 @@
-// $Id: gpe_pba_pgas.pS,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_pba_pgas.pS,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-        
-/// \file gpe_pba.pS
-/// \brief PBA subroutines for PORE-GPE procedures
-
-        .nolist
-#include "ssx.h"
-#include "pgas.h"
-#include "pgp_config.h"
-#include "gpe.h"
-#include "gpe_pba.h"
-        .list
-
-        .oci
-
-        .text.pore
-
-        // Reset a PBA slave from a GpePbaParms structure.  A setup sequence
-        // looks like
-        //
-        //     gpe_pba_reset
-        //     gpe_pba_setup
-        //
-        // The subroutine gpe_pba_reset can also be called by itself to insure
-        // that all write data has been flushed to mainstore.  
-        //
-        // Note that any PORE program that reads or writes Centaur will need
-        // to execute its code from SRAM since it is not possible to set up
-        // the slave for reading from Centaur while executing from main memory.
-        //
-        // Slave reset for PBA is a complex issue, especially in cases like
-        // this where the entity requesting the reset may be executing from
-        // main memory - i.e., continuing to read from the slave being
-        // reset.  To work around potential issues the code that polls for
-        // reset is PowerBus cache-line aligned, and we re-hit the reset
-        // button each time we get an unsuccessful poll for the reset being
-        // done.  This should guarantee that the slave will go to reset
-        // status as soon as any PowerBus blockages (if any) clear.  For
-        // details see HW228485.
-        //
-        // At entry :   
-        //
-        // A0 :  The (constant) address of the GpePbaParms structure
-        //
-        // Clobbered:   
-        //
-        // D0 :  scratched
-        // D1 :  scratched
-        // A1 :  Holds PBA_SLVRST
-
-        .global gpe_pba_reset
-
-        .balign 128
-gpe_pba_reset:  
-        la      A1, PBA_SLVRST
-        ld      D0, GPEPBAPARMS_SLVRST, A0
-        std     D0, 0, A1
-
-        ld      D0, GPEPBAPARMS_SLVRST_IN_PROGRESS, A0
-        ld      D1, 0, A1
-        and     D0, D0, D1
-        branz   D0, gpe_pba_reset
-        
-        ret
-
-        .epilogue gpe_pba_reset
-        
-
-        // Set up a PBA slave from a GpePbaParms structure.  A setup sequence
-        // looks like
-        //
-        //     gpe_pba_reset
-        //     gpe_pba_setup
-        //
-        // At entry :   
-        //
-        // A0 :  The (constant) address of the GpePbaParms structure
-        //
-        // Clobbered:   
-        //
-        // D0 :  scratch
-        // A1 :  Holds PBA_SLVCTL address for the indicated slave
-
-
-        .global gpe_pba_setup
-gpe_pba_setup:  
-        
-        // Write the new SLVCTL value under MASK
-        
-        ld      D0, GPEPBAPARMS_SLVCTL_ADDRESS, A0
-        mr      A1, D0
-
-        ld      D0, 0, A1
-        ld      D1, GPEPBAPARMS_MASK, A0
-        and     D0, D0, D1
-
-        ld      D1, GPEPBAPARMS_SLVCTL, A0
-        or      D0, D0, D1
-        
-        std     D0, 0, A1
-
-        ret
-
-        .epilogue gpe_pba_setup
diff --git a/src/lib/gpe_scom.h b/src/lib/gpe_scom.h
deleted file mode 100644
index 3f8f26e..0000000
--- a/src/lib/gpe_scom.h
+++ /dev/null
@@ -1,471 +0,0 @@
-#ifndef __GPE_SCOM_H__
-#define __GPE_SCOM_H__
-
-// $Id: gpe_scom.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_scom.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpe_scom.h
-/// \brief Generic SCOM procedures for PORE-GPE
-///
-/// We provide 2 generic SCOM procedures for PORE-GPE, one for P8 SCOMs and
-/// another for Centaur SCOMS. The setup and control of the procedures is
-/// roughly modeled after the way the simple SCOM-ing programs were described
-/// and implemented by the P7 OCA unit. This facility was written primarily to
-/// support SCOM-ing Centaur from OCC (which requires a complex setup),
-/// however for some core applications it may also be simpler to use a generic
-/// procedure rather than creating a custom GPE program to read/write P8 SCOM
-/// registers.
-///
-/// SCOM programs are set up and controlled through a GpeScomParms
-/// structure. This structure contains overall control and status information,
-/// as well as a pointer to an array of scomList_t structures which decribes
-/// the program. Each entry of the scomList_t describes one of several
-/// operations that can be performed on a SCOM address including read, write,
-/// and read-modify-write. Special control-only entries are also supported
-/// including a NOP, a programmable wait delay, timestamping with the TOD and
-/// special "SYNC" commands for Centaur. For more on the commands and their
-/// actions please see \ref gpe_scom_commands.
-///
-/// Each scomList_t entry also includes a data field and a mask field. The
-/// data field contains the data to write for SCOM writes and
-/// read-modify-writes, holds the data returned for SCOM reads, or contains a
-/// pointer to a data vector for vector commands. The mask is used in the case
-/// of read-modify-write to indicate which bits of the SCOM to modify. Control
-/// commands may also interpret these fields in different ways.
-
-
-#ifndef __ASSEMBLER__
-
-/// A SCOM command descriptor for gpe_scom_centaur amd gpe_scom_p8.
-///
-/// For an introduction to the use of this structure and the procedures that
-/// use please see the commants for the file gpe_scom.h
-///
-/// The \a scom field is the full 32-bit SCOM address of the targeted SCOM,
-/// initialized by the caller.  SCOM addresses for P8 core SCOMs can be
-/// created from the chiplet-0 address using the macro
-/// CORE_CHIPLET_ADDRESS(). Multicast addresses for P8 can be generated using
-/// the macro MC_ADDRESS(). The notions of internal "chiplets" and "multicast"
-/// are not supported for Centaur SCOM addreses, so for Centaur this is always
-/// a simple SCOM address. The procedure gpe_scom_centaur() does support an
-/// iterative notion of multicast however. Some special control commands do
-/// not use this field at all; see \ref gpe_scom_commands.
-///
-/// The \a errorFlags field contains error status associated with the
-/// (attempted) SCOM access.  This field is set by the procedure. For futher
-/// informaton on error handling please see each individual procedure.
-///
-/// The \a instanceNumber field is currently only used by
-/// gpe_scom_centaur(). For further details please see the documentation for
-/// gpe_scom_centaur(). 
-///
-/// The \a commandType field is initialized by the caller. For command
-/// documentation see \ref gpe_scom_commands and the individual procedures.
-///
-/// The \a data field is used to hold write data for SCOM write and
-/// read-modify-write commands (including the "all" forms), contains the
-/// returned read data for scalar SCOM read commands, and contains a pointer
-/// to a data vector for vector commands. Other commands may also use the \a
-/// data field for other purposes as documented with each command.
-///
-/// The \a mask field contains a positive bit mask used to identify the fields
-/// to update for SCOM read-modify-write. Other commands may also use the \a
-/// mask field for other purposes as documented with each command.
-///
-/// \note Because this structure is read and written by the GPE engine it is
-/// strongly recommended to allocate instances of this structure in
-/// non-cacheable data sections, with the caveat that data structures assigned
-/// to non-default data sections must always be initialized. For example:
-///
-/// \code
-///
-/// static scomList_t S_scomList[10] 
-///     SECTION_ATTRIBUTE(".noncacheable") = {0};
-///
-/// \endcode
-
-typedef struct {
-    union
-    {
-        struct {
-            uint32_t scom;
-            uint8_t reserved;
-            uint8_t errorFlags;
-            uint8_t instanceNumber;
-            uint8_t commandType;
-        };
-        uint64_t command;
-    };
-    uint64_t mask;
-    union
-    {
-        uint64_t data;
-        struct {
-            uint32_t unused;
-            uint64_t* pData;
-        };
-    };
-}  scomList_t;
-
-#else // __ASSEMBLER__
-
-        // scomList_t structure offsets
-
-        .set    SCOM_LIST_COMMAND,  0x0
-        .set    SCOM_LIST_MASK,     0x8
-        .set    SCOM_LIST_DATA,     0x10
-        .set    SIZEOF_SCOM_LIST_T, 0x18
-
-        // PGAS macros to extract fields of the scomList_t command. The source
-        // and target must be data registers, and they can be the same data
-        // register.
-
-        .macro  scom_list_get_scom, target:req, source:req
-        extrdi  \target, \source, 32, 0
-        .endm
-
-        .macro  scom_list_get_instance_number, target:req, source:req
-        extrdi  \target, \source, 8, 48
-        .endm
-
-        .macro  scom_list_get_command_type, target:req, source:req
-        extrdi  \target, \source, 8, 56
-        .endm
-
-        // PGAS macros to update fields of the scomList_t command. The source
-        // and target must be different data registers. The target is the
-        // current value and is updated with the new field held
-        // right-justified in the source. The source register is effectively
-        // destroyed by these operations.
-
-        .macro  scom_list_set_error_flags, target:req, source:req
-        insrdi  \target, \source, 8, 40
-        .endm
-
-        .macro  scom_list_set_instance_number, target:req, source:req
-        insrdi  \target, \source, 8, 48
-        .endm
-
-#endif // __ASSEMBLER__
-
-/// \defgroup gpe_scom_commands GPE SCOM Procedure Commands
-///
-/// \note Command 0 is not defined on purpose to trap errors.
-/// @{
-
-/// No operation
-#define GPE_SCOM_NOP 1
-
-/// Read from SCOM, depositing read data into the \a data field of the
-/// scomList_t.
-#define GPE_SCOM_READ 2
-
-/// Write to SCOM, taking write data from the \a data field of the scomList_t.
-#define GPE_SCOM_WRITE 3
-
-/// Read-Modify-Write.
-///
-/// This operation first reads the SCOM. Bits under the \a mask field of the
-/// scomList_t are then cleared in the read data. The masked read data is then
-/// ORed with the contents of the \a data field of the scomList_t and the
-/// result is written back to the SCOM address.
-///
-/// \note This command \e does \e not apply the mask to the data from the \a
-/// data field of the scomList_t. The caller should do this (if necessary)
-/// when setting up the scomList_t.
-///
-/// \note The procedures do not provide a way to distinguish errors that may
-/// have occurred on the initial read vs. those that may have occurred on the
-/// subsequenct write. 
-#define GPE_SCOM_RMW 4
-
-/// For gpe_scom_centaur(), the \a data field of the scomList_t contains a
-/// 32-bit pointer (cast to a uint64_t) to an array of PGP_NCENTAUR uint64_t
-/// values. SCOM read data for each configured Centaur (MCS) is deposited in
-/// this array.  Array entries for unconfigured Centaur are zeroed.
-#define GPE_SCOM_READ_VECTOR 5
-
-/// For gpe_scom_centaur(), write the \a data field of the scomList_t to
-/// all configured Centaur. Currently unsupported for gpe_scom_p8().
-#define GPE_SCOM_WRITE_ALL 6
-
-/// For gpe_scom_centaur(), perform read-modify write for all configured
-/// Centaur. Currently unsupported for gpe_scom_p8().
-#define GPE_SCOM_RMW_ALL 7
-
-/// Programmable wait delay
-///
-/// This command simply waits for an interval of time specified by the \a data
-/// field of the scomList_t. Use the macro GPE_SCOM_WAIT_DELAY() to convert
-/// SSX (OCC timebase) ticks into the correct units for this command.  For
-/// example use GPE_SCOM_WAIT_DELAY(SSX_MILLISECONDS(10)) to wait 10 ms.
-///
-/// \note This operation blocks the GPE from completing any other work until
-/// the delay is finished.
-///
-/// \note This time delay can not be implemented with extreme precision due to
-/// the lack of a programmable wait delay in the PORE architecture, plus
-/// procedure overhead, bus and bus interface contention, etc. For
-/// applications requiring extremely precise timing it will be best to code
-/// those by hand in PORE assembler and run them in a dedicated lab-only
-/// setting.
-#define GPE_SCOM_WAIT 8
-
-/// Issue a generic Centaur SYNC
-///
-/// This command is only valid for gpe_scom_centaur(). This command creates
-/// and issues a generic SYNC command to Centaur.  The caller is completely
-/// responsible for creating the contents of the data packet sent as part of
-/// the Centaur SYNC. The data packet is taken verbatim from the \a data field
-/// of the scomList_t, and sent to the MCS designated as the SYNC MCS in the
-/// global G_centaurConfiguration.  For further details see the comments with
-/// the procedure gpe_scom_centaur() and the CentaurConfiguration structure.
-#define GPE_SCOM_CENTAUR_SYNC 9
-
-/// Issue a Centaur SYNC to all configured Centaur
-///
-/// This command is only valid for gpe_scom_centaur(). This command creates
-/// and issues a SYNC command to all configured Centaur. The data packet is
-/// taken from the \a data field of the scomList_t, and sent to the MCS
-/// designated as the SYNC MCS in the global G_centaurConfiguration. The
-/// caller is responsible for setting the SYNC command bits (bits 8:N); The
-/// procedure will fill bits 0:7 with a mask of all configured Centaur.  For
-/// further details see the comments with the procedure gpe_scom_centaur() and
-/// the CentaurConfiguration structure.
-#define GPE_SCOM_CENTAUR_SYNC_ALL 10
-
-/// Read the TOD clock
-///
-/// This command reads the TOD clock and deposits the value into the \a data
-/// field of the scomList_t.
-#define GPE_SCOM_TOD 11
-
-/// @}
-
-
-#ifndef __ASSEMBLER__
-
-/// \defgroup centaur_sync_commands Centaur SYNC Command Bits
-///
-/// The Centaur SYNC command is an 8-byte word written to a specific in-band
-/// address. SYNC commands are generated by the gpe_scom_centaur() procedure
-/// in response to the GPE_SCOM_CENTAUR_SYNC and GPE_SCOM_CENTAUR_SYNC_ALL
-/// commands (which see).
-///
-/// \note From the MCS Unit Workbook: Note that only the N/M Throttle sync
-/// command will be used operationally in P-series, although if will be
-/// possible to test all the sync commands in P-series lab testing. Z-series
-/// will use all specified sync command types. ... Valid combinations of bits
-/// (8:15) are: b00000000, bVVVVVV0V, and b00000010, where V = 0 or 1.
-///
-/// @{
-
-#define CENTAUR_GENERATE_REFRESH_COUNTER_SYNC    0x0080000000000000ull
-#define CENTAUR_RESET_CALIBRATION_COUNTER_1_SYNC 0x0040000000000000ull
-#define CENTAUR_RESET_CALIBRATION_COUNTER_2_SYNC 0x0020000000000000ull
-#define CENTAUR_RESET_CALIBRATION_COUNTER_3_SYNC 0x0010000000000000ull
-#define CENTAUR_RESET_N_M_THROTTLE_COUNTER_SYNC  0x0008000000000000ull
-#define CENTAUR_RESET_MB_TIMEBASE_SYNC           0x0004000000000000ull
-#define CENTAUR_SUPER_SYNC                       0x0002000000000000ull
-#define CENTAUR_MYSTERY_SYNC                     0x0001000000000000ull
-
-/// \todo Figure out what is the "mystery sync"
-
-/// @}
-
-
-/// Convert an SsxInterval to a delay specification for gpe_scom_*()
-
-// Yes, Virginia, the PORE engine takes 20 cycles to decrement and branch :(
-#define GPE_SCOM_WAIT_DELAY(x) ((x) / 20)
-
-
-/// Parameters for gpe_scom_centaur() and gpe_scom_p8().
-///
-/// A pointer to an initialized GpeScomParms structure is passed as the
-/// parameter to the GPE procedures gpe_scom_centaur() and gpe_scom_p8.
-///
-/// \note Because this structure is read and written by the GPE engine it is
-/// strongly recommended to allocate instances of this structure in
-/// non-cacheable data sections, with the caveat that data structures assigned
-/// to non-default data sections must always be initialized. For example:
-///
-/// \code
-///
-/// static GpeScomParms S_scomParms 
-///     SECTION_ATTRIBUTE(".noncacheable") = {0};
-///
-/// \endcode
-
-typedef struct {
-
-    /// Input: The SCOM list
-    ///
-    /// This is a right-justfied pointer to an array of scomList_t structures
-    /// describing the sequence of commands to execute.
-    uint64_t scomList;
-
-    /// Input: The number of entries in the scomList.
-    ///
-    /// \note It is considered an error if \a entries is 0, under the
-    /// assumption that the caller must have neglected to initialize the
-    /// structure.
-    uint32_t entries;
-
-    /// Input: Procedure options
-    ///
-    /// An OR-mask of option flags; See \ref gpe_scom_options;
-    uint32_t options;
-
-    /// Output: The procedure return code
-    ///
-    /// This field will contain 0 in the event of a successful return, and a
-    /// non-zero value in the event of an error. See \ref gpe_scom_rc for
-    /// documentation of the possible return codes.
-    uint32_t rc;
-
-    /// Output: The index of the entry that failed
-    ///
-    /// In the event that \a rc != 0, this field will contain the 0-based
-    /// index of the \a scomList entry that was being processed at the time of
-    /// the failure, or -1 for failures associated with the parameters or
-    /// setup of the procedure.
-    int32_t errorIndex;
-
-} GpeScomParms;
-
-#else // __ASSEMBLER__
-
-        // Offsets into the GpeScomParms structure
-
-        .set    GPE_SCOM_PARMS_SCOM_LIST,       0x00
-        .set    GPE_SCOM_PARMS_ENTRIES_OPTIONS, 0x08
-        .set    GPE_SCOM_PARMS_RC_ERROR_INDEX,  0x10
-
-        // PGAS macros to extract fields of the GpeScomParms. The source
-        // and target must be data registers, and they can be the same data
-        // register.
-
-        .macro  gpe_scom_parms_get_entries, target:req, source:req
-        extrdi  \target, \source, 32, 0
-        .endm
-
-        .macro  gpe_scom_parms_get_options, target:req, source:req
-        extrdi  \target, \source, 32, 32
-        .endm
-
-        .macro  gpe_scom_parms_get_rc, target:req, source:req
-        extrdi  \target, \source, 32, 0
-        .endm
-
-        // PGAS macros to update fields of the GpeScomParms. The source
-        // and target must be different data registers. The target is the
-        // current value and is updated with the new field held
-        // right-justified in the source. The source register is effectively
-        // destroyed by these operations.
-
-        .macro  gpe_scom_parms_set_rc, target:req, source:req
-       insrdi   \target, \source, 32, 0
-        .endm
-
-        .macro  gpe_scom_parms_set_error_index, target:req, source:req
-        insrdi  \target, \source, 32, 32
-        .endm
-
-#endif // __ASSEMBLER__
-
-        
-/// \defgroup gpe_scom_rc Return Codes From GPE SCOM Procedures
-///
-/// @{
-
-/// Successful completion of a GPE SCOM program
-#define GPE_SCOM_SUCCESS 0
-
-/// An error occurred during setup of the PBA for Centaur access. If this
-/// error code is returned then the \a errorIndex field of the GpeScomParms
-/// structure will be set to -1.
-#define GPE_SCOM_SETUP_ERROR 1
-
-/// One of the fields of the GpeScomParms structure is invalid. In the case of
-/// gpe_scom_centaur(), this code may also be returned if there is a problem
-/// with the global structure G_centaurConfiguration.  If this error code is
-/// returned then the \a errorIndex field of the GpeScomParms structure will
-/// be set to -1 if the error occurred before command processing begins. 
-#define GPE_SCOM_INVALID_ARGUMENT 2
-
-/// The procedure died. Since GPE procedures do not trap errors by default
-/// they will typically die on the first hardware-detected error, and GPE
-/// error recovery procedures will clean up the failed job. If this error code
-/// is returned then the \a errorIndex field of the GpeScomParms structure
-/// will indicate the \a scomList entry being processed at the time of the
-/// failure.
-#define GPE_SCOM_DIED 3
-
-/// The \a commandType field of the scomList_t was not valid for the procedure.
-/// When this error is signalled then the \a errorIndex field of the
-/// GpeScomParms structure contains the index of the failing entry.
-#define GPE_SCOM_INVALID_COMMAND 4
-
-/// Signalled only by gpe_scom_centaur(), the \a instanceNumber field of the
-/// scomList_t did not index a valid (configured) Centaur. This error is only
-/// signalled by the GPE_SCOM_READ, GPE_SCOM_WRITE and GPE_SCOM_RMW commands
-/// that require a valid Centaur to be specified. When this error is signalled
-/// then the \a errorIndex field of the GpeScomParms structure contains the
-/// index of the failing entry.
-#define GPE_SCOM_INVALID_CENTAUR 5
-
-/// @}
-
-
-/// Execute a SCOM program for Centaur SCOMs
-///
-/// \param[in,out] io_parms A pointer to an initialized GpeScomParms
-/// structure. Since this structure is used both for input of parameterization
-/// and output of return codes it is imperitive that this structure is
-/// allocated in non-cacheable memory to avoid cache-related bugs.  See the
-/// documentation for the fields of GpeScomParms for more information.
-///
-/// gpe_scom_centaur() is a GPE program that takes a pointer to an initialized
-/// GpeScomParms structure as input and executes the list of SCOMs and other
-/// commands. Return codes are returned in the GpeScomParms.
-///
-/// The following notes relate to the fields of the scomList_t structure when
-/// used by gpe_scom_centaur().
-///
-/// - \a instanceNumber : This field must be set to the index (0 - 7) of the
-/// Centaur (MCS) to access for the commands GPE_SCOM_READ, GPE_SCOM_WRITE and
-/// GPE_SCOM_RMW. This field is ignored by other commands.
-///
-/// - \a commandType : gpe_scom_centaur() supports the special command types
-/// GPE_SCOM_CENTAUR_SYNC and GPE_CENTAUR_SYNC_ALL as documented in \ref
-/// gpe_scom_commands.
-///
-/// - \a data : The commands GPE_SCOM_CENTAUR_SYNC and
-/// GPE_SCOM_CENTAUR_SYNC_ALL require a unique format for the \a data field as
-/// documented with the command.
-#ifdef DOXYGEN_ONLY
-void gpe_scom_centaur(GpeScomParms *io_parms);
-#endif
-
-#ifndef __ASSEMBLER__
-
-// Procedure entry points
-
-PoreEntryPoint gpe_scom_centaur;
-PoreEntryPoint gpe_scom_p8;
-
-// Debugging symbols
-
-extern uint64_t G_gsc_lastSlaveControl SECTION_ATTRIBUTE(".data.pore");
-extern uint64_t G_gsc_lastScomAddress  SECTION_ATTRIBUTE(".data.pore");
-extern uint64_t G_gsc_lastOciAddress   SECTION_ATTRIBUTE(".data.pore");
-
-#endif // __ASSEMBLER__
-
-#endif // __GPE_SCOM_H__
diff --git a/src/lib/gpe_scom.pS b/src/lib/gpe_scom.pS
deleted file mode 100644
index 2df1b78..0000000
--- a/src/lib/gpe_scom.pS
+++ /dev/null
@@ -1,709 +0,0 @@
-// $Id: gpe_scom.pS,v 1.2 2013/12/13 23:04:33 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpe_scom.pS,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-        
-/// \file gpe_scom.pS
-/// \brief Generic SCOM procedures for PORE-GPE
-
-        .nolist
-
-#include "ssx.h"
-#include "pgas.h"
-#include "pgp_config.h"
-#include "gpe.h"
-#include "gpe_pba.h"
-#include "gpe_scom.h"
-
-        .list
-
-        .oci
-        .text.pore
-
-        
-//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-// Common Routines
-//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gsWait
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // The wait loop is implemented as a decrement and branch guaranteed
-        // to hit in the I-cache. This is used both by gpe_scom_centaur() and
-        // gpe_scom_p8(). 
-gsWait:
-        ld      D0, SCOM_LIST_DATA, A1
-        braz    D0, gsWaitDone
-        bra     gsWaitLoop
-
-        .set    PORE_INSTRUCTION_BUFFER_SIZE, 8 # Should be global?
-        .balign PORE_INSTRUCTION_BUFFER_SIZE
-gsWaitLoop:
-        subs    D0, D0, 1
-        branz   D0, gsWaitLoop
-
-gsWaitDone:
-        ret
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gsTod
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-gsTod:
-        lpcs    P0, TOD_VALUE_REG
-        ld      D0, TOD_VALUE_REG, P0
-        std     D0, SCOM_LIST_DATA, A1
-        ret
-        
-
-//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-// gpe_scom_centaur
-//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-// gpe_scom_centaur() has 2 entry points: The first, gpe_scom_centaur(), is for
-// the "normal" case that the job is kicked off by the async drivers.  The
-// second, _gpe_scom_centaur() is for use as a subroutine call.
-
-// Implementation note: Correctness requires that gpe_scom_centaur() maintins
-// strict control over the PBA slave as the command list is processed. At
-// entry the slave is reset, and then set up to do the cache-inibited partial
-// writes used for Centaur inband SCOM. Prior to every access the extended
-// address portion of the slave control register needs to be modified as it
-// contains part of the address that actually goes out on the PowerBus.  For
-// reads there is no issue with setting the extended address at any
-// time. Since cache-inhibited partial reads are not prefetched, once a read
-// completes to the GPE the extended address is no longer in play.  This is
-// not the case for writes. Just because a write completes on the OCI does not
-// mean that the write has completed at Centaur, and it is possible that
-// modifying the extended address before the write completes at Centaur can
-// cause a write to be corrrupted.  The means that in general we need to reset
-// the slave prior to modifying the extended address to guarantee that any
-// outstanding write has made it to Centaur. As a run-time optimization we
-// only reset the slave after doing write operations.
-
-// At entry (gpe_scom_centaur):
-//
-//     ETR : Contains a pointer to the GpeScomParms structure to interpret.
-//
-// At entry (_gpe_scom_centaur):
-//
-//     A0  : Contains a pointer to the GpeScomParms structure to interpret.
-//
-//     The caller should assume that all register state is destroyed by
-//     calling _gpe_scom_centaur
-
-        .macro  gscExit
-        la      A0, gscCalledAsSubroutine
-        ld      D0, 0, A0
-        braz    D0, 4723948f
-        ret
-4723948:
-        halt
-        .endm
-
-
-        .global gpe_scom_centaur
-        .global _gpe_scom_centaur
-
-gpe_scom_centaur:
-        mr      D0, ETR
-        ls      D1, 0
-        bra     gpe_scom_centaur_begin
-
-_gpe_scom_centaur:
-        mr      D0, A0
-        ls      D1, 1
-
-gpe_scom_centaur_begin:
-        la      A0, gscParameters
-        std     D0, 0, A0
-        la      A0, gscCalledAsSubroutine
-        std     D1, 0, A0
-        mr      A1, D0
-
-        // Establish the "invalid argument" return code and check that the
-        // global centaur configuration is valid and the number of entries is
-        // non-zero and the pointer to the scomList is non-zero.
-
-        la      A0, G_centaurConfiguration
-
-        ls      D0, GPE_SCOM_INVALID_ARGUMENT
-        gpe_scom_parms_set_rc D1, D0
-        ls      D0, -1
-        gpe_scom_parms_set_error_index D1, D0
-        std     D1, GPE_SCOM_PARMS_RC_ERROR_INDEX, A1
-
-        ld      D0, CENTAUR_CONFIGURATION_CONFIG_RC, A0
-        braz    D0, 1f
-        gscExit                    # Configuration RC != 0 (Structure is invalid)
-
-1:
-        ld      D0, GPE_SCOM_PARMS_ENTRIES_OPTIONS, A1
-        gpe_scom_parms_get_entries D1, D0
-        branz   D1, 1f
-        gscExit                    # entries == 0
-
-1:      
-        ld      D0, GPE_SCOM_PARMS_SCOM_LIST, A1
-        branz   D1, 1f
-        gscExit                    # scomList == 0
-
-1:
-        // Establish the "setup error" return code and error index for the PBA
-        // Slave reset, then reset the slave. 
-        //
-        // At entry:
-        //
-        //     A0 = &G_centaurConfiguration
-        //     A1 = &GpeScomParms
-
-        ls      D0, GPE_SCOM_SETUP_ERROR
-        gpe_scom_parms_set_rc D1, D0
-        ls      D0, -1
-        gpe_scom_parms_set_error_index D1, D0
-        std     D1, GPE_SCOM_PARMS_RC_ERROR_INDEX, A1
-        
-        adds    A0, A0, CENTAUR_CONFIGURATION_SCOM_PARMS
-        bsr     gpe_pba_reset
-        bsr     gpe_pba_setup
-
-
-        // Establish the "procedure died" return code, establish variables
-        // used during the iteration over the scomList, then begin iteration:
-        //
-        // GpeScomParms.[rc, errorIndex]
-        // CTR         : The number of entries left to process.
-        // A1          : The address of the scomList_t being processed
-
-        la      A0, gscParameters
-        ld      D0, 0, A0
-        mr      A0, D0
-
-        ls      D0, GPE_SCOM_DIED
-        gpe_scom_parms_set_rc D1, D0
-        ls      D0, 0
-        gpe_scom_parms_set_error_index D1, D0
-        std     D1, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-
-        ld      D0, GPE_SCOM_PARMS_SCOM_LIST, A0
-        mr      A1, D0
-
-        ld      D0, GPE_SCOM_PARMS_ENTRIES_OPTIONS, A0
-        gpe_scom_parms_get_entries D0, D0
-        mr      CTR, D0
-        loop    gscLoop         # We know CTR != 0, so this is a branch to
-                                # gscLoop w/side effect of CTR--
-
-        // Loop over the scomList, dispatching the commands.  
-        //
-        // Loop invariants:
-        //
-        //     GpeScomParms.entries has the number of entries processed so
-        //     far.
-        //
-        //     A1  : The address of the scomList_t being processed
-        //
-        //     CTR : Counting down the entries left to process.
-        //
-        // Command dispatch invariants
-        //
-        //     A1 : Holds the pointer to the scomList being processed
-gscLoop:
-        ld      D1, SCOM_LIST_COMMAND, A1
-        scom_list_get_command_type D0, D1
-
-        // Commands listed in rough order of expected use
-
-        cmpibraeq D0, gscReadVector,  GPE_SCOM_READ_VECTOR
-        cmpibraeq D0, gscWriteAll,    GPE_SCOM_WRITE_ALL
-        cmpibraeq D0, gscRMWAll,      GPE_SCOM_RMW_ALL
-        cmpibraeq D0, gscRead,        GPE_SCOM_READ
-        cmpibraeq D0, gscSyncAll,     GPE_SCOM_CENTAUR_SYNC_ALL
-        cmpibraeq D0, gscWrite,       GPE_SCOM_WRITE
-        cmpibraeq D0, gscRMW,         GPE_SCOM_RMW
-        cmpibraeq D0, gscSync,        GPE_SCOM_CENTAUR_SYNC
-        cmpibraeq D0, gscTod,         GPE_SCOM_TOD
-        cmpibraeq D0, gscWait,        GPE_SCOM_WAIT
-        cmpibraeq D0, gscContinue,    GPE_SCOM_NOP
-
-        bra     gscInvalidCommand
-
-
-        // Continue the loop. Update the index number and scomList pointer.
-gscContinue:
-        la      A0, gscParameters
-        ld      D0, 0, A0
-        mr      A0, D0
-
-        ld      D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-        adds    D0, D0, 1       # errorIndex is in low-order word
-        std     D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-
-        adds    A1, A1, SIZEOF_SCOM_LIST_T
-
-        loop    gscLoop
-
-        // We completed successfully. Set the final rc to 0 and halt.
-
-        ls      D0, 0
-        std     D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-        gscExit
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscWrite
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // Do a single Centaur in-band SCOM write.  The actual SCOM write is
-        // coded as a subroutine for use by the write-all as well.
-gscWrite:
-        ld      D0, SCOM_LIST_COMMAND, A1
-        scom_list_get_instance_number D0, D0
-        bsr     gscScomSetup
-        branz   D0, gscInvalidCentaur
-
-        bsr     gscWrite1
-        bsr     gscResetSlave
-        bra     gscContinue
-        
-
-gscWrite1:      
-        ld      D0, SCOM_LIST_DATA, A1
-        std     D0, 0, A0
-        ret
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscWriteAll
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // It is simplest here to simply unroll a loop that does the SCOM
-        // write for all Centaur indices that pass as being valid.
-gscWriteAll:
-        .set     __CENTAUR__, 0
-        .rept    PGP_NCENTAUR
-                ls      D0, __CENTAUR__
-                bsr     gscScomSetup
-                branz   D0, 1f
-                        bsr     gscWrite1
-                        bsr     gscResetSlave
-1:      
-               .set    __CENTAUR__, __CENTAUR__ + 1
-        .endr
-
-        bra     gscContinue
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscRMW
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // Do a single Centaur in-band SCOM read-modify-write. SCOM data is
-        // ANDed with the inverted mask, then the new data is OR-ed in and
-        // stored back to SCOM. The actual RMW is coded as a subroutine for
-        // use by the RMW-all as well.
-gscRMW:
-        ld      D0, SCOM_LIST_COMMAND, A1
-        scom_list_get_instance_number D0, D0
-        bsr     gscScomSetup
-        branz   D0, gscInvalidCentaur
-
-        bsr     gscRMW1
-        bsr     gscResetSlave                
-        bra     gscContinue
-
-
-gscRMW1:        
-        ld      D0, 0, A0
-        ld      D1, SCOM_LIST_MASK, A1
-        xori    D1, D1, 0xffffffffffffffff
-        and     D0, D0, D1
-        ld      D1, SCOM_LIST_DATA, A1
-        or      D0, D0, D1
-        std     D0, 0, A0
-        
-        ret                
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscRMWAll
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // It is simplest here to simply unroll a loop that does the SCOM
-        // RMW for all Centaur indices that pass as being valid.
-gscRMWAll:
-        .set     __CENTAUR__, 0
-        .rept    PGP_NCENTAUR
-                ls      D0, __CENTAUR__
-                bsr     gscScomSetup
-                branz   D0, 1f
-                        bsr     gscRMW1
-                        bsr     gscResetSlave
-1:      
-               .set    __CENTAUR__, __CENTAUR__ + 1
-        .endr
-
-        bra     gscContinue
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscRead
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // Do a single Centaur in-band SCOM read
-gscRead:
-        ld      D0, SCOM_LIST_COMMAND, A1
-        scom_list_get_instance_number D0, D0
-        bsr     gscScomSetup
-        branz   D0, gscInvalidCentaur
-
-        ld      D0, 0, A0
-        std     D0, SCOM_LIST_DATA, A1
-        bra     gscContinue
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscReadVector
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // It is simplest here to simply unroll a loop that does the SCOM
-        // read for all Centaur indices that pass as being valid.
-gscReadVector:
-        .set     __CENTAUR__, 0
-        .rept    PGP_NCENTAUR
-                ls      D0, __CENTAUR__
-                bsr     gscScomSetup
-                ls      D1, __CENTAUR__ * 8 # Byte offset
-                bsr     gscReadVector1
-               .set    __CENTAUR__, __CENTAUR__ + 1
-        .endr
-
-        bra     gscContinue
-
-
-gscReadVector1: 
-        // At entry, A1 points to the scomList_t, and D1 has the index of the
-        // Centaur being processed.  If D0 == 0 then the read is indicated and
-        // A0 contains the address to dereference to accomplish the read. If
-        // D0 != 0, then the Centaur is invalid and we'll zero the data.
-
-        braz    D0, 1f
-
-        // No read indicated.  Load the data pointer, convert to an indexed
-        // address and store a 0. We can scratch A0 here.
-
-        ld      D0, SCOM_LIST_DATA, A1
-        add     D0, D0, D1
-        mr      A0, D0
-        ls      D0, 0
-        std     D0, 0, A0
-        ret     
-        
-        // A read is indicated.   Load the data pointer and convert to an
-        // indexed address in D1. Then load the SCOM data into D0 and store it
-        // back at the indexed address.
-1:      
-        ld      D0, SCOM_LIST_DATA, A1
-        add     D1, D0, D1
-        ld      D0, 0, A0
-        mr      A0, D1
-        std     D0, 0, A0
-        ret
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscSync
-        // gscSyncAll
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // These commands only differ in whether the user fills in the mask of
-        // valid Centaurs or the procedure fills in the mask of valid Centaurs
-        // from the global configuration.  The extended address needed for the
-        // sync is stored in the global data structure, and it is only
-        // necessary to update the slave and store to the base address of the
-        // PBA BAR to accomplish the SYNC.
-gscSync:
-        bsr     gscSyncSetup
-        ld      D0, SCOM_LIST_DATA, A1
-        bra     gscSyncContinue
-        
-gscSyncAll:
-        bsr     gscSyncSetup
-        la      A0, G_centaurConfiguration
-        ld      D0, CENTAUR_CONFIGURATION_CONFIG, A0
-        left_justify_centaur_config D0
-        ld      D1, SCOM_LIST_DATA, A1 
-        or      D0, D0, D1
-        bra     gscSyncContinue
-        
-
-        // To set up the SYNC we only have to update the extended address
-        // field (bits 35:48) of the slave control register from the slave
-        // control register image held in the G_centaurConfiguration. We can't
-        // destroy A1 so it's a little tedious as we have to load the slave
-        // control register address twice.
-gscSyncSetup:
-        la      A0, G_centaurConfiguration
-        ld      D1, \
-                (CENTAUR_CONFIGURATION_SCOM_PARMS + \
-                GPEPBAPARMS_SLVCTL_ADDRESS), \
-                A0
-        mr      A0, D1
-        ld      D0, 0, A0
-
-        la      A0, G_centaurConfiguration
-        ld      D1, CENTAUR_CONFIGURATION_SYNC_SLAVE_CONTROL, A0
-        rldimi  D0, D1, 0, 35, 48
-
-        la      A0, G_centaurConfiguration
-        ld      D1, \
-                (CENTAUR_CONFIGURATION_SCOM_PARMS + \
-                GPEPBAPARMS_SLVCTL_ADDRESS), \
-                A0
-        mr      A0, D1
-        std     D0, 0, A0
-
-        ret
-
-        
-        // Once it's set up, simply issue a store to complete the sync.  The
-        // caller has placed the correct data in D0.
-gscSyncContinue:
-        la      A0, (PBA_BAR_CENTAUR << 28)
-        std     D0, 0, A0
-        bsr     gscResetSlave
-        bra     gscContinue   
-        
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscWait
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-gscWait:        
-        bsr     gsWait
-        bra     gscContinue
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscTod
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-gscTod:        
-        bsr     gsTod
-        bra     gscContinue
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscScomSetup
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // At entry:    
-        //
-        //     A1 : The address of the scomList_t being processed
-        //     D0 : The Centaur instance number to set up
-        //
-        // At exit:     
-        //
-        //     PBA : Programmed to do the SCOM
-        //     A1  : The address of the scomList_t being processed
-        //     A0  : On success, the OCI address to load/store to do the SCOM
-        //     D0  : 0 = Success, otherwise an error code
-        //     
-        // This routine checks the Centaur instance number for validity.  If
-        // the instance number is valid then the PBA is programmed to access
-        // the SCOM address held in the scomList_t.  This requires
-        // reprogramming the PBA because part of the SCOM address must be
-        // stored as the extended address field of the PBA slave control
-        // register. It is not necessary to reset the PBA slave for each SCOM
-        // operation. The way SCOM operations are set up they "complete
-        // immediately" in the PBA so there is no issue with lingering state.
-        //
-        // Note:  this routine is written this way (separating setup from
-        // execution) to support the Centaur "multicast" and read-modify-write
-        // operations. The multicast loop simply tries all Centaur and ignores
-        // the ones that fail.
-gscScomSetup: 
-        
-        // Check the Centaur instance number (D0) for validity.
-
-        ls      D1, PGP_NCENTAUR
-        sub     D1, D0, D1
-        tfbult  D1, 1f
-
-        ls      D0, GPE_SCOM_INVALID_ARGUMENT
-        ret                     # Centaur instance too big
-
-1:
-        // Check to make sure the Centaur is configured by testing the base
-        // address for 0. The instance number is first multiplied by 8 to
-        // create an array offset.
-
-        rotldi  D0, D0, 3
-        la      D1, G_centaurConfiguration
-        adds    D1, D1, CENTAUR_CONFIGURATION_BASE_ADDRESS
-        add     D0, D0, D1
-        mr      A0, D0
-        ld      D0, 0, A0
-        branz   D0, 1f
-
-        ls      D0, GPE_SCOM_INVALID_ARGUMENT
-        ret                     # Base address is 0
-
-1:
-        // We have the Centaur base address in D0, and convert it to the full
-        // PowerBus address for the inband SCOM. Bit 27 is set to indicate OCC
-        // (vs. FSP) access. Bit 28 remains 0 to indicate a SCOM (vs. sensor
-        // cache) access. Bits 29:60 are the SCOM address. (The SCOM address
-        // is shifted up by 3 bit positions). We need to save A1 to SPRG0 to
-        // continue from here.
-
-        ori     D0, D0, 0x0000001000000000
-        ld      D1, SCOM_LIST_COMMAND, A1
-        scom_list_get_scom D1, D1
-        rotldi  D1, D1, 3
-        or      D0, D0, D1
-
-        mr      SPRG0, A1
-
-#if 1
-        la      A1, G_gsc_lastScomAddress # Debug
-        std     D0, 0, A1
-#endif
-
-        // The low-order 27 bits of the PowerBus address are OR-ed with the
-        // PBA BAR base address and go into A0 as the returned OCI address.
-
-        andi    D1, D0, 0x7ffffff
-        ori     D1, D1, (PBA_BAR_CENTAUR << 28)
-        mr      A0, D1
-
-        // Bits 23:36 of the address go into the extended address field (35:
-        // 48) of the PBA slave control register by a read-modify-write
-        // operation. Note: We're using rldimi explicitly here - not an
-        // extended mnemonic - to save having to justify the data.
-
-        la      A1, G_centaurConfiguration
-        ld      D1, \
-                (CENTAUR_CONFIGURATION_SCOM_PARMS + \
-                 GPEPBAPARMS_SLVCTL_ADDRESS), \
-                 A1
-        mr      A1, D1
-        ld      D1, 0, A1
-        rldimi  D1, D0, 64 - (35 - 23), 35, 48
-        std     D1, 0, A1
-
-#if 1
-        la      A1, G_gsc_lastSlaveControl # Debug
-        std     D1, 0, A1
-        mr      D1, A0
-        la      A1, G_gsc_lastOciAddress
-        std     D1, 0, A1
-#endif
-        
-        // Restore A1 to its invariant state, clear D0 to signal success and 
-        // we're out
-
-        mr      A1, SPRG0
-        ls      D0, 0
-        ret
-                 
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscResetSlave
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // Reset the PBA slave after a write. This requires saving and
-        // restoring A1. To avoid PORE stack overflow we have to inline
-        // gpe_pba_reset() here.  See the file gpe_pba_pgas.pS for comments on
-        // why the slave reset is written like this.
-
-gscResetSlave:
-        la      A0, gscSaveA1
-        mr      D0, A1
-        std     D0, 0, A0
-
-        la      A0, G_centaurConfiguration + CENTAUR_CONFIGURATION_SCOM_PARMS
-        bra     gscGpePbaReset
-
-        .balign 128
-gscGpePbaReset:
-                la      A1, PBA_SLVRST
-                ld      D0, GPEPBAPARMS_SLVRST, A0
-                std     D0, 0, A1
-
-                ld      D0, GPEPBAPARMS_SLVRST_IN_PROGRESS, A0
-                ld      D1, 0, A1
-                and     D0, D0, D1
-        branz   D0, gscGpePbaReset
- 
-        la      A0, gscSaveA1
-        ld      D0, 0, A0
-        mr      A1, D0
-
-        ret
-
-
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gscInvalidCommand
-        // gscInvalidCentaur
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        //
-        // Set the rc field.  The errorIndex has already been set.
-
-gscInvalidCommand:
-        ls      D1, GPE_SCOM_INVALID_COMMAND
-        bra     1f
-gscInvalidCentaur:      
-        ls      D1, GPE_SCOM_INVALID_CENTAUR
-1:      
-        la      A0, gscParameters
-        ld      D0, 0, A0
-        mr      A0, D0
-
-        ld      D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-        gpe_scom_parms_set_rc D0, D1
-        std     D0, GPE_SCOM_PARMS_RC_ERROR_INDEX, A0
-        gscExit
-
-        
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-        // gpe_scom_centaur Global Data
-        //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-        .data.pore
-
-        // Set to 0/1 when gpe_scom_centaur() is called via
-        // gpe_scom_centaur (ASYNC) / _gpe_scom_centaur (Subroutine)
-
-gscCalledAsSubroutine:  
-        .quad   0
-
-
-        // Used to store the parameter block pointer
-
-gscParameters:
-        .quad   0
-
-
-        // Used to store A1 during the inner loop when we need to reset the
-        // slave after a write
-
-gscSaveA1:
-        .quad   0
-
-
-        // Debug only, the last values computed by gscScomSetup.
-        
-        .global G_gsc_lastSlaveControl
-G_gsc_lastSlaveControl:
-        .quad   0
-
-        .global G_gsc_lastScomAddress
-G_gsc_lastScomAddress:
-        .quad   0
-
-        .global G_gsc_lastOciAddress
-G_gsc_lastOciAddress:
-        .quad   0
diff --git a/src/lib/gpsm.c b/src/lib/gpsm.c
deleted file mode 100755
index e2b71d6..0000000
--- a/src/lib/gpsm.c
+++ /dev/null
@@ -1,600 +0,0 @@
-// $Id: gpsm.c,v 1.2 2014/02/03 01:30:24 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpsm.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpsm.c
-/// \brief Global Pstate Mechanism procedures
-///
-/// \todo : Should we initialize any/all iVRM delays in gpsm_lpsa_install()?
-
-#include "ssx.h"
-#include "pstates.h"
-#include "gpe_control.h"
-#include "gpsm.h"
-#include "vrm.h"
-
-/// The semaphore used to block threads waiting for GPSM protocol actions
-
-SsxSemaphore G_gpsm_protocol_semaphore;
-
-
-////////////////////////////////////////////////////////////////////////////
-// Private Utilities
-////////////////////////////////////////////////////////////////////////////
-
-// The mechanical transition to Firmware Pstate Mode - Not a procedure
-
-static void
-_gpsm_fw_mode(void)
-{
-    pmc_mode_reg_t pmr;
-
-    pmr.value = in32(PMC_MODE_REG);
-    pmr.fields.enable_hw_pstate_mode = 0;
-    pmr.fields.enable_fw_auction_pstate_mode = 0;
-    pmr.fields.enable_fw_pstate_mode = 1;
-    out32(PMC_MODE_REG, pmr.value);
-}
-
-
-// The mechanical transition to Firmware Auction Pstate Mode - Not a procedure
-
-static void
-_gpsm_fw_auction_mode(void)
-{
-    pmc_mode_reg_t pmr;
-
-    pmr.value = in32(PMC_MODE_REG);
-    pmr.fields.enable_hw_pstate_mode = 0;
-    pmr.fields.enable_fw_auction_pstate_mode = 1;
-    pmr.fields.enable_fw_pstate_mode = 0;
-    out32(PMC_MODE_REG, pmr.value);
-}
-
-
-// The mechanical transition to Hardware Pstate Mode - Not a procedure.
-// Disable voltage change via safe_mode_without_spivid 
-// before enter hw mode to prevent possible glitch that 
-// hw momentarily flush turbo to pstate actual, 
-// After enter hw mode, we will enable back the spivid
-
-static void
-_gpsm_hw_mode(void)
-{
-    pmc_mode_reg_t pmr;
-
-    if (!gpsm_dcm_slave_p()) {
-        pmr.value = in32(PMC_MODE_REG);
-        pmr.fields.safe_mode_without_spivid = 1;
-        out32(PMC_MODE_REG, pmr.value);
-    }
-
-    pmr.value = in32(PMC_MODE_REG);
-    pmr.fields.enable_hw_pstate_mode = 1;
-    pmr.fields.enable_fw_auction_pstate_mode = 0;
-    pmr.fields.enable_fw_pstate_mode = 0;
-    out32(PMC_MODE_REG, pmr.value);
-
-    if (!gpsm_dcm_slave_p()) {
-        pmr.value = in32(PMC_MODE_REG);
-        pmr.fields.safe_mode_without_spivid = 0;
-        out32(PMC_MODE_REG, pmr.value);
-    }
-
-}
-
-    
-////////////////////////////////////////////////////////////////////////////
-// Private Sub-Procedures
-////////////////////////////////////////////////////////////////////////////
-
-// By definition, quiescing the GPSM always leaves the system in firmware
-// Pstate mode.  This is necessary for a consistent specification due to the
-// fact that in general, Hardware Pstate mode can not be quiesced without
-// leaving that mode.
-
-// To quiesce the GPSM in firmware or firmware auction mode requires waiting
-// for both the voltage and frequency changes to be complete.  Note that they
-// will never be ongoing simultaneously. This predicate is used for all
-// firmware-mode quiesce, even though normally only one part or the other
-// (voltage/protocol) is active.
-//
-// Recall that PMC interrupts are level-low, so if ongoing status is clear,
-// the operation is ongoing.
-
-static int
-gpsm_fw_quiesce(void)
-{
-    int rc = 0;
-    
-    if (!ssx_irq_status_get(PGP_IRQ_PMC_PROTOCOL_ONGOING)) {
-        ssx_irq_enable(PGP_IRQ_PMC_PROTOCOL_ONGOING);
-        rc = ssx_semaphore_pend(&G_gpsm_protocol_semaphore, SSX_WAIT_FOREVER);
-    }
-
-    if ((!rc) && !ssx_irq_status_get(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING)) {
-        ssx_irq_enable(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING);
-        rc = ssx_semaphore_pend(&G_gpsm_protocol_semaphore, SSX_WAIT_FOREVER);
-    }
-
-    if (!rc) {
-        _gpsm_fw_mode();
-    }
-
-    return rc;
-}
-
-
-// To quiesce the GPSM in hardware mode requires waiting for any ongoing
-// Pstate change to be complete.  Note that there is no guarantee that this
-// condition will ever be true in general unless something external to PMC
-// ensures that Global bids stop coming in to the GPSM.  An alternative used
-// here is to 'lock' the GPSM temporarily by setting the rail bounds min and
-// max to the current Global Pstate Actual.  The GPSM will eventually quiesce
-// at the global actual, and we can safely move to Firmware Pstate mode and
-// release the lock.
-//
-// Recall that PMC 'ongoing' interrupts are level-low, so if ongoing status is
-// clear, the operation is ongoing.
-
-static int
-gpsm_hw_quiesce(void)
-{
-    int rc = 0;
-    pmc_rail_bounds_register_t prbr, original_prbr;
-    pmc_pstate_monitor_and_ctrl_reg_t ppmacr;
-
-    ppmacr.value = in32(PMC_PSTATE_MONITOR_AND_CTRL_REG);
-    
-    original_prbr.value = prbr.value = in32(PMC_RAIL_BOUNDS_REGISTER);
-    prbr.fields.pmin_rail = ppmacr.fields.gpsa;
-    prbr.fields.pmax_rail = ppmacr.fields.gpsa;
-    out32(PMC_RAIL_BOUNDS_REGISTER, prbr.value);
-
-    rc = _gpsm_hw_quiesce();
-    
-    if (!rc) {
-        _gpsm_fw_mode();
-        out32(PMC_RAIL_BOUNDS_REGISTER, original_prbr.value);
-    }
-
-    return rc;
-}
-
-////////////////////////////////////////////////////////////////////////////
-// Public Predicates
-////////////////////////////////////////////////////////////////////////////
-
-/// Is the Global Pstate Mechanism quiesced?
-///
-/// This predicate can only truly be answered 'true' if we are not in
-/// hardware Pstate mode.  
-///
-/// \retval 0 Either we're in Hardware Pstate Mode, or a Voltage/Frequency
-/// operation is ongoing.
-///
-/// \retval 1 We're not in Hardware Pstate Mode and no Voltage/Frequency
-/// operation is ongoing.
-
-int
-gpsm_quiesced_p(void)
-{
-    return !(gpsm_hw_mode_p() ||
-             !ssx_irq_status_get(PGP_IRQ_PMC_PROTOCOL_ONGOING) ||
-             !ssx_irq_status_get(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING));
-}
-
-/// Predicate: Is the PMC in hardware Pstate mode?
-///
-/// \returns 0/1
-
-int
-gpsm_hw_mode_p(void)
-{
-    pmc_mode_reg_t pmr;
-
-    pmr.value = in32(PMC_MODE_REG);
-    return (pmr.fields.enable_hw_pstate_mode != 0);
-}
-
-
-/// Predicate: Is the PMC in firmware auction Pstate mode?
-///
-/// \returns 0/1
-
-int
-gpsm_fw_auction_mode_p(void)
-{
-    pmc_mode_reg_t pmr;
-
-    pmr.value = in32(PMC_MODE_REG);
-    return (pmr.fields.enable_fw_auction_pstate_mode != 0);
-}
-
-
-/// Predicate: Is the PMC in firmware Pstate mode?
-///
-/// \returns 0/1
-
-int
-gpsm_fw_mode_p(void)
-{
-    pmc_mode_reg_t pmr;
-
-    pmr.value = in32(PMC_MODE_REG);
-    return (pmr.fields.enable_fw_pstate_mode != 0);
-}
-
-
-/// Predicate: Is the chip configured as a DCM?
-///
-/// \returns 0/1
-
-int
-gpsm_dcm_mode_p(void)
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    return pmc_mode_reg.fields.enable_interchip_interface;
-}
-
-
-/// Predicate: Is the chip configured as a DCM Slave?
-///
-/// \returns 0/1
-
-int
-gpsm_dcm_master_p(void)
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    return 
-        pmc_mode_reg.fields.enable_interchip_interface &&
-        pmc_mode_reg.fields.interchip_mode;
-}
-
-
-/// Predicate: Is the chip configured as a DCM Slave?
-///
-/// \returns 0/1
-
-int
-gpsm_dcm_slave_p(void)
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    return 
-        pmc_mode_reg.fields.enable_interchip_interface &&
-        (pmc_mode_reg.fields.interchip_mode == 0);
-}
-    
-
-        
-
-////////////////////////////////////////////////////////////////////////////
-// Procedures
-////////////////////////////////////////////////////////////////////////////
-
-/// Recover the GlobalPstateTable object from the PMC
-///
-/// \note It is assumed that the pointer to the Global Pstate table installed
-/// in the PMC is actually a pointer to a complete GlobalPstateTable object
-/// (which contains a Global Pstate table as its first element).
-///
-/// \returns A pointer to the currently active GlobalPstateTable object.
-
-GlobalPstateTable*
-gpsm_gpst(void)
-{
-    pmc_parameter_reg1_t ppr1;
-
-    ppr1.value = in32(PMC_PARAMETER_REG1);
-    return (GlobalPstateTable*)
-        (ppr1.fields.ba_sram_pstate_table << GLOBAL_PSTATE_TABLE_ALIGNMENT);
-}
-
-
-/// Quiesce the GPSM to firmware mode from any other mode
-///
-/// At the exit of this procedure, the PMC will be in Firmware Pstate Mode and
-/// there will be no ongoing voltage or frequency transitions.
-int
-gpsm_quiesce(void)
-{
-    int rc;
-
-    if (gpsm_hw_mode_p()) {
-        rc = gpsm_hw_quiesce();
-    } else {
-        rc = gpsm_fw_quiesce();
-    }
-
-    return rc;
-}
-
-/// Quiesce the GPSM in Hardware Pstate Mode
-///
-/// In general there is no guarantee that the GPSM will ever quiesce, or
-/// remain quiesced in Hardware Pstate Mode unless something like the
-/// procedure in gpsm_hw_quiesce() is used.  This procedure is provided for
-/// the benefit of applications that are in complete control of Pstates
-/// (including idle state Pstates) to simply wait for the Pstate protocol to
-/// quiesce, without quiescing and entering Firmware Pstate mode like
-/// gpsm_hw_quiesce(). 
-
-int
-_gpsm_hw_quiesce(void)
-{
-    int rc;
-
-    do {
-        rc = 0;
-
-        if (!gpsm_hw_mode_p()) {
-            rc = -GPSM_ILLEGAL_MODE_HW_QUIESCE;
-            break;
-        }
-
-        if (!ssx_irq_status_get(PGP_IRQ_PMC_PROTOCOL_ONGOING)) {
-            ssx_irq_enable(PGP_IRQ_PMC_PROTOCOL_ONGOING);
-            rc = ssx_semaphore_pend(&G_gpsm_protocol_semaphore, 
-                                    SSX_WAIT_FOREVER);
-            if (rc) break;
-        }
-    } while (0);
-    
-    return rc;
-}
-
-
-/// Change to GPSM firmware mode from any mode
-
-int
-gpsm_fw_mode(void)
-{
-    return gpsm_quiesce();
-}
-
-
-/// Change to GPSM firmware auction mode from any mode
-
-int
-gpsm_fw_auction_mode(void)
-{
-    int rc;
-
-    rc = gpsm_quiesce();
-    if (!rc) {
-        _gpsm_fw_auction_mode();
-    }
-    return rc;
-}
-
-
-/// Change to Hardware Pstate Mode
-///
-/// The (unchecked) assumption behind this procedure is that the caller has
-/// run through Pstate intialization and enablement, and the system is in a
-/// state where the entry to Hardware Pstate Mode is safe once the GPSM is
-/// quiesced. 
-
-int
-gpsm_hw_mode(void)
-{
-    int rc;
-
-    TRACE_GPSM(TRACE_GPSM_HW_MODE);
-
-    rc = gpsm_quiesce();
-    if (!rc) {
-        _gpsm_hw_mode();
-    }
-    return rc;
-}
-
-
-/// The default GPSM auction procedure
-///
-/// The default auction returns the value of
-/// PMC_HARDWARE_AUCTION_PSTATE_REG.haps.
-
-Pstate
-gpsm_default_auction(void)
-{
-    pmc_hardware_auction_pstate_reg_t phapr;
-
-    phapr.value = in32(PMC_HARDWARE_AUCTION_PSTATE_REG);
-    return phapr.fields.haps;
-}
-
-
-/// Update a user-supplied vector of Pstates with the current Global bid of
-/// each core.
-///
-/// \param[out] o_bids A vector of Pstates; The vector must be large enough to
-/// hold the bid of every possible core.
-///
-/// This routine is provided for use by non-default Global Pstate auction
-/// procedures.
-
-void
-gpsm_get_global_bids(Pstate *o_bids)
-{
-    // This takes advantage of the implicit layout of the
-    // PMC_CORE_PSTATE_REG<n>.
-
-    uint32_t *bids32 = (uint32_t *)o_bids;
-
-    bids32[0] = in32(PMC_CORE_PSTATE_REG0);
-    bids32[1] = in32(PMC_CORE_PSTATE_REG1);
-    bids32[2] = in32(PMC_CORE_PSTATE_REG2);
-    bids32[3] = in32(PMC_CORE_PSTATE_REG3);
-}
-
-
-/// Update a current Global bid of each core from a user supplied vector.
-///
-/// \param[in] i_bids An array of Global Pstate bids.
-///
-/// This routine is provided for use by test procedures; there is likely no
-/// product-level energy management application for this procedure.
-
-void
-gpsm_set_global_bids(const Pstate *i_bids)
-{
-    // This takes advantage of the implicit layout of the
-    // PMC_CORE_PSTATE_REG<n>.
-
-    uint32_t *bids32 = (uint32_t *)i_bids;
-
-    out32(PMC_CORE_PSTATE_REG0, bids32[0]);
-    out32(PMC_CORE_PSTATE_REG1, bids32[1]);
-    out32(PMC_CORE_PSTATE_REG2, bids32[2]);
-    out32(PMC_CORE_PSTATE_REG3, bids32[3]);
-}
-
-    
-/// Application-controlled Global Actual Broadcast
-///
-/// \param[in] i_pstate The Global Actual Pstate to broadcast
-///
-/// \param[in] i_entry A gpst_entry_t containing the information to be used by
-/// the iVRM. If iVRM are not enabled then \a entry can be initialized to 0.
-///
-/// This API is provided for advanced applications to have complete control
-/// over a firmware-mode Global Actual broadcast.  There is no error
-/// checking. Most applications in Firware Pstate mode will use the
-/// higher-level gpsm_broadcast_global_actual() API.
-
-void
-_gpsm_broadcast_global_actual(const Pstate i_pstate, 
-                              const gpst_entry_t i_entry)
-{
-    pmc_pstate_monitor_and_ctrl_reg_t ppmacr;
-    pmc_eff_global_actual_voltage_reg_t pegavr;
-
-    ppmacr.value = 0;
-    ppmacr.fields.gpsa = i_pstate;
-    out32(PMC_PSTATE_MONITOR_AND_CTRL_REG, ppmacr.value);
-
-    pegavr.value = 0;
-    pegavr.fields.maxreg_vdd = i_entry.fields.maxreg_vdd;
-    pegavr.fields.maxreg_vcs = i_entry.fields.maxreg_vcs;
-    pegavr.fields.eff_evid_vdd = i_entry.fields.evid_vdd_eff; 
-    pegavr.fields.eff_evid_vcs = i_entry.fields.evid_vcs_eff; 
-    out32(PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG, pegavr.value);
-
-    TRACE_GPSM(TRACE_GPSM_BROADCAST_GLOBAL_ACTUAL);
-}
-
-
-/// Broadcast the Global Actual Pstate in firmware Pstate mode.
-///
-/// \param[in] i_gpst An initialized GlobalPstateTable structure used to
-/// define the legal Pstate range, and to provide the voltage settings
-/// (maxreg_vxx and eff_evid_vxx) for the internal VRM.
-///
-/// \param[in] i_pstate The pstate specfiying the Global Actual Pstate to be
-/// broadast to the core chiplets.
-///
-/// \param[in] i_bias This is a signed bias used to obtain the voltage Pstate,
-/// <em> in addition to the \a undervolting_bias already built into the Pstate
-/// table </em>. The iVRM information sent with the Global Actual Pstate comes
-/// from the \a pstate - \a undervolting_bias + \a bias entry of the Pstate
-/// table.
-///
-/// This API can be used in firware Pstate mode to broadcast a Global Actual
-/// Pstate and iVRM settings to the core chiplets. The API also supports
-/// optional under/over-volting.  The requested Pstate will be broadcast along
-/// with the voltage information from the associated Pstate table entry. 
-///
-/// Under/over-volting is specified by setting the \a bias to a non-0
-/// (signed) value.  For example, to undervfolt by one Pstate (if possible),
-/// call the API with \a bias = -1.
-///
-/// This API always waits for the Global Pstate Machine to quiesce before
-/// proceeding with the Global Actual broadcast. Therefore it can only be
-/// called from thread mode, or from a non-thread mode guaranteed by the
-/// caller to have quiesced.
-///
-/// \note The application can use the _gpsm_broadcast_global_actual() API for
-/// complete control over the information transmitted to the cores.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -GPST_PSTATE_CLIPPED_HIGH_GPSM_BGA The requested Pstate does not 
-/// exist in the table. The maximum Pstate entry in the table has been 
-/// broadcast as the voltage Pstate.
-///
-/// \retval -GPST_PSTATE_CLIPPED_LOW_GPSM_BGA The requested Pstate does not 
-/// exist in the table. The minimum Pstate entry in the table has been 
-/// broadcast as the voltage Pstate.
-///
-/// The following return codes are considered errors:
-///
-/// \retval -GPSM_INVALID_OBJECT The Global Pstate Table is either null (0) or
-/// otherwise invalid.
-///
-/// \retval -GPSM_INVALID_ARGUMENT One or more arguments are invalid or
-/// inconsistent in some way.
-///
-/// \retval -GPSM_ILLEGAL_MODE_BGA The PMC is not in firmware pstate mode.
-///
-/// This API may also return errors from the SSX semaphore operations that
-/// implement the wait for quiescence.
-
-int
-gpsm_broadcast_global_actual(const GlobalPstateTable* i_gpst, 
-                             const Pstate i_pstate, 
-                             const int i_bias)
-{
-    int rc, bias_rc, entry_rc;
-    gpst_entry_t entry;
-    Pstate voltage_pstate;
-
-    do {
-
-        if (!gpsm_fw_mode_p()) {
-            rc = GPSM_ILLEGAL_MODE_BGA;
-            break;
-        }
-
-        // Bias the pstate, fetch the Pstate entry, quiesce and broadcast.
-        // bias_pstate() only returns saturation warnings. These are turned
-        // into bounds warnings if necessary (indicating that the Pstate
-        // saturated but the PMAX or PMIN was also a legal entry in the
-        // table).
-
-        bias_rc = bias_pstate(i_pstate, i_bias, &voltage_pstate);
-        entry_rc = gpst_entry(i_gpst, voltage_pstate, 0, &entry);
-        if (entry_rc && 
-            (entry_rc != -GPST_PSTATE_CLIPPED_LOW_GPST_ENTRY) &&
-            (entry_rc != -GPST_PSTATE_CLIPPED_HIGH_GPST_ENTRY)) {
-            rc = entry_rc;
-            break;
-        }
-
-        rc = gpsm_quiesce();
-        if (rc) break;
-
-        _gpsm_broadcast_global_actual(i_pstate, entry);
-
-        if (entry_rc != 0) {
-            rc = entry_rc;
-        } else if (bias_rc == -PSTATE_OVERFLOW_BIAS_PS) {
-            rc = -GPST_PSTATE_CLIPPED_HIGH_GPSM_BGA;
-        } else if (bias_rc == -PSTATE_UNDERFLOW_BIAS_PS) {
-            rc = -GPST_PSTATE_CLIPPED_LOW_GPSM_BGA;
-        }
-    } while (0);
-
-    return rc;
-}
-
-
diff --git a/src/lib/gpsm.h b/src/lib/gpsm.h
deleted file mode 100755
index 5af2e8d..0000000
--- a/src/lib/gpsm.h
+++ /dev/null
@@ -1,191 +0,0 @@
-#ifndef __GPSM_H__
-#define __GPSM_H__
-
-// $Id: gpsm.h,v 1.2 2014/02/03 01:30:24 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpsm.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpsm.h
-/// \brief PgP Global Pstate Machine (Mechanism)
-
-#include "ssx.h"
-#include "gpe_control.h"
-#include "pgp_async.h"
-#include "pstates.h"
-
-// GPSM modes
-
-#define GPSM_MODE_HW          1
-#define GPSM_MODE_FW_AUCTION  2
-#define GPSM_MODE_FW          3
-
-// Misc./Error/Panic codes
-
-#define GPSM_INVALID_OBJECT                0x00477601
-#define GPSM_INVALID_ARGUMENT_GPST_INSTALL 0x00477602
-#define GPSM_INVALID_ARGUMENT_LPST_INSTALL 0x00477603
-#define GPSM_INVALID_ARGUMENT_RCLK_INSTALL 0x00477604
-#define GPSM_INVALID_ARGUMENT_EPSS         0x00477605
-#define GPSM_ILLEGAL_MODE_HW_QUIESCE       0x00477606
-#define GPSM_ILLEGAL_MODE_BGA              0x00477607
-#define GPSM_ILLEGAL_MODE_GPST_INSTALL     0x00477608
-#define GPSM_ILLEGAL_MODE_LPST_INSTALL     0x00477609
-#define GPSM_ILLEGAL_MODE_RCLK_INSTALL     0x0047760a
-#define GPSM_ILLEGAL_MODE_GPSM_INIT        0x0047760b
-#define GPSM_ILLEGAL_MODE_EPSM             0x0047760c
-#define GPSM_ILLEGAL_MODE_EPSS             0x0047760d
-#define GPSM_SYNC_ERROR                    0x0047760e
-#define GPSM_PSTATE_CLIPPED                0x0047760f
-#define GPSM_BUG                           0x00477610
-#define GPSM_CONFIGURATION_ERROR           0x00477611
-#define GPSM_ERROR_BREAK                   0x00477612
-#define GPSM_INVALID_MAGIC                 0x00477613
-#define GPSM_IVRM_CALIBRATION_TIMEOUT      0x00477614
-#define GPSM_IVRM_GROSS_OR_FINE            0x00477615
-#define GPSM_PSTATE_ENABLED                0x00477616
-#define GPSM_BABYSTEPPER_SYNC_TIMEOUT      0x00477617
-#ifndef __ASSEMBLER__
-
-// Lab/VBU/VPO debugging
-
-#if 0
-#include "trace.h"
-#define TRACE_GPSM(i_code) trace_tbl_bbbb(1, i_code, 0, 0, 0);
-#define TRACE_GPSM_B(i_code, i_b0) trace_tbl_bbbb(1, i_code, i_b0, 0, 0);
-#define TRACE_GPSM_H(i_code, i_h0) trace_tbl_bbh(1, i_code, 0, i_h0);
-#else
-#define TRACE_GPSM(i_code)
-#define TRACE_GPSM_B(i_code, i_b0)
-#define TRACE_GPSM_H(i_code, i_h0)
-#endif
-
-
-/// Information required by an SCM or a DCM master to be passed from
-/// gpsm_enable_pstates_master() to gpsm_enable_pstates_slave().
-
-typedef struct {
-
-    /// Indicates whether or not gpsm_enable_pstates_slave() should move the
-    /// voltage. 
-    ///
-    /// If 0, it means that the master has already moved the voltage and only
-    /// the frequency needs to move.  If 1, voltage is moved after frequency
-    /// moves. 
-    int move_voltage;
-
-    /// The current and target external voltage settings as VRM11 VID codes.
-    Vid11 currentVdd, currentVcs, targetVdd, targetVcs;
-
-} GpsmEnablePstatesMasterInfo;
-
-
-/// A GpsmAuctionProcedure is any function of no arguments that returns a
-/// Pstate
-
-typedef Pstate (*GpsmAuctionProcedure)();
-
-extern SsxSemaphore G_gpsm_protocol_semaphore;
-
-extern uint8_t G_gpsm_initialized;
-
-// APIs defined in gpsm_init.c
-
-int
-gpsm_gpst_install(GlobalPstateTable* o_gpst,
-                  const GlobalPstateTable* i_source);
-
-int
-gpsm_lpsa_install(const LocalPstateArray* i_lpsa,
-                  const PstateOptions* i_options);
-
-int
-gpsm_resclk_install(const ResonantClockingSetup* i_resclk,
-                    const GlobalPstateTable* i_gpst,
-                    const PstateOptions* i_options);
-
-int
-gpsm_initialize(const PstateSuperStructure* i_pss, 
-                GlobalPstateTable* o_gpst);
-
-int
-gpsm_enable_pstates_master(GpsmEnablePstatesMasterInfo* o_info,
-                           Pstate* o_voltage_pstate,
-                           Pstate* o_frequency_pstate);
-
-int
-gpsm_enable_pstates_slave(const GpsmEnablePstatesMasterInfo* i_info,
-                          const Pstate i_voltage_pstate,
-                          const Pstate i_frequency_pstate);
-
-// APIs defined in gpsm.c
-
-int
-gpsm_quiesced_p(void);
-
-int
-gpsm_hw_mode_p(void);
-
-int
-gpsm_fw_auction_mode_p(void);
-
-int
-gpsm_fw_mode_p(void);
-
-int
-gpsm_dcm_mode_p(void);
-
-int
-gpsm_dcm_master_p(void);
-
-int
-gpsm_dcm_slave_p(void);
-
-GlobalPstateTable*
-gpsm_gpst();
-
-int
-gpsm_quiesce(void);
-
-int
-_gpsm_hw_quiesce(void);
-
-int
-gpsm_fw_mode(void);
-
-int
-gpsm_fw_auction_mode(void);
-
-int
-gpsm_hw_mode(void);
-
-Pstate
-gpsm_default_auction(void);
-
-void
-gpsm_get_global_bids(Pstate* o_bids);
-
-void
-gpsm_set_global_bids(const Pstate* i_bids);
-
-void
-_gpsm_broadcast_global_actual(const Pstate i_pstate, 
-                              const gpst_entry_t i_entry);
-
-int
-gpsm_broadcast_global_actual(const GlobalPstateTable *i_gpst, 
-                             const Pstate i_pstate, 
-                             const int i_bias);
-
-int
-gpsm_set_pstate(const Pstate i_pstate);
-
-int
-gpsm_hold_auction(const GpsmAuctionProcedure i_procedure);
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __GPSM_H__ */
diff --git a/src/lib/gpsm_dcm.c b/src/lib/gpsm_dcm.c
deleted file mode 100755
index 452f7cf..0000000
--- a/src/lib/gpsm_dcm.c
+++ /dev/null
@@ -1,753 +0,0 @@
-// $Id: gpsm_dcm.c,v 1.2 2014/02/03 01:30:24 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpsm_dcm.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpsm_dcm.h
-/// \brief PgP Global PState Machine (Mechanism) in Dual Chip Model
-
-#include "ssx.h"
-#include "pmc_dcm.h"
-#include "gpsm_dcm.h"
-#include "gpsm.h"
-
-/// Timeout object and methods
-
-typedef struct {
-    SsxTimebase timeout;
-} Timeout;
-
-static void
-timeout_start(Timeout* t, SsxInterval timeout_period)
-{
-    t->timeout = ssx_timebase_get() + timeout_period;
-}
-
-static int
-timeout_timed_out(Timeout* t)
-{
-    return ssx_timebase_get() > t->timeout;
-}
-
-
-/// Internal API : Send packet with timeout
-///
-/// \param hwPacket pointer to the packet to be sent
-///
-/// \param timeout_period The SSX timeout variable
-///
-/// This API sends \a hwPacket within \a timeout_period
-/// if timed out, the function returns an error code 
-///
-/// \retval GPSM_DCM_SUCCESS
-///
-/// \retval GPSM_DCM_SEND_PACKET_TIMEOUT
-///
-
-static int
-_gpsm_dcm_send(PmcDcmPacket* hwPacket,
-               SsxInterval timeout_period)
-{
-    int rc = GPSM_DCM_SUCCESS;
-    Timeout  timeout;
-
-    //set timeout
-    timeout_start(&timeout, timeout_period);
-
-    //try to send packet within timeout
-    while( (rc=pmc_dcm_send(hwPacket)) == PMC_DCM_OUTSTANDING_TRANSFER ) {
-        if( timeout_timed_out(&timeout)) {
-            rc = GPSM_DCM_SEND_PACKET_TIMEOUT;
-            break;
-        }
-    }
-
-    return rc;
-}
-
-/// Internal API : Receive packet with timeout
-///
-/// \param hwPacket pointer to the packet structure to receive
-///
-/// \param timeout_period The SSX timeout variable
-///
-/// This API receives a \a hwPacket within \a timeout
-/// if timed out, the function returns an error code 
-///
-/// \retval GPSM_DCM_SUCCESS
-///
-/// \retval GPSM_DCM_RECV_PACKET_TIMEOUT
-///
-
-static int
-_gpsm_dcm_receive(PmcDcmPacket* hwPacket,
-                  SsxInterval timeout_period)
-{
-    int rc = GPSM_DCM_SUCCESS; 
-    Timeout  timeout;
-    
-    //set timeout 
-    timeout_start(&timeout, timeout_period);
-
-    //try to receive packet within timeout
-    while( (rc=pmc_dcm_receive(hwPacket)) == PMC_DCM_RECEIVE_NOT_DETECTED ) {
-        if( timeout_timed_out(&timeout)) {
-            rc = GPSM_DCM_RECV_PACKET_TIMEOUT;
-            break;
-        }
-    }
-
-    return rc;
-}
-
-////////////////////////////////////////////////////////////////////////////
-// High-level GPSM-DCM Interfaces
-////////////////////////////////////////////////////////////////////////////
-
-/// Abstract non-blocking send over the DCM interchip link
-///
-/// The GPSM-DCM abstract interface guarantees that the PMC-DCM link is always
-/// clear for use by the master sender.  This API (which should be called from
-/// a thread context) transmits an abstract packet, then polls for the hardware
-/// ACK - which must always indicate that the packet was received.  This ACK
-/// will always occur very quickly.
-///
-/// \param fwPacket a GpsmDcmPacket structure to be sent as part of the 
-/// PmcDcmPacket/hwPacket of MSG type via PMC interchip link. 
-/// The fwPacket includes a firmware command and 16 bits payload. 
-/// The firmware command will be filled in the cmd_ext field of the 
-/// hwPacket structure, and payload 0,1 will be filled in the 
-/// corresponding slots also in hwPacket structure.
-/// This argument is provided by the caller and passed in as reference.
-///
-/// hwPacket:
-///
-/// cmd_code | cmd_ext | payload 0 | payload 1 | ECC
-/// [0:3]    | [4:7]   | [8:15]    | [16:23]   | [24:31]
-///
-/// fwPacket:
-///       
-///          | command | payload 0 | payload 1 |
-///          | [4:7]   | [8:15]    | [16:23]   |
-///
-/// firmware command:
-///
-/// GPSM_DCM_DATA                       0 //0b0000
-/// GPSM_DCM_WRITE                      1 //0b0001
-/// GPSM_DCM_ENABLE_PSTATES             2 //0b0010
-/// GPSM_DCM_ENTER_HW_PSTATE_MODE       3 //0b0011
-///
-/// This API implements the lower level pmc_dcm_send API to send a firmware
-/// command as part of the PMC interchip message packet. 
-/// 
-/// This API is working under a default time out, if send cannot be completed 
-/// within the default timeout period due to possible busy interchip link,
-/// the function will exit with returning an error code: 
-/// \a GPSM_DCM_SEND_PACKET_TIMEOUT
-/// 
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               and lower level PMC-DCM API is required to use this 
-///               high level GPSM-DCM API.
-///               Also, the hardware must be in DCM setup.
-/// 
-/// Note: This API must be called by the DCM Master, meaning the firmware 
-///       command can only be given by the master to the slave. 
-///       Also the API will check if the firmware command to be sent is valid.
-///  
-/// \retval SUCCESS
-///
-/// \retval GPSM_DCM_ARG_INVALID_OBJ_SND
-///
-/// \retval GPSM_DCM_PKT_INVALID_CMD_SND
-///
-/// \retval GPSM_DCM_CMD_NOT_FROM_MASTER 
-///
-
-int
-gpsm_dcm_send(GpsmDcmPacket* fwPacket) {
-
-    int rc = GPSM_DCM_SUCCESS;
-    PmcDcmPacket hwPacket;
-
-    TRACE_GPSM_B(TRACE_GPSM_DCM_SEND, fwPacket->command);
-
-    do {
-
-        //check if argument is NULL
-        SSX_ERROR_IF_CHECK_API(
-             (fwPacket == 0),
-             GPSM_DCM_ARG_INVALID_OBJ_SND);
-
-        //check if firmware command is valid             
-        SSX_ERROR_IF_CHECK_API( 
-             (fwPacket->command >= GPSM_DCM_NUMBER_OF_COMMANDS ||
-              fwPacket->command == GPSM_IC_DATA), 
-             GPSM_DCM_PKT_INVALID_CMD_SND);
-     
-        //check if is dcm master, note only master can send command to slave
-        SSX_ERROR_IF_CHECK_API( 
-             (!pmc_dcm_if_dcm_master()), 
-             GPSM_DCM_CMD_NOT_FROM_MASTER);
-     
-        //form hardware packet from given firmware packet
-        hwPacket.value = 0;
-        hwPacket.fields.cmd_code   = PMC_IC_MSG_CC;
-        hwPacket.fields.cmd_ext    = fwPacket->command;
-        hwPacket.fields.payload[0] = fwPacket->payload.u8[0];
-        hwPacket.fields.payload[1] = fwPacket->payload.u8[1];
-    
-        //send hardware packet 
-        rc = _gpsm_dcm_send(&hwPacket, GPSM_DCM_DEFAULT_TIMEOUT);
-     
-    } while (0);
-
-    TRACE_GPSM(TRACE_GPSM_DCM_SENT);
-
-    return rc;    
-}
-
-
-/// Abstract blocking/non-blocking receive over the DCM interchip link
-///
-/// \param fwPacket A GpsmDcmPacket structure as the part of the 
-/// PmcDcmPacket/hwPacket received from PMC interchip link.  
-/// This argument is passed by the caller as reference. The corresponding 
-/// fields of the received packet will filled in this data structure.
-///
-/// \param timeout_period A SsxInterval variable for time out period
-///
-/// This API implements the lower level pmc_dcm_receive API to receive a firmware
-/// command as part of the PMC interchip message packet.
-///
-/// This API is working under a user given time out, if receive cannot be 
-/// completed within the given timeout period,
-/// the function will exit with returning an error code:
-/// \a GPSM_DCM_RECV_PACKET_TIMEOUT
-///
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               and lower level PMC-DCM API is required to use this
-///               high level GPSM-DCM API.
-///               Also, the hardware must be in DCM setup.
-///
-/// Note: This API must be called by the DCM Slave, meaning the firmware
-///       command can only be received by the slave.
-///       Also the API will check if the received firmware command is valid.
-//  
-/// \retval GPSM_DCM_SUCCESS
-///
-/// \retval GPSM_DCM_ARG_INVALID_OBJ_RCV
-///
-/// \retval GPSM_DCM_CMD_SHOULD_TO_SLAVE 
-///
-/// \retval GPSM_DCM_PKT_INVALID_CMD_RCV
-///
-
-int
-gpsm_dcm_receive(GpsmDcmPacket* fwPacket,                 
-                 SsxInterval timeout_period) {
-
-    int rc = GPSM_DCM_SUCCESS;
-    PmcDcmPacket hwPacket;
-
-    TRACE_GPSM(TRACE_GPSM_DCM_RECEIVE);
-
-    do {    
-        
-        //check if argument is NULL
-        SSX_ERROR_IF_CHECK_API(
-             (fwPacket == 0),
-            GPSM_DCM_ARG_INVALID_OBJ_RCV);
-
-        //check if is dcm slave, note only slave receives command from master
-        SSX_ERROR_IF_CHECK_API(
-            (pmc_dcm_if_dcm_master()), 
-            GPSM_DCM_CMD_SHOULD_TO_SLAVE);
-    
-        //receive hardware packet
-        hwPacket.value = 0;
-        rc = _gpsm_dcm_receive(&hwPacket, timeout_period);
-        if( rc ) break;
-
-        //check if the received command is valid
-        fwPacket->command = hwPacket.fields.cmd_ext;
-        SSX_ERROR_IF_CHECK_API(
-            (fwPacket->command >= GPSM_DCM_NUMBER_OF_COMMANDS ||
-             fwPacket->command == 0), 
-            GPSM_DCM_PKT_INVALID_CMD_RCV);
-    
-        //load payload from hardware packet into firmware packet
-        fwPacket->payload.u8[0] = hwPacket.fields.payload[0];
-        fwPacket->payload.u8[1] = hwPacket.fields.payload[1];
-    
-    } while (0);
-
-    TRACE_GPSM_B(TRACE_GPSM_DCM_RECEIVED, fwPacket->command);
-
-    return rc;     
-}
-
-////////////////////////////////////////////////////////////////////////////
-// Generic communication using GPSM-DCM 'write' command
-////////////////////////////////////////////////////////////////////////////
-///
-/// These APIs allow applications to perform generic communication over the
-/// GPSM-DCM link using the GPSM-DCM 'write' command.  Like all GPSM-DCM
-/// commands, communication is always controlled/initiated by the master. The
-/// infrastructure assumes that the master and slave applications argee on the
-/// maximum amount of data that may be transmitted generically as a single
-/// abstract transaction.  It is legal for the data transmission size to be 0.
-///
-/// In the following APIs, the \a timeout parameter is a timeout for any
-/// single send/receive transaction to complete, not a timeout covering the
-/// entire send/receive.  The timeout may be specified as SSX_WAIT_FOREVER to
-/// indicate no timeout.
-///
-/// One typical use of these APIs would be to implement a polled 'ping' of the
-/// slave from the master.  This sequence might be implemented as follows:
-///
-/// - Master: Calls gpsm_dcm_write() with 0 size [ping]
-/// - Master: Blocks on gpsm_dcm_read [Wait for ping response]
-/// - Slave: GpsmSlaveControl.write_handler() is activated to handle the ping
-/// - Slave: write_handler() responds by calling gpsm_dcm_write()
-/// - Master: Unblocks and processes ping reqponse
-
-
-/// Send an arbitrary amount of data (max 2^16 - 1 bytes) using GPSM-DCM
-///
-/// This API is typically used by the master to initiate generic
-/// communication.  When received by the slave the application-specific
-/// callback is activated on the slave to handle the write.
-/// The slave will only use this API when it is known that the master is
-/// expecting a communication from the slave and has blocked on a call of
-/// gpsm_dcm_read().
-///
-/// The receiver must be prepared to accept \a size bytes of data, otherwise
-/// the call will fail immediately.
-///
-/// \param buf The buffer contains the sending message prepared by the caller
-///
-/// \param size The size of a message, in number of bytes, given by the caller
-///
-/// \param timeout_period The SSX timeout variable
-///
-/// The firmware level API for sending a generic PMC interchip message
-/// This API sends the message by calling lower level API: pmc_dcm_send
-///
-/// The API times out upon \a timeout_period.
-///
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               and lower level PMC-DCM API is required to use this
-///               high level GPSM-DCM API.
-///               Also, the hardware must be in DCM setup.
-///
-/// Note: When this API is called by the DCM Master, 
-///       the slave will need to provide its own write_handler to process
-///       the receiving message, The counterpart gpsm_dcm_read API of this
-///       gpsm_dcm_write API is not designed for slave to read the master 
-///       sending message.
-///
-/// \retval GPSM_DCM_SUCCESS
-///
-/// \retval GPSM_DCM_ARG_INVALID_OBJ_WRT
-///
-
-int
-gpsm_dcm_write(void* buf,
-               uint16_t size,
-               SsxInterval timeout_period)
-{
-    int rc = GPSM_DCM_SUCCESS; 
-    PmcDcmPacket     hwPacket;
-    GpsmDcmFastData  fastData;
-
-    TRACE_GPSM_H(TRACE_GPSM_DCM_WRITE, size);
-
-    //setup send irq
-    ssx_irq_setup(PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING,
-                  SSX_IRQ_POLARITY_ACTIVE_LOW,
-                  SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-    do {
-
-        //check if buffer is allocated
-        SSX_ERROR_IF_CHECK_API(
-            (buf == 0 && size != 0),
-            GPSM_DCM_ARG_INVALID_OBJ_WRT);
- 
-         //form initial hardware packet as header packet
-         hwPacket.value = 0;
-         hwPacket.fields.cmd_code = PMC_IC_MSG_CC;
-         hwPacket.fields.cmd_ext  = GPSM_IC_WRITE;
-         hwPacket.value += SET_PAYLOAD_FIELD(size);   
- 
-         //setup data structure for fast write handler
-         fastData.buffer_pointer = buf;
-         fastData.remaining_size = size;
-         ssx_semaphore_create(&(fastData.fast_semaphore), 0, 1);
- 
-         //setup fast write handler for send irq
-         ssx_irq_handler_set(PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING,
-                             gpsm_dcm_fast_write,
-                             (void*)(&fastData), 
-                             SSX_NONCRITICAL);
- 
-         //send header packet
-         rc = _gpsm_dcm_send(&hwPacket, timeout_period);
-         if( rc ) break;
-         
-         //enable interrupt and semaphore
-         ssx_irq_enable(PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING);     
-         ssx_semaphore_pend(&(fastData.fast_semaphore), timeout_period);
-         
-     } while (0); 
-
-    TRACE_GPSM(TRACE_GPSM_DCM_WRITE_COMPLETE);
- 
-     return rc;
-}
-
-
-/// Receive a transmission from the slave
-///
-/// This API is only called on the master, as part of an application-specific
-/// protocol where a transmission is expected from the slave.
-///
-/// The call will fail immediately if the slave attempts to send more than \a
-/// buf_size bytes. The actual number of bytes received is returned as \a
-/// data_size.
-///
-/// \param buf The buffer for storing the incoming messages,
-/// return to caller as reference
-///
-/// \param buf_size The maximum size of the buffer, given by caller
-/// fail operation if data_size > buf_size
-///
-/// \param data_size The size of acutal receiving message,
-/// return to caller as refernce
-///
-/// \param timeout_period The SSX timeout variable
-///
-/// The firmware level API for receiving a PMC interchip message
-/// This API recevies the message by calling lower level API: pmc_dcm_receive
-/// and then checks \a buf_size and \a data_size for unexpected message size
-/// if the size overflow, the function will exit with returning an error code:
-/// \a GPSM_DCM_DAT_BIGGER_THAN_BUF
-/// The valid receive message will be placed into \a buf and return with
-/// the actual \a data_size. The API times out upon \a timeout.
-///
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               and lower level PMC-DCM API is required to use this
-///               high level GPSM-DCM API.
-///               Also, the hardware must be in DCM setup.
-///
-/// Note: This API is only designed for master to read/receive a message from
-///       slave (slave will have its own write_handler). Therefore, this API
-///       can only called by DCM master, and the API will check if the received
-///       message is from a write command.    
-///
-/// \retval GPSM_DCM_SUCCESS
-///
-/// \retval GPSM_DCM_ARG_INVALID_OBJ_RED
-///
-/// \retval GPSM_DCM_READ_RECV_NOT_WRITE
-///
-/// \retval GPSM_DCM_DAT_BIGGER_THAN_BUF
-///
-
-int
-gpsm_dcm_read(void* buf,
-              uint16_t buf_size,
-              uint16_t* data_size,
-              SsxInterval timeout_period)
-{
-    int rc = GPSM_DCM_SUCCESS;
-    PmcDcmPacket    hwPacket;
-    GpsmDcmFastData fastData;
-
-    TRACE_GPSM(TRACE_GPSM_DCM_READ);
-
-    //setup receive irq
-    ssx_irq_setup(PGP_IRQ_PMC_INTERCHIP_MSG_RECV,
-                  SSX_IRQ_POLARITY_ACTIVE_HIGH,
-                  SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-
-    do {
-
-        //check if buffer is allocated
-        SSX_ERROR_IF_CHECK_API(
-            (buf == 0 && buf_size != 0),
-            GPSM_DCM_ARG_INVALID_OBJ_RED);
-
-        //try to receive the header packet
-        hwPacket.value = 0;
-        rc = _gpsm_dcm_receive(&hwPacket, timeout_period);
-        if( rc ) break;
-
-        //check if command code of header packet is valid
-        SSX_ERROR_IF_CHECK_API(
-            (hwPacket.fields.cmd_ext != GPSM_IC_WRITE),
-            GPSM_DCM_READ_RECV_NOT_WRITE);
-
-        //load size from header packet
-        *data_size = GET_PAYLOAD_FIELD(hwPacket.value);
-
-        //check if data size will fit in the buffer
-        if( *data_size > buf_size ) {
-            rc = GPSM_DCM_DAT_BIGGER_THAN_BUF;
-            break;
-        }
-
-        //check if data size is 0
-        if( *data_size == 0 ) 
-            break;
-
-        //setup data structure for fast read
-        fastData.buffer_pointer = buf;
-        fastData.remaining_size = *data_size;
-        ssx_semaphore_create(&(fastData.fast_semaphore), 0, 1);
-
-        //setup fast read handler for receive irq
-        ssx_irq_handler_set(PGP_IRQ_PMC_INTERCHIP_MSG_RECV,
-                            gpsm_dcm_fast_read,
-                            (void*)(&fastData),
-                            SSX_NONCRITICAL);
- 
-        //enable interrupt and semaphore
-        ssx_irq_enable(PGP_IRQ_PMC_INTERCHIP_MSG_RECV);    
-        ssx_semaphore_pend(&(fastData.fast_semaphore), timeout_period);
-        
-    } while (0);
-
-    TRACE_GPSM_H(TRACE_GPSM_DCM_READ_COMPLETE, *data_size);
-
-    return rc;
-}
-
-/// Method to sync between two chips using write/read API
-///
-/// This API can be called before a piece of application code to sync
-/// between master and slave to enter the same code block together 
-/// as well as after a piece of code to sync on exiting the block of code
-///
-/// \param state use 0 for enter and use 1 for exit
-///
-/// \retval GPSM_DCM_SUCCESS
-///
-
-int 
-gpsm_dcm_sync(int state)
-{
-   int rc = GPSM_DCM_SUCCESS;
-   int master = pmc_dcm_if_dcm_master();
-   uint16_t buf_size = sizeof(uint16_t);
-   uint16_t wbuf = 0x7962; //SYNC
-   uint16_t rbuf;
-   uint16_t size;
-   SsxMachineContext smc;
-
-   do {
-
-       ssx_critical_section_enter(SSX_NONCRITICAL, &smc);
-
-       if( master ^ state ) {
-           rc = gpsm_dcm_write((void*)&wbuf,buf_size,SSX_WAIT_FOREVER);
-           if(rc) break;
-           rc = gpsm_dcm_read((void*)&rbuf,buf_size,&size,SSX_WAIT_FOREVER);
-           if(rc) break;
-       } else {
-           rc = gpsm_dcm_read((void*)&rbuf,buf_size,&size,SSX_WAIT_FOREVER);
-           if(rc) break;
-           rc = gpsm_dcm_write((void*)&wbuf,buf_size,SSX_WAIT_FOREVER);
-           if(rc) break;
-       }          
-
-       ssx_critical_section_exit(&smc);
-
-   } while (0);
-  
-   return rc;    
-}
-
-
-/// GPSM DCM Slave function
-///
-/// This function must be called from a thread, as if a command is available
-/// it may always be necessary for the thread to block during command
-/// execution. The \a wait argument indicates whether the caller is willing to
-/// wait for a command indefinitely, or prefers for gpsm_dcm_slave() to retun
-/// immediately if no command is available. \a wait would normally be non-0 if
-/// \a gpsm_dcm_slave() were used as a standalone thread body, and 0 if
-/// gpsm_dcm_slave() were called from another thread.
-///
-/// \param control The callback table structure that allows the user to
-/// implement callback function in addition to completion of each command.
-/// 
-/// \param wait The SsxInterval type timeout variable
-///
-/// This API is the control function running on a slave thread.  The function
-/// will first try to receive a message from master, and then take the
-/// corresponding action according to the command in the message. Upon
-/// completion of the default action designed for each command, any user
-/// provided callback function for that command in the control structure will
-/// be called.
-///  
-/// Prerequisite: This API must be called from a DCM slave SSX thread
-///               The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               and lower level PMC-DCM API is required to use this
-///               high level GPSM-DCM API.
-///               Also, the hardware must be in DCM setup.
-///
-/// Similar to other SSX drivers, the callback is always called regardless of
-/// whether the slave command succeeds or fails.
-///
-/// \retval 0 Success
-///
-/// \retval GPSM_DCM_SLAVE_TIMEOUT The call timed out before a packet was
-/// received from the master.  The application may or may not treat this as an
-/// error. 
-///
-/// \retval GPSM_DCM_SLAVE_ERROR In the event of a this return code, the
-/// application will need to query 3 return codes stored in the \a control
-/// structure to understand the source of the error.  The \a
-/// control->protocol_rc contains the return code for all GPSM-DCM protocol
-/// actions, other than the simple timeout mentioned above.  The \a
-/// control->slave_rc is the return code for the slave action commanded by the
-/// master.  This is also the code sent back to the master as an
-/// acknowledgement. The control->callback_rc is the return code from the
-/// callback, if any.
-///
-///  The return value of the function is either 0,
-/// GPSM_DCM_SLAVE_TIMEOUT, or 
-/// GPSM_DCM_SLAVE_ERROR.  
-/// 
-
-int
-gpsm_dcm_slave(GpsmSlaveControl *control, 
-               SsxInterval wait)
-{
-    GpsmDcmPacket fwPacket;
-    int rc, protocolRc, slaveRc, callbackRc;
-
-    TRACE_GPSM(TRACE_GPSM_DCM_SLAVE);
-
-    protocolRc = 0;
-    slaveRc = 0;
-    callbackRc = 0;
-
-    do {
-        protocolRc = gpsm_dcm_receive(&fwPacket, wait);
-        if(protocolRc) {
-            control->command = GPSM_IC_NO_COMMAND;
-            break;
-        }
-
-        control->command = fwPacket.command;
-
-        switch (fwPacket.command) {
-
-        case GPSM_IC_ENABLE_PSTATES:
-
-            slaveRc = gpsm_enable_pstates_slave(0, 
-                                                fwPacket.payload.pstate[0],
-                                                fwPacket.payload.pstate[1]);
-
-            if(control->gpsm_dcm_callback_enable_pstates != 0) {
-                callbackRc =
-                    control->gpsm_dcm_callback_enable_pstates(&fwPacket);
-            }
-
-            break;
-
-        case GPSM_IC_HW_PSTATE_MODE:
-
-            slaveRc = gpsm_hw_mode();
-
-            if(control->gpsm_dcm_callback_hw_pstate_mode != 0) {
-                callbackRc =
-                    control->gpsm_dcm_callback_hw_pstate_mode(&fwPacket);
-            }
-
-            break;
-
-        case GPSM_IC_WRITE:
-            slaveRc = control->write_handler(control->buffer, 
-                                             control->buffer_size, 
-                                             control->write_arg);
-            break;
-        default: 
-            slaveRc = GPSM_DCM_PKT_INVALID_CMD_RCV;
-            break;
-        }
-          
-        if(fwPacket.command != GPSM_IC_WRITE) {
-            protocolRc = gpsm_dcm_write((void*)(&slaveRc),
-                                        sizeof(int),
-                                        SSX_WAIT_FOREVER);
-        }
-    } while(0);   
-
-    control->protocol_rc = protocolRc;
-    control->slave_rc = slaveRc;
-    control->callback_rc = callbackRc;
-
-    if (protocolRc == GPSM_DCM_RECV_PACKET_TIMEOUT) {
-        rc = GPSM_DCM_SLAVE_TIMEOUT;
-    } else if (protocolRc || slaveRc || callbackRc) {
-        rc = GPSM_DCM_SLAVE_ERROR;
-    } else {
-        rc = 0;
-    }
-
-    TRACE_GPSM_B(TRACE_GPSM_DCM_SLAVE_COMPLETE, fwPacket.command);
-
-    return rc;
-}
-
-
-/// Master an abstract transaction with a return code response from the slave
-///
-/// \param fwPacket A legal, initalized GpsmDcmPacket.  This packet may be of
-/// any type other than GPSM_IC_DATA or GPSM_IC_WRITE.  The GPSM_IC_WRITE does
-/// not get a response from the slave.
-///
-/// \param slaveRc The return code from running the protocol action on the
-/// slave.  This includes any return code from a callback installed on the
-/// slave. If the return value of the function is non-0 then \a slaveRc is
-/// considered undefined.
-///
-/// This API send \a fwPacket to the slave and blocks waiting for the slave to
-/// respond with the \a slaveRc.  The return value of the API indicates any
-/// problems with sending the packet or receiving the response. 
-
-int
-gpsm_dcm_master(GpsmDcmPacket* fwPacket, int* slaveRc)
-{
-   int rc;
-   uint16_t size;
-
-   do {
-
-       rc = gpsm_dcm_send(fwPacket);
-       if(rc) break;
-       
-       rc = gpsm_dcm_read((void*)slaveRc,
-                          sizeof(int),
-                          &size,
-                          SSX_WAIT_FOREVER);
-       if(rc) break;
-       
-       //check if command_reply has correct size
-       SSX_ERROR_IF_CHECK_API((size != sizeof(int)),
-                              GPSM_DCM_CMD_REPLY_NOT_INT);
-    
-   }while(0);
-
-   return rc;
-}
diff --git a/src/lib/gpsm_dcm.h b/src/lib/gpsm_dcm.h
deleted file mode 100755
index 407ddbb..0000000
--- a/src/lib/gpsm_dcm.h
+++ /dev/null
@@ -1,192 +0,0 @@
-#ifndef __GPSM_DCM_H__
-#define __GPSM_DCM_H__
-
-// $Id: gpsm_dcm.h,v 1.2 2014/02/03 01:30:24 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpsm_dcm.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpsm_dcm.h
-/// \brief PgP Global PState Machine (Mechanism) in Dual Chip Model
-
-#include "pmc_dcm.h"
-
-/// GPSM-DCM Return Code
-#define GPSM_DCM_SUCCESS             0
-#define GPSM_DCM_ARG_INVALID_OBJ_SND 0x00326401 //ssx panic
-#define GPSM_DCM_ARG_INVALID_OBJ_RCV 0x00326402 //ssx panic
-#define GPSM_DCM_ARG_INVALID_OBJ_WRT 0x00326403 //ssx panic
-#define GPSM_DCM_ARG_INVALID_OBJ_RED 0x00326404 //ssx panic
-#define GPSM_DCM_PKT_INVALID_CMD_SND 0x00326405 //ssx panic
-#define GPSM_DCM_PKT_INVALID_CMD_RCV 0x00326406 //ssx panic
-#define GPSM_DCM_CMD_NOT_FROM_MASTER 0x00326407 //ssx panic
-#define GPSM_DCM_CMD_SHOULD_TO_SLAVE 0x00326408 //ssx panic
-#define GPSM_DCM_SEND_PACKET_TIMEOUT 0x00326409 //user handle
-#define GPSM_DCM_RECV_PACKET_TIMEOUT 0x0032640a //user handle
-#define GPSM_DCM_READ_RECV_NOT_WRITE 0x0032640b //ssx panic
-#define GPSM_DCM_READ_NOT_WRITE_DATA 0x0032640c //ssx panic
-#define GPSM_DCM_DAT_BIGGER_THAN_BUF 0x0032640d //user handle
-#define GPSM_DCM_CMD_REPLY_NOT_INT   0x0032640e //ssx panic
-#define GPSM_DCM_SLAVE_TIMEOUT       0x0032640f //user handle
-#define GPSM_DCM_SLAVE_ERROR         0x00326410 //user handle
-
-/// GPSM Interchip Command Code
-#define GPSM_IC_DATA           0 //0b0000
-#define GPSM_IC_WRITE          1 //0b0001
-#define GPSM_IC_ENABLE_PSTATES 2 //0b0010
-#define GPSM_IC_HW_PSTATE_MODE 3 //0b0011
-
-#define GPSM_DCM_NUMBER_OF_COMMANDS  4
-
-/// This is a special command return code returned by gpsm_dcm_slave() when it
-/// times out.
-#define GPSM_IC_NO_COMMAND GPSM_DCM_NUMBER_OF_COMMANDS
-
-
-/// Timeout Parameter
-#define GPSM_DCM_DEFAULT_TIMEOUT SSX_MICROSECONDS(15)
-
-#ifndef __ASSEMBLER__
-
-/// GPSM-DCM abstract packet
-
-typedef struct {
-    /// Firmware command
-    uint8_t command : 4;
-    union {
-        /// Used for Pstate-based protocols
-        Pstate pstate[2];
-        /// Generic byte data
-        uint8_t u8[2];
-    } payload;
-} GpsmDcmPacket;
-
-/// Data Structure for Fast Write/Read Handlers
-
-typedef struct {
-  void*        buffer_pointer;
-  uint32_t     remaining_size;
-  SsxSemaphore fast_semaphore;
-} GpsmDcmFastData;
-
-/// Data Structure for Sync Mehotds
-
-
-/// Abstract type of gpsm_dcm_slave() callbacks
-///
-/// The callback receives the (first) master packet of the exchange.  The
-/// return code is passed back to the master.
-
-typedef int (*GpsmDcmSlaveCallback)(GpsmDcmPacket* fwPacket);
-
-
-/// Control structure for gpsm_dcm_slave()
-
-typedef struct {
-    /// Slave timeout when waiting for next packet to arrive in long commands.
-    SsxInterval timeout;
-
-    /// Callback called after "Enable Pstates" command
-    GpsmDcmSlaveCallback gpsm_dcm_callback_enable_pstates;
-
-    /// Callback called after "Enter HW Pstate Mode" command
-    GpsmDcmSlaveCallback gpsm_dcm_callback_hw_pstate_mode;
-
-    /// Callback for GPSM-DCM write command
-    ///
-    /// Will be called with the application-supplied buffer and the actual
-    /// size of the data transmission.
-    int (*write_handler)(void* buffer, uint16_t size, void* arg);
-
-    /// Application-supplied buffer for GPSM-DCM write commands
-    void* buffer;
-
-    /// Size of the application-supplied write buffer
-    uint16_t buffer_size;
-
-    /// Application-supplied generic argument to the write handler
-    void* write_arg;
-
-    /// Callback when slave detects timeout from master
-    GpsmDcmSlaveCallback timeout_handler;
-
-    /// The last command recieved by the slave.
-    int command;
-
-    /// Return code from gpsm_dcm protocol actions
-    int protocol_rc;
-
-    /// Return code from slave action in response to master command
-    int slave_rc;
-
-    /// Return code from the application specific callback, if any.
-    int callback_rc;
-
-} GpsmSlaveControl;
-
-////////////////////////////////////////////////////////////////////////////
-// High-level GPSM-DCM Interchip Communication Methods
-////////////////////////////////////////////////////////////////////////////
-
-int
-gpsm_dcm_send(GpsmDcmPacket* fwPacket);
-
-
-
-int
-gpsm_dcm_receive(GpsmDcmPacket* fwPacket,
-                 SsxInterval timeout_period);
-
-
-////////////////////////////////////////////////////////////////////////////
-// Generic Data Communication using GPSM-DCM 'write' command
-////////////////////////////////////////////////////////////////////////////
-
-int
-gpsm_dcm_write(void* buf,
-               uint16_t size,
-               SsxInterval timeout_period);
-
-
-int
-gpsm_dcm_read(void* buf,
-              uint16_t buf_size,
-              uint16_t* data_size,
-              SsxInterval timeout_period);
-
-////////////////////////////////////////////////////////////////////////////
-// Fast Interrrupt Handlers for Data Transfer of GPSM-DCM 'write' command
-////////////////////////////////////////////////////////////////////////////
-
-SSX_IRQ_HANDLER(gpsm_dcm_fast_write);
-SSX_IRQ_HANDLER(gpsm_dcm_fast_read);
-
-////////////////////////////////////////////////////////////////////////////
-// Generic Synchronization Mechanism using GPSM-DCM 'write' command
-////////////////////////////////////////////////////////////////////////////
-
-int
-gpsm_dcm_sync(int state);
-
-////////////////////////////////////////////////////////////////////////////
-// The Control Method for Slave Thread
-////////////////////////////////////////////////////////////////////////////
-
-int
-gpsm_dcm_slave(GpsmSlaveControl *control,
-               SsxInterval wait);
-
-
-////////////////////////////////////////////////////////////////////////////
-// The Command Method for Master Thread
-////////////////////////////////////////////////////////////////////////////
-
-int
-gpsm_dcm_master(GpsmDcmPacket* fwPacket, int* slaveRc);
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __GPSM_DCM_H__ */
diff --git a/src/lib/gpsm_dcm_fast_handler.S b/src/lib/gpsm_dcm_fast_handler.S
deleted file mode 100755
index 01cbb2d..0000000
--- a/src/lib/gpsm_dcm_fast_handler.S
+++ /dev/null
@@ -1,147 +0,0 @@
-// $Id: gpsm_dcm_fast_handler.S,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-
-/// \file gpsm_dcm_fast_handler.S
-/// \brief Assembler support for GPSM_DCM procedures
-/// \cond
-        .nolist
-#include "ssx.h"
-#include "pmc_dcm.h"
-#include "gpsm_dcm.h"
-        .list
-
-#define GPSM_IC_CONTINUOUS_DATA (PMC_IC_MSG_CC << 4 | GPSM_IC_DATA)
-
-        // The gpsm_dcm_write fast handler.  
-
-        // Register use:        
-        //
-        // R3 = Entry: void *arg;    *arg -> GpsmDcmFast
-        // R4 = Entry: SsxIrqId irq; irq : constant
-        // R5 = Entry: int priority; priority -> data 
-        // R6 = data_pointer
-        // R7 = remaining_size
-        // CR = <condition>
-        // LR = <return address>
-        // No other registers can be used, other than SPRG
-         
-        .global_function gpsm_dcm_fast_write
-
-gpsm_dcm_fast_write:
-        
-        _ssx_irq_status_clear %r4, %r6, %r7 //clear status first
-
-        lwz    %r6, 0(%r3)                  //load data pointer
-        lwz    %r7, 4(%r3)                  //load remaining size
-
-        cmpwi  %r7, 0                       //if size == 0
-        beq    exit_write_handler           //exit fast write
-        cmpwi  %r7, 1                       //if size == 1
-        beq    load_one_byte                //load only one byte 
-
-        lhz    %r5, 0(%r6)                  //otherwise load two bytes 
-        addi   %r6, %r6, 2                  //data pointer+2
-        addi   %r7, %r7,-2                  //remaining size-2
-        b      form_and_send_packet         //then form and send packet
-
-load_one_byte:
-
-        lbz    %r5, 0(%r6)                  //load one byte from buffer
-        addi   %r6, %r6, 1                  //data pointer+1
-        addi   %r7, %r7,-1                  //remaining size-1
-        
-form_and_send_packet:
-
-        stw    %r6, 0(%r3)                  //store updated data pointer
-        stw    %r7, 4(%r3)                  //store updated remaining size
-                                            
-        lis    %r6, GPSM_IC_CONTINUOUS_DATA //load cmd code to upper bits 
-        or     %r5, %r5, %r6                //load data into lower bits
-        slwi   %r5, %r5, 8                  //packet<<8 to give ecc field
-        _stwi  %r5, %r7, PMC_INTCHP_MSG_WDATA               //send packet 
-        blr                                                 //return
-
-exit_write_handler:       
-
-        bl __ssx_irq_fast2full              //convert fast to full irq handler
-        _ssx_irq_disable %r4, %r6, %r7      //disable this irq
-        addi %r3, %r3, 8                    //argument pointer to semaphore
-        bl ssx_semaphore_post               //post to that semaphore
-        b  __ssx_irq_full_mode_exit         //exit
-
-        .epilogue gpsm_dcm_fast_write
-
-
-
-        // The gpsm_dcm_read fast handler.  
-
-        // Register use:        
-        //
-        // R3 = Entry: void *arg;    *arg -> GpsmDcmFast(data,size,semaphore)
-        // R4 = Entry: SsxIrqId irq; irq : constant
-        // R5 = Entry: int priority; priority -> data 
-        // R6 = data_pointer
-        // R7 = remaining_size
-        // CR = <condition>
-        // LR = <return address>
-        // No other registers can be used, other than SPRG
-         
-        .global_function gpsm_dcm_fast_read
-
-gpsm_dcm_fast_read:
-        
-        _ssx_irq_status_clear %r4, %r6, %r7 //clear status first
-
-        lwz    %r7, 4(%r3)                  //load remaining size
-        cmpwi  %r7, 0                       //if size == 0
-        beq    exit_read_handler            //then exit fast read      
-
-        _lwzi  %r6, %r7, PMC_INTCHP_MSG_RDATA    //receive packet     
-        
-        extrwi %r5, %r6, 16, 8              //extract data to r5
-        extrwi %r6, %r6, 8,  0              //extract cmd code to r6
-        li     %r7, GPSM_IC_CONTINUOUS_DATA //designated cmd code to r7
-
-        cmpw   %r6, %r7                     //compare and check cmd code
-        bne    panic_read_packet            //panic on wrong cmd code 
-
-        lwz    %r6, 0(%r3)                  //load data pointer
-        lwz    %r7, 4(%r3)                  //load remaining size
-
-        cmpwi  %r7, 1                       //if only one byte left
-        beq    store_one_byte               //then store only one byte
-
-        sth    %r5, 0(%r6)                  //otherwise store two bytes to buf
-        addi   %r6, %r6, 2                  //data pointer+2
-        addi   %r7, %r7,-2                  //remaining size-2 
-        b      check_read_status            //check read status
-
-store_one_byte:
-
-        stb    %r5, 0(%r6)                  //store one byte to buf
-        addi   %r6, %r6, 1                  //data pointer+1
-        addi   %r7, %r7,-1                  //remaining size-1
- 
-check_read_status:
-
-        stw    %r6, 0(%r3)                  //store updated data pointer
-        stw    %r7, 4(%r3)                  //store updated remaining size
-
-        cmpwi  %r7, 0                       //if size == 0
-        beq    exit_read_handler            //then terminate fast read
-        blr                                 //return if still data left
-
-exit_read_handler:
-
-        bl __ssx_irq_fast2full              //convert fast to full irq handler
-        _ssx_irq_disable %r4, %r6, %r7      //disable this irq 
-        addi %r3, %r3, 8                    //argument pointer to semaphore
-        bl ssx_semaphore_post               //post to that semaphore
-        b  __ssx_irq_full_mode_exit         //exit
-
-panic_read_packet:
-
-        SSX_PANIC(GPSM_DCM_READ_NOT_WRITE_DATA) //PANIC if cmd code is wrong
-
-        .epilogue gpsm_dcm_fast_read
-/// \endcond
-
diff --git a/src/lib/gpsm_init.c b/src/lib/gpsm_init.c
deleted file mode 100755
index ff0f68b..0000000
--- a/src/lib/gpsm_init.c
+++ /dev/null
@@ -1,1639 +0,0 @@
-// $Id: gpsm_init.c,v 1.10 2015/05/16 17:43:12 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/gpsm_init.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file gpsm_init.c
-/// \brief Global Pstate Machine procedures only required to initialize Pstate
-/// and Pstate modes.
-///
-/// In OCC product firmware this code is only needed immediately after IPL to
-/// set up Pstate tables and enable Pstates.  This code could be run from an
-/// applet or otherwise removed once Pstates are initialized. Note that this
-/// file cointains code only; some global variables referenced here are
-/// defined in gpsm.c, along with the run-time APIs for GPSM.
-///
-/// The following sequence of procedures is required to initialize the GPSM
-/// mechanism, enable Pstate mode, and further enable Hardware Pstate Mode.
-///
-/// \code
-///
-/// PstateSuperStructure* pss;
-/// GlobalPstateTable *gpst;
-/// GpsmEnablePstatesMasterInfo info;
-/// Pstate voltage_pstate, frequency_pstate;
-///
-/// gpsm_initialize(pss, gpst);
-/// gpsm_enable_pstates_master(&info, &voltage_pstate, &frequency_pstate);
-/// gpsm_enable_pstates_slave(&info, voltage_pstate, frequency_pstate);
-/// gpsm_hw_mode();
-///
-/// \endcode
-///
-/// Executing these procedures enables Pstate control of voltage and
-/// frequency, and leaves the chip quiesced in Firmware Pstate mode. These
-/// procedures initializes both central (PMC) and remote (PCB Slave) Pstate
-/// hardware to fully enable Pstate control of voltage and frequency.
-/// Carefully note the procedure sequence preconditions and postconditions.
-///
-/// In the case of a DCM environment, the DCM master must execute the sequence
-/// as follows:
-///
-/// \code
-///
-/// PstateSuperStructure* pss;
-/// GlobalPstateTable *gpst;
-/// GpsmEnablePstatesMasterInfo info;
-/// Pstate voltage_pstate, frequency_pstate;
-///
-/// gpsm_initialize(pss, gpst);
-/// gpsm_enable_pstates_master(&info, &voltage_pstate, &frequency_pstate);
-///
-/// <em> Send voltage_pstate and frequency_pstate to the slave and wait for
-/// confirmation that the procedure has completed. </em>
-///
-/// gpsm_enable_pstates_slave(&info, voltage_pstate, frequency_pstate);
-/// gpsm_hw_mode();
-///
-/// <em> Send command to the slave to execute gpsm_hw_mode() </em>
-///
-/// \endcode
-///
-/// The DCM slave executes the following sequence
-/// \code
-/// PstateSuperStructure* pss;
-/// GlobalPstateTable *gpst;
-/// Pstate voltage_pstate, frequency_pstate;
-///
-/// gpsm_initialize(pss, gpst);
-///
-/// <em> Receive voltage_pstate and frequency_pstate from the masterand wait for
-/// confirmation that the procedure has completed. </em>
-///
-/// gpsm_enable_pstates_slave(0, voltage_pstate, frequency_pstate);
-///
-/// <em> Wait for a command from the master to execute gpsm_hw_mode(). </em>
-///
-/// \endcode
-///
-/// <b> Preconditions </b>
-///
-/// - This sequence must be called from a thread as it must be able to block
-/// for the completion of GPSM events.
-///
-/// - The fundamental precondition is the assumption that any snapshot of the
-/// voltage/frequency state of the system yields a legal state. As long as
-/// this is true, then this sequence should never take the system to an
-/// illegal V/F state.
-///
-/// - CPM-DPLL mode should be disabled, and all undervolting controls are
-/// assumed to be at their nominal values.  Correctness can not guaranteed
-/// otherwise.
-///
-/// - iVRM mode should be disabled prior to calling this procedure.
-/// Correctness can not be guaranteed otherwise.
-///
-///
-/// <b> Standard/Benign Postconditions after executing
-/// gpsm_enable_pstates_slave() </b>
-///
-/// - The system will be in Firmware Pstate Mode, using the Local and Global
-/// Pstate tables installed by gpsm_initialize().  Pstate 0 will be mapped to
-/// the nominal frequency (modulo rounding down) of the
-/// 'nominal_frequency_khz' field of the Global Pstate table.
-///
-/// - All core chiplet frequencies will be under the control of the PMCR Local
-/// Pstate.
-///
-/// - The Global Actual Pstate immediately prior to the final entry of Pstate
-/// mode is the Pstate that most closely matches an arbitrary snapshot of the
-/// system voltage during the execution of this procedure.
-///
-/// - The PMCR and PMICR are not modified, therefore the Global Pstate
-/// subsequent to the release of Hardware Pstate mode is arbitrary.
-///
-/// - The PMC_RAIL_BOUNDS register is set to the maximum legal bounds allowed
-/// by Global Pstate Table
-///
-/// - IVRM is setup and enabled if Local Pstate Table is installed.
-///
-/// - Resonant Clock is setup and enabled if Resonant Clock is installed.
-///
-/// <b> Side-Effects </b>
-///
-/// - The dpll_fmax and dpll_fmin fields of the FREQ_CTRL_REG in each core are
-/// set to an arbitrary value. The dpll_fmax_bias is set to the value of the
-/// 'dpll_fmax_bias' field of the \a gpst.
-///
-/// - The core-level PCBS_POWER_MANAGEMENT_BOUNDS_REG registers are
-/// set to the maximum legal bounds.  This is required due to Pstate table
-/// constraints.
-///
-/// \todo - How to handle redundant SPIVID interfaces?  Here we get the
-/// current volatge from interface 0.
-///
-/// \bug Check to make sure that the PMC_CORE_DECONFIGURATION_REG matches
-/// multicast group 1.
-///
-/// \bug Code marked with ** VBU ** is necessary for VBU/EPO simulation, needs
-/// to be scrubbed once this is working in VBU.
-
-#include "ssx.h"
-#include "ssx_io.h"
-#include "gpsm.h"
-#include "vrm.h"
-#include "heartbeat.h"
-#include "special_wakeup.h"
-
-// Debugging support
-
-#if 0
-#define _BREAK                                                          \
-    {                                                                   \
-        fprintf(stderr, "%s:%d: _BREAK trapped error rc = 0x%08x (-0x%08x)\n", \
-                __FILE__, __LINE__, rc, -rc);                           \
-        SSX_PANIC(GPSM_ERROR_BREAK);                                    \
-    }
-#else
-#define _BREAK break;
-#endif
-
-
-/// Flag set once gpsm_initialize() has been successfully completed.
-uint8_t G_gpsm_initialized = 0;
-
-
-/// Install a (new) Global Pstate Table
-///
-/// \param[out] o_gpst A pointer to a properly-aligned GlobalPstateTable
-///
-/// \param[in] i_source A pointer to an initialized source GlobalPstateTable
-/// that will be copied to \a gpst (if not in fact the same as \a gpst).
-///
-/// This procedure will likely only be called once, at initialization, and
-/// then only as part of the gpsm_initialize() procedure.  The procedure:
-///
-/// - Copies the \a source to the \a gpst if required.
-///
-/// - Installs a pointer to the Global Pstate Table in the PMC hardware.
-///
-/// - Sets up the PMC Pstate clipping bounds.
-///
-/// - Sets up the Pstate stepping parameters from the GlobalPstateTable
-///
-/// - Clears the local undervolting register (via multicast) and sets the
-/// default undervolting bounds to the entire Local Pstate Table.
-///
-/// - Broadcasts the safe mode Pstate Psafe to the cores and clears the other
-/// fields of the PCBS_OCC_HEARTBEAT_REG, disabling the heartbeat timer.
-/// However the heartbeat timer must not have been active anyway.
-///
-/// \note This procedure does modify the rail bounds.
-///
-/// \note The caller is responsible for the mode-correctness of this
-/// procedure.  This procedure must only be called when the PMC is in Firmware
-/// Pstate Mode.
-///
-/// \retval 0 Success
-///
-/// \retval -GPSM_INVALID_ARGUMENT_GPST_INSTALL The Global Pstate table argument
-/// was either NULL (0) or improperly aligned, or the \a source was NULL (0).
-///
-/// \retval -GPSM_ILLEGAL_MODE_GPST_INSTALL The PMC does not indicate that the
-//  system is in Firmware Pstate Mode, or the heartbeat is enabled.
-
-int
-gpsm_gpst_install(GlobalPstateTable* o_gpst,
-                  const GlobalPstateTable* i_source)
-{
-    pmc_occ_heartbeat_reg_t pohr;
-    pmc_parameter_reg0_t ppr0;
-    pmc_parameter_reg1_t ppr1;
-    pmc_global_pstate_bounds_reg_t pgpbr;
-    pmc_rail_bounds_register_t prbr;
-    pmc_undervolting_reg_t pur;
-    pcbs_occ_heartbeat_reg_t pcbsohr;
-
-    int rc;
-
-    TRACE_GPSM(TRACE_GPSM_GPST_INSTALL);
-
-    do {
-
-        // Optional bypass of the procedure
-
-        if (i_source->options.options & PSTATE_NO_INSTALL_GPST) {
-
-            rc = 0;
-            break;
-        }
-
-        // Check presence and alignment of the Pstate table, and proper Pstate
-        // and heartbeat modes.
-
-        if ((o_gpst == 0) ||
-            ((unsigned long)o_gpst % POW2_32(GLOBAL_PSTATE_TABLE_ALIGNMENT))) {
-            rc = -GPSM_INVALID_ARGUMENT_GPST_INSTALL;
-            _BREAK;
-        }
-
-        pohr.value = in32(PMC_OCC_HEARTBEAT_REG);
-        rc = getscom(MC_ADDRESS(PCBS_OCC_HEARTBEAT_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(pcbsohr.value));
-        if (rc) _BREAK;
-
-        if (!gpsm_fw_mode_p() || pohr.fields.pmc_occ_heartbeat_en
-            || pcbsohr.fields.occ_heartbeat_enable) {
-            rc = -GPSM_ILLEGAL_MODE_GPST_INSTALL;
-            _BREAK;
-        }
-
-
-        // Copy \a source to \a gpst if required, then install the Pstate
-        // table, Pvsafe and Pstate stepping parameters, and set the clipping
-        // bounds as well as the rail bounds
-
-        if ((o_gpst != i_source) &&
-            !(i_source->options.options & PSTATE_NO_COPY_GPST)) {
-
-            memcpy(o_gpst, i_source, sizeof(*o_gpst));
-        }
-
-        ppr1.value = in32(PMC_PARAMETER_REG1);
-        ppr1.fields.ba_sram_pstate_table =
-            (unsigned long)o_gpst >> GLOBAL_PSTATE_TABLE_ALIGNMENT;
-        ppr1.fields.pvsafe = i_source->pvsafe;
-
-        // This fix is added per SW260911
-        // Minimum Frequency in the system is given by MRW attribute
-        // PState Datablock procedure will read the attribute then
-        // convert it into pstate _pfloor_ and put it into
-        // Global Pstate Table. GPSM here consumes the value
-        // and set both lower bounds: pmin_rail(PMC) and pmin_clip(PCBS)
-        // and two safe pstates: pvsafe(PMc) and psafe(PCBS) to be
-        // _pfloor_ if _pfloor_ is higher than their default(gpst_pmin)
-        // so that we should never run with frequency below the floor
-        // even in safe mode
-        if (ppr1.fields.pvsafe < i_source->pfloor && i_source->pfloor != 0)
-            ppr1.fields.pvsafe = i_source->pfloor;
-
-        out32(PMC_PARAMETER_REG1, ppr1.value);
-
-        pgpbr.value = 0;
-        pgpbr.fields.gpsi_min = gpst_pmin(i_source) - PSTATE_MIN;
-        pgpbr.fields.gpst_number_of_entries_minus_one = i_source->entries - 1;
-        out32(PMC_GLOBAL_PSTATE_BOUNDS_REG, pgpbr.value);
-
-        ppr0.value = in32(PMC_PARAMETER_REG0);
-        ppr0.fields.pstate_stepsize = i_source->pstate_stepsize;
-        ppr0.fields.vrm_stepdelay_range = i_source->vrm_stepdelay_range;
-        ppr0.fields.vrm_stepdelay_value = i_source->vrm_stepdelay_value;
-        ppr0.fields.gpsa_timeout_value_sel = 1;
-        out32(PMC_PARAMETER_REG0, ppr0.value);
-
-        prbr.value = 0;
-        prbr.fields.pmin_rail = gpst_pmin(i_source)+1;
-        prbr.fields.pmax_rail = gpst_pmax(i_source);
-
-        // This fix is added per SW260911
-        // Minimum Frequency in the system is given by MRW attribute
-        // PState Datablock procedure will read the attribute then
-        // convert it into pstate _pfloor_ and put it into
-        // Global Pstate Table. GPSM here consumes the value
-        // and set both lower bounds: pmin_rail(PMC) and pmin_clip(PCBS)
-        // and two safe pstates: pvsafe(PMc) and psafe(PCBS) to be
-        // _pfloor_ if _pfloor_ is higher than their default(gpst_pmin)
-        // so that we should never run with frequency below the floor
-        // even in safe mode
-        if (prbr.fields.pmin_rail < i_source->pfloor && i_source->pfloor != 0)
-            prbr.fields.pmin_rail = i_source->pfloor;
-
-        out32(PMC_RAIL_BOUNDS_REGISTER, prbr.value);
-
-        // Clear the undervolting control, and set the undervolting range to
-        // the entire Global Pstate Table range.
-
-        pur.value = 0;
-        pur.fields.puv_min = gpst_pmin(i_source);
-        pur.fields.puv_max = gpst_pmax(i_source);
-        pur.fields.kuv_request = 0;
-        out32(PMC_UNDERVOLTING_REG, pur.value);
-
-
-        // Broadcast the safe mode Pstate Psafe to the cores, disabling the
-        // heartbeat (which must have been disabled anyway) and clearing any
-        // other heartbeat setup.
-
-        pcbsohr.value = 0;
-        pcbsohr.fields.psafe = i_source->psafe;
-
-        // This fix is added per SW260911
-        // Minimum Frequency in the system is given by MRW attribute
-        // PState Datablock procedure will read the attribute then
-        // convert it into pstate _pfloor_ and put it into
-        // Global Pstate Table. GPSM here consumes the value
-        // and set both lower bounds: pmin_rail(PMC) and pmin_clip(PCBS)
-        // and two safe pstates: pvsafe(PMc) and psafe(PCBS) to be
-        // _pfloor_ if _pfloor_ is higher than their default(gpst_pmin)
-        // so that we should never run with frequency below the floor
-        // even in safe mode
-        if (pcbsohr.fields.psafe < i_source->pfloor && i_source->pfloor != 0)
-            pcbsohr.fields.psafe = i_source->pfloor;
-
-        rc = putscom(MC_ADDRESS(PCBS_OCC_HEARTBEAT_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     pcbsohr.value);
-        if (rc) _BREAK;
-
-        rc = 0;
-
-    } while(0);
-
-    return rc;
-}
-
-
-/// Install a (new) Local Pstate Array
-///
-/// \param[in] i_lpsa A pointer to a LocalPstateArray to install in every
-/// configured core.
-///
-/// \param[in] i_options Options controlling the installation, or a NULL (0)
-/// pointer to indicate fully default behavior.
-///
-/// This procedure will likely only be called once, at initialization, and
-/// then only as part of the gpsm_initialize() procedure.  The procedure:
-///
-/// - Power on PFET Voltage Reference Circuit
-///
-/// - Perform the binary search for IVRM Calibration
-///
-/// - Uploads the LocalPstateArray to every core using multicast.
-///
-/// - Sets up the Local Pstate table bounds in every core using multicast.
-///
-/// - Sets the step delay parameters for every core using multicast.
-///
-/// - Clears the local undervolting register (via multicast) and sets the
-/// default undervolting bounds to the entire Local Pstate Table.
-///
-/// - Setup IVRM delay parameters
-///
-/// - Enable IVRM
-///
-/// \note This procedure \e does \e not modify the rail bounds.
-///
-/// \note The caller is responsible for the mode-correctness of this
-/// procedure.  This procedure must only be called when the iVRM are
-/// disabled, the DPLL is in "normal" (not CPM-DPLL) mode, and core heartbeats
-/// are disabled.
-///
-/// \retval 0 Success
-///
-/// \retval -GPSM_INVALID_ARGUMENT_LPST_INSTALL The Local Pstate array argument
-/// was NULL (0).
-///
-/// \retval -GPSM_ILLEGAL_MODE_LPST_INSTALL iVRM mode, CPM-DPLL mode, or the
-/// local heartbeat appears to be enabled in at least one core.
-///
-/// \retval -GPSM_IVRM_CALIBRATION_TIMEOUT, if IVRM Calibration does not
-/// complete in time.
-///
-/// \retval -GPSM_IVRM_GROSS_OR_FINE, if ivrm_gross_or_fine_err is set
-///
-/// \retval -GPSM_PSTATE_ENABLED, if pstate is enabled before enabling IVRM
-///
-/// \retval others This API may also return non-0 codes from
-/// getscom()/putscom()
-
-int
-gpsm_lpsa_install(const LocalPstateArray* i_lpsa,
-                  const PstateOptions* i_options)
-{
-    pcbs_ivrm_control_status_reg_t picsr;
-    pcbs_dpll_cpm_parm_reg_t pdcpr;
-    pcbs_pstate_index_bound_reg_t ppibr;
-    pcbs_ivrm_vid_control_reg0_t pivcr0;
-    pcbs_ivrm_vid_control_reg1_t pivcr1;
-    pcbs_undervolting_reg_t pur;
-    pcbs_pmerr_reg_t ppr;
-    pcbs_pcbspm_mode_reg_t ppmr;
-    pmc_core_deconfiguration_reg_t pcdr;
-    ChipConfigCores cores, wakedup;
-    SsxTimebase timeout;
-    int i, rc, timeout_rc = 0;
-    uint32_t configured_cores;
-    int flag, core;
-
-    TRACE_GPSM(TRACE_GPSM_LPSA_INSTALL);
-
-    do {
-
-        // Optional bypass of this procedure
-
-        if ((i_options != 0) &&
-            (i_options->options & PSTATE_NO_INSTALL_LPSA)) {
-
-            rc = 0;
-            break;
-        }
-
-        // No LPST Install and IVRM Enable if there is no configued cores
-
-        configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);
-        flag = 1;
-        for (core = 0; core < PGP_NCORES; core++, configured_cores <<= 1) {
-            if (!(configured_cores & 0x80000000)) continue;
-            flag = 0;
-        }
-        if (flag == 1) {
-            rc = 0;
-            break;
-        }
-
-        // Check the array for existence.  Do an OR-combining multicast read
-        // to see if any of the cores have iVRM enabled, have the heartbeat
-        // enabled, or any cores are running in CPM-DPLL mode.
-
-        if (i_lpsa == 0) {
-            rc = -GPSM_INVALID_ARGUMENT_LPST_INSTALL;
-            _BREAK;
-        }
-        rc = getscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(picsr.value));
-        if (rc) _BREAK;
-        rc = getscom(MC_ADDRESS(PCBS_DPLL_CPM_PARM_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(pdcpr.value));
-        if (rc) _BREAK;
-
-        if (picsr.fields.ivrm_fsm_enable ||
-            pdcpr.fields.cpm_filter_enable) {
-            rc = -GPSM_ILLEGAL_MODE_LPST_INSTALL;
-            _BREAK;
-        }
-
-        // In case cores are in deep winkle so that ivrm caliburation
-        // will fail, insert special wakeup first
-        pcdr.value = in32(PMC_CORE_DECONFIGURATION_REG);
-        cores = ~pcdr.fields.core_chiplet_deconf_vector;
-        rc = occ_special_wakeup(1, cores, 25, &wakedup);
-        if (rc) _BREAK;
-
-        // Power on PFET Voltage Reference Circuit
-        picsr.fields.pvref_en = 1;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     picsr.value);
-        if (rc) _BREAK;
-
-        // Wait 10us for circuit to power on
-        timeout = ssx_timebase_get() + SSX_MICROSECONDS(10);
-        while (ssx_timebase_get() < timeout) {;}
-
-        // Perform the binary search
-        picsr.fields.binsearch_cal_ena = 1;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     picsr.value);
-        if (rc) _BREAK;
-
-        // Check IVRM Calibration is completed
-        // Poll for up to 100us for done before erroring out
-        timeout_rc = -GPSM_IVRM_CALIBRATION_TIMEOUT;
-        timeout = ssx_timebase_get() + SSX_MICROSECONDS(100);
-        while (ssx_timebase_get() < timeout) {
-            rc = getscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                    MC_GROUP_EX, PCB_MULTICAST_AND),
-                         &(picsr.value));
-            if (rc) _BREAK;
-            if (picsr.fields.binsearch_cal_done) {
-                timeout_rc=0;
-                break;
-            }
-        }
-        if (timeout_rc||rc) _BREAK;
-
-        // IVRM Calibration complete, Clear binary search enable
-        picsr.fields.binsearch_cal_ena = 0;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     picsr.value);
-        if (rc) _BREAK;
-
-        // Check if IVRM Gross or Fine Error is set after calibration!
-        rc = getscom(MC_ADDRESS(PCBS_PMERR_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(ppr.value));
-        if (rc) _BREAK;
-        if (ppr.fields.pcbs_ivrm_gross_or_fine_err) {
-            rc = -GPSM_IVRM_GROSS_OR_FINE;
-            _BREAK;
-        }
-
-        // Deassert Special Wakeup
-        rc = occ_special_wakeup(0, cores, 25, &wakedup);
-        if (rc) _BREAK;
-
-        // Upload the Local Pstate Array.  The array is loaded via multicast,
-        // using the built-in auto-increment mechanism.  Then upload the
-        // Pstate bounds register via multicast. Pstate clipping is not
-        // modified.
-
-        rc = putscom(MC_ADDRESS(PCBS_PSTATE_TABLE_CTRL_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     0);
-        if (rc) _BREAK;
-
-        for (i = 0; i < LOCAL_PSTATE_ARRAY_ENTRIES+VDSVIN_ARRAY_ENTRIES; i++) {
-
-            if (i < LOCAL_PSTATE_ARRAY_ENTRIES) {
-                rc = putscom(MC_ADDRESS(PCBS_PSTATE_TABLE_REG,
-                                        MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                i_lpsa->pstate[i].value);
-                if (rc) _BREAK;
-            } else {
-                rc = putscom(MC_ADDRESS(PCBS_PSTATE_TABLE_REG,
-                                        MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                i_lpsa->vdsvin[i-LOCAL_PSTATE_ARRAY_ENTRIES].value);
-                if (rc) _BREAK;
-            }
-
-        }
-
-        ppibr.value = 0;
-        ppibr.fields.lpsi_min = lpst_pmin(i_lpsa) - PSTATE_MIN;
-        ppibr.fields.lpsi_entries_minus_1 = i_lpsa->entries - 1;
-        rc = putscom(MC_ADDRESS(PCBS_PSTATE_INDEX_BOUND_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     ppibr.value);
-        if (rc) _BREAK;
-
-
-        // Install the step delay parameters, then clear the undervolting
-        // control (applicable to the entire range) via multicast.
-
-        pivcr0.value = 0;
-        if (i_lpsa->stepdelay_rising)
-            pivcr0.fields.ivrm_req_pstate_stepdelay_rising =
-                                         i_lpsa->stepdelay_rising;
-        else
-            pivcr0.fields.ivrm_req_pstate_stepdelay_rising = 0xFF;
-        if (i_lpsa->stepdelay_lowering)
-            pivcr0.fields.ivrm_req_pstate_stepdelay_lowering =
-                                         i_lpsa->stepdelay_lowering;
-        else
-            pivcr0.fields.ivrm_req_pstate_stepdelay_lowering = 0XFF;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_VID_CONTROL_REG0,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     pivcr0.value);
-        if (rc) _BREAK;
-
-        ///bug need to determine where these values come from
-        pivcr1.value = 0;
-        pivcr1.fields.ivrm_stabilize_delay_run   = 0x40;
-        pivcr1.fields.ivrm_stabilize_delay_idle  = 0x40;
-        pivcr1.fields.ivrm_pfstr_prop_delay      = 0x1E;
-        pivcr1.fields.ivrm_pfstrvalid_prop_delay = 0xFF;
-        pivcr1.fields.ivrm_vpump_poweron_time    = 0xFF;
-        pivcr1.fields.ivrm_bypass_delay          = 0x1E;
-        pivcr1.fields.pfet_vpump_enable_delay    = 0x4E;
-        pivcr1.fields.ivrm_vid_vout_threshold    = 0x00;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_VID_CONTROL_REG1,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     pivcr1.value);
-        if (rc) _BREAK;
-
-        pur.value = 0;
-        pur.fields.puv_min = lpst_pmin(i_lpsa);
-        pur.fields.puv_max = lpst_pmax(i_lpsa);
-        pur.fields.kuv = 0;
-        rc = putscom(MC_ADDRESS(PCBS_UNDERVOLTING_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     pur.value);
-        if (rc) _BREAK;
-
-        // Set pre_vret_pstate to Non-Functional Pstate
-        // \bug currently set to pmin, is it always same as psafe?
-        rc = getscom(MC_ADDRESS(PCBS_DPLL_CPM_PARM_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(pdcpr.value));
-        if (rc) _BREAK;
-        pdcpr.fields.pre_vret_pstate = lpst_pmin(i_lpsa);
-        rc = putscom(MC_ADDRESS(PCBS_DPLL_CPM_PARM_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     pdcpr.value);
-        if (rc) _BREAK;
-
-        // Checking that PStates are NOT enabled
-        rc = getscom(MC_ADDRESS(PCBS_PCBSPM_MODE_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(ppmr.value));
-        if (rc) _BREAK;
-        if (ppmr.fields.enable_pstate_mode) {
-            rc = -GPSM_PSTATE_ENABLED;
-            _BREAK;
-        }
-
-        // Enable I-VRM FSM
-        rc = getscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_OR),
-                     &(picsr.value));
-        if (rc) _BREAK;
-        picsr.fields.ivrm_fsm_enable = 1;
-        rc = putscom(MC_ADDRESS(PCBS_IVRM_CONTROL_STATUS_REG,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     picsr.value);
-        if (rc) _BREAK;
-
-    } while (0);
-
-    if (timeout_rc && !rc)
-        return timeout_rc;
-    else
-        return rc;
-}
-
-
-/// Install (new) Resonant Clocking Setup
-///
-/// \param[in] i_resclk A pointer to a ResonantClockingSetup to install in
-/// every configured core.
-///
-/// \param[in] i_options Options controlling the installation, or a NULL (0)
-/// pointer to indicate fully default behavior.
-///
-/// This procedure will likely only be called once, at initialization, and
-/// then only as part of the gpsm_initialize() procedure.  The procedure:
-///
-/// - Initializes the Pstate resonance range limits in the register
-/// PCBS_RESONANT_CLOCK_CONTROL_REG1 by multicast.
-///
-/// - Setup parameters in PCBS_RESONANT_CLOCK_CONTROL_REG0 and turn on
-/// Resonant Clock in Hardware Pstate Mode.
-///
-/// \note The caller is responsible for the mode-correctness of this
-/// procedure.  This procedure must only be called when resonant clocking is
-/// disabled and the controls are set for manual mode. Because of the way the
-/// resonant clocking controls are designed we must enable resonant clocking
-/// to update the Pstate bounds! After the bounds are updated resonant
-/// clocking is disabled again.
-///
-/// \retval 0 Success
-///
-/// \retval -GPSM_INVALID_ARGUMENT_RCLK_INSTALL The ResonantClockingSetup
-/// argument was NULL (0).
-///
-/// \retval -GPSM_ILLEGAL_MODE_RCLK_INSTALL Resonant clocking appears to be
-/// enabled or not in manual mode in at least one configured core.
-///
-/// \retval others This API may also return non-0 codes from
-/// getscom()/putscom()
-
-int
-gpsm_resclk_install(const ResonantClockingSetup* i_resclk,
-                    const GlobalPstateTable* i_gpst,
-                    const PstateOptions* i_options)
-{
-    ResonantClockingSetup d_resclk;
-    pcbs_resonant_clock_control_reg0_t prccr0;
-    pcbs_resonant_clock_control_reg1_t prccr1;
-    int rc;
-    uint32_t configured_cores;
-    int flag, core;
-
-    TRACE_GPSM(TRACE_GPSM_RESCLK_INSTALL);
-
-    do {
-
-        // Optional bypass of this procedure
-
-        if ((i_options != 0) &&
-            (i_options->options & PSTATE_NO_INSTALL_RESCLK)) {
-
-            rc = 0;
-            break;
-        }
-
-        // No Resonant Clock Install and Enable if there is no configued cores
-
-        configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);
-        flag = 1;
-        for (core = 0; core < PGP_NCORES; core++, configured_cores <<= 1) {
-            if (!(configured_cores & 0x80000000)) continue;
-            flag = 0;
-        }
-        if (flag == 1) {
-            rc = 0;
-            break;
-        }
-
-        // Check the setup for existence.  Do an AND-combining multicast read
-        // to see if any of the cores have resonant clocking enabled, or are
-        // not in manual mode.
-
-        if (i_resclk == 0) {
-            rc = -GPSM_INVALID_ARGUMENT_RCLK_INSTALL;
-            _BREAK;
-        }
-        rc = getscom(MC_ADDRESS(PCBS_RESONANT_CLOCK_CONTROL_REG0,
-                                MC_GROUP_EX, PCB_MULTICAST_AND),
-                     &(prccr0.value));
-        if (rc) _BREAK;
-
-        if (!prccr0.fields.resclk_dis || !prccr0.fields.resclk_control_mode) {
-            rc = -GPSM_ILLEGAL_MODE_RCLK_INSTALL;
-            _BREAK;
-        }
-
-
-        // Resonant clocking is specified such that it must be enabled (in a
-        // benign manual mode) in order to be set up.
-
-        // Enable resonant clocking in the GP3 register (AND), bit 22. Our
-        // Simics environment does not model the GP3->PRCCR0 connection
-        // currently, and does not enforce the register locks.
-
-        if (!SIMICS_ENVIRONMENT) {
-
-            rc = putscom(MC_ADDRESS(0x100f0013, MC_GROUP_EX,
-                                    PCB_MULTICAST_WRITE),
-                         ~0x0000020000000000ull);
-            if (rc) _BREAK;
-        }
-
-        // Write the PCBS_RESONANT_CLOCK_CONTROL_REG1 with the
-        // Pstate setup, clearing all manual fields.
-
-        // If at least one resonant clocking parm was 0 in PstateSuperStructure
-        // write the register with default values
-        // Low Band  : 2 GHZ to 3.2 GHz
-        // High Band : 3.2 GHZ - Up
-
-        gpst_frequency2pstate(i_gpst, 0,       &(d_resclk.full_csb_ps));
-        gpst_frequency2pstate(i_gpst, 2000000, &(d_resclk.res_low_lower_ps));
-        gpst_frequency2pstate(i_gpst, 3200000, &(d_resclk.res_low_upper_ps));
-        gpst_frequency2pstate(i_gpst, 3200000, &(d_resclk.res_high_lower_ps));
-        gpst_frequency2pstate(i_gpst, 9999999, &(d_resclk.res_high_upper_ps));
-
-        prccr1.value = 0;
-        if (!(i_resclk->full_csb_ps &&
-              i_resclk->res_low_lower_ps &&
-              i_resclk->res_low_upper_ps &&
-              i_resclk->res_high_lower_ps &&
-              i_resclk->res_high_upper_ps)) {
-            prccr1.fields.full_csb_ps       = d_resclk.full_csb_ps;
-            prccr1.fields.res_low_lower_ps  = d_resclk.res_low_lower_ps;
-            prccr1.fields.res_low_upper_ps  = d_resclk.res_low_upper_ps;
-            prccr1.fields.res_high_lower_ps = d_resclk.res_high_lower_ps;
-            prccr1.fields.res_high_upper_ps = d_resclk.res_high_upper_ps;
-        } else {
-            prccr1.fields.full_csb_ps       = i_resclk->full_csb_ps;
-            prccr1.fields.res_low_lower_ps  = i_resclk->res_low_lower_ps;
-            prccr1.fields.res_low_upper_ps  = i_resclk->res_low_upper_ps;
-            prccr1.fields.res_high_lower_ps = i_resclk->res_high_lower_ps;
-            prccr1.fields.res_high_upper_ps = i_resclk->res_high_upper_ps;
-        }
-
-        ///bug need to determine where these values come from
-        prccr1.fields.nonres_csb_value_ti  = 0xC;
-        prccr1.fields.full_csb_value_ti    = 0xF;
-
-        rc = putscom(MC_ADDRESS(PCBS_RESONANT_CLOCK_CONTROL_REG1,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     prccr1.value);
-        if (rc) _BREAK;
-
-
-        // Disable resonant clocking in the GP3 register (OR), bit 22.
-
-        if (!SIMICS_ENVIRONMENT) {
-
-            rc = putscom(MC_ADDRESS(0x100f0014, MC_GROUP_EX,
-                                    PCB_MULTICAST_WRITE),
-                         0x0000020000000000ull);
-            if (rc) _BREAK;
-        }
-
-        // Enable resonant clock pstate hardware mode(control_mode = 0)
-        // Sync Pulse Width maximum value : 0x7  of nest/4 cycles
-        // Sync Delay       maximum value : 0x7F of nest/4 cycles
-        // Sector Buffer Strength Instruction . Low Band  : 0xAAA
-        // Sector Buffer Strength Instruction . High Band : 0xAAA
-
-        prccr0.fields.resclk_control_mode  = 0;
-        prccr0.fields.resclk_sync_pw       = 0x7;
-        prccr0.fields.res_sync_delay_cnt   = 0x7F;
-        prccr0.fields.res_csb_str_instr_lo = 0xAAA;
-        prccr0.fields.res_csb_str_instr_hi = 0x1FF;
-
-        rc = putscom(MC_ADDRESS(PCBS_RESONANT_CLOCK_CONTROL_REG0,
-                                MC_GROUP_EX, PCB_MULTICAST_WRITE),
-                     prccr0.value);
-        if (rc) break;
-
-        // Enable resonant clocking in the GP3 register (AND), bit 22.
-        if (!SIMICS_ENVIRONMENT) {
-
-            rc = putscom(MC_ADDRESS(0x100f0013, MC_GROUP_EX,
-                                PCB_MULTICAST_WRITE),
-                     ~0x0000020000000000ull);
-            if (rc) break;
-        }
-
-    } while (0);
-
-    return rc;
-}
-
-
-/// Initialize the GPSM procedure mechanism
-///
-/// \param[in] i_pss A pointer to the PstateSuperStructure containing the
-/// Global and Local Pstate tables, plus resonant clocking setup and other
-/// options.
-///
-/// \param[out] o_gpst A pointer to a 1-KB aligned GlobalPstateTable which
-/// will be updated with a copy of the GlobalPstateTable from the
-/// PstateSuperStructure.
-///
-/// This API is designed to be called once at system initialization, to set up
-/// GPSM mechanisms, install the Global and Local Pstate tables, and set up
-/// resonant clocking from the PstateSuperStructure.  At the entry of this
-/// procedure it is assumed that the system firmware has initialized the PMC
-/// mode register to either no mode, or to indicate Firmware Pstate Mode.  It
-/// is further assumed that the core chiplets are in a state which will allow
-/// the Local Pstate tables and resonant clocking setup to be installed
-/// without affecting system stability.  Such a state must be guaranteed at
-/// system initialization and after any OCC reset.  If called from any other
-/// context the caller is responsible for ensuring that the system is in a
-/// state that will allow the procedure to run correctly.
-///
-/// This procedure does not enable Pstates or enter any Pstate mode, and does
-/// not alter any voltage or frequency settings.  After the Pstate tables have
-/// been installed, Pstate mode is enabled by calls of
-/// gpsm_enable_pstates_master() and gpsm_enable_pstates_slave() as described
-/// in the commenst for gpsm_init.c.
-///
-/// The initialization of Pstates was split up into these three steps to best
-/// handle the initialization of the slave chip in a DCM.  This procedure
-/// (gpsm_initialize()) can be called by the DCM slave whenever a
-/// PstateSuperStructure is available.  By requirememt and convention this
-/// Pstate SuperStructure will be identical with the one installed by the DCM
-/// master.
-///
-/// The GPSM driver makes few assumptions about how the system firmware has
-/// set up the PMC, but does require some critical setup.
-///
-/// - It is assumed that for DCM configurations the system firmware will have
-/// set the PMC_MODE_REG.enable_interchip_interface (to indicate a DCM
-/// configuration), and set the PMC_MODE_REG.interchip_mode appropriately for
-/// the master and the slave.
-///
-/// - It is assumed that the PMC Core Deconfiguration register implies the
-/// same set of configured cores as the set included in the PCB multicast
-/// group covering all cores.
-///
-/// All GPSM procedures use the same semaphore, which is set by the interrupt
-/// handler for all GPSM interrupts.  The GPSM driver claims the PMC protocol
-/// ongoing, voltage change ongoing, and PMC Sync interrupts.
-///
-/// Once the interrupts are set up, the GlobalPstateTable is copied from the
-/// PstateSuperStructure to its proper location and installed.  Next, the
-/// Local Pstate tables and resonant clocking setup are installed into all
-/// cores by multicast SCOM.
-///
-/// \retval 0 Success
-///
-/// \retval -GPSM_INVALID_OBJECT Either the \a i_pss or \a o_gpst are NULL (0).
-///
-/// \retval -GPSM_INVALID_MAGIC The 'magic number' of the PstateSuperStructure
-/// is different from that expected.
-///
-/// \retval -GPSM_ILLEGAL_MODE_GPSM_INIT Either the PMC indicates a Pstate mode
-/// is active, one or more cores appear to have iVRM enabled, or one or more
-/// cores appear to have resonant clocking enabled.
-///
-/// \retval others This API may also return codes from gpsm_gpst_install(),
-/// gpsm_lpsa_install() and gpsm_resclk_install().
-
-int
-gpsm_initialize(const PstateSuperStructure* i_pss,
-                GlobalPstateTable* o_gpst)
-{
-    pmc_mode_reg_t pmr;
-    int rc;
-
-    TRACE_GPSM(TRACE_GPSM_INITIALIZE);
-
-    do {
-
-        // Check for a valid PstateSuperStructure and GlobalPstateTable
-
-        if ((i_pss == 0) || (o_gpst == 0)) {
-
-            rc = -GPSM_INVALID_OBJECT;
-            _BREAK;
-        }
-
-        if (i_pss->magic != PSTATE_SUPERSTRUCTURE_GOOD1 &&
-            i_pss->magic != PSTATE_SUPERSTRUCTURE_GOOD2 &&
-            i_pss->magic != PSTATE_SUPERSTRUCTURE_GOOD3 &&
-            i_pss->magic != PSTATE_SUPERSTRUCTURE_GOOD4) {
-
-            rc = -GPSM_INVALID_MAGIC;
-            _BREAK;
-        }
-
-
-        // Check/set up the PMC mode register
-
-        pmr.value = in32(PMC_MODE_REG);
-        if (pmr.fields.enable_hw_pstate_mode ||
-            pmr.fields.enable_fw_auction_pstate_mode) {
-            rc = -GPSM_ILLEGAL_MODE_GPSM_INIT;
-            _BREAK;
-        }
-        if (!pmr.fields.enable_fw_pstate_mode) {
-
-            pmr.fields.enable_fw_pstate_mode = 1;
-            out32(PMC_MODE_REG, pmr.value);
-        }
-
-        // ** VBU **
-        pmr.fields.halt_pstate_master_fsm = 0;
-        out32(PMC_MODE_REG, pmr.value);
-
-
-        // Initialize interrupt handling
-
-        ssx_semaphore_create(&G_gpsm_protocol_semaphore, 0, 1);
-
-        ssx_irq_disable(PGP_IRQ_PMC_PROTOCOL_ONGOING);
-        ssx_irq_disable(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING);
-        ssx_irq_disable(PGP_IRQ_PMC_SYNC);
-
-        ssx_irq_setup(PGP_IRQ_PMC_PROTOCOL_ONGOING,
-                      SSX_IRQ_POLARITY_ACTIVE_LOW,
-                      SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-
-        ssx_irq_setup(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING,
-                      SSX_IRQ_POLARITY_ACTIVE_LOW,
-                      SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-
-        ssx_irq_setup(PGP_IRQ_PMC_SYNC,
-                      SSX_IRQ_POLARITY_ACTIVE_HIGH,
-                      SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-
-
-        ssx_irq_handler_set(PGP_IRQ_PMC_PROTOCOL_ONGOING,
-                            ssx_semaphore_post_handler,
-                            (void *)(&G_gpsm_protocol_semaphore),
-                            SSX_NONCRITICAL);
-
-        ssx_irq_handler_set(PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING,
-                            ssx_semaphore_post_handler,
-                            (void *)(&G_gpsm_protocol_semaphore),
-                            SSX_NONCRITICAL);
-
-        ssx_irq_handler_set(PGP_IRQ_PMC_SYNC,
-                            ssx_semaphore_post_handler,
-                            (void *)(&G_gpsm_protocol_semaphore),
-                            SSX_NONCRITICAL);
-
-        // Install the Global Pstate table, Local Pstate Array and resonant
-        // clocking setup, using options contained in the PstateSuperStructure.
-
-        rc = gpsm_gpst_install(o_gpst, &(i_pss->gpst));
-        if (rc) _BREAK;
-
-        rc = gpsm_lpsa_install(&i_pss->lpsa,
-                               &(i_pss->gpst.options));
-        if (rc) _BREAK;
-
-        rc = gpsm_resclk_install(&i_pss->resclk,
-                                 &(i_pss->gpst),
-                                 &(i_pss->gpst.options));
-        if (rc) _BREAK;
-
-        G_gpsm_initialized = 1;
-
-    } while (0);
-
-    return rc;
-}
-
-
-// Step voltage manually
-//
-// This API is only (?) used by gpsm_enable_pstates_master[slave]().  It is
-// used to make a (hopefully) minor adjustment between the current voltage and
-// the target voltage associated with the initial Global Actual Pstate. In
-// cases where the current voltage is not represented in the new Pstate table,
-// this routine may take a long time as it will do many single-VID-code steps
-// as it gradually moves between the current and target voltages.
-//
-// Voltage change direction is determined by the difference in the Vdd VIDs,
-// and the alogorithm mimics the P7 PVID stepping protocol.  If voltage is
-// going up, Vdd and Vcs slew together.  If voltage is going down, Vdd slews
-// twice for every change in Vcs.  Note that given a Vdd differential we can't
-// assume which way Vcs is moving.
-//
-// The use of Vcs offsets instead of straight-up VID codes in the hardware is
-// extremely confusing, especially since the offsets are defined in normal
-// order as opposed to VID codes which decrease as voltage increases.
-
-// Racall that the inputs are VID codes (lower VID --> higher voltage)
-
-static int
-_manual_step_voltage(const uint8_t i_currentVdd,
-                     const uint8_t i_currentVcs,
-                     const uint8_t i_targetVdd,
-                     const uint8_t i_targetVcs)
-{
-    int rc, parity;
-    pmc_global_actual_voltage_reg_t pgavr;
-    uint8_t currentVdd, currentVcs;
-
-    TRACE_GPSM(TRACE_MANUAL_STEP_VOLTAGE);
-
-    do {
-
-        rc = 0;
-        currentVdd = i_currentVdd;
-        currentVcs = i_currentVcs;
-        parity = 1;
-
-        while ((currentVdd != i_targetVdd) &&
-               (currentVcs != i_targetVcs)) {
-
-            if (currentVdd > i_targetVdd) {
-
-                // Voltage going up, slew Vdd and Vcs together. Parity remains
-                // 1.
-
-                currentVdd--;
-
-            } else if (currentVdd > i_targetVdd) {
-
-                // Voltage going down, only slew Vcs every other time. Parity
-                // is inverted.
-
-                currentVdd++;
-                parity = 1 - parity;
-
-            } else {
-
-                // Vdd not moving, set parity so Vcs will move every time.
-
-                parity = 1;
-            }
-
-            if (parity) {
-                if (currentVcs < i_targetVcs) {
-                    currentVcs++;
-                } else if (currentVcs > i_targetVcs) {
-                    currentVcs--;
-                }
-            }
-
-            rc = gpsm_quiesce();
-            if (rc) _BREAK;
-
-            pgavr.value = 0;
-            pgavr.fields.evid_vdd = currentVdd;
-            pgavr.fields.evid_vcs = -((int)currentVcs - (int)currentVdd);
-            out32(PMC_GLOBAL_ACTUAL_VOLTAGE_REG, pgavr.value);
-        }
-        if (rc) _BREAK;
-
-        rc = gpsm_quiesce();
-        if (rc) _BREAK;
-
-    } while (0);
-
-    return rc;
-}
-
-
-// This is a 'prologue' sequence executed in each core chiplet during the
-// initialization of Pstates.  The set of cores to operate on is taken from
-// the current value of the PMC_CORE_DECONFIGURATION_REG.
-//
-// At entry it assumed that iVRM and CPM-DPLL are disabled. It also clears
-// possible safe mode dails before enable pstate.
-//
-// At exit, the following will be true for all configured cores:
-//
-// - The core will be in DPLL frequency override mode with Fmin and Fmax set
-// to the frequency implied by the given Pstate in the given Pstate table with
-// 0 undervolting.
-//
-// - The Fmax bias of the core is set from the Pstate table.
-//
-// - The Fnom of the core is set from the Pstate table.
-//
-// - Pstate mode is enabled in the core and global requests are enabled.
-//
-// - The Local Actual Pstate is being controlled by the Pstate mechanism.
-//
-// - The PMCR will have been updated to the \a frequencyPstate (both global
-// and local) and the global bids (should be) consistent. Auto-override modes
-// in the PMCR are not modified.
-
-static int
-_enable_pstates_core_prologue(const GlobalPstateTable* i_gpst,
-                              const Pstate i_frequency_pstate,
-                              const gpst_entry_t i_entry)
-{
-    int rc, core;
-    unsigned int bogus;
-    uint32_t configured_cores;
-    DpllCode fNom, fPstate;
-    pcbs_pmgp1_reg_t pmgp1;
-    pcbs_freq_ctrl_reg_t pfcr;
-    pcbs_pcbspm_mode_reg_t ppmr;
-    pcbs_power_management_control_reg_t pmcr;
-    pcbs_power_management_bounds_reg_t ppmbr;
-    pcbs_pmc_vf_ctrl_reg_t ppvcr;
-
-    TRACE_GPSM(TRACE_ENABLE_PSTATES_CORE_PROLOGUE);
-
-    do {
-
-        /* In the event of no configured cores, FW requested to not error out */
-        //rc = -GPSM_CONFIGURATION_ERROR;
-        rc = 0;
-
-        // Do for each core chiplet...
-        configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);
-
-        // Turn off possible safe mode so we can move pstate
-        pcbs_hb_config(0, configured_cores, 0, 0, 0, &bogus);
-        pmc_hb_config(0, 0, 0, &bogus);
-
-        for (core = 0; core < PGP_NCORES; core++, configured_cores <<= 1) {
-
-            if (!(configured_cores & 0x80000000)) continue;
-
-            // The 'nominal' frequency code may be biased per core. This
-            // should not under/over-flow.
-
-            fNom = i_gpst->pstate0_frequency_code[core];
-            rc = bias_frequency(fNom, i_frequency_pstate, &fPstate);
-            if (rc) _BREAK;
-
-
-            /// \bug HW Bug: Chicken-and-egg problem with frequency override
-            /// mode.  We need a different HW control structure here.  This
-            /// may glitch frequency.
-
-            // Initial PMGP1_REG setup
-            //
-            // - Force OCC control of the PM SPRS.  This may have to be
-            // rethought if PHYP ever controls Pstates.
-            //
-            // - Enable DPLL frequency overrides
-
-            pmgp1.value = 0;
-            pmgp1.fields.pm_spr_override_en = 1;
-            pmgp1.fields.dpll_freq_override_enable = 1;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_OR, core),
-                         pmgp1.value);
-            if (rc) _BREAK;
-
-
-            // Update Fmin, Fmax, Fmax bias and Pstate0 frequency.
-
-            pfcr.value = 0;
-            pfcr.fields.dpll_fmin = fPstate;
-            pfcr.fields.dpll_fmax = fPstate;
-            pfcr.fields.dpll_fmax_bias = i_gpst->dpll_fmax_bias[core];
-            pfcr.fields.frequ_at_pstate0 = fNom;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_FREQ_CTRL_REG, core),
-                         pfcr.value);
-            if (rc) _BREAK;
-
-
-            /// \bug HW BUG : PCBS_Power_Management_Bounds_reg hardware reset
-            /// is whack, violating the Pstate constraints. (HW216565).
-            /// Deferred to Venice.  Not a problem for us, we always set up
-            /// this register.
-
-            // The PCBS clipping is initialized to the limits present in the
-            // _global_ Pstate table.  This is necessary for correctness of
-            // the PCBS state machines. If fast-idle modes with retention are
-            // enabled this is also necessary to protect against trying to
-            // drop into non-functional Pstates required to be present in the
-            // _local_ pstate table.
-
-            // \bug Workaround, since pre_vret_pstate is set to pmin currently
-            // until pstate super structure and pstate data block procedure
-            // support an entry as non-functional pstate, need to set lower
-            // clip bound to be the pstate one above pmin to make pmin
-            // essentially a non-functional pstate for now
-
-            ppmbr.value = 0;
-            ppmbr.fields.pmin_clip = gpst_pmin(i_gpst)+1;
-            ppmbr.fields.pmax_clip = gpst_pmax(i_gpst);
-
-            // This fix is added per SW260911
-            // Minimum Frequency in the system is given by MRW attribute
-            // PState Datablock procedure will read the attribute then
-            // convert it into pstate _pfloor_ and put it into
-            // Global Pstate Table. GPSM here consumes the value
-            // and set both lower bounds: pmin_rail(PMC) and pmin_clip(PCBS)
-            // and two safe pstates: pvsafe(PMc) and psafe(PCBS) to be
-            // _pfloor_ if _pfloor_ is higher than their default(gpst_pmin)
-            // so that we should never run with frequency below the floor
-            // even in safe mode
-            if (ppmbr.fields.pmin_clip < i_gpst->pfloor && i_gpst->pfloor != 0)
-                ppmbr.fields.pmin_clip = i_gpst->pfloor;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_POWER_MANAGEMENT_BOUNDS_REG,
-                                              core),
-                         ppmbr.value);
-            if (rc) _BREAK;
-
-
-            // Now that we've locked the frequency and set valid clipping
-            // bounds, disable the local Pstate override and allow Global Acks
-            // and Pmax-Sync to propogate.
-
-            rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG, core),
-                         &(pmgp1.value));
-            if (rc) _BREAK;
-
-            pmgp1.value = 0;
-            pmgp1.fields.enable_occ_ctrl_for_local_pstate_eff_req = 1;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_AND, core),
-                         ~pmgp1.value);
-            if (rc) _BREAK;
-
-
-            // Setup PCBS_PMC_VF_CTRL_REG before enable Pstate
-
-            rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_PMC_VF_CTRL_REG, core),
-                         &(ppvcr.value));
-            if (rc) _BREAK;
-
-            ppvcr.fields.pglobal_actual = i_frequency_pstate;
-            ppvcr.fields.maxregvcs = i_entry.fields.maxreg_vdd;
-            ppvcr.fields.maxregvdd = i_entry.fields.maxreg_vcs;
-            ppvcr.fields.evidvcs_eff = i_entry.fields.evid_vdd_eff;
-            ppvcr.fields.evidvdd_eff = i_entry.fields.evid_vcs_eff;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMC_VF_CTRL_REG, core),
-                         ppvcr.value);
-            if (rc) _BREAK;
-
-
-            // Enable Pstate in PCB Slave
-
-            rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, core),
-                         &(ppmr.value));
-            if (rc) _BREAK;
-
-            ppmr.fields.enable_pstate_mode = 1;
-            ppmr.fields.enable_global_pstate_req = 1;
-            ppmr.fields.enable_pmc_pmax_sync_notification = 1;
-
-            // ** VBU **
-            ppmr.fields.dpll_lock_replacement_timer_mode_en = 1;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, core),
-                         ppmr.value);
-            if (rc) _BREAK;
-
-            // Update the PMCR to propagate the global bids
-
-            rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_POWER_MANAGEMENT_CONTROL_REG,
-                                              core),
-                         &(pmcr.value));
-            if (rc) _BREAK;
-
-            pmcr.fields.global_pstate_req = i_frequency_pstate;
-            pmcr.fields.local_pstate_req = i_frequency_pstate;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_POWER_MANAGEMENT_CONTROL_REG,
-                                              core),
-                         pmcr.value);
-            if (rc) _BREAK;
-        }
-        if (rc) _BREAK;
-
-    } while (0);
-
-    return rc;
-}
-
-
-// This is an 'epilogue' sequence executed in each core chiplet during the
-// enablement of Pstate mode.  When this code is executed, the core is in
-// frequency override mode at (or below) the frequency of the Global Pstate
-// Actual. This procedure releases frequency override mode and core-level
-// Pstate operations commence.
-//
-// retval -GPSM_BABYSTEPPER_SYNC_TIMEOUT, if baby stepper sync
-// local_pstate_actual times out
-//
-static int
-_enable_pstates_core_epilogue(void)
-{
-    int rc = 0, timeout_rc = 0, core;
-    uint32_t configured_cores;
-    pcbs_pmgp1_reg_t pmgp1;
-    pcbs_power_management_status_reg_t ppmsr;
-    SsxTimebase timeout;
-
-    TRACE_GPSM(TRACE_ENABLE_PSTATES_CORE_EPILOGUE);
-
-    do {
-
-        configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);
-        for (core = 0; core < PGP_NCORES; core++, configured_cores <<= 1) {
-
-            if (!(configured_cores & 0x80000000)) continue;
-
-            pmgp1.value = 0;
-            pmgp1.fields.dpll_freq_override_enable = 1;
-
-            rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_AND, core),
-                         ~pmgp1.value);
-            if (rc) _BREAK;
-        }
-        if (rc) _BREAK;
-
-        // For Babystepper to catch up sync the local_pstate_actual
-        // Poll for up to 300us for done before erroring out
-
-        timeout_rc = -GPSM_BABYSTEPPER_SYNC_TIMEOUT;
-        timeout = ssx_timebase_get() + SSX_MICROSECONDS(300);
-        while (ssx_timebase_get() < timeout) {
-            rc = getscom(MC_ADDRESS(PCBS_POWER_MANAGEMENT_STATUS_REG,
-                                    MC_GROUP_EX, PCB_MULTICAST_AND),
-                         &(ppmsr.value));
-            if (rc) _BREAK;
-            if (ppmsr.fields.local_pstate_actual ==
-                ppmsr.fields.global_pstate_actual) {
-                timeout_rc = 0;
-                break;
-            }
-        }
-        if (timeout_rc||rc) _BREAK;
-
-    } while(0);
-
-    if (timeout_rc && !rc)
-        return timeout_rc;
-    else
-        return rc;
-
-}
-
-
-/// Enable Pstates in Firmware Mode, initial Master-only phase
-///
-/// \param[out] o_info This structure is populated by this API for use
-/// by a DCM master in gpsm_enable_pstates_slave.  The DCM slave does not
-/// require this information.
-///
-/// \param[out] o_voltage_pstate This parameter returns the Pstate
-/// corresponding to the current system voltage (or the closest safe
-/// approximation).  This parameter must be communicated to the slave before
-/// the slave can call gpsm_enable_pstates_slave().
-///
-/// \param[out] o_frequency_pstate *DEPRECATED* This parameter returns the
-/// Pstate corresponding to the current system voltage (or the closest safe
-/// approximation).  This parameter must be communicated to the slave before
-/// the slave can call gpsm_enable_pstates_slave().
-///
-/// \note This procedure is only called on an SCM or a DCM master.  It will
-/// fail if called on a DCM slave.
-///
-/// \retval 0 Success
-///
-/// \returns All other return codes indicate an error.
-
-int
-gpsm_enable_pstates_master(GpsmEnablePstatesMasterInfo* o_info,
-                           Pstate* o_voltage_pstate,
-                           Pstate* o_frequency_pstate)
-{
-    int rc, search_rc;
-    GlobalPstateTable* gpst;
-    gpst_entry_t voltage_entry;
-
-    TRACE_GPSM(TRACE_GPSM_ENABLE_PSTATES_MASTER);
-
-    do {
-
-        if (gpsm_dcm_slave_p()) {
-            rc = -GPSM_ILLEGAL_MODE_EPSM;
-            _BREAK;
-        }
-
-        // Enter Firmware Pstate Mode.  The gpsm_fw_mode() procedure
-        // guarantees that the GPSM is quiesced at this point.  Recover a
-        // pointer to the Pstate table from PMC.
-
-        rc = gpsm_fw_mode();
-        if (rc) _BREAK;
-
-        gpst = gpsm_gpst();
-
-        // Map the current Vdd VID to a pstate in the new Pstate table.
-        //
-        // As an option (workaround, simulation hack), force the assumption
-        // that the current voltage corresponds to PMIN.  This will not move
-        // the external voltage, however it will force the frequency down to
-        // the PMIN frequency prior to starting Pstate operations.  It is
-        // always safe to change the Pstate from "PMIN", regardless of the
-        // actual external voltage, since the PMIN frequency is safe at any
-        // voltage.
-
-        if (!(gpst->options.options & PSTATE_FORCE_INITIAL_PMIN)) {
-
-            rc = vrm_voltage_read(SPIVRM_PORT(0),
-                                  VRM_RD_VDD_RAIL,
-                                  &(o_info->currentVdd));
-            if (rc) _BREAK;
-            rc = vrm_voltage_read(SPIVRM_PORT(0),
-                                  VRM_RD_VCS_RAIL,
-                                  &(o_info->currentVcs));
-            if (rc) _BREAK;
-
-        } else {
-
-            rc = gpst_entry(gpst, gpst_pmin(gpst), 0, &voltage_entry);
-            if (rc) {
-                SSX_PANIC(GPSM_BUG); /* This can't happen */
-            }
-
-            o_info->currentVdd = voltage_entry.fields.evid_vdd;
-            o_info->currentVcs = voltage_entry.fields.evid_vcs;
-        }
-
-        search_rc = gpst_vdd2pstate(gpst, o_info->currentVdd,
-                                    o_voltage_pstate, &voltage_entry);
-        if (search_rc &&
-            (search_rc != -GPST_PSTATE_CLIPPED_LOW_GPST_V2P) &&
-            (search_rc != -GPST_PSTATE_CLIPPED_HIGH_GPST_V2P)) {
-            rc = search_rc;
-            break;
-        }
-
-        o_info->targetVdd = voltage_entry.fields.evid_vdd;
-        o_info->targetVcs = voltage_entry.fields.evid_vcs;
-
-
-        // If the Pstate was 'clipped low', it indicates that the current
-        // voltage is lower than the lowest new Pstate.  Therefore we need to
-        // manually step voltage up before locking in the Pmin frequency.  If
-        // the Pstate was 'clipped high' it means that the current voltage is
-        // higher than the highest Pstate, and we need to lock frequency at
-        // the Pmax frequency prior to stepping voltage down. The unclipped
-        // case is lumped with the 'clipped low' case as this case might
-        // entail a slight rise of voltage. V/F stepping must be split across
-        // the calls of gpsm_enable_pstates_master[slave].
-
-        if ((search_rc == 0)||(search_rc = -GPST_PSTATE_CLIPPED_LOW_GPST_V2P)) {
-
-            rc = _manual_step_voltage(o_info->currentVdd, o_info->currentVcs,
-                                      o_info->targetVdd, o_info->targetVcs);
-            if (rc) _BREAK;
-
-            o_info->move_voltage = 0;
-
-        } else {
-
-            o_info->move_voltage = 1;
-
-        }
-    } while (0);
-
-    /// \todo The o_frequency_pstate parameter is no longer needed.  It was
-    /// originally needed when the Pstate table had an undervolting bias.
-    *o_frequency_pstate = *o_voltage_pstate;
-
-    return rc;
-}
-
-
-/// Enable Pstates in Firmware Pstate Mode, final Master/Slave phase
-///
-/// \param[in] i_info This structure is populated by
-/// gpsm_enable_pstates_master(), and only required in an SCM or DCM master.
-/// When this API is called on a DCM slave the parameter may be passed as NULL
-/// (0).
-///
-/// \param[in] i_voltage_pstate This parameter is computed by
-/// gpsm_enable_pstates_master(), and is required in every case.
-///
-/// \param[in] i_frequency_pstate This parameter is computed by
-/// gpsm_enable_pstates_master(), and is required in every case.
-///
-/// \note This procedure is called in all cases as the final step in enabling
-/// Pstate mode: SCM, DCM master, DCM slave.
-///
-/// \retval 0 Success
-///
-/// \returns All other return codes indicate an error.
-
-int
-gpsm_enable_pstates_slave(const GpsmEnablePstatesMasterInfo* i_info,
-                          const Pstate i_voltage_pstate,
-                          const Pstate i_frequency_pstate)
-{
-    int rc;
-    GlobalPstateTable* gpst;
-    pmc_mode_reg_t pmr;
-    gpst_entry_t voltage_entry;
-
-    TRACE_GPSM(TRACE_GPSM_ENABLE_PSTATES_SLAVE);
-
-    do {
-
-        // Enter Firmware Pstate Mode.  The gpsm_fw_mode() procedure
-        // guarantees that the GPSM is quiesced at this point for the slave;
-        // the master must already be quiesced.  Recover a pointer to the
-        // Pstate table from PMC.
-
-        if (gpsm_dcm_slave_p()) {
-
-            rc = gpsm_fw_mode();
-            if (rc) _BREAK;
-
-        } else {
-
-            if (!i_info) {
-                rc = -GPSM_INVALID_ARGUMENT_EPSS;
-                _BREAK;
-
-            } else if (!gpsm_fw_mode_p() || !gpsm_quiesced_p()) {
-
-                rc = -GPSM_ILLEGAL_MODE_EPSS;
-                _BREAK;
-
-            }
-        }
-
-        gpst = gpsm_gpst();
-        gpst_entry(gpst, i_voltage_pstate, 0, &voltage_entry);
-
-        // Execute the core prologue.  An SCM or DCM master may need to move
-        // voltage after the frequency move.  Since this is guaranteed to be a
-        // safe downward move (otherwise we would have moved voltage already),
-        // it is safe for the DCM slave to go ahead and finish its Pstate
-        // setup before the master has moved the voltage.
-
-        rc = _enable_pstates_core_prologue(gpst, i_frequency_pstate,
-                                                 voltage_entry);
-        if (rc) _BREAK;
-
-        if (!gpsm_dcm_slave_p()) {
-
-            rc = _manual_step_voltage(i_info->currentVdd, i_info->currentVcs,
-                                      i_info->targetVdd, i_info->targetVcs);
-            if (rc) _BREAK;
-        }
-
-
-        // The Voltage and Frequency state is now consistent in the cores and
-        // in PMC. Make sure that PMC modes are set correctly for Hardware
-        // Pstate Mode.
-
-        pmr.value = in32(PMC_MODE_REG);
-        pmr.fields.enable_pstate_voltage_changes = 1;
-        pmr.fields.enable_global_actual_pstate_forwarding = 1;
-        //pmr.fields.enable_pstate_stepping = 1;
-        out32(PMC_MODE_REG, pmr.value);
-
-
-        // Since we're in Firmware Pstate mode and all cores are
-        // frequency-locked, we can set the Global Actual without stepping -
-        // under the assumption that the caller has disabled iVRM prior to the
-        // call.  The master has already computed the volatge_pstate.  We
-        // allow the GPSM to quiesce before unlocking the core frequencies.
-
-        _gpsm_broadcast_global_actual(i_frequency_pstate, voltage_entry);
-
-        rc = gpsm_quiesce();
-        if (rc) _BREAK;
-
-        rc = _enable_pstates_core_epilogue();
-        if (rc) _BREAK;
-
-    } while (0);
-
-    return rc;
-}
-
diff --git a/src/lib/heartbeat.c b/src/lib/heartbeat.c
deleted file mode 100755
index 51be390..0000000
--- a/src/lib/heartbeat.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// $Id: heartbeat.c,v 1.5 2014/07/16 18:07:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/heartbeat.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file heartbeat.c
-/// \brief PgP PMC/PCBS heartbeat configuration procedures
-
-#include "ssx.h"
-#include "heartbeat.h"
-
-/// Configure/Enable/Disable the pmc heartbeat register.
-///
-/// \param enable 1 = enable, 0 = disable, all other values will cause error.
-///
-/// \param req_time_us heartbeat interval time request (in microseconds).
-/// If the pmc does not detect a heartbeat within this time the pmc will
-/// set the corresponding fir bit and enter safe mode.  This interval
-/// is the requested value.  The return value will be the actual setting.
-/// The procedure well attempt to get as close to the requested time as possible
-/// without choosing a setting lower then requested.
-/// Legal values: 1-4194240 (us).  Ignored if force = 1 or enable = 0
-///
-/// \param force 1 = force safe mode (debug), 0 = do not force, all other values
-/// will cause an error.  enable = 0 and force = 1 will return an error
-///
-/// \param[out] o_time_us Actual configured time rounded down to the nearest us.
-/// This will be as close as the procedure could get to the requested time given
-/// the frequency and pulse time settings.  Returns 0 if hearbeat was disabled or
-/// if safe mode was forced.
-///
-/// \retval 0 Success
-///
-/// \retval -HB_INVALID_ARGUMENT_PMC One of the arguments was invalid in 
-/// some way
-
-int
-pmc_hb_config(unsigned int enable,
-              unsigned int req_time_us,
-              unsigned int force,
-              unsigned int *o_time_us
-              )
-
-{
-    pmc_parameter_reg0_t ppr0;
-    pmc_occ_heartbeat_reg_t pohr;
-    tpc_hpr2_t l_hpr2;
-    uint64_t divider, pulses, total_pulses, hp_freq;
-    int rc = 0;
-
-    // @dyd SW238882 fix
-    // remove req_time_us overflow check since the upper boundary of 
-    // the req_time_us doesnt depand on certain static value but based on 
-    // the value set in hang_pulse_2_reg at runtime.
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((enable > 1) || 
-                     (force > 1) ||
-                     ((req_time_us < 1) && enable && (! force)) ||
-                     ((force == 1 && enable == 0)),
-                     HB_INVALID_ARGUMENT_PMC);
-    }
-
-    do {
-
-        // in case firmware does not call ocb_timer_setup 
-        // before calling this procedure to setup g_ocb_timer_divider
-        rc = getscom(TPC_HPR2, &l_hpr2.value);
-        if(rc) break;
-        g_ocb_timer_divider = 1 << l_hpr2.fields.hang_pulse_reg;
-
-        // calculation based on pmc_occ_heartbeat_reg defination
-        hp_freq = (__ssx_timebase_frequency_mhz/g_ocb_timer_divider);
-        if(hp_freq < 1)
-           hp_freq = 1;
-        total_pulses = (req_time_us * hp_freq);
-        
-        // this may be an overkill for safety but no one should notice
-        if ((req_time_us*__ssx_timebase_frequency_mhz) % g_ocb_timer_divider) {
-            total_pulses++;
-        }     
-
-        divider = 0;
-        // determine values for predivider and number of pulses.
-        if (force || (! enable)) {  // predivider a don't care in this case
-            pulses = 0; 
-            *o_time_us = 0;
-        } else {
-            // can count up to 2^16 pulses with no pre-divide, first determine
-            // minimum pre-divider needed
-            do {
-                divider++;
-            } while ((((divider << 16) - 1) / total_pulses) < 1);
-
-            // @dyd SW238882 fix
-            // underflow case
-            // since pmc heartbeat counter counts with nest_nclk/4 
-            // instead of hang pulse when hangpulse_predivider==0,
-            // this procedure doesnt allow predivider to be set to
-            // zero as it is a special case which doesnt work with
-            // occ heartbeat time value calculated by this procedure.
-            // Given hangpulse_predivider = divider - 1, 
-            // set divider to 2 if it is 1, zero not possible.  
-            if (divider < 2) { 
-                divider = 2;
-                //rc = HB_UNDERFLOW_DIVIDER_PMC;
-                //break;
-            }
-            // overflow case
-            // since hangpulse_predivider field is only 6 bit long, 
-            // check the overflow first, set to maximum if larger.
-            if (divider > 64) {
-                divider = 64;            
-                //rc = HB_OVERFLOW_DIVIDER_PMC;
-                //break;
-            }
-            
-            // divider is determined, now setup number of pulses
-            pulses = total_pulses / divider;
-            if (total_pulses % divider) {
-                pulses++;
-            }
-
-            // @dyd SW238882 fix
-            // there is no underflow case for pulses, because pulses=0 as 
-            // intended immediate timeout is allowed, plus no mathematical 
-            // substraction from pulses is done; however there is an overflow 
-            // case: the value of pulses doesnt fit into 16 bits HW field.
-            // Here we set pulses to the maximum value that HW allows, 
-            // and use the o_time_us to feedback the caller this is done. 
-            if (pulses > 0xFFFF) {
-                pulses = 0xFFFF;
-                //rc = HB_OVERFLOW_PULSES_PMC;
-                // break;
-            }
-
-            // calculating real timeout duration 
-            // that this procedure is going to set
-            *o_time_us = (divider*pulses)/hp_freq;
-
-            // @dyd SW238882 fix
-            // in force == 0 && enable == 1 case
-            // disable heartbeat first before reset hang pulse predivider 
-            // and new heartbeat time value to prevent immediate timeout.
-            // if force == 1 then it is intended to be immediate timeout anyway
-            // if enable == 0 then it is going to set this bit to zero anyway
-            pohr.value = 0;
-            pohr.fields.pmc_occ_heartbeat_en = 0;
-            if (cfam_id() == CFAM_CHIP_ID_MURANO_10) {
-                out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-            }
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-        }
-
-        // Note through experiments, the divider=predivider+1 isnt always 
-        // in effect in hardware due to missing last pulse in tight timing, 
-        // some setup will end up with just divider=predivider; therefore,
-        // in order to not result unexpected heartbeat timeout, always
-        // set divider to predivider to be safe. 
-        if (enable && (! force)) {
-            ppr0.value = in32(PMC_PARAMETER_REG0);
-            ppr0.fields.hangpulse_predivider = divider;
-            out32(PMC_PARAMETER_REG0, ppr0.value);
-        }
-   
-        pohr.value = 0;
-        pohr.fields.pmc_occ_heartbeat_en = enable;
-        pohr.fields.pmc_occ_heartbeat_time = pulses;
-        // Due to Issue HW219480, the heartbeat register needs to be written
-        // Twice in order for the heartbeat count value to take correctly.
-        // Technically it would not be harmful to just double-write in
-        // every case, but this is currently written to only double-write
-        // if a Murano dd1.0 part is detected
-        if (cfam_id() == CFAM_CHIP_ID_MURANO_10) {
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-        }
-        out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-
-    }while(0);
-    return rc;
-
-}
-    
-   
-
-/// Configure/Enable/Disable the pcbs heartbeat registers.
-///
-/// \param enable 1 = enable, 0 = disable, all other values will cause error.
-///
-/// \param cores Use this mask to select which cores to update.  This routine
-/// will cross reference the current pmc deconfig vector and only update
-/// those cores that are both selected here and configured.
-///
-/// \param hb_reg 32-bit unsigned address of register to setup as the
-/// PCBS heartbeat register.  This must be a PCBS address.
-/// Ignored unless enable = 1 
-///
-/// \param req_time_us heartbeat interval time request (in microseconds).
-/// If the pcbs does not detect a heartbeat within this time the pcbs will
-/// set the corresponding fir bit and enter safe mode.  This interval
-/// is the requested value.  The return value will be the actual setting and
-/// the procedure will attempt go get as close to possible to this without
-/// choosing a setting lower then requested.
-/// Legal values: 1 - 16320 (ignored unless enable = 1)
-///
-/// \param force 1 = force safe mode (debug), 0 = do not force, all other values
-/// will cause an error.  In PCBS, the force safe mode is not related to
-/// the heartbeat so forcing safe mode while also enabling the heartbeat
-/// is allowed.
-///
-/// \param[out] o_time_us Actual configured time in us.  This represents the
-/// actual setting rounded down to the nearest us.  0 if heartbeat was disabled.
-///
-/// \retval 0 Success
-
-/// \retval -HB_INVALID_ARGUMENT_PCBS One of the arguments was invalid in 
-/// some way
-///
-/// \retval others This API may also return non-0 codes from
-/// getscom()/putscom()
-
-
-int
-pcbs_hb_config(unsigned int enable,
-               ChipConfigCores cores,
-               uint32_t hb_reg,
-               unsigned int req_time_us,
-               unsigned int force,
-               unsigned int *o_time_us)
-{
-    pcbs_occ_heartbeat_reg_t pohr;
-    pcbs_pmgp1_reg_t pp1r;
-    pmc_core_deconfiguration_reg_t pcdr;
-    uint32_t reg_offset;
-    uint32_t pp1r_addr;
-    uint64_t pp1r_data;
-    ChipConfigCores core_list;
-    ChipConfigCores deconfig;
-    int core;
-    int rc = 0;
-    unsigned int pulses;
-      
-    reg_offset = hb_reg - PCBS_PIB_BASE;
-    
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((enable > 1) ||
-                     ((reg_offset > 0xFF) && enable) ||
-                     ((req_time_us < 64) && enable) ||
-                     ((req_time_us > 16320) && enable) ||
-                     (force > 1),
-                     HB_INVALID_ARGUMENT_PCBS);
-    }
-
-
-    do {
-
-        // calculation based on pcbs_occ_heartbeat_reg defination
-        pulses = req_time_us/64;
-        if (req_time_us % 64) {
-            pulses++;
-        }
-   
-        // @dyd SW238882 fix
-        // overflow handling: HW only allows 8 bits in the field.
-        // set pulses to maximum allowed value in HW if it overflows,
-        // and o_time_us will feedback to caller this is done.
-        if (pulses > 0xFF) {
-            pulses = 0xFF;
-            //rc = HB_PULSES_OVERFLOW_PCBS;
-            //break;
-        }
-        // underflow case, pulses cannot be zero due to undefined HW behavior
-        if (pulses < 1) {
-            pulses = 1;
-            //rc = HB_PULSES_UNDERFLOW_PCBS;
-            //break;
-        }
-
-        pp1r.value = 0;
-        pp1r.fields.force_safe_mode = 1;
-        if (force) {
-            pp1r_addr = PCBS_PMGP1_REG_OR;
-            pp1r_data = pp1r.value;
-        } else {
-            pp1r_addr = PCBS_PMGP1_REG_AND;
-            pp1r_data = ~(pp1r.value);
-        }
-    
-        pcdr.value = in32(PMC_CORE_DECONFIGURATION_REG);
-        deconfig = pcdr.fields.core_chiplet_deconf_vector;
-    
-        pohr.value = 0;
-        pohr.fields.occ_heartbeat_enable = enable;
-        pohr.fields.occ_heartbeat_time = pulses;
-        pohr.fields.occ_heartbeat_reg_addr_offset = reg_offset;
-    
-        if (enable) {
-            *o_time_us = pulses * 64;
-        } else {
-            *o_time_us = 0;
-        }
-    
-        do {
-            core_list = cores & (~deconfig);
-            for (core = 0; core < PGP_NCORES; core++, core_list <<= 1) {
-                if (core_list & 0x8000) {
-                    // read modify write to preserve psafe
-                    rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_OCC_HEARTBEAT_REG,
-                                                          core), &pohr.value);
-                    if (rc) break;
-                    pohr.fields.occ_heartbeat_enable = enable;
-                    pohr.fields.occ_heartbeat_time = pulses;
-                    pohr.fields.occ_heartbeat_reg_addr_offset = reg_offset;
-                    rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_OCC_HEARTBEAT_REG,
-                                                          core), pohr.value);
-                    if (rc) break;
-                    rc = putscom(CORE_CHIPLET_ADDRESS(pp1r_addr, core),
-                                     pp1r_data);
-                    if (rc) break;
-                }
-            }
-        } while (0); 
-    
-   }while(0); 
-   return rc;
-}
diff --git a/src/lib/heartbeat.h b/src/lib/heartbeat.h
deleted file mode 100755
index 6c8616b..0000000
--- a/src/lib/heartbeat.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __HEARTBEAT_H__
-#define __HEARTBEAT_H__
-
-// $Id: heartbeat.h,v 1.3 2014/02/12 05:48:48 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/heartbeat.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file heartbeat.h
-/// \brief PgP PMC/PCBS heartbeat configuration procedures
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-#define HB_INVALID_ARGUMENT_PMC  0x00482801
-#define HB_INVALID_ARGUMENT_PCBS 0x00482802
-#define HB_UNDERFLOW_DIVIDER_PMC 0x00482803
-#define HB_OVERFLOW_DIVIDER_PMC  0x00482804
-#define HB_OVERFLOW_PULSES_PMC   0x00482805
-#define HB_OVERFLOW_PULSES_PCBS  0x00482806
-#define HB_UNDERFLOW_PULSES_PCBS 0x00482807
-
-int
-pmc_hb_config(unsigned int enable,
-              unsigned int req_time_us,
-              unsigned int force,
-              unsigned int *o_time_us);
-
-int
-pcbs_hb_config(unsigned int enable,
-               ChipConfigCores cores,
-               uint32_t hb_reg,
-               unsigned int req_time_us,
-               unsigned int force,
-               unsigned int *o_time_us);
-
-
-
-#endif  /* __ASEMBLER__ */
-
-
-#endif  /* __HEARTBEAT_H__ */
diff --git a/src/lib/libfiles.mk b/src/lib/libfiles.mk
deleted file mode 100755
index 55773a4..0000000
--- a/src/lib/libfiles.mk
+++ /dev/null
@@ -1,57 +0,0 @@
-# $Id: libfiles.mk,v 1.5 2014/06/26 12:51:16 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/libfiles.mk,v $
-#  @file libofiles.mk
-#
-#  @brief mk for libssx.a object files
-#
-#  @page ChangeLogs Change Logs
-#  @section ofiles.mk
-#  @verbatim
-#
-#
-# Change Log ******************************************************************
-# Flag     Defect/Feature  User        Date         Description
-# ------   --------------  ----------  ------------ -----------
-# @pb00E                   pbavari     03/11/2012   Makefile ODE support
-# @at007                   alvinwan    05/25/2012   Use complex method for linking pore and PPC objects
-#
-# @endverbatim
-#
-##########################################################################
-# INCLUDES
-##########################################################################
-
-C-SOURCES = \
-	assert.c \
-	ctype.c \
-	ctype_table.c \
-	fgetc.c  \
-	gpe_pba.c \
-	gpsm.c \
-	gpsm_dcm.c \
-	gpsm_init.c \
-	heartbeat.c \
-	memcpy.c \
-	memset.c \
-	pmc_dcm.c \
-	polling.c \
-	printf.c \
-	pstates.c \
-	puts.c \
-	simics_stdio.c \
-	special_wakeup.c \
-	sprintf.c \
-	ssx_dump.c \
-	ssx_io.c \
-	stdlib.c \
-	strcasecmp.c \
-	strdup.c \
-	string.c \
-	string_stream.c \
-	strtox.c \
-	time.c \
-	vrm.c \
-
-S-SOURCES =  gpsm_dcm_fast_handler.S
-
-LIBSSX_OBJECTS = $(C-SOURCES:.c=.o) $(S-SOURCES:.S=.o)
diff --git a/src/lib/libgpefiles.mk b/src/lib/libgpefiles.mk
deleted file mode 100755
index 3f4efe1..0000000
--- a/src/lib/libgpefiles.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-# $Id: libgpefiles.mk,v 1.3 2014/06/26 12:48:31 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/libgpefiles.mk,v $
-#  @file libgpefiles.mk
-#
-#  @brief mk for libssx.a gpe object files
-#
-#  @page ChangeLogs Change Logs
-#  @section libgpefiles.mk
-#  @verbatim
-#
-#
-# Change Log ******************************************************************
-# Flag     Defect/Feature  User        Date         Description
-# ------   --------------  ----------  ------------ -----------
-# @at007                   alvinwan    05/25/2012   Use complex method for linking pore and PPC objects
-#
-# @endverbatim
-#
-##########################################################################
-# INCLUDES
-##########################################################################
-pS-SOURCES = \
-	gpe_control.pS \
-	gpe_data.pS \
-	gpe_scom.pS \
-	gpe_pba_pgas.pS
-
-LIB_PSOBJECTS = ${pS-SOURCES:.pS=.o}
-
-
diff --git a/src/lib/libssx.h b/src/lib/libssx.h
deleted file mode 100755
index 2bdffd4..0000000
--- a/src/lib/libssx.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __LIBSSX_H__
-#define __LIBSSX_H__
-
-// $Id: libssx.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/libssx.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file libssx.h
-/// \brief Header definitions with no other obvious home
-
-// Kernel panics
-
-#define ASSERTION_FAILURE 0x00542701
-#define ERROR_EXIT        0x00542702
-
-#endif // __LIBSSX_H__
diff --git a/src/lib/occlib/Makefile b/src/lib/occlib/Makefile
new file mode 100644
index 0000000..9f86413
--- /dev/null
+++ b/src/lib/occlib/Makefile
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/occlib/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  This Makefile currently builds a single archive, 'libocc.a', from
+#  various library source files. 
+#
+#  part of the complete application build.
+#
+
+#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/occ
+export SUB_OBJDIR = /occlib
+
+include img_defs.mk
+include liboccfiles.mk
+
+OBJS := $(addprefix $(OBJDIR)/, $(LIBOCC_OBJECTS))
+
+libocc.a: local
+	$(AR) crs $(OBJDIR)/libocc.a $(OBJDIR)/*.o
+
+.PHONY: clean
+
+local: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/lib/occlib/README.txt b/src/lib/occlib/README.txt
new file mode 100644
index 0000000..2f3667f
--- /dev/null
+++ b/src/lib/occlib/README.txt
@@ -0,0 +1 @@
+This directory contains all code that is common for all processors in the OCC complex (405 + 4 GPE's)
diff --git a/src/lib/occlib/ipc_api.h b/src/lib/occlib/ipc_api.h
new file mode 100644
index 0000000..e4756f5
--- /dev/null
+++ b/src/lib/occlib/ipc_api.h
@@ -0,0 +1,519 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_api.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __IPC_API_H__
+#define __IPC_API_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_api.h
+/// \brief Common header for Interprocessor Communications API
+///
+#include "ipc_structs.h"
+
+#ifndef __ASSEMBLER__
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC command message
+///
+/// \param msg A pointer to the command message
+///
+/// \param func_id A user-defined function ID that is known to both the sender
+/// and receiver of a command message.  (Defined in \a ipc_func_ids.h)
+///
+/// \param resp_callback A user-defined function that should be called when
+/// the message is returned as a response to the command.  This must be set
+/// to 0 if no callback function should be called.
+///
+/// \param callback_arg A pointer to user-defined data that will be passed in
+/// to the callback function when it is called. This should be set to 0 if
+/// no data needs to be passed.
+///
+/// This function (or \a ipc_init_msgq_msg) must be called on a message at
+/// least once before it is sent via the \a ipc_send_msg interface.
+///
+/// There are two types of function ID's. Function ID's that only work on a
+/// single processor are called \e single-target ID's.  These function
+/// ID's have the target ID embedded as part of the ID.  FUnction ID's
+/// that are supported on multiple processors are called \e multi-target ID's.
+/// Command messages associated with multi-target function ID's must go through
+/// the extra step of setting the target ID by calling the \a ipc_set_cmd_target
+/// interface on the command message.
+///
+/// If a callback function is provided, that callback function should cause
+/// (directly or indirectly) the \ipc_free_msg interface to be called once it
+/// is known that it is safe for the message to be reused (sent as a command
+/// again).
+///
+void ipc_init_msg(ipc_msg_t* msg, 
+                 uint32_t func_id,
+                 ipc_msg_handler_t resp_callback,
+                 void* callback_arg);
+
+//Use these to statically initialize an IPC message
+#define IPC_MSG_INIT(_func_id, _resp_callback, _callback_arg) \
+{\
+    {.node = KERN_DEQUE_ELEMENT_INIT()}, \
+    .func_id.word32 = _func_id, \
+    .ipc_rc = IPC_RC_SUCCESS, \
+    .resp_callback = _resp_callback, \
+    .callback_arg = _callback_arg \
+}
+
+#define IPC_MSG_CREATE(msg_name, _func_id, _resp_callback, _callback_arg) \
+ipc_msg_t msg_name = IPC_MSG_INIT(_func_id, _resp_callback, _callback_arg)
+
+///////////////////////////////////////////////////////////////////////////////
+/// Free up a message to be reused.
+///
+/// \param msg a pointer to a message.
+/// 
+/// This interface should be called on a message when it is known that it is
+/// safe to reuse the message.  Normally, this would be one of the last things
+/// performed in the response callback function for a command, but it may also
+/// be called when it is known that a peer has stopped functioning.
+///
+static inline void ipc_free_msg(ipc_msg_t* msg)
+{
+    msg->func_id.active_flag = 0;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Set the target ID for a multi-target command message.
+///
+/// \param cmd A pointer to an initialized command message.
+///
+/// \param target_id The target ID of the processor the command is intended
+/// for.
+///
+/// The following return codes are possible:
+///
+/// \retval IPC_RC_SUCCESS The command's target ID was updated.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The function ID associated with this
+/// command is not a valid mult-target function ID.
+///
+int ipc_set_cmd_target(ipc_msg_t* cmd, uint32_t target_id);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Send a message as a command
+///
+/// \param cmd A pointer to an initialized command message
+///
+/// It is expected that at some point prior to calling this function the
+/// message was initialized with a call to \a ipc_init_msg or 
+/// \a ipc_init_msgq_msg.
+///
+/// Once a message has been sent it is not safe to send again until it has been
+/// sent back to the sender as a response.
+///
+/// The following return codes are possible:
+///
+/// \retval IPC_RC_SUCCESS The message was successfully placed on the target's
+/// receive buffer.
+///
+/// \retval IPC_RC_SELF_BLOCKED The call was made prior to calling 
+/// \a ipc_enable.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The command was initialized with an invalid
+/// function ID.
+///
+/// \retval IPC_RC_MSG_ACTIVE The message is currently in use.
+///
+/// \retval IPC_RC_INVALID_TARGET_ID The message was initialized with an
+/// invalid target ID.  This can happen if a multi-target command has not had
+/// its target set via the \a ipc_set_cmd_target function at least one time.
+///
+/// \retval IPC_RC_BUFFER_FULL The command could not be sent because the target's
+/// receive buffer is full.
+///
+/// \retval IPC_RC_TARGET_BLOCKED The command could not be sent because the
+/// target is blocking any new messages.
+/// 
+int ipc_send_cmd(ipc_msg_t* cmd);
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// Send a command message back to the sender as a response message with status.
+///
+/// \param rsp A pointer to a message that was recieved as a command message.
+///
+/// \param ipc_rc This should be either \a IPC_RC_SUCCESS if the command was
+/// successful or \a IPC_RC_CMD_FAILED if the command failed.  If
+/// command-specific return codes are needed, they should be returned as
+/// command-specific fields instead of returning them here so that there
+/// is no risk of overlapping return codes.
+///
+/// It is expected that at some point prior to calling this function the
+/// message was initialized with a call to \a ipc_init_msg or 
+/// \a ipc_init_msgq_msg.
+///
+/// Once a message has been sent it is not safe to send again until it has been
+/// sent back to the sender as a response.
+///
+/// The following return codes are possible:
+///
+/// \retval IPC_RC_SUCCESS The message was successfully placed on the target's
+/// receive buffer.
+///
+/// \retval IPC_RC_MSG_NOT_ACTIVE The message is not from an active command.
+///
+/// \retval IPC_RC_INVALID_TARGET_ID The target id for the sender is invalid.
+/// This likely means that the message has been corrupted.
+///
+/// \retval IPC_RC_BUFFER_FULL The response could not be sent because the target's
+/// recieve buffer is full.
+///
+/// \retval IPC_RC_TARGET_BLOCKED The response could not be sent because the
+/// target is blocking any new messages.
+///
+int ipc_send_rsp(ipc_msg_t* rsp, uint32_t return_code);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieves the IPC return code embedded in the response message.
+///
+/// \param rsp A pointer to a response message.
+///
+/// The embedded IPC return code is how the remote processor communicates
+/// IPC internal failures to the local processor.  It can also be used by
+/// non-IPC code on the remote processor to signal success or failure when it
+/// sends the response message via the \a ipc_send_rsp interface.
+///
+/// The IPC return code should always be checked to verify that a command
+/// message was processed successfully.
+///
+/// The following return codes are possible:
+///
+/// \retval IPC_RC_SUCCESS The message was successfully processed.
+///
+/// \retval IPC_RC_CMD_FAILED The command was processed on the remote end but
+/// did not complete successfully.
+///
+/// \retval IPC_RC_CMD_NOT_SUPPORTED The function ID for the command is valid
+/// but the remote end does not have support for that function ID.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The function ID for the command is invalid.
+///
+static inline int ipc_get_rc(ipc_msg_t* rsp)
+{
+    return rsp->ipc_rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieve the IPC function ID for a message
+///
+/// \param msg A pointer to an IPC message
+///
+/// This interface should be used to extract the IPC function ID of a message.
+///
+/// The IPC function ID is returned.
+///
+static inline int ipc_get_funcid(ipc_msg_t* msg)
+{
+    int func_id = msg->func_id.word32;
+
+    //Multi-target function ID's always have the target ID set to
+    //so that if the caller doesn't set it to a proper target id it will
+    //flag an error.
+    if(func_id & IPC_FLAG_MT)
+    {
+        func_id |= IPC_TARGET_MASK;
+    }
+
+    //Clear the active and response flags in case they are set along
+    //with the sender ID.
+    func_id &= ~(IPC_FLAG_ACTIVE | IPC_FLAG_RESPONSE | IPC_SENDER_MASK);
+
+    return func_id;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Determine if a message is a response or a command
+///
+/// \param msg A pointer to an IPC message
+///
+/// This function should be used to determine if a message is a response or a
+/// command.  The function will return a non-zero value if the message is a
+/// response and 0 otherwise.
+///
+static inline int ipc_is_a_response(ipc_msg_t* msg)
+{
+    return msg->func_id.response_flag;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Determine if a message is free to be re-used
+///
+/// \param msg A pointer to an IPC message
+///
+/// This function should be used to determine if a message is free to re-use.
+/// The function will return a non-zero value if the message is free and
+/// 0 otherwise.
+///
+static inline int ipc_is_free(ipc_msg_t* msg)
+{
+    return !msg->func_id.active_flag;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieve the sender ID of a message.
+///
+/// \param msg A pointer to an IPC message
+///
+/// This function should be used to retrieve the sender ID of a message.  It
+/// returns the sender ID.
+///
+static inline int ipc_sender_id(ipc_msg_t* msg)
+{
+    return msg->func_id.sender_id;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieve the target ID of a message.
+///
+/// \param msg A pointer to an IPC message
+///
+/// This function should be used to retrieve the target ID of a message.  It
+/// returns the target ID.
+///
+static inline int ipc_target_id(ipc_msg_t* msg)
+{
+    return msg->func_id.target_id;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initializes IPC control structures.
+///
+/// Clears the IPC buffers for this processor and places them in a state
+/// where new messages are blocked.  Also initializes the IPC handler table
+/// for this processor if STATIC_IPC_TABLES has not been defined.
+///
+/// This function always returns \a IPC_RC_SUCCESS
+///
+int ipc_init(void);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Enables IPC communications.
+///
+/// Unmasks the IPC interrupt for this processor and places the circular
+/// buffers in a state where they can recieve messages.
+///
+/// This function must be called before using the \a ipc_send_cmd function or
+/// it will return \a IPC_RC_SELF_BLOCKED.
+///
+/// The function always returns \a IPC_RC_SUCCESS.
+///
+int ipc_enable(void);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Disable recieving new IPC commands for a processor.
+///
+/// \param target_id The target ID of the processor to disable receiving new
+/// IPC commands on.
+///
+/// This interface should be used by a processor that knows it is about to go
+/// down or by a processor that knows that one of its peers has halted.
+///
+/// Calling this function on a processor will cause other processors to get
+/// a return code of \a IPC_RC_TARGET_BLOCKED with subsequent calls to
+/// \a ipc_send_cmd.  Calling this function on one's self (using a target ID of
+/// OCCHW_INST_ID_SELF) will cause subsequent calls to \a ipc_send_cmd to
+/// return \a IPC_RC_SELF_BLOCKED.
+///
+/// Possible return codes for this function are:
+///
+/// \retval IPC_RC_SUCCESS The target processor was successfully disabled.
+///
+/// \retval IPC_RC_INVALID_TARGET_ID The target ID is invalid.
+///
+int ipc_disable(uint32_t target_id);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Associates an IPC function ID with a handler function
+///
+/// \param func_id A user-defined function ID that is known to both the sender
+/// and receiver of a command message.  (Defined in \a ipc_func_ids.h)
+///
+/// \param handler A pointer to the function that handles command messages that
+/// have been initialized with \a func_id.
+///
+/// \param callback_arg A pointer to data that is passed as an argument to the
+/// handler function when it is called.
+///
+/// This function should be used to link an IPC function ID with a function.
+/// Once this has been done, if the local processor recieves a command message
+/// with an IPC function ID that matches \a func_id then it will call the
+/// handler function that was specified by \a handler.
+///
+/// NOTE: All handler functions will be called from an interrupt context.
+///
+/// Possible return codes are:
+///
+/// \retval IPC_RC_SUCCESS The operation completed successfully.
+///
+/// \retval IPC_RC_INVALID_TARGET_ID The function ID is a single-target
+/// function ID that does not target this processor.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The function ID is not a valid IPC function
+/// ID.
+///
+/// \retval IPC_RC_INVALID_ARG The handler parameter must be a non-zero value.
+///
+int ipc_set_handler(uint32_t func_id,
+                    ipc_msg_handler_t handler,
+                    void* callback_arg);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC message queue.
+///
+/// \param msgq A pointer to a message queue.
+///
+/// All message queues must be initialized one time prior to use with other
+/// interfaces.
+///
+void ipc_init_msgq(ipc_msgq_t* msgq);
+
+//Use this to statically initialize an IPC message queue
+#define IPC_MSGQ_CREATE(msgq) \
+ipc_msgq_t msgq = \
+{\
+    .msg_head = KERN_DEQUE_SENTINEL_INIT(&msgq.msg_head),\
+    .msg_sem = KERN_SEMAPHORE_INITIALIZATION(0, 0)\
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC message and associate it with an IPC message queue
+///
+/// \param msg A pointer to an IPC message.
+///
+/// \param func_id A user-defined function ID that is known to both the sender
+/// and receiver of the command message.  (Defined in \a ipc_func_ids.h)
+///
+/// \param msgq A pointer to an initialized IPC message queue.
+///
+/// This interface should be used in place of \a ipc_init_msg when the caller
+/// wishes to have the command response placed on the specified IPC message
+/// queue.  This allows a thread to block (via the \a ipc_msq_recv interface)
+/// on the message queue until a response to a command has arrived.
+/// 
+/// \note An IPC message queue can be associated with more than one IPC
+/// message.
+///
+/// See \a ipc_init_msg for more information.
+///
+void ipc_init_msgq_msg(ipc_msg_t* msg, uint32_t func_id, ipc_msgq_t* msgq);
+
+//Use this to statically create an initialized IPC message queue message
+#define IPC_MSGQ_MSG_CREATE(msg_name, func_id, msgq) \
+    IPC_MSG_CREATE(msg_name, func_id, ipc_msgq_handler, msgq)
+
+///////////////////////////////////////////////////////////////////////////////
+/// Wait (with timeout) for an IPC message on an IPC message queue.
+///
+/// \param msg A pointer to an IPC message pointer.
+///
+/// \param msgq A pointer to an initialized IPC message queue.
+///
+/// \param timeout The time to wait for the next IPC message to arrive.
+///
+/// This interface can be used in a thread context to block while waiting for
+/// the next message (command or response) to arrive on an IPC message queue.
+///
+/// For an IPC command message to be placed on an IPC message queue, the
+/// function ID for the command must first be associated with the message queue
+/// by making a call to \a ipc_register_msgq.
+///
+/// For an IPC response message to be placed on an IPC message queue, the
+/// message must be initialized via the \a ipc_init_msgq_msg interface.
+///
+/// If \a ipc_msgq_recv returns a value of \a IPC_RC_SUCCESS then \a msg is
+/// guaranteed to point to a new message.  Otherwise, an IPC message was not
+/// retrieved from the message queue and \a msg will be set to 0.
+///
+/// Possible return codes for this function are:
+///
+/// \retval IPC_RC_SUCCESS A new IPC message was received and \a msg has been
+/// set to point to the new message.
+///
+/// \retval IPC_RC_TIMEOUT No new messages were recieved within the timeout
+/// period and \msg was set to 0.
+///
+/// \retval IPC_RC_NO_MSG This should never happen, but if it does it indicates
+/// an internal failure occurred.
+///
+int ipc_msgq_recv(ipc_msg_t** msg, ipc_msgq_t* msgq, KERN_INTERVAL timeout);
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Associate an IPC message queue with an IPC function ID
+///
+/// \param func_id A user-defined function ID that is known to both the sender
+/// and receiver of a command message.  (Defined in \a ipc_func_ids.h)
+///
+/// \param msgq A pointer to an initialized IPC message queue.
+///
+/// This interface associates an IPC function ID with an IPC message queue so
+/// that when the calling processor recieves a command with the specified
+/// function ID the message will be place on the message queue and a thread
+/// that is blocked waiting for a message on the queue (using the
+/// \a ipc_msgq_recv interface) will be woken up and given the message.
+///
+/// This function should be called in place of the \a ipc_set_handler
+/// interface.
+///
+/// NOTE: Multiple function ID's can be associated with a single queue.
+///
+/// Possible return codes are:
+///
+/// \retval IPC_RC_SUCCESS The operation completed successfully.
+///
+/// \retval IPC_RC_INVALID_TARGET_ID The function ID is a single-target
+/// function ID that does not target this processor.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The function ID is not a valid IPC function
+/// ID.
+///
+int ipc_register_msgq(uint32_t func_id, ipc_msgq_t* msgq);
+
+///////////////////////////////////////////////////////////////////////////////
+/// Internal function that places an IPC message on an IPC message queue
+///
+void ipc_msgq_handler(ipc_msg_t* msg, void* arg);
+
+///////////////////////////////////////////////////////////////////////////////
+/// The default IPC command handler simply sends a response with the IPC return
+/// code set to IPC_RC_CMD_NOT_SUPPORTED
+///
+void ipc_default_handler(ipc_msg_t* msg, void* arg);
+
+#endif /*__ASSEMBLER__*/
+#endif  /* __IPC_API_H__ */
diff --git a/src/lib/occlib/ipc_async_cmd.h b/src/lib/occlib/ipc_async_cmd.h
new file mode 100644
index 0000000..db09e9e
--- /dev/null
+++ b/src/lib/occlib/ipc_async_cmd.h
@@ -0,0 +1,49 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_async_cmd.h $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __IPC_ASYNC_CMD_H__
+#define __IPC_ASYNC_CMD_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_async_cmd.h
+/// \brief This header is shared between the 405 and GPE's that need to
+/// support IPC command messages that are sent from the occhw_async_gpe.c
+/// code.
+///
+
+#include "ipc_api.h"
+
+#ifndef __ASSEMBLER__
+
+typedef struct {
+    ipc_msg_t   cmd;
+    void*       cmd_data;
+}ipc_async_cmd_t;
+
+#endif /*__ASSEMBLER__*/
+#endif /*__IPC_ASYNC_CMD_H__*/
diff --git a/src/lib/occlib/ipc_core.c b/src/lib/occlib/ipc_core.c
new file mode 100644
index 0000000..342f024
--- /dev/null
+++ b/src/lib/occlib/ipc_core.c
@@ -0,0 +1,484 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_core.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_core.c
+/// \brief Implementation of core IPC (InterProcessor Communication) routines
+
+#include "kernel.h"
+#include "ipc_api.h"
+#include "occhw_shared_data.h"
+
+/// If G_ipc_enabled is zero then calls to ipc_send_cmd() will return
+/// IPC_RC_SELF_BLOCKED.
+uint8_t     G_ipc_enabled = 0;
+
+#ifndef STATIC_IPC_TABLES
+ipc_func_table_entry_t G_ipc_mt_handlers[IPC_MT_MAX_FUNCTIONS];
+ipc_func_table_entry_t G_ipc_st_handlers[IPC_ST_MAX_FUNCTIONS];
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+/// Helper function used by ipc_send_cmd and ipc_send_rsp to send a message
+///
+int ipc_send_msg(ipc_msg_t* msg, uint32_t target_id)
+{
+    ipc_target_t*           target_cbufs;
+    uint8_t*                read_count;
+    uint8_t*                write_count;
+    ipc_msg_t**             msgs;
+    KERN_MACHINE_CONTEXT    ctx;
+    int                     rc = IPC_RC_SUCCESS;
+    uint8_t                 num_entries;
+
+    do
+    {
+        // Check for invalid target ID
+        if(target_id > OCCHW_INST_ID_MAX)
+        {
+            rc = IPC_RC_INVALID_TARGET_ID;
+            break;
+        }
+
+        target_cbufs = &OSD_PTR->ipc_data.targets[target_id];
+        msgs = &target_cbufs->cbufs[OCCHW_INST_ID_SELF][0];
+        read_count = &target_cbufs->counts.reads.counts8[OCCHW_INST_ID_SELF];
+        write_count = &target_cbufs->counts.writes.counts8[OCCHW_INST_ID_SELF];
+
+        //Prevent other threads on this processor from updating the cbuf
+        KERN_CRITICAL_SECTION_ENTER(KERN_CRITICAL, &ctx);
+
+        //Determine the number of entries in the buffer
+        num_entries = *write_count - *read_count;
+
+        //If the cbuf isn't full, then add the message and raise an interrupt
+        if(num_entries < IPC_CBUF_SIZE)
+        {
+            // Mark the message as being active
+            msg->func_id.active_flag = 1;
+
+            msgs[*write_count % IPC_CBUF_SIZE] = msg;
+            (*write_count)++;
+
+            //raise the IPC interrupt on the target
+            KERN_IRQ_STATUS_SET(IPC_GET_IRQ(target_id), 1);
+        }
+        else
+        {
+            //Check if cbuf is just full or is blocked
+            if(num_entries == IPC_CBUF_SIZE)
+            {
+                rc = IPC_RC_BUFFER_FULL;
+            }
+            else
+            {
+                rc = IPC_RC_TARGET_BLOCKED;
+            }
+        }
+        KERN_CRITICAL_SECTION_EXIT(&ctx);
+    }while(0);
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Send a message as a command
+///
+int ipc_send_cmd(ipc_msg_t* cmd)
+{
+    int rc;
+    do
+    {
+        //don't allow sending new commands if IPC is disabled
+        if(!G_ipc_enabled)
+        {
+            rc = IPC_RC_SELF_BLOCKED;
+            break;
+        }
+
+        //don't send a command if the valid flag is not set
+        if(!cmd->func_id.valid_flag)
+        {
+            rc = IPC_RC_INVALID_FUNC_ID;
+            break;
+        }
+
+        //don't send a command if the active flag is set
+        if(cmd->func_id.active_flag)
+        {
+            rc = IPC_RC_MSG_ACTIVE;
+            break;
+        }
+
+        cmd->func_id.response_flag = 0;
+
+        //Set the sender ID here.  Remote side uses this for sending responses.
+        cmd->func_id.sender_id = OCCHW_INST_ID_SELF;
+
+        cmd->ipc_rc = 0;
+
+        //place the message on the target's circular buffer
+        rc = ipc_send_msg(cmd, cmd->func_id.target_id);
+
+        cmd->ipc_rc = rc;
+    }while(0);
+    return rc;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// Send a command message back to the sender as a response message with status.
+/// 
+int ipc_send_rsp(ipc_msg_t* rsp, uint32_t ipc_rc)
+{
+    int rc;
+    if(rsp->func_id.active_flag)
+    {
+        rsp->func_id.response_flag = 1;
+        rsp->ipc_rc = ipc_rc;
+        rc = ipc_send_msg(rsp, rsp->func_id.sender_id);
+    }
+    else
+    {
+        rc = IPC_RC_MSG_NOT_ACTIVE;
+    }
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Default IPC handler that is called when no IPC handler has been
+/// installed for the IPC function that is being requested.
+void ipc_default_handler(ipc_msg_t* msg, void* arg)
+{
+    //Return code is ignored.  If failure occurs in sending
+    //the response then the sender of the command should eventually
+    //time out waiting for a response or the sender may be incapacitated.
+    ipc_send_rsp(msg, IPC_RC_CMD_NOT_SUPPORTED);
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Set the target ID for a multi-target command message.
+///
+int ipc_set_cmd_target(ipc_msg_t* cmd, uint32_t target_id)
+{
+    int rc = IPC_RC_SUCCESS;
+    do
+    {
+        //verify that this is a muti-target function
+        if(!cmd->func_id.multi_target_flag)
+        {
+            rc = IPC_RC_INVALID_FUNC_ID;
+            break;
+        }
+        else
+        {
+            cmd->func_id.target_id = target_id;
+        }
+    }while(0);
+
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Processes an incoming message (response or command) after it has been
+/// removed from the circular buffer.
+/// This function is for internal use only!
+///
+void ipc_process_msg(ipc_msg_t* msg)
+{
+    uint32_t                table_index;
+    uint32_t                table_limit;
+    ipc_func_table_entry_t *func_table;
+
+    do
+    {
+        // If this is a response message, call the response callback function
+        if(msg->func_id.response_flag)
+        {
+            if(msg->resp_callback)
+            {
+                msg->resp_callback(msg, msg->callback_arg);
+            }
+            else
+            {
+                //normally, the resp_callback function would call this function
+                //to notify users of the message that it is free to be re-used.
+                //Since there is no callback for this message we call it here.
+                ipc_free_msg(msg);
+            }
+
+            break;
+        }
+
+        // extract the function table index
+        table_index = msg->func_id.table_index;
+
+        //setup for multi-target commands
+        if(msg->func_id.multi_target_flag)
+        {
+            table_limit = IPC_MT_NUM_FUNCIDS;
+            func_table = G_ipc_mt_handlers;
+        }
+        //setup for single-target commands
+        else
+        {
+            table_limit = IPC_ST_NUM_FUNCIDS;
+            func_table = G_ipc_st_handlers;
+        }
+
+        //Common command handling code
+        if(table_index < table_limit)
+        {
+            func_table[table_index].handler(msg, func_table[table_index].arg);
+        }
+        else
+        {
+            //drop errors if this fails.  If target was waiting for a response
+            //it should eventually time out and log the message as FFDC.
+            ipc_send_rsp(msg, IPC_RC_INVALID_FUNC_ID);
+        }
+    }while(0);
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Removes messages from the circular buffer for the processor associated with
+/// sender_id and processes them one at a time.
+/// This function is for internal use only!
+///
+void ipc_process_cbuf(uint32_t sender_id)
+{
+    ipc_target_t            *my_cbufs = &OSD_PTR->ipc_data.targets[OCCHW_INST_ID_SELF];
+    uint8_t                 *read_count = &my_cbufs->counts.reads.counts8[sender_id];
+    uint8_t                 *write_count = &my_cbufs->counts.writes.counts8[sender_id];
+    ipc_msg_t               **msg_ptrs = &my_cbufs->cbufs[sender_id][0];
+    ipc_msg_t               *cur_msg;
+    
+
+    while(*read_count != *write_count)
+    {
+        // extract the message pointer
+        cur_msg = msg_ptrs[*read_count % IPC_CBUF_SIZE];
+
+        // increment the read count
+        (*read_count)++;
+
+        ipc_process_msg(cur_msg);
+    }
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// The IPC interrupt handler.  Finds which circular buffers have messages
+/// and processes them.
+///
+#ifdef __SSX__
+KERN_IRQ_HANDLER(ipc_irq_handler_full)
+#else
+KERN_IRQ_HANDLER(ipc_irq_handler)
+#endif
+{
+    ipc_counts_t    xored_counts;
+    ipc_target_t    *my_cbufs;
+    uint32_t        sender_id;
+
+    // Processors could be sending us new packets while we're
+    // processing this interrupt.  We need to mask all new
+    // IPI interrupts until we are done processing so that we don't
+    // end up processing an interrupt that was already handled.
+    KERN_IRQ_DISABLE(IPC_GET_IRQ(OCCHW_INST_ID_SELF));
+
+    // Clear the interrupt bit in the OISR before we check for
+    // status.  Checking status and then clearing the OISR bit
+    // can lead to a race condition where we loose an interrupt.
+    KERN_IRQ_STATUS_CLEAR(IPC_GET_IRQ(OCCHW_INST_ID_SELF));
+
+    my_cbufs = &OSD_PTR->ipc_data.targets[OCCHW_INST_ID_SELF];
+
+    // Make sure we get the most recent write counts from SRAM
+    // dcbf(&my_cbufs->counts.writes.counts64);
+
+    // Use XOR to find the buffers that aren't empty (read count != write count)
+    xored_counts.counts64 = my_cbufs->counts.reads.counts64 ^
+                            my_cbufs->counts.writes.counts64;
+
+    while(1)
+    {
+        // Use cntlzw to find the first buffer that isn't empty
+        sender_id = cntlz64(xored_counts.counts64) / IPC_CBUF_COUNT_BITS;
+
+    
+        // If all buffers are empty then we're done
+        if(sender_id > OCCHW_INST_ID_MAX)
+        {
+            break;
+        }
+
+        // Mark the buffer as empty in our local snapshot
+        xored_counts.counts8[sender_id] = 0;
+
+        // Process all new messages in the buffer
+        ipc_process_cbuf(sender_id);
+    }
+
+    // Unmask the irq before returning
+    KERN_IRQ_ENABLE(IPC_GET_IRQ(OCCHW_INST_ID_SELF));
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// This macro creates an assembly function named ipc_irq_handler which handles
+/// saving/restoring the context that is required for calling a C
+/// function.
+///
+/// NOTE: This is only needed for SSX.  PK only supports full interrupts.
+///
+#ifdef __SSX__
+KERN_IRQ_FAST2FULL(ipc_irq_handler, ipc_irq_handler_full);
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize IPC control structures.
+///
+int ipc_init(void)
+{
+    //prevent new messages from coming in.
+    ipc_disable(OCCHW_INST_ID_SELF);
+
+#ifndef STATIC_IPC_TABLES
+    int i;
+    for(i = 0; i < IPC_MT_MAX_FUNCTIONS; i++)
+    {
+        G_ipc_mt_handlers[i].handler = ipc_default_handler;
+        G_ipc_mt_handlers[i].arg = 0;
+    }
+    for(i = 0; i < IPC_ST_MAX_FUNCTIONS; i++)
+    {
+        G_ipc_st_handlers[i].handler = ipc_default_handler;
+        G_ipc_st_handlers[i].arg = 0;
+    }
+#endif
+    return IPC_RC_SUCCESS;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Enables IPC communications.
+///
+int ipc_enable(void)
+{
+    int rc;
+    ipc_target_t* my_cbufs;
+
+    do
+    {
+        // Install the IPI interrupt handler for this processor
+        rc = KERN_IRQ_HANDLER_SET(IPC_GET_IRQ(OCCHW_INST_ID_SELF),
+                          ipc_irq_handler,
+                          0,
+                          KERN_CRITICAL);
+
+        if(rc)
+        {
+            break;
+        }
+
+        my_cbufs = &OSD_PTR->ipc_data.targets[OCCHW_INST_ID_SELF];
+
+        //Any messages that were placed on the cbufs before this point
+        //are dropped.  Clear any interrupts that might have been raised
+        //before this point.
+        KERN_IRQ_STATUS_CLEAR(IPC_GET_IRQ(OCCHW_INST_ID_SELF));
+
+        // Clear and open up all receive buffers for this processor
+        // by setting the read counts equal to the write counts
+        my_cbufs->counts.reads.counts64 = my_cbufs->counts.writes.counts64;
+
+        // Unmask the IPI interrupt for this processor
+        KERN_IRQ_ENABLE(IPC_GET_IRQ(OCCHW_INST_ID_SELF));
+
+        //Allow us to send out new commands
+        G_ipc_enabled = 1;
+
+    }while(0);
+
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Disable recieving new IPC commands for a processor.
+///
+int ipc_disable(uint32_t target_id)
+{
+    int i;
+    int rc = IPC_RC_SUCCESS;
+    ipc_target_t* target_cbufs;
+    KERN_MACHINE_CONTEXT    ctx;
+
+    do
+    {
+        // Check for invalid target ID
+        if(target_id > OCCHW_INST_ID_MAX)
+        {
+            rc = IPC_RC_INVALID_TARGET_ID;
+            break;
+        }
+
+        // Prevent us from sending out new commands
+        if(target_id == OCCHW_INST_ID_SELF)
+        {
+            G_ipc_enabled = 0;
+        }
+
+        //disable interrupts to prevent the IPC interrupt handler or other threads
+        //on this instance from interrupting us and changing the read count or
+        //interrupt mask bits under our feet.
+        KERN_CRITICAL_SECTION_ENTER(KERN_CRITICAL, &ctx);
+
+        //mask off the IPC interrupt for the target (this is mostly for the case
+        //where we are diabling IPC for ourselves).
+        KERN_IRQ_DISABLE(IPC_GET_IRQ(target_id));
+
+        target_cbufs = &OSD_PTR->ipc_data.targets[target_id];
+
+        // Make each cbuf appear to be more than full. This signals to
+        // senders that the buffer is not just full, but blocked.  When
+        // the sender sees this it knows not to place more messages on the cbuf.
+        // NOTE: we are updating the read register, which is allowed if the cbuf
+        // is owned by the instance this code is running on OR if the instance
+        // is known to be halted.
+        for(i = 0; i <= OCCHW_INST_ID_MAX; i++)
+        {
+            target_cbufs->counts.reads.counts8[i] = 
+                target_cbufs->counts.writes.counts8[i] - (IPC_CBUF_SIZE * 2);
+        }
+
+        KERN_CRITICAL_SECTION_EXIT(&ctx);
+
+    }while(0);
+    return rc;
+}
+
diff --git a/src/lib/occlib/ipc_init.c b/src/lib/occlib/ipc_init.c
new file mode 100644
index 0000000..4d732b7
--- /dev/null
+++ b/src/lib/occlib/ipc_init.c
@@ -0,0 +1,153 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_init.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_init.c
+/// \brief Implementation of IPC (InterProcessor Communication) routines for
+///        Setting up the IPC function tables, messages and message queues.
+///
+/// NOTE: The functions that these interfaces peform can all be done statically.
+/// This code will not be included in an image if none of the functions are
+/// referenced.
+
+#include "ipc_api.h"
+#include "ipc_ping.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// Associate an IPC function ID with a handler function
+///
+int ipc_set_handler(uint32_t            function_id,
+                    ipc_msg_handler_t   handler,
+                    void*               callback_arg)
+{
+    ipc_func_table_entry_t *func_table;
+    uint32_t                table_limit;
+    int                     rc = IPC_RC_SUCCESS;
+    ipc_func_id_t           func_id = {{0}};
+
+    do
+    {
+        func_id.word32 = function_id;
+
+        //setup for multi-target commands
+        if(func_id.multi_target_flag)
+        {
+            table_limit = IPC_MT_NUM_FUNCIDS;
+            func_table = G_ipc_mt_handlers;
+        }
+        //setup for single-target commands
+        else
+        {
+            //make sure the function id targets this processor
+            if(func_id.target_id != OCCHW_INST_ID_SELF)
+            {
+                rc = IPC_RC_INVALID_TARGET_ID;
+                break;
+            }
+            table_limit = IPC_ST_NUM_FUNCIDS;
+            func_table = G_ipc_st_handlers;
+        }
+
+        //make sure the function id is valid
+        if((func_id.table_index >= table_limit) || !func_id.valid_flag)
+        {
+            rc = IPC_RC_INVALID_FUNC_ID;
+            break;
+        }
+
+        if(!handler)
+        {
+            rc = IPC_RC_INVALID_ARG;
+            break;
+        }
+
+        func_table[func_id.table_index].handler = handler;
+        func_table[func_id.table_index].arg = callback_arg;
+    }while(0);
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC command message
+///
+void ipc_init_msg(ipc_msg_t* msg, 
+                 uint32_t func_id,
+                 ipc_msg_handler_t resp_callback,
+                 void* callback_arg)
+{
+    KERN_DEQUE_ELEMENT_CREATE(&msg->node);
+    msg->func_id.word32 = func_id;
+    msg->ipc_rc = IPC_RC_SUCCESS;
+    msg->resp_callback = resp_callback;
+    msg->callback_arg = callback_arg;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC message queue.
+///
+void ipc_init_msgq(ipc_msgq_t* msgq)
+{
+    KERN_DEQUE_SENTINEL_CREATE(&msgq->msg_head);
+
+    //set the initial count to 0 with no max count
+    KERN_SEMAPHORE_CREATE(&msgq->msg_sem, 0, 0);
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC message and associate it with an IPC message queue
+///
+void ipc_init_msgq_msg(ipc_msg_t* msg, uint32_t func_id, ipc_msgq_t* msgq)
+{
+    ipc_init_msg(msg, func_id, ipc_msgq_handler, msgq);
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Initialize an IPC ping command message
+///
+#ifdef IPC_ENABLE_PING
+int ipc_ping_cmd_init(ipc_ping_cmd_t* ping_cmd)
+{
+    int rc;
+
+    do
+    {
+        //initialize the message
+        ipc_init_msg(&ping_cmd->msg, IPC_MT_PING, ipc_ping_response, 0);
+
+        //initialize the semaphore count to 0 and set the max count to 1
+        rc = KERN_SEMAPHORE_CREATE(&ping_cmd->sem, 0, 1);
+        if(rc)
+        {
+            break;
+        }
+    }while(0);
+    return rc;
+}
+#endif /*IPC_ENABLE_PING*/
diff --git a/src/lib/occlib/ipc_macros.h b/src/lib/occlib/ipc_macros.h
new file mode 100644
index 0000000..c95bff6
--- /dev/null
+++ b/src/lib/occlib/ipc_macros.h
@@ -0,0 +1,197 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_macros.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __IPC_MACROS_H__
+#define __IPC_MACROS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_macros.h
+/// \brief Contains macros related to the Interprocessor Communications (IPC)
+/// API.
+///
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieves the IRQ number for the specified OCC processor instance
+///
+#define IPC_GET_IRQ(instance_id) (OCCHW_IRQ_IPI0_HI_PRIORITY + instance_id)
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the start of the IPC function ID table
+///
+#define IPC_FUNCIDS_TABLE_START \
+    typedef enum \
+{
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the end of the IPC function ID table
+///
+#define IPC_FUNCIDS_TABLE_END \
+} ipc_func_enum_t;
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the start of the IPC multi-target function IDs within the IPC
+/// function ID table.
+///
+#define IPC_FUNCIDS_MT_START \
+    IPC_MT_START = (int)((IPC_TARGET_MASK | IPC_FLAG_MT | IPC_FLAG_VALID | (((uint32_t)((uint8_t)OCCHW_INST_ID_SELF)) << 16)) - 1),
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the end of the IPC multi-target function IDs within the IPC function
+/// ID table.
+///
+#define IPC_FUNCIDS_MT_END \
+    IPC_MT_END,
+
+#define IPC_CONCAT_INST(name, inst) name ## inst
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the start of the IPC single-target function IDs within the IPC
+/// ID table.
+///
+/// \param target_id The instance ID of the processor that the following
+/// function IDs will target.
+///
+/// Each processor has it's own set of single-target function IDs.  Messages
+/// that are initialized with these function ID's can only be sent to the
+/// processor specified by \a target_id.
+///
+#define IPC_FUNCIDS_ST_START(target_id) \
+    IPC_CONCAT_INST(IPC_ST_START_, target_id) = \
+    (int)(((((uint32_t)target_id) << 24) | IPC_FLAG_VALID ) - 1),
+
+///////////////////////////////////////////////////////////////////////////////
+/// Marks the end of the IPC single-target function IDs for the specified
+/// target ID, \a target_id.
+///
+#define IPC_FUNCIDS_ST_END(target_id) \
+    IPC_CONCAT_INST(IPC_ST_END_, target_id),
+
+///////////////////////////////////////////////////////////////////////////////
+/// Create an IPC function ID.
+///
+/// \param The name of the IPC function ID
+///
+/// This macro should only be used inside the IPC function ID table.  Under
+/// the covers, an enum with a name of \a name is created.
+///
+#define IPC_FUNC_ID(name) \
+    name,
+
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_MT_NUM_FUNCIDS \
+    ((IPC_MT_END - IPC_MT_START) - 1)
+
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_ST_TARGET_NUM_FUNCIDS(target_id) \
+    ((IPC_CONCAT_INST(IPC_ST_END_, target_id) - IPC_CONCAT_INST(IPC_ST_START_, target_id)) - 1)
+
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_ST_NUM_FUNCIDS IPC_ST_TARGET_NUM_FUNCIDS(OCCHW_INST_ID_SELF)
+
+///////////////////////////////////////////////////////////////////////////////
+/// Macros for statically initializing the IPC function tables
+#ifdef STATIC_IPC_TABLES
+
+#define IPC_MT_FUNC_TABLE_START \
+    ipc_func_table_entry_t G_ipc_mt_handlers[IPC_MT_MAX_FUNCTIONS] = \
+{
+
+#define IPC_ST_FUNC_TABLE_START \
+    ipc_func_table_entry_t G_ipc_st_handlers[IPC_ST_MAX_FUNCTIONS] = \
+{
+
+#define IPC_HANDLER(func, arg) \
+    {func, arg},
+
+#define IPC_HANDLER_DEFAULT \
+    {ipc_default_handler, 0},
+
+#define IPC_MSGQ_HANDLER(msgq_ptr) \
+    {ipc_msgq_handler, msgq_ptr},
+
+#define IPC_MT_FUNC_TABLE_END \
+};
+
+#define IPC_ST_FUNC_TABLE_END \
+};
+
+#else
+
+#define IPC_MT_FUNC_TABLE_START
+
+#define IPC_ST_FUNC_TABLE_START 
+
+#define IPC_HANDLER(func, arg)
+
+#define IPC_HANDLER_DEFAULT
+
+#define IPC_MSGQ_HANDLER(msgq_ptr)
+
+#define IPC_MT_FUNC_TABLE_END
+
+#define IPC_ST_FUNC_TABLE_END 
+
+#endif /*STATIC_IPC_TABLES*/
+
+///////////////////////////////////////////////////////////////////////////////
+/// Convenience macro for defering handling of a command or
+/// response in a noncritical interrupt context.  This was
+/// specifically added for ipc functions that need to call
+/// ssx functions on the 405. (ssx functions can not be called
+/// inside a critical interrupt context).
+#ifdef __SSX__
+#define IPC_DEFER_TO_NONCRITICAL(ipc_msg) \
+{ \
+    ssx_deque_push_back(&G_ipc_deferred_queue, &ipc_msg->node); \
+    ssx_irq_status_set(OCCHW_IRQ_ASYNC_IPI, 1); \
+}
+
+#else
+#define IPC_DEFER_TO_NONCRITICAL(ipc_msg)
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+/// Determine if an IPC function ID is a multi-target ID
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_FUNCID_IS_MT(funcid) (IPC_FLAG_MT & (funcid))
+
+///////////////////////////////////////////////////////////////////////////////
+/// Set the target ID of a multi-target function ID
+/// Sets the target to be invalid if it's not a multi-target function id
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_SET_MT_TARGET(funcid, targetid) \
+(((funcid) & IPC_FLAG_MT)?  \
+  (((targetid) << IPC_TARGET_SHIFT)  | ((funcid) & ~(IPC_TARGET_MASK))): \
+  (IPC_TARGET_MASK | (funcid)))
+
+///////////////////////////////////////////////////////////////////////////////
+/// Retrieve the target ID from an IPC function id
+///////////////////////////////////////////////////////////////////////////////
+#define IPC_GET_TARGET_ID(funcid) (((uint32_t)(funcid)) >> IPC_TARGET_SHIFT)
+
+#endif /*__IPC_MACROS_H__*/
diff --git a/src/lib/occlib/ipc_msgq.c b/src/lib/occlib/ipc_msgq.c
new file mode 100644
index 0000000..8048b72
--- /dev/null
+++ b/src/lib/occlib/ipc_msgq.c
@@ -0,0 +1,108 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_msgq.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_msgq.c
+/// \brief Implementation of IPC (InterProcessor Communication) routines that
+///        involve using message queues (primarily in a thread context).
+
+#include "ipc_api.h"
+
+///////////////////////////////////////////////////////////////////////////////
+// Handles msgq messages (commands and responses) by placing them on a message
+// queue and then posting the message queue semaphore.
+// This function is for internal use only!
+void ipc_msgq_handler(ipc_msg_t* msg, void* arg)
+{
+    ipc_msgq_t  *msgq = (ipc_msgq_t*)arg;
+
+    //NOTE: this is hard coded to 0 on PPE
+    if(KERN_CONTEXT_CRITICAL_INTERRUPT())
+    {
+        //NOTE: this is a no-op on PPE
+        IPC_DEFER_TO_NONCRITICAL(msg);
+    }
+    else
+    {
+        KERN_DEQUE_PUSH_BACK(&msgq->msg_head, &msg->node);
+        KERN_SEMAPHORE_POST(&msgq->msg_sem);
+    }
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// Wait (with timeout) for an IPC message on an IPC message queue.
+///
+int ipc_msgq_recv(ipc_msg_t** msg, ipc_msgq_t* msgq, KERN_INTERVAL timeout)
+{
+    int                     rc;
+    ipc_msg_t               *popped_msg = 0;
+    KERN_MACHINE_CONTEXT    ctx;
+
+    rc = KERN_SEMAPHORE_PEND(&msgq->msg_sem, timeout);
+    if(rc)
+    {
+        if(rc == -KERN_SEMAPHORE_PEND_TIMED_OUT ||
+           rc == -KERN_SEMAPHORE_PEND_NO_WAIT)
+        {
+            rc = IPC_RC_TIMEOUT;
+        }
+    }
+    else
+    {
+        //The queue is also modified in the IPC interrupt context so
+        //we need to make sure interrupts are disabled while we modify it.
+        KERN_CRITICAL_SECTION_ENTER(KERN_CRITICAL, &ctx);
+        popped_msg = (ipc_msg_t*)KERN_DEQUE_POP_FRONT(&msgq->msg_head);
+        KERN_CRITICAL_SECTION_EXIT(&ctx);
+
+        if(popped_msg)
+        {
+            rc = IPC_RC_SUCCESS;
+        }
+        else
+        {
+            rc = IPC_RC_NO_MSG;
+        }
+    }
+    *msg = popped_msg;
+    return rc;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+/// Associate a message queue with a function ID (commands recieved with the
+/// specified function id will be placed on the message queue).
+///
+int ipc_register_msgq(uint32_t func_id, ipc_msgq_t* msgq)
+{
+    return ipc_set_handler(func_id, ipc_msgq_handler, msgq);
+}
+
+
+
diff --git a/src/lib/occlib/ipc_ping.c b/src/lib/occlib/ipc_ping.c
new file mode 100644
index 0000000..f295c99
--- /dev/null
+++ b/src/lib/occlib/ipc_ping.c
@@ -0,0 +1,96 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_ping.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "ipc_ping.h"
+
+#ifdef IPC_ENABLE_PING
+//server side ping message handler
+void ipc_ping_handler(ipc_msg_t* cmd, void* arg)
+{
+    //NOTE: this will run in a critical interrupt when sent to the 405
+    //ignore return codes
+    ipc_send_rsp(cmd, IPC_RC_SUCCESS);
+}
+
+//Note: This runs in a critical interrupt on the 405 but SSX functions
+//      can not be called from a critical interrupt.  Instead, it must be
+//      deferred to a non-critical handler.
+void ipc_ping_response(ipc_msg_t* rsp, void* arg)
+{
+    ipc_ping_cmd_t *ping_cmd = (ipc_ping_cmd_t*)rsp;
+
+    if(KERN_CONTEXT_CRITICAL_INTERRUPT())
+    {
+        //NOTE: this is a no-op on PPE
+        IPC_DEFER_TO_NONCRITICAL(rsp);
+    }
+    else
+    {
+        KERN_SEMAPHORE_POST(&ping_cmd->sem);
+        ipc_free_msg(&ping_cmd->msg);
+    }
+
+}
+
+
+//Command that can be run in a thread context to ping another target
+//The message is allocated on the stack
+int ipc_ping(ipc_ping_cmd_t* ping_cmd, uint32_t target_id)
+{
+    int rc;
+
+    do
+    {
+        //set the target (since this is a multi-target command)
+        rc = ipc_set_cmd_target(&ping_cmd->msg, target_id);
+        if(rc)
+        {
+            break;
+        }
+
+        //send the command
+        rc = ipc_send_cmd(&ping_cmd->msg);
+        if(rc)
+        {
+            break;
+        }
+
+        //assume that if we timed out then the target must have gone down.
+        rc = KERN_SEMAPHORE_PEND(&ping_cmd->sem, KERN_SECONDS(1));
+        if(rc)
+        {
+            if(rc == -KERN_SEMAPHORE_PEND_TIMED_OUT)
+            {
+                rc = IPC_RC_TIMEOUT;
+            }
+            break;
+        }
+
+        //response message was received.  Now return the ipc_rc
+        rc = ipc_get_rc(&ping_cmd->msg);
+        
+    }while(0);
+    return rc;
+}
+#endif /*IPC_ENABLE_PING*/
diff --git a/src/lib/occlib/ipc_ping.h b/src/lib/occlib/ipc_ping.h
new file mode 100644
index 0000000..0b315ee
--- /dev/null
+++ b/src/lib/occlib/ipc_ping.h
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_ping.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "ipc_api.h"
+
+typedef struct
+{
+    ipc_msg_t msg;
+    KERN_SEMAPHORE sem;
+}ipc_ping_cmd_t;
+
+#ifdef IPC_ENABLE_PING
+//server side ping message handler
+void ipc_ping_handler(ipc_msg_t* cmd, void* arg);
+
+//Initialize a ping command.  
+int ipc_ping_cmd_init(ipc_ping_cmd_t* ping_cmd);
+
+//function for handling the ping response on the local processor
+void ipc_ping_response(ipc_msg_t* rsp, void* arg);
+
+//Statically initialize a ping command
+#define IPC_PING_CMD_CREATE(name) \
+ipc_ping_cmd_t name = \
+{\
+    .msg = IPC_MSG_INIT(IPC_MT_PING, ipc_ping_response, 0), \
+    .sem = KERN_SEMAPHORE_INITIALIZATION(0, 1) \
+}
+
+//blocking command that can be run in a thread context to ping another target
+int ipc_ping(ipc_ping_cmd_t* ping_cmd, uint32_t target_id);
+#endif /*IPC_ENABLE_PING*/
diff --git a/src/lib/occlib/ipc_structs.h b/src/lib/occlib/ipc_structs.h
new file mode 100644
index 0000000..5f1c90b
--- /dev/null
+++ b/src/lib/occlib/ipc_structs.h
@@ -0,0 +1,226 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/ipc_structs.h $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __IPC_STRUCTS_H__
+#define __IPC_STRUCTS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ipc_structs.h
+/// \brief Common header for Interprocessor Communication structures in the
+///        OCC complex
+///
+#include "kernel.h"         //kernel wrapper macros
+#include "occhw_common.h"
+#include "ipc_macros.h"
+
+
+#ifndef IPC_CBUF_SIZE
+#define IPC_CBUF_SIZE 8 //number of messages must be a power of 2
+#endif
+
+//the maximum number of multi-target functions (common functions)
+//This can be overriden in a global header that's included by all occ images
+//so that it is the same across all processors.
+#ifndef IPC_MT_MAX_FUNCTIONS
+#define IPC_MT_MAX_FUNCTIONS 8
+#endif
+
+//the maximum number of single-target functions (processor-specific functions)
+//This can be overridden in a local header file and does not need to be the
+//same across all processors.
+#ifndef IPC_ST_MAX_FUNCTIONS 
+#define IPC_ST_MAX_FUNCTIONS 16
+#endif
+
+/// IPC return codes
+#define IPC_RC_SUCCESS               0
+#define IPC_RC_CMD_FAILED            0x00472000
+#define IPC_RC_BUFFER_FULL           0x00472001
+#define IPC_RC_SELF_BLOCKED          0x00472002
+#define IPC_RC_TARGET_BLOCKED        0x00472003
+#define IPC_RC_MSG_ACTIVE            0x00472004
+#define IPC_RC_INVALID_FUNC_ID       0x00472005
+#define IPC_RC_CMD_NOT_SUPPORTED     0x00472006
+#define IPC_RC_INVALID_TARGET_ID     0x00472007
+#define IPC_RC_INVALID_ARG           0x00472008
+#define IPC_RC_MSG_NOT_ACTIVE        0x00472009
+#define IPC_RC_NO_MSG                0x0047200a
+#define IPC_RC_TIMEOUT               0x0047200b
+
+/// IPC Message Flags
+#define IPC_FLAG_MT             0x00000100
+#define IPC_FLAG_RESPONSE       0x00000200
+#define IPC_FLAG_VALID          0x00000400
+#define IPC_FLAG_ACTIVE         0x00000800
+
+// Function ID field masks
+#define IPC_TARGET_MASK         0xff000000
+#define IPC_SENDER_MASK         0x00ff0000
+#define IPC_FLAGS_MASK          0x0000ff00
+#define IPC_INDEX_MASK          0x000000ff
+
+#define IPC_TARGET_SHIFT        24
+
+#define IPC_CBUF_COUNT_BYTES        1
+#define IPC_CBUF_COUNT_BITS         8
+
+#ifndef __ASSEMBLER__
+
+// If an occ application does not wish to use IPC then it should not
+// define the GLOBAL_CFG_USE_IPC macro.  This allows IPC to compile
+// without errors.
+#ifdef GLOBAL_CFG_USE_IPC
+#include "ipc_func_ids.h"
+#else
+IPC_FUNCIDS_TABLE_START
+    IPC_FUNCIDS_MT_START
+    IPC_FUNCIDS_MT_END
+    IPC_FUNCIDS_ST_START(OCCHW_INST_ID_GPE0)
+    IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE0)
+    IPC_FUNCIDS_ST_START(OCCHW_INST_ID_GPE1)
+    IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE1)
+    IPC_FUNCIDS_ST_START(OCCHW_INST_ID_GPE2)
+    IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE2)
+    IPC_FUNCIDS_ST_START(OCCHW_INST_ID_GPE3)
+    IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE3)
+    IPC_FUNCIDS_ST_START(OCCHW_INST_ID_PPC)
+    IPC_FUNCIDS_ST_END(OCCHW_INST_ID_PPC)
+IPC_FUNCIDS_TABLE_END
+#endif /*GLOBAL_CFG_USE_IPC*/
+
+//Statically check that the function tables are large enough
+KERN_STATIC_ASSERT(IPC_MT_NUM_FUNCIDS <= IPC_MT_MAX_FUNCTIONS);
+KERN_STATIC_ASSERT(IPC_ST_NUM_FUNCIDS <= IPC_ST_MAX_FUNCTIONS);
+
+#ifdef __SSX__
+extern KERN_DEQUE G_ipc_deferred_queue;
+#endif
+
+struct ipc_msg;
+typedef struct ipc_msg ipc_msg_t;
+
+typedef union
+{
+    uint64_t    counts64;
+    uint8_t     counts8[sizeof(uint64_t) / IPC_CBUF_COUNT_BYTES];
+} ipc_counts_t;
+
+/// Circular buffer read and write counts are grouped together by target_id
+/// so that an interrupt hander can quickly tell which buffer requires
+/// service. Each counter is 1 byte.
+///
+/// Note: index 0 (or most significant byte) is for GPE0
+typedef struct
+{
+    ipc_counts_t    reads;
+    ipc_counts_t    writes;
+}ipc_rwcounts_t;
+
+typedef struct
+{
+    ipc_rwcounts_t counts;
+    ipc_msg_t*     cbufs[OCCHW_MAX_INSTANCES][IPC_CBUF_SIZE];
+    uint8_t        pad[16]; 
+}ipc_target_t; //size is 6 x 32 = 192 bytes
+
+/// All of the shared data for IPC is contained in this structure
+typedef struct
+{
+    ipc_target_t      targets[OCCHW_MAX_INSTANCES]; //880 bytes
+}ipc_shared_data_t;
+
+//prototype for ipc handlers and callback functions
+typedef void (*ipc_msg_handler_t)(ipc_msg_t*, void *);
+
+//function table entry
+typedef struct
+{
+    ipc_msg_handler_t   handler;
+    void*               arg;
+}ipc_func_table_entry_t;
+
+extern ipc_func_table_entry_t G_ipc_mt_handlers[IPC_MT_MAX_FUNCTIONS];
+
+extern ipc_func_table_entry_t G_ipc_st_handlers[IPC_ST_MAX_FUNCTIONS];
+
+typedef union
+{
+    struct
+    {
+        uint32_t    target_id:          8;
+        uint32_t    sender_id:          8;
+        uint32_t    reserved:           4;
+        uint32_t    active_flag:        1;
+        uint32_t    valid_flag:         1;
+        uint32_t    response_flag:      1;
+        uint32_t    multi_target_flag:  1;
+        uint32_t    table_index:        8;
+    };
+    uint32_t    word32;
+}ipc_func_id_t;
+
+#define IPC_MSG_DEQUEUE_SZ 8 //expected size of a deque structure
+struct ipc_msg
+{
+    // but this file is shared by both, so use a void* type
+    // instead.
+    union
+    {
+        KERN_DEQUE          node;
+        uint8_t             pad[IPC_MSG_DEQUEUE_SZ];
+    };
+
+    //function ID of the function that the sender wants executed
+    volatile ipc_func_id_t  func_id;
+
+    //The IPC return code
+    volatile uint32_t       ipc_rc;
+
+    //function to call if this is a response message
+    ipc_msg_handler_t       resp_callback;
+
+    //Argument passed into the callback function
+    void                    *callback_arg;
+};
+
+//Do a static check on the size of KERN_DEQUE.  IPC_MSG_DEQUE_SZ must be <= sizeof(KERN_DEQUE).
+//If the compiler fails here then you probably need to update the value of IPC_MSG_DEQUEUE_SZ.
+//NOTE: this is needed because ipc_msg_t is used in both PK and SSX environments and there is
+//      no guarantee that the size of a deque will be the same in both environments.
+KERN_STATIC_ASSERT(sizeof(KERN_DEQUE) <= IPC_MSG_DEQUEUE_SZ);
+
+//A message queue that threads can block on while they wait for new messages.
+typedef struct
+{
+    KERN_DEQUE          msg_head;
+    KERN_SEMAPHORE      msg_sem; //posted whenever a new message is queued
+}ipc_msgq_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif  /* __IPC_STRUCTS_H__ */
diff --git a/src/lib/occlib/liboccfiles.mk b/src/lib/occlib/liboccfiles.mk
new file mode 100644
index 0000000..7b3c80a
--- /dev/null
+++ b/src/lib/occlib/liboccfiles.mk
@@ -0,0 +1,53 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/occlib/liboccfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file liboccfiles.mk
+#
+#  @brief mk for libocc.a object files
+#
+#  @page ChangeLogs Change Logs
+#  @section liboccfiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# INCLUDES
+##########################################################################
+
+C-SOURCES = \
+    ipc_core.c \
+	ipc_init.c \
+	ipc_msgq.c \
+	ipc_ping.c \
+	occhw_xir_dump.c
+
+S-SOURCES =  
+
+LIBOCC_OBJECTS = $(C-SOURCES:.c=.o) $(S-SOURCES:.S=.o)
diff --git a/src/lib/occlib/occhw_scom_cmd.h b/src/lib/occlib/occhw_scom_cmd.h
new file mode 100644
index 0000000..c6051f5
--- /dev/null
+++ b/src/lib/occlib/occhw_scom_cmd.h
@@ -0,0 +1,93 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/occhw_scom_cmd.h $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_SCOM_CMD_H__
+#define __OCCHW_SCOM_CMD_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_scom_cmd.h
+/// \brief Defines the shared scom command control block
+///
+/// This file contains definitions that are used by both ppc405 and GPE
+/// instances inside the OCC.  
+
+// The most significant bit of scom addresses is always 0, so we use this
+// bit to tell the SCOM proxy server (GPE) whether a getscom or putscom is
+// needed.
+#define OCCHW_SCOM_READ_MASK        0x80000000
+
+// This is a status value that the ppc405 will write to the status
+// word prior to starting a new request.  This value can be used to
+// detect that the GPE has not yet written status for the request.
+// Note: The GPE simply copies it's MSR value to the status field
+// when it completes.  This value is not a valid MSR value.
+#define OCCHW_SCOM_PENDING          0x0000EF00
+
+// Define the structure offsets for use in assembly code on the GPE
+#define OCCHW_SCOM_STATUS_OFFSET    0
+#define OCCHW_SCOM_ADDR_OFFSET      4
+#define OCCHW_SCOM_DATA_OFFSET      8
+
+#ifndef __ASSEMBLER__
+typedef union
+{
+    uint32_t    status32;
+    struct
+    {
+        uint32_t rsvd0  :  1;
+        uint32_t mask   :  7;
+        uint32_t is0    :  1;
+        uint32_t sibrc  :  3;
+        uint32_t lp     :  1;
+        uint32_t we     :  1;
+        uint32_t is1    :  1;
+        uint32_t uie    :  1;
+        uint32_t ee     :  1;
+        uint32_t rsvd1  :  2;
+        uint32_t me     :  1;
+        uint32_t rsvd2  :  3;
+        uint32_t ipe    :  1;
+        uint32_t sibrca :  8;
+    };
+}occhw_scom_status_t;
+
+typedef struct
+{
+    //MSR is saved here
+    volatile occhw_scom_status_t    scom_status;
+
+    //msg is used to communicate read/!write
+    volatile uint32_t               scom_addr;
+
+    //data for putscom or from getscom
+    volatile uint64_t               scom_data;
+} occhw_scom_cmd_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif  /* __OCCHW_SCOM_CMD_H__ */
diff --git a/src/lib/occlib/occhw_shared_data.h b/src/lib/occlib/occhw_shared_data.h
new file mode 100644
index 0000000..643691a
--- /dev/null
+++ b/src/lib/occlib/occhw_shared_data.h
@@ -0,0 +1,93 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/occhw_shared_data.h $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_OSD_H__
+#define __OCCHW_OSD_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_osd.h
+/// \brief Common header for shared data within the OCC complex
+///
+
+#include "kernel.h"
+#include "ipc_structs.h"
+#include "occhw_scom_cmd.h"
+
+/// Hardcoded address for the location of the OCC shared data segment
+/// This is placed in the non-cacheable aliased region of SRAM space
+#ifndef OSD_ADDR
+#define OSD_ADDR 0xf7f00000
+#endif
+
+/// Total space of the OCC shared data segment
+#define OSD_TOTAL_SHARED_DATA_BYTES 4096
+
+/// Reserve space for IPC data in case it needs to grow
+#define OSD_IPC_RESERVED_BYTES 2048
+
+/// Reserve space for Debug
+#define OSD_DEBUG_RESERVED_BYTES 512
+
+#define OSD_GPE_SCOM_ADDR (OSD_ADDR + OSD_IPC_RESERVED_BYTES + OSD_DEBUG_RESERVED_BYTES)
+
+#define OSD_GPE_SCOM_RESERVED_BYTES 32
+
+#ifndef __ASSEMBLER__
+typedef union
+{
+    struct
+    {
+        union
+        {
+            ipc_shared_data_t   ipc_data;   //880 bytes
+            uint8_t             ipc_reserved[OSD_IPC_RESERVED_BYTES];
+        };
+        union
+        {
+            //debug_shared_data_t debug_data;
+            uint8_t             debug_reserved[OSD_DEBUG_RESERVED_BYTES];
+        };
+        union
+        {
+            occhw_scom_cmd_t    scom_cmd;
+            uint8_t             gpe_scom_reserved[OSD_GPE_SCOM_RESERVED_BYTES];
+        };
+
+    };
+    uint8_t total_reserved[OSD_TOTAL_SHARED_DATA_BYTES];
+} occhw_osd_t;
+
+// Fail to compile if ipc_shared_data exceeds the reserved space
+KERN_STATIC_ASSERT((sizeof(ipc_shared_data_t) <= OSD_IPC_RESERVED_BYTES));
+
+/// Hardcoded pointer for the location of the OCC shared data segment
+#define OSD_PTR ((occhw_osd_t*) OSD_ADDR)
+
+#endif /*__ASSEMBLER__*/
+
+#endif  /* __OCCHW_OSD_H__ */
diff --git a/src/lib/occlib/occhw_xir_dump.c b/src/lib/occlib/occhw_xir_dump.c
new file mode 100644
index 0000000..7ff2e4e
--- /dev/null
+++ b/src/lib/occlib/occhw_xir_dump.c
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/occhw_xir_dump.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_xir_dump.c
+/// \brief Implementation of the occhw_xir_dump function
+#include "kernel.h"
+#include "occhw_common.h"
+#include "occhw_xir_dump.h"
+
+int32_t occhw_xir_dump(uint32_t inst_id, occhw_xir_dump_t* xir_dump)
+{
+    int rc;
+    do
+    {
+        if(!xir_dump)
+        {
+            rc = OCCHW_XIR_INVALID_POINTER;
+            break;
+        }
+
+        if(inst_id > OCCHW_INST_ID_MAX_GPE)
+        {
+            rc = OCCHW_XIR_INVALID_GPE;
+            break;
+        }
+
+        //TODO: dump the XIR regs once the addresses are available
+        rc = 0;
+
+    }while(0);
+
+    return rc;
+}
diff --git a/src/lib/occlib/occhw_xir_dump.h b/src/lib/occlib/occhw_xir_dump.h
new file mode 100644
index 0000000..85e52ad
--- /dev/null
+++ b/src/lib/occlib/occhw_xir_dump.h
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/occlib/occhw_xir_dump.h $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_XIR_DUMP_H__
+#define __OCCHW_XIR_DUMP_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_xir_dump.h
+/// \brief header for the occhw_xir_dump function
+///
+
+#ifndef __ASSEMBLER__
+#include "stdint.h"
+
+/// Structure for dumping XIR data for a GPE
+typedef struct
+{
+    uint32_t    xsr;
+    uint32_t    sprg0;
+    uint32_t    edr;
+    uint32_t    ir;
+    uint32_t    iar;
+    uint32_t    sib_upper;
+    uint32_t    sib_lower;
+} occhw_xir_dump_t;
+
+///////////////////////////////////////////////////////////////////////////////
+/// Dump the XIR registers for a GPE engine
+///
+/// \param inst_id The instance ID of the target GPE.
+///
+/// \param xir_dump Pointer to a occhw_xir_dump_t structure.
+///
+/// Possible return codes are:
+///
+/// \retval 0 XIR registers were successfully dumped
+///
+/// \retval OCCHW_XIR_INVALID_GPE \a inst_id is not for a valid GPE instance.
+///
+/// \retval OCCHW_XIR_INVALID_POINTER \a xir_dump is NULL
+///
+int32_t occhw_xir_dump(uint32_t inst_id, occhw_xir_dump_t* xir_dump);
+
+#endif /*__ASSEMBLER__*/
+#endif /*__OCCHW_XIR_DUMP_H__*/
diff --git a/src/lib/pgas.h b/src/lib/pgas.h
deleted file mode 100755
index bdd3ba1..0000000
--- a/src/lib/pgas.h
+++ /dev/null
@@ -1,1153 +0,0 @@
-#ifndef __PGAS_H__
-#define __PGAS_H__
-
-#define __PGAS__
-
-// $Id: pgas.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pgas.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-// ** WARNING : This file is maintained as part of the OCC firmware.  Do **
-// ** not edit this file in the PMX area, the hardware procedure area,   **
-// ** or the PoreVe area as any changes will be lost.                    **
-
-/// \file pgas.h
-/// \brief Pore GAS
-///
-/// PGAS is documented in a seperate standalone document entitled <em> PGAS :
-/// PORE GAS (GNU Assembler) User's and Reference Manual </em>.
-///
-/// This file defines support macros for the GNU PORE assembler, and the PORE
-/// inline assembler and disassebler which follow the PGAS assembly syntax.
-/// If the compile swith PGAS_PPC is defined in the environment then pgas.h
-/// includes pgas_ppc.h which transforms a PowerPC assembler into an assembler
-/// for PORE.
-
-// These are the opcodes and mnemonics as defined by the PORE hardware
-// manual.  Many of them will change names slightly in PGAS.  
-
-#define PORE_OPCODE_NOP     0x0f
-#define PORE_OPCODE_WAIT    0x01
-#define PORE_OPCODE_TRAP    0x02
-#define PORE_OPCODE_HOOK    0x4f
-
-#define PORE_OPCODE_BRA     0x10
-#define PORE_OPCODE_BRAZ    0x12
-#define PORE_OPCODE_BRANZ   0x13
-#define PORE_OPCODE_BRAI    0x51
-#define PORE_OPCODE_BSR     0x14
-#define PORE_OPCODE_BRAD    0x1c
-#define PORE_OPCODE_BSRD    0x1d
-#define PORE_OPCODE_RET     0x15
-#define PORE_OPCODE_CMPBRA  0x56
-#define PORE_OPCODE_CMPNBRA 0x57
-#define PORE_OPCODE_CMPBSR  0x58
-#define PORE_OPCODE_LOOP    0x1f
-
-#define PORE_OPCODE_ANDI    0x60
-#define PORE_OPCODE_ORI     0x61
-#define PORE_OPCODE_XORI    0x62
-        
-#define PORE_OPCODE_AND     0x25
-#define PORE_OPCODE_OR      0x26
-#define PORE_OPCODE_XOR     0x27
-        
-#define PORE_OPCODE_ADD     0x23
-#define PORE_OPCODE_ADDI    0x24
-#define PORE_OPCODE_SUB     0x29
-#define PORE_OPCODE_SUBI    0x28
-#define PORE_OPCODE_NEG     0x2a
-
-#define PORE_OPCODE_COPY    0x2c
-#define PORE_OPCODE_ROL     0x2e
-
-#define PORE_OPCODE_LOAD20  0x30
-#define PORE_OPCODE_LOAD64  0x71
-#define PORE_OPCODE_SCR1RD  0x32
-#define PORE_OPCODE_SCR1RDA 0x73
-#define PORE_OPCODE_SCR2RD  0x36
-#define PORE_OPCODE_SCR2RDA 0x77
-#define PORE_OPCODE_WRI     0x78
-#define PORE_OPCODE_BS      0x74
-#define PORE_OPCODE_BC      0x75
-#define PORE_OPCODE_SCR1WR  0x39
-#define PORE_OPCODE_SCR2WR  0x3a
-#define PORE_OPCODE_SCAND   0x7c
-
-
-// These are the PGAS versions of the PORE opcodes used in the legacy PGAS_PPC
-// assembler and the current PORE inline assembler/disassembler.
-
-#define PGAS_OPCODE_NOP       PORE_OPCODE_NOP     
-#define PGAS_OPCODE_WAITS     PORE_OPCODE_WAIT    
-#define PGAS_OPCODE_TRAP      PORE_OPCODE_TRAP    
-#define PGAS_OPCODE_HOOKI     PORE_OPCODE_HOOK    
-
-#define PGAS_OPCODE_BRA       PORE_OPCODE_BRA     
-#define PGAS_OPCODE_BRAZ      PORE_OPCODE_BRAZ    
-#define PGAS_OPCODE_BRANZ     PORE_OPCODE_BRANZ   
-#define PGAS_OPCODE_BRAI      PORE_OPCODE_BRAI    
-#define PGAS_OPCODE_BSR       PORE_OPCODE_BSR 
-#define PGAS_OPCODE_BRAD      PORE_OPCODE_BRAD    
-#define PGAS_OPCODE_BSRD      PORE_OPCODE_BSRD    
-#define PGAS_OPCODE_RET       PORE_OPCODE_RET     
-#define PGAS_OPCODE_CMPIBRAEQ PORE_OPCODE_CMPBRA  
-#define PGAS_OPCODE_CMPIBRANE PORE_OPCODE_CMPNBRA 
-#define PGAS_OPCODE_CMPIBSREQ PORE_OPCODE_CMPBSR  
-#define PGAS_OPCODE_LOOP      PORE_OPCODE_LOOP    
-
-#define PGAS_OPCODE_ANDI      PORE_OPCODE_ANDI    
-#define PGAS_OPCODE_ORI       PORE_OPCODE_ORI     
-#define PGAS_OPCODE_XORI      PORE_OPCODE_XORI    
-
-#define PGAS_OPCODE_AND       PORE_OPCODE_AND     
-#define PGAS_OPCODE_OR        PORE_OPCODE_OR      
-#define PGAS_OPCODE_XOR       PORE_OPCODE_XOR     
-
-#define PGAS_OPCODE_ADD       PORE_OPCODE_ADD     
-#define PGAS_OPCODE_ADDS      PORE_OPCODE_ADDI    
-#define PGAS_OPCODE_SUB       PORE_OPCODE_SUB     
-#define PGAS_OPCODE_SUBS      PORE_OPCODE_SUBI    
-#define PGAS_OPCODE_NEG       PORE_OPCODE_NEG     
-
-#define PGAS_OPCODE_MR        PORE_OPCODE_COPY    
-#define PGAS_OPCODE_ROLS      PORE_OPCODE_ROL     
-
-#define PGAS_OPCODE_LS        PORE_OPCODE_LOAD20  
-#define PGAS_OPCODE_LI        PORE_OPCODE_LOAD64  
-#define PGAS_OPCODE_LD0       PORE_OPCODE_SCR1RD  /* Used by LD */
-#define PGAS_OPCODE_LD0ANDI   PORE_OPCODE_SCR1RDA /* Used by LDANDI */
-#define PGAS_OPCODE_LD1       PORE_OPCODE_SCR2RD  /* Used by LD */
-#define PGAS_OPCODE_LD1ANDI   PORE_OPCODE_SCR2RDA /* Used by LDANDI */
-#define PGAS_OPCODE_STI       PORE_OPCODE_WRI     
-#define PGAS_OPCODE_STD0      PORE_OPCODE_SCR1WR  /* Used by STD */
-#define PGAS_OPCODE_STD1      PORE_OPCODE_SCR2WR  /* Used by STD */
-#define PGAS_OPCODE_SCAND     PORE_OPCODE_SCAND   
-
-#ifdef IGNORE_HW274735
-
-// BSI and BCI are normally redacted due to HW274735. See also pgas.h
-
-#define PGAS_OPCODE_BSI       PORE_OPCODE_BS      
-#define PGAS_OPCODE_BCI       PORE_OPCODE_BC      
-
-#endif // IGNORE_HW274735
-
-// These are the programmer-visible register names as defined by the PORE
-// hardware manual.  All of these names (except the PC) appear differently in
-// the PGAS syntax, in some cases to reduce confusion, in other cases just to
-// have more traditional short mnemonics.
-
-#define PORE_REGISTER_PRV_BASE_ADDR0  0x0
-#define PORE_REGISTER_PRV_BASE_ADDR1  0x1
-#define PORE_REGISTER_OCI_BASE_ADDR0  0x2
-#define PORE_REGISTER_OCI_BASE_ADDR1  0x3
-#define PORE_REGISTER_SCRATCH0        0x4
-#define PORE_REGISTER_SCRATCH1        0x5
-#define PORE_REGISTER_SCRATCH2        0x6
-#define PORE_REGISTER_ERROR_MASK      0x7
-#define PORE_REGISTER_EXE_TRIGGER     0x9
-#define PORE_REGISTER_DATA0           0xa
-#define PORE_REGISTER_PC              0xe
-#define PORE_REGISTER_IBUF_ID         0xf
-
-
-// PgP IBUF_ID values
-
-#define PORE_ID_GPE0 0x00
-#define PORE_ID_GPE1 0x01
-#define PORE_ID_SLW  0x08
-#define PORE_ID_SBE  0x04
-
-
-// Condition Codes
-
-#define PORE_CC_UGT 0x8000
-#define PORE_CC_ULT 0x4000
-#define PORE_CC_SGT 0x2000
-#define PORE_CC_SLT 0x1000
-#define PORE_CC_C   0x0800
-#define PORE_CC_V   0x0400
-#define PORE_CC_N   0x0200
-#define PORE_CC_Z   0x0100
-
-
-// Memory Spaces
-
-#define PORE_SPACE_UNDEFINED 0xffff
-#define PORE_SPACE_OCI       0x8000
-#define PORE_SPACE_PNOR      0x800b
-#define PORE_SPACE_OTPROM    0x0001
-#define PORE_SPACE_SEEPROM   0x800c
-#define PORE_SPACE_PIBMEM    0x0008             
-
-
-#ifdef __ASSEMBLER__
-
-////////////////////////////////////////////////////////////////////////////
-// PGAS Base Assembler Support
-////////////////////////////////////////////////////////////////////////////    
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Condition Codes
-        //////////////////////////////////////////////////////////////////////
-
-        .set    CC_UGT, PORE_CC_UGT 
-        .set    CC_ULT, PORE_CC_ULT 
-        .set    CC_SGT, PORE_CC_SGT 
-        .set    CC_SLT, PORE_CC_SLT 
-        .set    CC_C,   PORE_CC_C   
-        .set    CC_V,   PORE_CC_V   
-        .set    CC_N,   PORE_CC_N   
-        .set    CC_Z,   PORE_CC_Z
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Utility Macros
-        //////////////////////////////////////////////////////////////////////
-
-        // 'Undefine' PowerPC mnemonics to trap programming errors
-
-        .macro  ..undefppc1, i
-        .ifnc   \i, ignore
-        .macro  \i, args:vararg
-        .error  "This is a PowerPC opcode - NOT a PGAS opcode or extended mnemonic"
-        .endm
-        .endif
-        .endm
-
-        .macro  .undefppc, i0, i1=ignore, i2=ignore, i3=ignore
-        ..undefppc1 \i0
-        ..undefppc1 \i1
-        ..undefppc1 \i2
-        ..undefppc1 \i3
-        .endm
-
-      
-        //////////////////////////////////////////////////////////////////////
-        // Argument Checking Macros
-        //////////////////////////////////////////////////////////////////////
-        //
-        // These macros remain in the final pgas.h file because 1) they are
-        // required for some PGAS pseudo-ops, and 2) to support robust
-        // assembler macro definitions. 
-
-         // Check an unsigned immediate for size
-
-        .macro  ..checku, x:req, bits:req, err="Unsigned value too large"
-
-        .if     (((\bits) <= 0) || ((\bits) > 63))
-        .error  "The number of bits must be in the range 0 < bits < 64"
-        .endif
-
-        .iflt   (\x)
-        .error  "An unsigned value is required here"
-        .endif
-        
-        .ifgt   ((\x) - (0xffffffffffffffff >> (64 - (\bits))))
-        .error  "\err"
-        .endif
-
-        .endm
-
-        // Check unsigned 16/22-bit immediates for size
-        //
-        // In general, PGAS can check immediate values for size restrictions,
-        // but unfortunately is not able to check address offset immediates for
-        // range. 
-
-        .macro  ..check_u16, u16
-        ..checku (\u16), 16, "Unsigned immediate is larger than 16 bits"
-        .endm
-
-        .macro  ..check_u24, u24
-        ..checku (\u24), 24, "Unsigned immediate is larger than 24 bits"
-        .endm
-
-        // Check a 16/20/22-bit signed immediate for size
-
-        .macro  ..check_s16, s16
-        .iflt   \s16
-        .iflt   \s16 + 0x8000
-        .error  "Immediate value too small for a signed 16-bit field"
-        .endif
-        .else
-        .ifgt   \s16 - 0x7fff
-        .error  "Immediate value too large for a signed 16-bit field"
-        .endif
-        .endif
-        .endm
-
-        .macro  ..check_s20, s20
-        .iflt   \s20
-        .iflt   \s20 + 0x80000
-        .error  "Immediate value too small for a signed 20-bit field"
-        .endif
-        .else
-        .ifgt   \s20 - 0x7ffff
-        .error  "Immediate value too large for a signed 20-bit field"
-        .endif
-        .endif
-        .endm
-
-        .macro  ..check_s22, s22
-        .iflt   \s22
-        .iflt   \s22 + 0x200000
-        .error  "Immediate value too small for a signed 22-bit field"
-        .endif
-        .else
-        .ifgt   \s22 - 0x1fffff
-        .error  "Immediate value too large for a signed 22-bit field"
-        .endif
-        .endif
-        .endm
-
-        // Check a putative SCOM address for bits 0 and 8:11 == 0.
-
-        .macro  ..check_scom, address
-        .if     ((\address) & 0x80f00000)
-        .error  "Valid SCOM addresses must have bits 0 and 8:11 equal to 0."
-        .endif
-        .endm
-
-        // A register required to be D0
-
-        .macro  ..d0, reg
-        .if     (\reg != D0)
-        .error  "Data register D0 is required here"
-        .endif
-        .endm
-
-        // A register pair required to be D0, D1 in order
-
-        .macro  ..d0d1, reg1, reg2
-        .if     (((\reg1) != D0) && ((\reg2) != D1))
-        .error  "Register-Register ALU operations are only defined on the source pair D0, D1"
-        .endif
-        .endm
-
-        // A register pair required to be D0, D1 in any order
-        .macro  ..dxdy, reg1, reg2, err="Expecting D0, D1 in either order"
-        .if     !((((\reg1) == D0) && ((\reg2) == D1)) || \
-                  (((\reg1) == D1) && ((\reg2) == D0)))
-        .error "\err"
-        .endif
-        .endm
-
-        // A register pair required to be A0, A1 in any order
-        .macro  ..axay, reg1, reg2, err="Expecting A0, A1 in either order"
-        .if     !((((\reg1) == A0) && ((\reg2) == A1)) || \
-                  (((\reg1) == A1) && ((\reg2) == A0)))
-        .error "\err"
-        .endif
-        .endm
-
-        // A register pair required to be the same register
-
-        .macro  ..same, dest, src
-        .if     ((\dest) != (\src))
-        .error  "PGAS requires the src and dest register of ADDS/SUBS to be explicit and identical"
-        .endif
-        .endm
-        
-        // A "Data" register    
-
-        .macro  ..data, reg:req, err="Expecting a 'Data' register"
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // An "Address" register
-
-        .macro  ..address, reg:req, err=:"Expecting an 'Address' register"
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // A "Pervasive Chiplet ID" register
-
-        .macro  ..pervasive_chiplet_id, reg:req, err="Expecting a 'Pervasive Chiplet ID' register"
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // A "Branch Compare Data" register
-
-        .macro  ..branch_compare_data, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1) 
-        .if     (\reg != CTR)
-        .error  "Expecting a 'Branch Compare Data' register"
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LS Destination" register; Also the set for ADDS/SUBS
-
-        .macro  ..ls_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .error "Expecting an 'LS Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LI Destination" register
-
-        .macro  ..li_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != CTR)
-        .error "Expecting an 'LI Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LIA Destination" register 
-
-        .macro  ..lia_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != TBAR)
-        .error "Expecting an 'LIA Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "MR Source" register
-
-        .macro  ..mr_source, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .if     (\reg != PC)
-        .if     (\reg != ETR)
-        .if     (\reg != SPRG0)
-        .if     (\reg != IFR)
-        .if     (\reg != EMR)
-        .error  "Expecting an 'MR Source' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "MR Destination" register
-
-        .macro  ..mr_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .if     (\reg != PC)
-        .if     (\reg != ETR)
-        .if     (\reg != SPRG0)
-        .if     (\reg != EMR)
-        .error "Expecting an 'MR Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // PORE address spaces
-        //////////////////////////////////////////////////////////////////////
-
-        // The ..set_address_space pseudo-op defines the default address
-        // space. It must be defined in order to use BRAA, BRAIA, BSR and
-        // CMPIBSR.  Pseudo-ops are provided to set the default space of the
-        // program.  Note that code assembled for PNOR will also work in the
-        // OCI space in the Sleep/Winkle engine.
-
-        .macro  ..set_default_space, s
-        ..check_u16 (\s)
-        .set    _PGAS_DEFAULT_SPACE, (\s)
-        .endm
-
-        .macro  ..check_default_space
-        .if     (_PGAS_DEFAULT_SPACE == PORE_SPACE_UNDEFINED)
-        .error  "The PGAS default address space has not been defined"
-        .endif
-        .endm   
-
-        ..set_default_space PORE_SPACE_UNDEFINED
-
-        .macro  .oci
-        ..set_default_space PORE_SPACE_OCI
-        .endm
-
-        .macro  .pnor
-        ..set_default_space PORE_SPACE_PNOR
-        .endm
-
-        .macro  .seeprom
-        ..set_default_space PORE_SPACE_SEEPROM
-        .endm
-
-        .macro  .otprom
-        ..set_default_space PORE_SPACE_OTPROM
-        .endm
-
-        .macro  .pibmem
-        ..set_default_space PORE_SPACE_PIBMEM
-#ifndef PGAS_PPC
-        .pibmem_port (PORE_SPACE_PIBMEM & 0xf)
-#else
-        // NB: PGAS_PPC does not support relocatable PIBMEM addressing
-#endif
-        .endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Address-Generation Pseudo Ops
-        //////////////////////////////////////////////////////////////////////
-
-        // .QUADA, .QUADIA
-
-        .macro  .quada, offset:req
-        ..check_default_space
-        .long   _PGAS_DEFAULT_SPACE
-        .long   (\offset)
-        .endm
-        
-        .macro  .quadia, space:req, offset:req
-        ..check_u16 (\space)
-        .long   (\space)
-        .long   (\offset)
-        .endm
-
-        //////////////////////////////////////////////////////////////////////
-        // Bug workarounds
-        //////////////////////////////////////////////////////////////////////
-
-#ifndef IGNORE_HW274735
-
-        // HW274735 documents that BC and BS are broken for the PORE-GPE0/1
-        // pair. This bug is unfixed in POWER8, and by default we require BSI
-        // and BCI to be implemented as macros on all engines. For
-        // compatability we continue to require that dx == D0.
-
-        .macro  bsi, dx:req, offset:req, base:req, imm:req
-        ..d0    (\dx)
-        ld      D0, (\offset), (\base)
-        ori     D0, D0, (\imm)
-        std     D0, (\offset), (\base)
-        .endm
-
-        .macro  bci, dx:req, offset:req, base:req, imm:req
-        ..d0    (\dx)
-        ldandi  D0, (\offset), (\base), ~(\imm)
-        std     D0, (\offset), (\base)
-        .endm
-
-#endif // IGNORE_HW274735
-
-        //////////////////////////////////////////////////////////////////////
-        // "A"- and "IA"-form Instructions
-        //////////////////////////////////////////////////////////////////////
-
-        // BRAA (Branch Address) is a 'long branch' to an address in the
-        // default memory space.
-
-        .macro  braa, offset:req
-        braia   _PGAS_DEFAULT_SPACE, (\offset)
-        .endm
-
-        // LA (Load Address) loads the full address of an address in the
-        // default memory space.
-
-        .macro  la, dest:req, offset:req
-        lia     (\dest), _PGAS_DEFAULT_SPACE, (\offset)
-        .endm
-
-        // STA (Store Address) stores the full address of an address in the
-        // default memory space.
-
-        .macro  sta, mem_offset:req, base:req, addr_offset:req
-        stia    (\mem_offset), (\base), _PGAS_DEFAULT_SPACE, (\addr_offset)
-        .endm
-
-        // BSRIA is a subroutine branch into another memory space.  This has to
-        // be emulated by a local subroutine branch and a BRAIA.
-        
-        .macro  bsria, space:req, offset:req
-        bsr     27742f
-        bra     27743f
-27742:
-        braia   (\space), (\offset)
-27743:  
-        .endm             
-
-
-////////////////////////////////////////////////////////////////////////////
-// Extended Mnemonics, Macros and Special Cases
-////////////////////////////////////////////////////////////////////////////
-
-        //////////////////////////////////////////////////////////////////////
-        // TFB<c> - Test flags and branch conditionally
-        //////////////////////////////////////////////////////////////////////'
-        
-        .macro  ..tfb, dest, target, flags
-        ..data  (\dest)
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), (\flags)
-        branz   (\dest), (\target)
-        .endm   
-
-        .macro  ..tfbn dest, target, flags
-        ..data  (\dest)
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), (\flags)
-        braz    (\dest), (\target)
-        .endm   
-
-        .macro  tfbcs, dest:req, target:req
-        ..tfb    (\dest), (\target), CC_C
-        .endm
-
-        .macro  tfbcc, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_C
-        .endm
-
-        .macro  tfbvs, dest:req, target:req
-        ..tfb    (\dest), (\target), CC_V
-        .endm
-
-        .macro  tfbvc, dest:req, target:req
-        ..tfbn   (\dest), (\target), CC_V
-        .endm
-
-        .macro  tfbns, dest:req, target:req
-        ..tfb    (\dest), (\target), CC_N
-        .endm
-
-        .macro  tfbnc, dest:req, target:req
-        ..tfbn   (\dest), (\target), CC_N
-        .endm
-
-        .macro  tfbeq, dest:req, target:req
-        ..tfb   (\dest), (\target), CC_Z
-        .endm
-
-        .macro  tfbne, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_Z
-        .endm
-
-        .macro  tfbult, dest:req, target:req
-        ..tfb   (\dest), (\target), CC_ULT
-        .endm
-
-        .macro  tfbule, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_UGT
-        .endm
-
-        .macro  tfbuge, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_ULT
-        .endm
-
-        .macro  tfbugt, dest:req, target:req
-        ..tfb   (\dest), (\target), CC_UGT
-        .endm
-
-        .macro  tfbslt, dest:req, target:req
-        ..tfb   (\dest), (\target), CC_SLT
-        .endm
-
-        .macro  tfbsle, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_SGT
-        .endm
-
-        .macro  tfbsge, dest:req, target:req
-        ..tfbn  (\dest), (\target), CC_SLT
-        .endm
-
-        .macro  tfbsgt, dest:req, target:req
-        ..tfb   (\dest), (\target), CC_SGT
-        .endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // TEB[N]<eng> - Test Engine and branch if [not] engine.
-        //////////////////////////////////////////////////////////////////////
-        //
-        // All but GPE0 use a 1-hot code.
-        
-        .macro  tebgpe0, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), 0xf
-        braz    (\dest), (\target)
-        .endm   
-
-        .macro  tebgpe1, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_GPE1
-        branz   (\dest), (\target)
-        .endm   
-
-        .macro  tebslw, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_SLW
-        branz   (\dest), (\target)
-        .endm   
-
-        .macro  tebsbe, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_SBE
-        branz   (\dest), (\target)
-        .endm   
-
-
-        .macro  tebngpe0, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), 0xf
-        branz   (\dest), (\target)
-        .endm   
-
-        .macro  tebngpe1, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_GPE1
-        braz    (\dest), (\target)
-        .endm   
-
-        .macro  tebnslw, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_SLW
-        braz    (\dest), (\target)
-        .endm   
-
-        .macro  tebnsbe, dest:req, target:req
-        mr      (\dest), IFR
-        andi    (\dest), (\dest), PORE_ID_SBE
-        braz    (\dest), (\target)
-        .endm   
-
-
-        //////////////////////////////////////////////////////////////////////
-        // EXTRPRC   - Extract and right-justify the PIB/PCB return code
-        // TPRCB[N]Z - Test PIB return code and branch if [not] zero
-        // TPRCBGT   - Test PIB return code and branch if greater-than
-        // TPRCBLE   - Test PIB return code and branch if less-then or equal
-        //////////////////////////////////////////////////////////////////////
-        //
-        // To support cases where PORE code expects or must explicitly handle
-        // non-0 PIB return codes, the PIB return code and parity indication
-        // are stored in bits 32 (parity) and 33-35 (return code) of the IFR.
-        // These macros extract the four PIB/PCB status bits from the IFR and
-        // right-justifies them into the data register provided. For EXTRPRC
-        // that is the total function of the macro. The TPRCB[N]Z macros
-        // provide a simple non-destructive test and branch for zero (success)
-        // and non-zero (potential problem) codes after the extraction.
-        //
-        // In complex error handling scenarios one would typically compare the
-        // PIB return code against an upper-bound, e.g., the offline response
-        // (0x2), and then take further action. If the parity error bit is set
-        // then this would produce an aggregate "return code" higher than any
-        // that one would typically want to ignore. The TPRCBGT/TPRCBLE macros
-        // provide this function; however the test destroys the extracted
-        // return code so that if further analysis is required the code will
-        // need to be a extracted again.
-        //////////////////////////////////////////////////////////////////////
-
-        .macro  extrprc, dest:req
-        ..data  (\dest)
-        mr      (\dest), IFR
-        extrdi  (\dest), (\dest), 4, 32             
-        .endm
-
-        .macro  tprcbz, dest:req, target:req
-        extrprc (\dest)
-        braz    (\dest), (\target)
-        .endm
-        
-        .macro  tprcbnz, dest:req, target:req
-        extrprc (\dest)
-        branz   (\dest), (\target)
-        .endm
-        
-        .macro  tprcbgt, dest:req, target:req, bound:req
-        extrprc (\dest)
-        subs    (\dest), (\dest), (\bound)
-        tfbugt  (\dest), (\target)
-        .endm
-        
-        .macro  tprcble, dest:req, target:req, bound:req
-        extrprc (\dest)
-        subs    (\dest), (\dest), (\bound)
-        tfbule  (\dest), (\target)
-        .endm
-        
-        //////////////////////////////////////////////////////////////////////
-        // LPCS - Load Pervasive Chiplet from Scom address
-        //////////////////////////////////////////////////////////////////////
-
-        .macro  lpcs, dest:req, scom:req
-        ..pervasive_chiplet_id (\dest)
-        ..check_scom (\scom)
-        ls      (\dest), (((\scom) >> 24) & 0x7f)
-        .endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Shift/Mask extended mnemonics
-        //////////////////////////////////////////////////////////////////////
-
-        // All of the 'dot-dot' macros assume that error and identity
-        // checking has been done on the arguments already.
-
-        // The initial register-register rotate.  If the incoming shift amount
-        // is 0 then the instruction generated is a simple MR.
-
-        .macro  ..rotlrr, ra, rs, sh
-
-        .if     (\sh) >= 32
-                rols    (\ra), (\rs), 32
-                ..rotlr  (\ra), ((\sh) - 32)
-        .elseif (\sh) >= 16
-                rols    (\ra), (\rs), 16
-                ..rotlr  (\ra), ((\sh) - 16)
-        .elseif (\sh) >= 8
-                rols    (\ra), (\rs), 8
-                ..rotlr  (\ra), ((\sh) - 8)
-        .elseif (\sh) >= 4
-                rols    (\ra), (\rs), 4
-                ..rotlr  (\ra), ((\sh) - 4)
-        .elseif (\sh) >= 1
-                rols    (\ra), (\rs), 1
-                ..rotlr  (\ra), ((\sh) - 1)
-        .else
-                mr      (\ra), (\rs)
-        .endif
-
-        .endm
-
-
-        // Subsequent rotation of the same register.  The SH should never be 0
-        // here. 
-
-        .macro  ..rotlr, ra, sh
-
-        .if     (\sh) >= 32
-                rols    (\ra), (\ra), 32
-                ..rotlr  (\ra), ((\sh) - 32)
-        .elseif (\sh) >= 16
-                rols    (\ra), (\ra), 16
-                ..rotlr  (\ra), ((\sh) - 16)
-        .elseif (\sh) >= 8
-                rols    (\ra), (\ra), 8
-                ..rotlr  (\ra), ((\sh) - 8)
-        .elseif (\sh) >= 4
-                rols    (\ra), (\ra), 4
-                ..rotlr  (\ra), ((\sh) - 4)
-        .elseif (\sh) >= 1
-                rols    (\ra), (\ra), 1
-                ..rotlr  (\ra), ((\sh) - 1)
-
-        .endif
-
-        .endm
-
-
-        // RLDINM RA, RS, SH, MB, ME
-        //
-        // Defined as if there were an equivalent PowerPC instruction. The
-        // 'word' forms of the PowerPC instructions and extended mnemonics are
-        // undefined in order to catch programming typos.
-
-        .undefppc       rlwinm, extrwi, rotlwi, rotrwi
-        .undefppc       slwi, srwi
-
-        .macro  rldinm, ra:req, rs:req, sh:req, mb:req, me:req
-
-        .if     ((\sh) < 0) || ((\sh) > 63)
-                .error  "SH must be in the range 0..63"
-        .endif
-        .if     ((\mb) < 0) || ((\mb) > 63)
-                .error  "MB must be in the range 0..63"
-        .endif
-        .if     ((\me) < 0) || ((\me) > 63)
-                .error  "ME must be in the range 0..63"
-        .endif
-        
-        .if     (((\mb) == 0) && ((\me) == 63) || ((\me) == ((\mb) - 1)))
-
-                // The mask is effectively 0..63, i.e., no mask. This is a
-                // simple rotate.
-                
-                ..rotlrr (\ra), (\rs), (\sh)
-        
-        .else
-        
-                // We need a mask step.  However if SH == 0 and RA == RS we can
-                // bypass the rotate step.
-                
-                .if     ((\sh) != 0) || ((\ra) != (\rs))
-                        ..rotlrr (\ra), (\rs), (\sh)
-                .endif
-                .if     ((\mb) <= (\me))
-
-                        // This is a straightforward masking operation with a
-                        // single mask.
-                
-                        andi    (\ra), (\ra), ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - (\me))))
-                .else
-                
-                        // This is a wrapped mask.  
-                        // It is created as 2 masks OR-ed together - 0-ME and MB-63
-                
-                        andi    (\ra), (\ra), (((0xffffffffffffffff >> 0) & (0xffffffffffffffff << (63 - (\me)))) | ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - 63))))
-                .endif
-        
-        .endif
-        
-        .endm           
-
-        // RLDINM Extended Mnemonics
-        //
-        // Defined as if they were equivalent to PowerPC 32-bit extended
-        // mnemonics
-
-        .macro  extldi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "EXTLDI requires N > 0"
-        .endif
-         rldinm (\ra), (\rs), (\b), 0, ((\n) - 1)
-        .endm
-
-        .macro  extrdi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "EXTRDI requires N > 0"
-        .endif
-        rldinm  (\ra), (\rs), (((\b) + (\n)) % 64), (64 - (\n)), 63
-        .endm
-
-        .macro  rotldi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (\n), 0, 63
-        .endm
-
-
-        .macro  rotrdi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (64 - (\n)), 0, 63
-        .endm
-
-
-        .macro  sldi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (\n), 0, (63 - (\n))
-        .endm
-        
-
-        .macro  srdi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (64 - (\n)), (\n), 63
-        .endm
-        
-
-        // RLDIMI RA, RS, SH, MB, ME
-        //
-        // Defined as if there were an equivalent PowerPC instruction. The
-        // 'word' forms of the PowerPC instructions and extended mnemonics are
-        // undefined in order to catch programming typos.
-        //
-        // Note that unlike the PowerPC instructions, here RLDIMI must destroy
-        // RS by masking and shifting it, and RA and RS may not be the same
-        // register. 
-
-        .undefppc       rlwimi, inslwi, insrwi
-
-        .macro  rldimi, ra:req, rs:req, sh:req, mb:req, me:req
-
-        ..dxdy  (\ra), (\rs)
-
-        // SH error checks are done by rldinm
-                
-        .if     (((\mb) == 0) && ((\me) == 63) || ((\me) == ((\mb) - 1)))
-
-                // The mask is effectively 0..63, i.e., no mask. This is a
-                // simple rotate of RS into RA
-                
-                rotldi  (\ra), (\rs), (\sh)
-        
-        .else
-
-                // Rotate RS and AND with mask
-
-                rldinm  (\rs), (\rs), (\sh), (\mb), (\me)
-
-                // Mask out the significant bits of RS, clear that section of
-                // RA, and logical OR RS into RA
-        
-                .if     ((\mb) <= (\me))
-
-                        // This is a straightforward masking operation with a
-                        // single mask.
-                
-                        andi    (\ra), (\ra), \
-                                 (~((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - (\me)))))
-                .else
-                
-                        // This is a wrapped mask.  
-                        // It is created as 2 masks OR-ed together - 0-ME and MB-63
-                
-                        andi    (\ra), (\ra), \
-                                (~(((0xffffffffffffffff >> 0) & (0xffffffffffffffff << (63 - (\me)))) | \
-                                  ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - 63)))))
-                .endif
-
-                or      (\ra), D0, D1
-        
-        .endif
-
-        .endm           
-
-        // RLDIMI Extended Mnemonics
-        //
-        // Defined as if they were equivalent to PowerPC 32-bit extended
-        // mnemonics
-
-        .macro  insldi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "INSLDI requires N > 0"
-        .endif
-        rldimi   (\ra), (\rs), (64 - (\b)), (\b), ((\b) + (\n) - 1)
-        .endm
-
-        .macro  insrdi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "INSRDI requires N > 0"
-        .endif
-        rldimi  (\ra), (\rs), (64 - (\b) - (\n)), (\b), ((\b) + (\n) - 1)
-        .endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // .HOOK
-        //////////////////////////////////////////////////////////////////////
-
-        // The PoreVe (PORE Virtual Environment) is a PORE simulation
-        // environment that allows the programmer to embed C/C++ code into the
-        // PORE assembler source code, and arranges for the C/C++ code to be
-        // executed in-line with the PORE assembly code.  Instances of the
-        // .hook macro are inserted into the assembler input by the
-        // hook_extractor script, to mark the locations where hooks are
-        // present.  The hook reference is a string that combines the source
-        // file name with an index number to uniquely identify the hook.
-        //
-        //     .hook <file name>_<sequence number>
-        //
-        // The .hook macro marks the location of each hook in the relocatable
-        // binaries with special symbols.  The symbol name includes the hook
-        // reference, which is used to locate the hook in the HookManager
-        // symbol table. Because hooks can be defined in macros, a hook that
-        // appears once in a source file may appear multiple times in the
-        // final binary.  For this reason each hook must also be tagged with a
-        // unique index number to avoid symbol name collisions.  The
-        // complexity of the .hook macro is due to the necessity to decode a
-        // dynamic symbol value (_PGAS_HOOK_INDEX) into its binary string form
-        // to create the unique symbol name.  The final hook symbol has the
-        // form:
-        //
-        // __hook__<unique>_<reference>
-        //
-        // where <unique> is a binary string. It is then straightforward to
-        // locate these symbols in the 'nm' output of the final link and
-        // create a map of final addresses to the hook routine to call (the
-        // <reference>) before executing the instruction at that address.
-        //
-        // Note: The maximum nesting depth of the recursive ..hook_helper
-        // macro is log2(index), and the assembler supports nesting of at
-        // least 32 which is much more than sufficient.
-
-        .set    _PGAS_HOOK_INDEX, 0
-
-        .macro  .hook, reference:req
-        .set    _PGAS_HOOK_INDEX, (_PGAS_HOOK_INDEX + 1)
-        ..hook_helper _PGAS_HOOK_INDEX, "", \reference
-        .endm
-
-        .macro  ..hook_helper, index, unique, reference
-        .ifeq   \index
-        __hook__\unique\()_\reference\():       
-        .elseif (\index % 2)
-        ..hook_helper (\index / 2), 1\unique, \reference
-        .else
-        ..hook_helper (\index / 2), 0\unique, \reference
-        .endif
-        .endm
-
-
-////////////////////////////////////////////////////////////////////////////
-// Help for Conversion from Old to New PGAS syntax
-////////////////////////////////////////////////////////////////////////////
-
-        .macro  loadp, arg:vararg
-        .error  "PGAS now implements 'lpcs' rather then 'loadp'"
-        .endm
-
-        .macro  loadx, arg:vararg
-        .error  "PGAS now implements 'la' rather than 'loadx'"
-        .endm
-
-#endif  // __ASSEMBLER__
-                    
-#ifdef PGAS_PPC
-#include "pgas_ppc.h"
-#endif
-
-#endif // __PGAS_H__
diff --git a/src/lib/pgas_ppc.h b/src/lib/pgas_ppc.h
deleted file mode 100755
index 6771e4b..0000000
--- a/src/lib/pgas_ppc.h
+++ /dev/null
@@ -1,529 +0,0 @@
-#ifndef __PGAS_PPC_H__
-#define __PGAS_PPC_H__
-
-// $Id: pgas_ppc.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pgas_ppc.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-// ** WARNING : This file is maintained as part of the OCC firmware.  Do **
-// ** not edit this file in the PMX area, the hardware procedure area,   **
-// ** or the PoreVe area as any changes will be lost.                    **
-
-/// \file pgas_ppc.h
-/// \brief Legacy PGAS assembler implemented as PowerPC assembler macros.
-///
-/// PGAS is documented in a seperate standalone document entitled <em> PGAS :
-/// PORE GAS (GNU Assembler) User's and Reference Manual </em>.
-///
-/// This file contains the legacy PGAS assembler, which was first implemented
-/// as this set of assembler macros for the PowerPC assembler.  This file is
-/// included into pgas.h if the compile switch PGAS_PPC is defined in the
-/// compile environment.
-
-#ifdef __ASSEMBLER__
-
-////////////////////////////////////////////////////////////////////////////
-// PGAS Base Assembler
-////////////////////////////////////////////////////////////////////////////    
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Symbolic Register Mnemonics
-        //////////////////////////////////////////////////////////////////////
-        //
-        // PGAS uses gas symbols for register mnemonics so that they will
-        // appear as-is in assembler listings, but we can still do arithmetic
-        // on the mnemonics in the PGAS macros.
-
-        .set    P0,    PORE_REGISTER_PRV_BASE_ADDR0 
-        .set    P1,    PORE_REGISTER_PRV_BASE_ADDR1 
-        .set    A0,    PORE_REGISTER_OCI_BASE_ADDR0 
-        .set    A1,    PORE_REGISTER_OCI_BASE_ADDR1 
-        .set    CTR,   PORE_REGISTER_SCRATCH0  
-        .set    D0,    PORE_REGISTER_SCRATCH1       
-        .set    D1,    PORE_REGISTER_SCRATCH2
-        .set    EMR,   PORE_REGISTER_ERROR_MASK
-        .set    ETR,   PORE_REGISTER_EXE_TRIGGER
-        .set    SPRG0, PORE_REGISTER_DATA0
-        .set    PC,    PORE_REGISTER_PC
-        .set    IFR,   PORE_REGISTER_IBUF_ID
-
-      
-        //////////////////////////////////////////////////////////////////////
-        // Core Instruction Set
-        //////////////////////////////////////////////////////////////////////
-
-        // The final construction of an instruction word.  The opcode is a
-        // 7-bit value and the operand is always a 24-bit value. Note that the
-        // parity bit is always 0.
-
-        .macro  ..instruction, opcode, operand
-        .long   (\opcode << 25) | (\operand)
-        .endm
-
-        // NOP, TRAP, RET
-
-        .macro  nop
-        ..instruction PGAS_OPCODE_NOP, 0
-        .endm
-
-        .macro  trap
-        ..instruction PGAS_OPCODE_TRAP, 0
-        .endm
-
-        .macro  ret
-        ..instruction PGAS_OPCODE_RET, 0
-        .endm
-
-        // WAITS, HALT, HOOKI
-
-        .macro  waits, u24:req
-        ..check_u24 (\u24)
-        .if     ((\u24) == 0)
-        .error "PGAS does not allow WAITS 0; Use HALT if the intention is to halt"
-        .endif
-        ..instruction PGAS_OPCODE_WAITS, (\u24)
-        .endm
-
-        .macro  halt
-        ..instruction PGAS_OPCODE_WAITS, 0
-        .endm
-
-        .macro  hooki, u24:req, imm:req
-        ..check_u24     (\u24)
-        ..instruction PGAS_OPCODE_HOOKI, (\u24) 
-        .quad   (\imm)  
-        .endm
-
-        .macro  wait, args:vararg
-        .error "PGAS implements the 'waits' mnemonic instead of PORE 'wait'"
-        .endm
-
-        .macro  hook, args:vararg
-        .error "PGAS implements the 'hooki' mnemonic instead of PORE 'hook'"
-        .endm
-
-        // BRA, LOOP
-        //
-        // Note that all branch offsets in PORE are WORD offsets, so the byte
-        // offsets computed by the underlying assembler need to be divided by
-        // 4. Unfortunately PGAS is not able to check whether the offsets fit
-        // in the allowed space.
-
-        .macro  ..bra, opcode, target
-        ..instruction \opcode, ((((\target) - $) / 4) & 0xffffff)
-        .endm
-
-        .macro  bra, target:req
-        ..bra   PGAS_OPCODE_BRA, (\target)
-        .endm
-
-        .macro  loop, target:req
-        ..bra   PGAS_OPCODE_LOOP, (\target)
-        .endm
-
-        // BRAZ, BRANZ
-
-        .macro  ..brac, opcode, src, target
-        ..branch_compare_data (\src)
-        ..instruction \opcode, ((\src << 20) | ((((\target) - $) / 4) & 0xfffff))
-        .endm
-
-        .macro  braz, src:req, target:req
-        ..brac PGAS_OPCODE_BRAZ, (\src), (\target)
-        .endm
-
-        .macro  branz, src:req, target:req
-        ..brac PGAS_OPCODE_BRANZ, (\src), (\target)
-        .endm
-
-        // CMPIBRAEQ, CMPIBRANE
-
-        .macro  ..cmpibra, opcode, src, target, imm
-        ..d0    (\src)
-        ..instruction \opcode, ((((\target) - $) / 4) & 0xffffff)
-        .quad   (\imm)
-        .endm
-
-        .macro  cmpibraeq, src:req, target:req, imm:req
-        ..cmpibra PGAS_OPCODE_CMPIBRAEQ, (\src), (\target), (\imm)
-        .endm
-
-        .macro  cmpibrane, src:req, target:req, imm:req
-        ..cmpibra  PGAS_OPCODE_CMPIBRANE, (\src), (\target), (\imm)
-        .endm
-
-        .macro  cmpbra, args:vararg
-        .error "PGAS implements the 'cmpibraeq' mnemonic instead of PORE 'cmpbra'"
-        .endm
-
-        .macro  cmpnbra, args:vararg
-        .error "PGAS implements the 'cmpibrane' mnemonic instead of PORE 'cmpnbra'"
-        .endm
-
-        // BRAD, BSRD
-
-        .macro  ..brad, opcode, src
-        ..data  (\src)
-        ..instruction \opcode, ((\src) << 20)
-        .endm   
-
-        .macro  brad, src:req
-        ..brad  PGAS_OPCODE_BRAD, (\src)
-        .endm
-
-        .macro  bsrd, src:req
-        ..brad  PGAS_OPCODE_BSRD, (\src)
-        .endm
-
-        // ANDI, ORI, XORI
-        
-        .macro  ..ilogic, opcode, dest, src, imm
-        ..data  (\dest)
-        ..data  (\src)
-        ..instruction \opcode, (((\dest) << 20) | ((\src) << 16))
-        .quad   \imm
-        .endm
-
-        .macro  andi, dest:req, src:req, imm:req
-        ..ilogic PGAS_OPCODE_ANDI, (\dest), (\src), (\imm)
-        .endm
-
-        .macro  ori, dest:req, src:req, imm:req
-        ..ilogic PGAS_OPCODE_ORI, (\dest), (\src), (\imm)
-        .endm
-
-        .macro  xori, dest:req, src:req, imm:req
-        ..ilogic PGAS_OPCODE_XORI, (\dest), (\src), (\imm)
-        .endm
-
-        // AND, OR, XOR, ADD, SUB
-
-        .macro  ..alurr, opcode, dest, src1, src2
-        ..data  (\dest)
-        ..d0d1  (\src1), (\src2)
-        ..instruction \opcode, ((\dest) << 20)
-        .endm
-
-        .macro  and, dest:req, src1:req, src2:req
-        ..alurr PGAS_OPCODE_AND, (\dest), (\src1), (\src2)
-        .endm
-
-        .macro  or, dest:req, src1:req, src2:req
-        ..alurr PGAS_OPCODE_OR, (\dest), (\src1), (\src2)
-        .endm
-
-        .macro  xor, dest:req, src1:req, src2:req
-        ..alurr PGAS_OPCODE_XOR, (\dest), (\src1), (\src2)
-        .endm
-
-        .macro  add, dest:req, src1:req, src2:req
-        ..alurr PGAS_OPCODE_ADD, (\dest), (\src1), (\src2)
-        .endm
-
-        .macro  sub, dest:req, src1:req, src2:req
-        ..alurr PGAS_OPCODE_SUB, (\dest), (\src1), (\src2)
-        .endm
-
-        // ADDS, SUBS
-
-        .macro  ..inc, opcode, dest, src, short
-        ..check_s16 (\short)
-        ..ls_destination (\dest)
-        ..same  (\dest), (\src)
-        ..instruction (\opcode), (((\dest) << 20) | ((\short) & 0xffff))
-        .endm
-        
-        .macro  adds, dest:req, src:req, short:req
-        ..inc   PGAS_OPCODE_ADDS, (\dest), (\src), (\short)
-        .endm
-
-        .macro  subs, dest:req, src:req, short:req
-        ..inc   PGAS_OPCODE_SUBS, (\dest), (\src), (\short)
-        .endm
-
-        .macro  addi, args:vararg
-        .error "PGAS implements the 'adds' mnemonic instead of PORE 'addi'"
-        .endm
-
-        .macro  subi, args:vararg
-        .error "PGAS implements the 'subs' mnemonic instead of PORE 'subi'"
-        .endm
-
-        // NEG
-        
-        .macro  neg, dest:req, src:req
-        ..data  (\dest)
-        ..data  (\src)
-        ..instruction PGAS_OPCODE_NEG, (((\dest) << 20) | ((\src) << 16))
-        .endm           
-             
-        // MR
-
-        .macro  mr, dest:req, src:req
-        ..mr_destination (\dest)
-        ..mr_source (\src)
-        ..instruction PGAS_OPCODE_MR, (((\dest) << 20) | ((\src) << 16))
-        .endm
-
-        .macro  copy, args:vararg
-        .error  "PGAS implents the 'mr' mnemonic instead of PORE 'copy'"
-        .endm
-
-        // ROLS
-
-        .macro  rols, dest:req, src:req, short:req
-        ..data  (\dest)
-        ..data  (\src)
-        .if     ((\short) != 1)
-        .if     ((\short) != 4)
-        .if     ((\short) != 8)
-        .if     ((\short) != 16)
-        .if     ((\short) != 32)
-        .error  "The legal ROLS shift amounts are 1, 4, 8, 16 and 32"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        ..instruction PGAS_OPCODE_ROLS, (((\dest) << 20) | ((\src) << 16) | (\short))
-        .endm
-
-        .macro  rol, args:vararg
-        .error "PGAS implements the 'rols' mnemonic instead of PORE 'rol'"
-        .endm
-
-        // LS
-        
-        .macro  ls, dest:req, short:req
-        ..ls_destination (\dest)
-        ..check_s20 (\short)
-        ..instruction PGAS_OPCODE_LS, (((\dest) << 20) | ((\short) & 0xfffff))
-        .endm
-
-        .macro  load20, args:vararg
-        .error  "PGAS implements the 'ls' mnemonic instead of PORE 'load20'"
-        .endm
-        
-        // LI, LIA
-
-        .macro  ..li, dest:req
-        ..li_destination (\dest)
-        ..instruction PGAS_OPCODE_LI, ((\dest) << 20)
-        .endm
-                
-        .macro  li, dest:req, imm:req
-        ..li    (\dest)
-        .quad   (\imm)
-        .endm
-
-        .macro  lia, dest:req, space:req, offset:req
-        ..lia_destination (\dest)
-        ..li    (\dest)
-        .quadia (\space), (\offset)
-        .endm
-
-        .macro  load64, args:vararg
-        .error  "PGAS implements the 'li' mnemonic instead of PORE 'load64'"
-        .endm
-
-        // LD, LDANDI, STD, STI, STIA, BSI, BCI
-        //
-        // For LD, LDANDI, and STD, PGAS does not expose the underlying
-        // register-specific opcodes but only provides the general form.  
-        //
-        // The base register is used to determine if this is a load/store from
-        // the pervasive or memory address spaces.  For memory space accesses
-        // the offset is a 22-bit unsigned value, and the final ima24 is
-        //
-        //     1<reg 0/1><offset>
-        //
-        // PGAS will not assemble relocatable offsets, and checks that offsets
-        // fit in 24 bits.
-        //
-        // For pervasive accesses, it is assumed that the offset provided is a
-        // 32-bit SCOM address.  Here the final ima24 is
-        // 
-        //     0<reg 0/1>00<port><local_address>
-        //
-        // PGAS checks that the 32-bit SCOM address looks like a SCOM address
-        // in that SCOM adresses are required to have bits 0 and 8:11 == 0.
-        //
-        // Note that memory and pervasive base registers use a 0/1 encoding
-        // here, not the 4-bit encoding used elsewhere in the ISA. The bit
-        // appearing in the instruction is the low-order bit of the register
-        // encoding.
-        
-        .macro  ..pervasive_ima24, opcode, offset, base
-        ..check_scom (\offset)
-        ..instruction (\opcode), ((((\base) % 2) << 22) | ((\offset) & 0x3fffff))
-        .endm
-
-        .macro  ..memory_ima24, opcode, offset, base
-        ..check_u24 (\offset)
-        .if     ((\offset) % 8)
-        .error  "The memory space offset is not a multiple of 8 - assumed alignment error"
-        .endif
-        ..instruction (\opcode), (0x800000 | (((\base) % 2) << 22) | ((\offset) & 0x3fffff))
-        .endm
-
-        .macro  ..ima24, opcode, offset, base
-        .if     ((\base == P0) || ((\base == P1)))
-        ..pervasive_ima24 (\opcode), (\offset), (\base)
-        .elseif ((\base == A0) || ((\base == A1)))
-        ..memory_ima24 (\opcode), (\offset), (\base)
-        .else
-        .error  "Expecting either a 'Pervasive Chiplet ID' or an 'Address' register"
-        .endif
-        .endm
-
-        .macro  ..ima24_select, opcode0, opcode1, dest, offset, base
-        ..data  (\dest)
-        .if     ((\dest) == D0)
-        ..ima24 (\opcode0), (\offset), (\base)
-        .else
-        ..ima24 (\opcode1), (\offset), (\base)
-        .endif
-        .endm
-
-        .macro  ld, dest:req, offset:req, base:req
-        ..ima24_select PGAS_OPCODE_LD0, PGAS_OPCODE_LD1, (\dest), (\offset), (\base)
-        .endm
-        
-        .macro  ldandi, dest:req, offset:req, base:req, imm:req
-        ..ima24_select PGAS_OPCODE_LD0ANDI, PGAS_OPCODE_LD1ANDI, (\dest), (\offset), (\base)
-        .quad   (\imm)
-        .endm
-
-        .macro  std, dest:req, offset:req, base:req
-        ..ima24_select PGAS_OPCODE_STD0, PGAS_OPCODE_STD1, (\dest), (\offset), (\base)
-        .endm
-
-        .macro  sti, offset:req, base:req, imm:req
-        ..ima24 PGAS_OPCODE_STI, (\offset), (\base)
-        .quad   (\imm)
-        .endm
-
-        .macro  stia, offset:req, base:req, space:req, addr:req
-        ..ima24 PGAS_OPCODE_STI, (\offset), (\base)
-        .quadia (\space), (\addr)
-        .endm
-
-        .macro  ..bsi, opcode, dest, offset, base, imm
-        ..d0    (\dest)
-        ..ima24 (\opcode), (\offset), (\base)
-        .quad   (\imm)
-        .endm
-
-#ifdef IGNORE_HW274735
-
-        // BSI and BCI are normally redacted due to HW274735. See also pgas.h
-        
-        .macro  bsi, dest:req, offset:req, base:req, imm:req
-        ..bsi   PGAS_OPCODE_BSI, (\dest), (\offset), (\base), (\imm)
-        .endm
-        
-        .macro  bci, dest:req, offset:req, base:req, imm:req
-        ..bsi   PGAS_OPCODE_BCI, (\dest), (\offset), (\base), (\imm)
-        .endm
-
-#endif // IGNORE_HW274735
-
-        .macro  scr1rd, args:vararg
-        .error  "PGAS implements the 'ld' mnemonic instead of the PORE 'scr1rd'"
-        .endm
-
-        .macro  scr2rd, args:vararg
-        .error  "PGAS implements the 'ld' mnemonic instead of the PORE 'scr2rd'"
-        .endm
-
-        .macro  scr1rda, args:vararg
-        .error  "PGAS implements the 'ldandi' mnemonic instead of the PORE 'scr1rda'"
-        .endm
-
-        .macro  scr2rda, args:vararg
-        .error  "PGAS implements the 'ldandi' mnemonic instead of the PORE 'scr2rda'"
-        .endm
-
-        .macro  scr1wr, args:vararg
-        .error  "PGAS implements the 'std' mnemonic instead of the PORE 'scr1wr'"
-        .endm
-
-        .macro  scr2wr, args:vararg
-        .error  "PGAS implements the 'std' mnemonic instead of the PORE 'scr2wr'"
-        .endm
-
-        .macro  wri, args:vararg
-        .error  "PGAS implements the 'sti' mnemonic instead of the PORE 'wri'"
-        .endm
-
-        .macro  bs, args:vararg
-        .error  "PGAS implements the 'bsi' mnemonic instead of the PORE 'bs'"
-        .endm
-
-        .macro  bc, args:vararg
-        .error  "PGAS implements the 'bci' mnemonic instead of the PORE 'bc'"
-        .endm
-
-        // SCAND
-        //
-        // The 24-bit operand here is
-        //
-        //     <update><capture>000000<length>
-
-        .macro  scand, update:req, capture:req, length:req, select:req, offset:req
-        .if     (((\update) != 0) && ((\update) != 1))
-        .error  "SCAND requires a binary value for 'update'"
-        .endif
-        .if     (((\capture) != 0) && ((\capture) != 1))
-        .error  "SCAND requires a binary value for 'capture'"
-        .endif
-        ..check_u16 (\length)
-        ..instruction PGAS_OPCODE_SCAND, ((\update << 23) | (\capture << 22) | (\length))
-        .long   (\select)
-        .long   (\offset)
-        .endm
-
-        // BRAIA, BSR, CMPIBSREQ
-        //
-        // In order to support separate compilation in PGAS programs being
-        // linked with the PowerPC linker it is necessary to implement BSR and
-        // CMPIBSREQ in terms of BRAIA.  These instructions require that the
-        // default address space have been defined.  The BSR instructions
-        // first take a short local subroutine branch to create a stack frame,
-        // then use BRAIA to branch to the (relocatable) target address. The
-        // return from the subroutine then branches around the BRAIA to
-        // complete the sequence.
-
-        .macro  braia, space:req, offset:req
-        ..instruction PGAS_OPCODE_BRAI, 0
-        .quadia (\space), (\offset)
-        .endm
-
-        .macro  ..bsr, target
-        ..bra   PGAS_OPCODE_BSR, (\target)
-        .endm
-        
-        .macro  bsr, target:req
-        ..check_default_space
-        ..bsr   (. + 8)
-        bra     (. + 16)
-        braia   _PGAS_DEFAULT_SPACE, (\target)
-        .endm
-
-        .macro  cmpibsreq, src:req, target:req, imm:req
-        ..d0    (\src)
-        ..check_default_space
-        cmpibrane (\src), (. + 32), (\imm)
-        ..bsr   (. + 8)
-        bra     (. + 16)
-        braia   _PGAS_DEFAULT_SPACE, (\target)
-        .endm
-
-#endif  // __ASSEMBLER__
-                    
-#endif // __PGAS_PPC_H__
diff --git a/src/lib/pgp_config.h b/src/lib/pgp_config.h
deleted file mode 100755
index f4041d4..0000000
--- a/src/lib/pgp_config.h
+++ /dev/null
@@ -1,108 +0,0 @@
-#ifndef __PGP_CONFIG_H__
-#define __PGP_CONFIG_H__
-
-// $Id: pgp_config.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pgp_config.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_config.h
-/// \brief Chip configuration data structures for PgP OCC procedures
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/// A bitmask defining a chip configuration
-///
-/// Since we are using the conventional big-endian notation, any use of these 
-/// bitmasks requires that the data being tested is of this type - otherwise
-/// the masks won't work.  
-///
-/// Layout: 
-///
-/// Bits 0:15  - Core chiplet 0..15 is configured
-/// Bits 16:23 - MCS 0..7 is configured
-/// Bits 24:31 - Centaur 0..7 is configured
-
-typedef uint64_t ChipConfig;
-typedef uint16_t ChipConfigCores;
-typedef uint8_t  ChipConfigMcs;
-typedef uint8_t  ChipConfigCentaur;
-
-
-/// Convert a ChipConfig into a mask suitable for use as the 32-bit chiplet
-/// mask argument of a PORE wakeup program.
-
-static inline uint32_t 
-pore_exe_mask(ChipConfig config)
-{
-    return (uint32_t)((config >> 32) & 0xffff0000);
-}
-
-/// Left justify and mask core chiplet configuration into a uint32_t
-
-static inline uint32_t
-left_justify_core_config(ChipConfig config)
-{
-    return (uint32_t)((config >> 32) & 0xffff0000);
-}
-
-/// Left justify and mask MCS configuration into a uint32_t
-
-static inline uint32_t
-left_justify_mcs_config(ChipConfig config)
-{
-    return (uint32_t)((config >> 16) & 0xff000000);
-}
-
-/// Left justify and mask Centaur configuration into a uint32_t
-
-static inline uint32_t
-left_justify_centaur_config(ChipConfig config)
-{
-    return (uint32_t)((config >> 8) & 0xff000000);
-}
-
-#endif // __ASSEMBLER__
-
-
-#define CHIP_CONFIG_CORE_BASE 0
-#define CHIP_CONFIG_CORE(n) \
-    ((0x8000000000000000ull >> CHIP_CONFIG_CORE_BASE) >> (n))
-
-#define CHIP_CONFIG_MCS_BASE 16
-#define CHIP_CONFIG_MCS(n) \
-    ((0x8000000000000000ull >> CHIP_CONFIG_MCS_BASE) >> (n))
-
-#define CHIP_CONFIG_CENTAUR_BASE 24
-#define CHIP_CONFIG_CENTAUR(n) \
-    ((0x8000000000000000ull >> CHIP_CONFIG_CENTAUR_BASE) >> (n))
-
-
-// PGAS macros to left justify configuration groups, allowing each member to
-// be tested in a loop that rotates the data (d) register left on each loop,
-// assuming standard big-endian bit assignments. The macros mask off all other
-// configuration bits so the destination register can also be tested for
-// 0/non-0 to determine if any of a configuration class are selected.
-
-#ifdef __PGAS__
-
-        .macro  left_justify_core_config, d
-        extldi  (\d), (\d), PGP_NCORES, CHIP_CONFIG_CORE_BASE
-        .endm
-
-        .macro  left_justify_mcs_config, d
-        extldi  (\d), (\d), PGP_NMCS, CHIP_CONFIG_MCS_BASE
-        .endm
-
-        .macro  left_justify_centaur_config, d
-        extldi  (\d), (\d), PGP_NCENTAUR, CHIP_CONFIG_CENTAUR_BASE
-        .endm
-
-#endif /* __PGAS__ */
-
-#endif  /* __PGP_CONFIG_H__ */
diff --git a/src/lib/pmc_dcm.c b/src/lib/pmc_dcm.c
deleted file mode 100755
index a0f7d82..0000000
--- a/src/lib/pmc_dcm.c
+++ /dev/null
@@ -1,425 +0,0 @@
-// $Id: pmc_dcm.c,v 1.2 2014/02/03 01:30:25 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pmc_dcm.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pmc_dcm.c
-/// \brief Genertic PMC Interhchip Communication Mechanism 
-
-#include "ssx.h"
-#include "pmc_dcm.h"
-
-////////////////////////////////////////////////////////////////////////////
-// Low-level PMC-DCM Interfaces
-////////////////////////////////////////////////////////////////////////////
-
-/// Non-blocking transmission of a packet over the PMC-DCM interface
-///
-/// Note: Locking/synchronization of the PMC-DCM interface is the
-/// responsibility of the application.
-///
-/// \param hwPacket A PmcDcmPacket structure to be sent via PMC interchip link
-/// This argument is provided by the caller and passed in as reference.
-/// 
-/// \code
-/// hwPacket: 
-/// 
-/// cmd_code | cmd_ext | payload 0 | payload 1 | ECC
-/// [0:3]    | [4:7]   | [8:15]    | [16:23]   | [24:31]
-/// 
-/// cmd_code:
-/// PMC_IC_GPA_CC      | 1  | 0b0001 | Global PState Actual  | Master to Slave
-/// PMC_IC_GPA_ACK_CC  | 2  | 0b0010 | Global PState Ack     | Slave to Master
-/// PMC_IC_GAR_CC      | 3  | 0b0011 | Global Actual Request | Slave to Master
-/// PMC_IC_PING_CC     | 4  | 0b0100 | Ping                  | Master to Slave
-/// PMC_IC_PING_ACK_CC | 6  | 0b0110 | Ping Acknowledge      | Slave to Master
-/// PMC_IC_MSG_CC      | 8  | 0b1000 | Message               | Bidirectional
-/// PMC_IC_MSG_NACK_CC | 10 | 0b1010 | Message NACK          | Bidirectional
-/// PMC_IC_MSG_ACK_CC  | 11 | 0b1011 | Message ACK           | Bidirectional
-/// PMC_IC_ERROR_CC    | 12 | 0b1111 | Error                 | Slave to Master
-/// \endcode
-/// 
-/// This API sends command to another chip through the PMC interchip wire 
-/// in DCM setup. The message will be sent out by writing the packet value 
-/// to the regisiter: PMC_INTCHP_MSG_WDATA
-///
-/// It also checks the interchip_ga_ongoing and interchip_msg_send_ongoing
-/// bits of PMC_INTCHP_STATUS_REG to detect if the channel is free
-/// If the channel is busy, the function will exit with returning 
-/// an error code \a PMC_DCM_OUTSTANDING_TRANSFER
-///
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG
-///               must be set to enable the PMC interchip transfer
-///               Also, the hardware must be in DCM setup
-///
-/// Note: This API can be used to send any valid command over the link
-///       however, both command code and corresponding direction of transfer
-///       will be checked to ensure correctness of the protocol. Upon 
-///       attempt to send an invalid command or an unexpected direction 
-///       of transfering certain command will cause this API to abort 
-///       which indicates a HW/FW bug 
-///
-/// \retval PMC_DCM_SUCCESS
-///
-/// \retval PMC_DCM_ARG_NULL_OBJECT_SEND
-///
-/// \retval PMC_DCM_INTCHP_DISABLED_SEND
-///
-/// \retval PMC_DCM_OUTSTANDING_TRANSFER
-/// 
-/// \retval PMC_DCM_INVALID_COMMAND_CODE
-///
-
-int
-pmc_dcm_send(PmcDcmPacket* hwPacket)
-{
-    int rc = PMC_DCM_SUCCESS;
- 
-    do {
-
-        // check if reference packet is null
-        SSX_ERROR_IF_CHECK_API(
-            (hwPacket == 0), 
-            PMC_DCM_ARG_NULL_OBJECT_SEND);
-
-        // check if interchip transfer is enabled on this chip
-        SSX_ERROR_IF_CHECK_API(
-            (pmc_dcm_if_interchip_interface_enabled() == 0),
-            PMC_DCM_INTCHP_DISABLED_SEND);
-
-        //check if command code is valid and direction of transfer is valid
-        rc = pmc_dcm_check_ic_command((int)hwPacket->fields.cmd_code);
-        if( rc ) break; 
-
-        // check if the interchip channel is busy
-        if( pmc_dcm_if_channel_busy() ) {
-            rc = PMC_DCM_OUTSTANDING_TRANSFER;
-            break;
-        }
-
-        // send out the command
-        _pmc_dcm_send(&hwPacket->value);
-
-    } while (0);
-
-    return rc;
-}
-
-/// Non-blocking reception of a packet from the PMC-DCM interface
-///
-/// Note: Locking/synchronization of the PMC-DCM interface is the
-/// responsibility of the application.
-///
-/// \param hwPacket A PmcDcmPacket structure passed by the caller 
-/// as reference to receive the message sent from PMC interchip link
-/// 
-/// This API receives the message from the PMC interchip wire 
-/// by reading the register: PMC_INTCHP_MSG_RDATA
-///
-/// It checks the interchip_msg_recv_detected bit of 
-/// PMC_INTCHP_STATUS_REG to know if there is a new message
-/// If no new message is detected, the receive function will 
-/// exit with returning an error code \a PMC_DCM_RECEIVE_NOT_DETECTRD
-///
-/// Prerequisite: The enable_interchip_interface bit of PMC_MODE_REG 
-///               must be set to enable the PMC interchip transfer
-///               Also, the hardware must be in DCM setup
-///
-/// Note: only MSG type message or cmd code should be received
-///       otherwise function aborts and indicates a hardware bug
-///
-/// \retval PMC_DCM_SUCCESS
-///
-/// \retval PMC_DCM_ARG_NULL_OBJECT_RECV
-///
-/// \retval PMC_DCM_INTCHP_DISABLED_RECV
-///
-/// \retval PMC_DCM_RECEIVE_NOT_DETECTRD
-///
-/// \retval PMC_DCM_RECEIVE_NOT_MSG_TYPE
-///
-
-int
-pmc_dcm_receive(PmcDcmPacket* hwPacket)
-{
-    int rc = PMC_DCM_SUCCESS;
-
-    do {
-
-        //check if reference packet is null
-        SSX_ERROR_IF_CHECK_API(
-            (hwPacket == 0),
-            PMC_DCM_ARG_NULL_OBJECT_RECV);
-
-        // check if interchip transfer is enabled on this chip
-        SSX_ERROR_IF_CHECK_API(
-            (!pmc_dcm_if_interchip_interface_enabled()),
-            PMC_DCM_INTCHP_DISABLED_RECV);   
- 
-        // check if there is a new incoming message
-        if( !pmc_dcm_if_new_message() ) {
-            rc = PMC_DCM_RECEIVE_NOT_DETECTED;
-            break; 
-        }
-    
-        // receive the new message
-        _pmc_dcm_receive(&hwPacket->value);
-    
-        // check if the command is MSG type
-        SSX_ERROR_IF_CHECK_API(
-            (hwPacket->fields.cmd_code != PMC_IC_MSG_CC), 
-            PMC_DCM_RECEIVE_NOT_MSG_TYPE);
-
-    } while (0);
-
-    return rc;
-}
-
-
-
-/// Internal API : Send data without error checking
-///
-/// \param value 32 bits data to be sent
-///
-/// This API send the interchip data by writing register:
-/// PMC_INTCHP_MSG_WDATA
-///
-/// \retval NONE
-///
-
-void
-_pmc_dcm_send(uint32_t *value)
-{
-    out32(PMC_INTCHP_MSG_WDATA, *value);
-}
-
-
-/// Internal API : Receive data without error checking
-///
-/// \param value 32 bits data to be received
-///
-/// This API receive the interchip data by reading register: 
-/// PMC_INTCHP_MSG_RDATA
-/// 
-/// \retval NONE
-///
-
-void
-_pmc_dcm_receive(uint32_t *value)
-{
-    *value = in32(PMC_INTCHP_MSG_RDATA);
-}
-
-/// This API tells if the given command is a valid pmc interchip command
-/// and if the command is given by the designated source
-///
-/// \param cmd_code the command code
-///
-/// \param rc the return code back to caller
-/// 
-/// \code
-/// cmd_code:
-///
-/// PMC_IC_GPA_CC      | 1  | 0b0001 | Global PState Actual  | Master to Slave
-/// PMC_IC_GPA_ACK_CC  | 2  | 0b0010 | Global PState Ack     | Slave to Master
-/// PMC_IC_GAR_CC      | 3  | 0b0011 | Global Actual Request | Slave to Master
-/// PMC_IC_PING_CC     | 4  | 0b0100 | Ping                  | Master to Slave
-/// PMC_IC_PING_ACK_CC | 6  | 0b0110 | Ping Acknowledge      | Slave to Master
-/// PMC_IC_MSG_CC      | 8  | 0b1000 | Message               | Bidirectional
-/// PMC_IC_MSG_NACK_CC | 10 | 0b1010 | Message NACK          | Bidirectional
-/// PMC_IC_MSG_ACK_CC  | 11 | 0b1011 | Message ACK           | Bidirectional
-/// PMC_IC_ERROR_CC    | 12 | 0b1111 | Error                 | Slave to Master
-/// \endcode
-///
-/// \retval PMC_DCM_INTCHP_CMD_ONLY_MTOS
-///
-/// \retval PMC_DCM_INTCHP_CMD_ONLY_STOM
-///
-/// \retval PMC_DCM_INVALID_COMMAND_CODE
-///
-
-int
-pmc_dcm_check_ic_command(int cmd_code)
-{
-    //note:certain command can only be transferred from master to slave
-    //     or from slave to master or bidirectional.
-    if( cmd_code == PMC_IC_GPA_CC ||
-        cmd_code == PMC_IC_PING_CC ) {
-        //those commands can only be sent from master to slave
-        SSX_ERROR_IF_CHECK_API(
-            (!pmc_dcm_if_dcm_master()),
-            PMC_DCM_INTCHP_CMD_ONLY_MTOS);            
-    } else if( cmd_code == PMC_IC_GPA_ACK_CC  ||
-               cmd_code == PMC_IC_GAR_CC      ||
-               cmd_code == PMC_IC_PING_ACK_CC ||
-               cmd_code == PMC_IC_ERROR_CC ) {
-        //those commands can only be sent from slave to master
-        SSX_ERROR_IF_CHECK_API(
-            (pmc_dcm_if_dcm_master()),
-            PMC_DCM_INTCHP_CMD_ONLY_STOM);
-    } else if( !(cmd_code == PMC_IC_MSG_CC      ||
-                 cmd_code == PMC_IC_MSG_NACK_CC ||
-                 cmd_code == PMC_IC_MSG_ACK_CC) ) {
-        //those commands are bidirectional
-        //none of above, invalid command
-        SSX_ERROR_IF_CHECK_API(
-            0,
-            PMC_DCM_INVALID_COMMAND_CODE);
-    } 
-    return PMC_DCM_SUCCESS;
-}
-
-
-
-/// This API tells if the current chip is the DCM master or slave
-///
-/// \param NONE
-///
-/// The DCM master/slave is configured as the interchip_mode bit in register:
-/// PMC_MODE_REG
-/// 
-/// \retval 1 Master
-/// 
-/// \retval 0 Slave
-///
-
-int
-pmc_dcm_if_dcm_master()
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    return pmc_mode_reg.fields.enable_interchip_interface && 
-           pmc_mode_reg.fields.interchip_mode;
-}
-
-/// This API sets the current chip to be the DCM master or slave
-///
-/// \param master if 1 then set to master otherwise slave
-///
-/// The DCM master/slave is configured as the interchip_mode bit in register:
-/// PMC_MODE_REG
-///
-/// \retval NONE
-///
-
-void
-pmc_dcm_set_interchip_mode(int master)
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    pmc_mode_reg.fields.enable_interchip_interface = 1;
-    if( master == 0 )
-        pmc_mode_reg.fields.interchip_mode = 0;
-    else
-        pmc_mode_reg.fields.interchip_mode = 1;
-    out32(PMC_MODE_REG, pmc_mode_reg.value);
-}
-
-/// This API tells if the current chip is enabled with interchip interface 
-///
-/// \param NONE
-///
-/// The DCM master/slave is configured as the enable_interchip_interface bit 
-/// in register: PMC_MODE_REG
-///
-/// Note: set this bit is required for any interchip communication
-///
-/// \retval 1 Enabled
-///
-/// \retval 0 Disabled
-///
-
-int
-pmc_dcm_if_interchip_interface_enabled()
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    return pmc_mode_reg.fields.enable_interchip_interface;
-}
-
-/// This API sets the current chip to be enabled with interchip interface
-///
-/// \param enable if 1 then interface enabled otherwise disabled
-///
-/// The DCM master/slave is configured as the enable_interchip_interface bit 
-/// in register: PMC_MODE_REG
-///
-/// \retval NONE
-///
-
-void
-pmc_dcm_set_interchip_interface(int enable)
-{
-    pmc_mode_reg_t pmc_mode_reg;
-    pmc_mode_reg.value = in32(PMC_MODE_REG);
-    if( enable == 0 )
-        pmc_mode_reg.fields.enable_interchip_interface = 0;
-    else
-        pmc_mode_reg.fields.enable_interchip_interface = 1;
-    out32(PMC_MODE_REG, pmc_mode_reg.value);
-}
-
-
-/// This API tells if the interchip channel is busy for outgoing communication
-///
-/// \param NONE
-///
-/// depends on bits: interchip_ga_ongoing and interchip_msg_send_ongoing
-/// in register: PMC_INTCHP_STATUS_REG
-///
-/// \retval 1 Busy
-///
-/// \retval 0 Free
-///
-
-int
-pmc_dcm_if_channel_busy()
-{
-    pmc_intchp_status_reg_t pmc_intchp_status_reg;
-    pmc_intchp_status_reg.value = in32(PMC_INTCHP_STATUS_REG);
-    return pmc_intchp_status_reg.fields.interchip_msg_send_ongoing;
-    //return (pmc_intchp_status_reg.fields.interchip_ga_ongoing ||
-    //        pmc_intchp_status_reg.fields.interchip_msg_send_ongoing); 
-}
-
-/// This API tells if there is a new message arrived from the interchip wire
-///
-/// \param NONE
-///
-/// if bit interchip_msg_recv_detected in register: PMC_INTCHP_STATUS_REG
-/// is set then new message otherwise none
-///
-/// \retval 1 New Message
-///
-/// \retval 0 NO New Message
-///
-
-int
-pmc_dcm_if_new_message()
-{
-    pmc_intchp_status_reg_t pmc_intchp_status_reg;
-    pmc_intchp_status_reg.value = in32(PMC_INTCHP_STATUS_REG);
-    return pmc_intchp_status_reg.fields.interchip_msg_recv_detected;
-}
-
-/// This API initializes the DCM setup 
-///
-/// \param master_or_slave configure the current chip to be master or slave
-///
-/// for current chip
-/// 1) enable interchip interface
-/// 2) configure to be DCM master or slave
-///
-/// Note: one chip has to be master and one chip has to be slave
-///
-/// \retval NONE
-///
-
-void
-pmc_dcm_init(int master_or_slave)
-{     
-    pmc_dcm_set_interchip_mode(master_or_slave);
-}
diff --git a/src/lib/pmc_dcm.h b/src/lib/pmc_dcm.h
deleted file mode 100755
index 3141aec..0000000
--- a/src/lib/pmc_dcm.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef __PMC_DCM_H__
-#define __PMC_DCM_H__
-
-// $Id: pmc_dcm.h,v 1.2 2014/02/03 01:30:25 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pmc_dcm.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pmc_dcm.h
-/// \brief Generic PMC Interhchip Communication Mechanism 
-
-
-/// PMC-DCM Return Code
-#define PMC_DCM_SUCCESS              0
-#define PMC_DCM_ARG_NULL_OBJECT_SEND 0x00326501 //ssx panic
-#define PMC_DCM_ARG_NULL_OBJECT_RECV 0x00326501 //ssx panic
-#define PMC_DCM_INTCHP_DISABLED_SEND 0x00326502 //ssx panic
-#define PMC_DCM_INTCHP_DISABLED_RECV 0x00326502 //ssx panic
-#define PMC_DCM_OUTSTANDING_TRANSFER 0x00326503 //user handle
-#define PMC_DCM_INTCHP_CMD_ONLY_MTOS 0x00326504 //ssx panic
-#define PMC_DCM_INTCHP_CMD_ONLY_STOM 0x00326504 //ssx panic
-#define PMC_DCM_INVALID_COMMAND_CODE 0x00326505 //ssx panic
-#define PMC_DCM_RECEIVE_NOT_DETECTED 0x00326506 //user handle
-#define PMC_DCM_RECEIVE_NOT_MSG_TYPE 0x00326507 //ssx panic
-    
-/// PMC Interchip Command Code
-#define PMC_IC_GPA_CC           1  //0b0001
-#define PMC_IC_GPA_ACK_CC       2  //0b0010
-#define PMC_IC_GAR_CC           3  //0b0011
-#define PMC_IC_PING_CC          4  //0b0100
-#define PMC_IC_PING_ACK_CC      6  //0b0110
-#define PMC_IC_MSG_CC           8  //0b1000
-#define PMC_IC_MSG_NACK_CC      10 //0b1010
-#define PMC_IC_MSG_ACK_CC       11 //0b1011
-#define PMC_IC_ERROR_CC         15 //0b1111
-
-#ifndef __ASSEMBLER__
-
-/// PMC-DCM low-level (hardware) packet
-
-typedef union PmcInterchipPacket { 
-    uint32_t value;
-    struct {
-        /// Hardware command code
-        uint8_t cmd_code : 4;
-        /// Hardware command extension; GPSM-DCM command code
-        uint8_t cmd_ext : 4;
-        /// Payload. The plan of record is to use payload[2] as HW-generated ECC.
-        uint8_t payload[3];
-    } fields;
-} PmcDcmPacket;
-
-/// Macro to set and get payload field
-#define SET_PAYLOAD_FIELD(value) (value << 8) & 0xFFFF00
-#define GET_PAYLOAD_FIELD(value) (value & 0xFFFF00) >> 8
-
-
-/// low-level PMC-DCM interchip communication methods
-
-int
-pmc_dcm_send(PmcDcmPacket* hwPacket);
-
-int
-pmc_dcm_receive(PmcDcmPacket* hwPacket);
-
-void
-_pmc_dcm_send(uint32_t *value);
-
-void
-_pmc_dcm_receive(uint32_t *value);
-
-int
-pmc_dcm_check_ic_command(int cmd_code);
-
-int
-pmc_dcm_if_dcm_master();
-
-void
-pmc_dcm_set_interchip_mode(int master);
-
-int
-pmc_dcm_if_interchip_interface_enabled();
-
-void
-pmc_dcm_set_interchip_interface(int enable);
-
-int
-pmc_dcm_if_channel_busy();
-
-int
-pmc_dcm_if_new_message();
-
-void
-pmc_dcm_init(int master_or_slace);
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __PMC_DCM_H__ */
-
diff --git a/src/lib/polling.c b/src/lib/polling.c
deleted file mode 100644
index 42e9fef..0000000
--- a/src/lib/polling.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// $Id: polling.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/polling.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file polling.c
-/// \brief Library APIs for polling
-
-#include "polling.h"
-
-int
-polling(int* o_rc,
-        int (*i_condition)(void* io_arg, int* o_satisfied),
-        void* io_arg,
-        SsxInterval i_timeout,
-        SsxInterval i_sleep)
-{
-    SsxTimebase start;
-    int rc, pollRc, timed_out, done;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((i_condition == 0), POLLING_ERROR);
-    }
-    
-    start = ssx_timebase_get();
-    timed_out = 0;
-
-    do {
-        pollRc = i_condition(io_arg, &done);
-        if (pollRc) {
-            rc = POLLING_CONDITION;
-            break;
-        }
-        if (done) {
-            rc = 0;
-            break;
-        }
-        if (timed_out) {
-            rc = POLLING_TIMEOUT;
-            break;
-        }
-        if (i_sleep != 0) {
-            rc = ssx_sleep(i_sleep);
-            if (rc) {
-                break;
-            }
-        }
-        timed_out = 
-            ((i_timeout != SSX_WAIT_FOREVER) &&
-             ((ssx_timebase_get() - start) >= i_timeout));
-
-    } while (1);
-
-    if (o_rc) {
-        *o_rc = pollRc;
-    }
-
-    return rc;
-}
-
-
-void
-busy_wait(SsxInterval i_interval)
-{
-    SsxTimebase start;
-
-    start = ssx_timebase_get();
-    while ((ssx_timebase_get() - start) < i_interval);
-}
-
diff --git a/src/lib/pore_hooks.h b/src/lib/pore_hooks.h
deleted file mode 100755
index f278acb..0000000
--- a/src/lib/pore_hooks.h
+++ /dev/null
@@ -1,171 +0,0 @@
-#ifndef __PORE_HOOKS_H__
-#define __PORE_HOOKS_H__
-
-// $Id: pore_hooks.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pore_hooks.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pore_hooks.h
-/// \brief Support for PORE hooks in Simics
-///
-/// Our Simics model of the PORE supports "hooks", that is, special forms of
-/// comments that include C++ code that is extracted and made available at
-/// simulation time in the Simics environment.
-///
-/// Besides hooks that do simple printf() type tracing, logging and tracing
-/// hooks are also provided that make use of the Simics log-level facility.
-/// This allows precise control over which PORE objects are logged/traced, and
-/// at which level.
-///
-/// In the Simics environment, hook routines have the following prototype:
-///
-///     void f(const PoreAddress& i_address,
-///            const HookType i_type,
-///            PoreSimics& io_pore);
-
-// Define the "1-liner" syntax
-
-#define HOOK_MARKER HOOK_INSERT_MARKER(#,#)
-#define HOOK_INSERT_MARKER(x,y) x##y##1@
-
-
-/// \defgroup standard_io_hooks Standard I/O Logging and Tracing Hooks
-///
-/// Standard I/O printing. The *TRACE* forms prefix the output with the file
-/// name and line number. 
-///
-/// @{
-
-#define PORE_PRINTF(...) HOOK_MARKER printf(__VA_ARGS__);
-
-#define PORE_FPRINTF(stream, ...) HOOK_MARKER fprintf(stream, __VA_ARGS__);
-
-#define PORE_TRACEF(fmt, ...)                                                \
-    HOOK_MARKER printf("%s:d:" fmt, __FILE__, __LINE__, ##__VA_ARGS__);
-
-#define PORE_FTRACEF(stream, fmt, ...)                                       \
-    HOOK_MARKER printf(stream, "%s:d:" fmt, __FILE__, __LINE__, ##__VA_ARGS__);
-
-/// @}
-
-/// \defgroup quickie_debugging_prints Quickie Debugging Print Hooks
-///
-/// Quickie debugging prints. You provide a register name and string (w/o
-/// newline), the macro formats the data.
-///
-/// @{
-
-#define PORE_PRINT_REG(msg, reg, fmt, fn)                        \
-    PORE_PRINTF(msg " : " #reg " = " FMT_##fmt "\n", fn)
-
-#define PORE_TRACE_REG(msg, reg, fmt, fn)                        \
-    PORE_TRACEF(msg " : " #reg " = " FMT_##fmt "\n", fn)
-
-#define PORE_PRINT_D0(msg)      PORE_PRINT_REG(msg, D0, DX, d0())
-#define PORE_PRINT_D1(msg)      PORE_PRINT_REG(msg, D1, DX, d1())
-#define PORE_PRINT_A0(msg)      PORE_PRINT_REG(msg, A0, AX, a0())
-#define PORE_PRINT_A1(msg)      PORE_PRINT_REG(msg, A1, AX, a1())
-#define PORE_PRINT_P0(msg)      PORE_PRINT_REG(msg, P0, PX, p0())
-#define PORE_PRINT_P1(msg)      PORE_PRINT_REG(msg, P1, PX, p1())
-#define PORE_PRINT_CTR(msg)     PORE_PRINT_REG(msg, CTR, CTR, ctr())
-#define PORE_PRINT_SPRG0(msg)   PORE_PRINT_REG(msg, SPRG0, SPRG0, sprg0())
-#define PORE_PRINT_STATUS(msg)  PORE_PRINT_REG(msg, STATUS, STATUS, status())
-#define PORE_PRINT_CONTROL(msg) PORE_PRINT_REG(msg, CONTROL, CONTROL, control())
-
-#define PORE_TRACE_D0(msg)      PORE_TRACE_REG(msg, D0, DX, d0())
-#define PORE_TRACE_D1(msg)      PORE_TRACE_REG(msg, D1, DX, d1())
-#define PORE_TRACE_A0(msg)      PORE_TRACE_REG(msg, A0, AX, a0())
-#define PORE_TRACE_A1(msg)      PORE_TRACE_REG(msg, A1, AX, a1())
-#define PORE_TRACE_P0(msg)      PORE_TRACE_REG(msg, P0, PX, p0())
-#define PORE_TRACE_P1(msg)      PORE_TRACE_REG(msg, P1, PX, p1())
-#define PORE_TRACE_CTR(msg)     PORE_TRACE_REG(msg, CTR, CTR, ctr())
-#define PORE_TRACE_SPRG0(msg)   PORE_TRACE_REG(msg, SPRG0, SPRG0, sprg0())
-#define PORE_TRACE_STATUS(msg)  PORE_TRACE_REG(msg, STATUS, STATUS, status())
-#define PORE_TRACE_CONTROL(msg) PORE_TRACE_REG(msg, CONTROL, CONTROL, control())
-
-/// @}
-
-/// \defgroup simics_style_logging Simics-style Logging Hooks
-///
-/// Simics-style logging.  All of these will produce a Simics prefix detailing
-/// the unit that failed. The *_TRACE_* forms add the file name and line number
-/// to the Simics info, print a newline and then format the trace message on
-/// the following line. 
-///
-/// @{
-
-#define SIM_LOG_INFO(level, group, ...) HOOK_MARKER             \
-    SIM_log_info(level, io_pore.d_log, group, __VA_ARGS__);
-
-#define SIM_LOG_ERROR(group, ...) HOOK_MARKER           \
-    SIM_log_error(io_pore.d_log, group, __VA_ARGS__);
-
-#define SIM_TRACE_INFO(level, group, fmt, ...) HOOK_MARKER              \
-    SIM_log_info(level, io_pore.d_log, group,                           \
-                 "%s:%d\n" fmt, __FILE__, __LINE__,## __VA_ARGS__);
-
-#define SIM_TRACE_ERROR(group, fmt, ...) HOOK_MARKER                    \
-    SIM_log_error(io_pore.d_log, group,                                 \
-                  "%s:%d\n" fmt, __FILE__, __LINE__, ##__VA_ARGS__);
-
-/// @}
-
-/// \defgroup vcl_style_3_level_printing VCL-style 3-Level Logging Hooks
-///
-/// Define VCL-style 3-level logging and tracing, with programmable Simics
-/// log-level selection. All logs are controlled by (?) group 0. Note that
-/// setting the Simics log-level to 4 produces gobs of output from every part
-/// of the system, however here at the debug level of 3 we only get messages
-/// from hooks.
-///
-/// @{
-
-#ifndef SIMICS_LOG_LEVEL_OUTPUT
-#define SIMICS_LOG_LEVEL_OUTPUT 1
-#endif
-
-#ifndef SIMICS_LOG_LEVEL_INFO
-#define SIMICS_LOG_LEVEL_INFO 2
-#endif
-
-#ifndef SIMICS_LOG_LEVEL_DEBUG
-#define SIMICS_LOG_LEVEL_DEBUG 3
-#endif
-
-#define PORE_LOG_OUTPUT(...) SIM_LOG_INFO(SIMICS_LOG_LEVEL_OUTPUT, 0, __VA_ARGS__)
-#define PORE_LOG_INFO(...)   SIM_LOG_INFO(SIMICS_LOG_LEVEL_INFO, 0, __VA_ARGS__)
-#define PORE_LOG_DEBUG(...)  SIM_LOG_INFO(SIMICS_LOG_LEVEL_DEBUG, 0, __VA_ARGS__)
-
-#define PORE_LOG_ERROR(...)  SIM_LOG_ERROR(0, __VA_ARGS__)
-
-#define PORE_TRACE_OUTPUT(...) SIM_TRACE_INFO(SIMICS_LOG_LEVEL_OUTPUT, 0, __VA_ARGS__)
-#define PORE_TRACE_INFO(...)   SIM_TRACE_INFO(SIMICS_LOG_LEVEL_INFO, 0, __VA_ARGS__)
-#define PORE_TRACE_DEBUG(...)  SIM_TRACE_INFO(SIMICS_LOG_LEVEL_DEBUG, 0, __VA_ARGS__)
-
-#define PORE_TRACE_ERROR(...)  SIM_TRACE_ERROR(0, __VA_ARGS__)
-
-/// @}
-
-/// Break Simics simulation
-#define SIM_BREAK_SIMULATION(msg) \
-    HOOK_MARKER SIM_break_simulation(msg); io_pore.dumpAll();
-
-
-/// A PORE Assertion
-#define PORE_ASSERT(assertion)                                  \
-    HOOK_MARKER                                                 \
-    if (!(assertion)) {                                         \
-        SIM_log_error(io_pore.d_log, 0,                         \
-                      "Assertion below failed\n" #assertion);   \
-        SIM_break_simulation("Assertion failure");              \
-    }
-    
-
-/// Dump the PORE state
-#define PORE_DUMP(...) LOG_OUTPUT(__VA_ARGS__) io_pore.dumpAll();
-
-#endif // __PORE_HOOKS_H__
diff --git a/src/lib/ppc405lib/Makefile b/src/lib/ppc405lib/Makefile
new file mode 100644
index 0000000..37ef2ea
--- /dev/null
+++ b/src/lib/ppc405lib/Makefile
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/ppc405lib/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  This Makefile currently builds a single archive, 'libppc405.a', from
+#  various library source files. 
+#
+#  part of the complete application build.
+#
+
+#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/ppc405lib
+export SUB_OBJDIR = /ppc405lib
+
+include img_defs.mk
+include libppc405files.mk
+
+OBJS := $(addprefix $(OBJDIR)/, $(LIBPPC405_OBJECTS))
+
+libppc405.a: local
+	$(AR) crs $(OBJDIR)/libppc405.a $(OBJDIR)/*.o
+
+.PHONY: clean
+
+local: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+#include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/lib/ppc405lib/README.txt b/src/lib/ppc405lib/README.txt
new file mode 100644
index 0000000..cc0076f
--- /dev/null
+++ b/src/lib/ppc405lib/README.txt
@@ -0,0 +1,4 @@
+This directory contains all of the library code that only can run on the ppc405.
+For most of the files, the only reason it can not run on the ppe42 is because of
+it's dependence on SSX.  Eventually, we would like to fix this so that most, if
+not all files can be made common.
diff --git a/src/lib/ppc405lib/assert.c b/src/lib/ppc405lib/assert.c
new file mode 100644
index 0000000..96143a4
--- /dev/null
+++ b/src/lib/ppc405lib/assert.c
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/assert.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: assert.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/assert.c,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file assert.c
+/// \brief Implementation of library routines implied by <assert.h>
+
+#include "ssx.h"
+#include "ssx_io.h"
+#include "libssx.h"
+
+/// The __assert_fail() function is used to implement the assert() interface
+/// of ISO POSIX (2003). The __assert_fail() function prints the given \a
+/// file filename, \a line line number, \a function function name and a
+/// message on the standard error stream then causes a kernel panic.  If there
+/// is no standard error stream then the error message is printed on the \a
+/// ssxout (printk()) stream.
+/// 
+/// If function is NULL, __assert_fail() omits information about the
+/// function. The aguments \a assertion, \a file, and \a line must be
+/// non-NULL.
+
+void
+__assert_fail(const char *assertion, 
+              const char *file, 
+              unsigned line, 
+              const char *function)
+{
+    FILE *stream;
+
+    stream = stderr;
+    if (stream == 0) {
+        stream = ssxout;
+    }
+
+    fprintf(stream, "%s:%u:%s%s Assertion '%s' failed\n",
+            file, line, 
+            function ? function : "", function ? ":" : "",
+            assertion);
+
+    SSX_PANIC(ASSERTION_FAILURE);
+}
+
diff --git a/src/lib/ppc405lib/byte_pool.c b/src/lib/ppc405lib/byte_pool.c
new file mode 100644
index 0000000..d382abc
--- /dev/null
+++ b/src/lib/ppc405lib/byte_pool.c
@@ -0,0 +1,1442 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/byte_pool.c $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file byte_pool.c
+/// \brief An implementation of a constant-time malloc() algorithm.
+///
+/// The 'byte-pool' API defined in this file is similar to ThreadX' byte-pool
+/// operations, with the major difference that here there is no concept of a
+/// thread blocking on memory allocation.  This is a concept that is difficult
+/// to implement correctly and efficiently, and several semantic options
+/// exist for how allocation and freeing memory should work in the presence of
+/// blocked threads. The application is always free to implement a blocking
+/// API using these APIs and SSX synchronization primitives.
+///
+/// For convenience this implementation also provides malloc() and calloc()
+/// calls.  These APIs depend on the application creating a byte pool and
+/// assigning it to the library variable \a _malloc_byte_pool.
+///
+/// \todo Consider separating the idea of creating a byte pool with a specific
+/// maximum-sized block, from the idea of adding memory to a byte pool. The
+/// idea is to allow pieces of memory required during initialization of the
+/// application to be added back to the pool at run time.  We could also
+/// simply add an API to allow memory to be added to a previously created
+/// pool, with the special case that if the block were 'too big' that it would
+/// be split into smaller chunks.
+///
+/// \todo Consider
+/// adding an option to store a pointer to the originating byte pool in the
+/// block header.  This would allow deallocation of any block with free()
+/// regardless of which pool it was allocated from, at a cost of 1 pointer per
+/// block.  This would simplify some of our validation test cases. We could
+/// also accomplish this by having each pool register ranges of addresses that
+/// it allocates from, but that would require a search every time we freed a
+/// block.
+
+#include "ssx.h"
+#include "byte_pool.h"
+
+// This is an implementation of the TLSF (Two-Level Segregate Fit) algorithm
+// described by M. Masmano, I. Ripoll and A Crespol,
+// http:/rtportal.upv.es/rtmalloc. A couple of their papers and presentations
+// are archived in /lib/doc/tlsf.  This is a 'clean-room' implementation of
+// their published ideas based solely on their papers and presentations.  No
+// part of their GPL implementation was used to create the byte-pool facility
+// implemented here. The algorithm as implemented here should port without
+// problem to either 32-bit or 64-bit implementations.
+//
+// TLSF has the nice property that it is a constant-time algorithm, both for
+// allocation and freeing allocated blocks.  This property is guaranteed by
+// always trading space for speed in the algorithm. This means that we can
+// (and do) run the allocation and freeing in a critical section. With all
+// error checking and statistics, a worst-case byte_bool_alloc() was
+// timed at 318 PowerPC instructions in the PgP OCC (PPC405) Simics
+// simulation.  A worst-case byte_pool_free() was timed at 368 PowerPC
+// instructions. These times are expected to equate to ~3us in OCC, a
+// reasonable value for a critical section. [The above times include all
+// error checking].
+//
+// An allocation unit requires two pointers of overhead - a pointer to the
+// previous block and a pointer to the next block (both in terms of linear
+// addresses). The minimum block size also includes the requirement for two
+// extra pointers used to link free blocks into their free lists. The final
+// size of the block (including user data) is simply computed as (next - self)
+// in terms of linear addresses.
+//
+// An allocated block is marked by setting the low-order bit of the 'previous'
+// pointer, which bit is otherwise guaranteed to be 0 due to alignment
+// restrictions. Whenever a block is freed it is immediately merged with the
+// previous and next blocks, if possible. Several places in the block
+// splitting and merging code take advantage of this invariant, and assume
+// that if a block is not already merged with its 'next' partner, then the
+// 'next' partner must be allocated.  Sentinel blocks are allocated at either
+// end of the managed area to avoid special checks for the first and last
+// memory blocks during merging.
+//
+// The 'Two-Level' in TLSF refers to the fact that there are multiple free
+// lists arranged in a 2-dimensional array.  Each free lists contains blocks
+// that fall into a particular size range.  The free list pointers and other
+// data structures described below are carved out of the initial free area
+// when a byte pool is initialized.
+//
+// The first dimension of the free list array is simply the floor(log2(size))
+// of the block. For the second dimension, a tuning parameter selects how many
+// columns each row in the table will contain. The number of columns must be
+// an even power-of-2. Each column represents a fixed power-of-2 size
+// increment of block sizes.  Given a block size, it is easy to compute the
+// row and column indices of a free list containing blocks of that size with
+// shifting and masking operation.
+//
+// It is assumed that the C type 'unsigned long' is the same size as a
+// pointer.  Therefore the number of rows in the table is less than or equal
+// to the number of bits in an unsigned long.  The number of columns is also
+// restricted to being in the range (1, 2, 4, ... number of bits in unsigned
+// long).
+//
+// The above restrictions make it very fast (and constant time) to find a free
+// list that contains a block that will satisfy the allocation request. The
+// byte pool structure maintains a 'row status' word that indicates whether
+// there are any blocks free in any of the free lists of the row.  Each row
+// also has an associated 'column status' word that indicates which free lists
+// have blocks free. A row status bit is set if and only if at least one bit
+// in the column status for that row is set.
+//
+// Note that although the 32-bit PowerPC implementation conceptually contains
+// a 32x32 array of free list pointers, only the free list pointers actually
+// required to hold the representable blocks are allocated. 
+//
+// The algorithm uses the GCC __builtin_clzl() function to count leading zeros
+// in the status words to find rows/columns that contain free blocks.  This
+// generates the 'cntlzw' instruction on 32-bit PowerPC and a similar
+// instruction on X86.  So the algorithm is also portable across machines -
+// which simplifies testing.
+//
+// A couple of final facts: When the application requests memory, the block
+// header overhead is added to the request and we look for a free list
+// guaranteed to contain blocks of the requested size. That means that the
+// request size must be rounded up to the next free list size, to avoid having
+// to search a list that might not contain a block of the proper size. This
+// leads to cases where allocation will fail, even though the requested memory
+// is actually available. That's just the price we have to pay for a
+// constant-time guarantee.
+//
+// This memory allocator will never be used in mission-mode for hard-real-time
+// applications, so the statistics are always kept up-to-date.  This adds some
+// overhead, but does not effect the constant-time behavior.
+// 
+// Given the above description, hopefuly the brief comments with the
+// implementation will make sense.
+
+
+/// The byte pool for use by malloc() and calloc().
+///
+/// The application must define a byte pool and assign it to _malloc_byte_pool
+/// in order for malloc() and calloc() to work.
+
+BytePool *_malloc_byte_pool = 0;
+
+
+// The byte pool memory block header.
+//
+// Each memory block requires 2 pointers of overhead - the pointers to the
+// previous and next (in terms of linear addresses) blocks. The low-order bit
+// of the \a previous pointer is used as the \e allocated flag, and is set
+// when a block is allocated.  The size of a block is computed simply as the
+// \a next - \a self. This header layout makes it very simple to merge blocks
+// when they are deallocated.
+
+typedef struct ByteBlock {
+
+    // Pointer to the previous (in terms of linear address) block.
+    //
+    // The low-order bit of the pointer is set to indicate a block that has
+    // been allocated.
+    struct ByteBlock *previous;
+
+    // Pointer to the next (in terms of linear address) block.
+    //
+    // The size of the block is computed simply as \a next - \a self.
+    struct ByteBlock *next;
+
+} ByteBlock;
+
+
+// A free byte-pool memory block
+//
+// Blocks stored in free lists require an additional 2 pointers of
+// overhead. The blocks are doubly-linked in the free lists to make deletion
+// a constant-time operation.  Note that the previous pointer is a pointer to
+// a pointer to a ByteBlock - it may be pointing to the free list
+// header. Since all blocks must be freeable, this structure defines the
+// minimum block size.
+
+typedef struct FreeByteBlock {
+
+    // The base object
+    ByteBlock block;
+
+    // Pointer to the next block in the free list
+    struct FreeByteBlock *next;
+
+    // Pointer to the \a next pointer of the previous element in the free
+    // list, or a pointer to the free list header.
+    struct FreeByteBlock **previous;
+
+} FreeByteBlock;
+
+
+// All blocks will be aligned to this size, so this size also defines the
+// minimum quantum of memory allocation.  The coice of 8 should give
+// good results for both 32-bit and 64-bit implementations.  
+//
+// NB : This implmentation assumes that the ByteBlock and FreeByteBLock are
+// aligned to this alignment - if this constant is ever changed from 8 then
+// the ByteBlock and FreeByteBlock may need to be padded to meet the alignment
+// assumptions, and the \a minimum_block_size may need to be adjusted.
+
+#define ALIGNMENT 8
+
+
+// An unsigned long, big-endian bit mask
+
+#define UL_BE_MASK(i) \
+    ((unsigned long)1 << (BITS_PER_UNSIGNED_LONG - (i) - 1))
+
+
+// Align a value to the alignment.  The direction is either positive or
+// negative to indicate alignment up or down.
+
+static inline unsigned long
+align(unsigned long x, int direction)
+{
+    if (x % ALIGNMENT) {
+	if (direction > 0) {
+	    return x + (ALIGNMENT - (x % ALIGNMENT));
+	} else {
+	    return x - (x % ALIGNMENT);
+	}	    
+    } else {
+	return x;
+    }
+}
+
+
+// Compute the floor(log2(x)) of x.  This is used to compute the row indices
+// of blocks based on the block size.
+
+static inline int
+floor_log2(unsigned long x)
+{
+    return BITS_PER_UNSIGNED_LONG - 1 - __builtin_clzl(x);
+}
+
+
+// In theory the tuning parameters might vary based on the amount of memory
+// being managed, but for now we simply use constants.  
+// 
+// The minimum block size includes both the size of the header, as well as the
+// requirement that the number of columns be <= the mimumum block size to make
+// the addressing uniform. For example, on PPC405 the minimum block size is 16
+// bytes (4 pointers) -- unless the number of columns is 32, in which case it
+// has to grow to 32 bytes.
+//
+// Note that no matter what, we may allocate free list pointers in the
+// lower-numbered rows that will never be populated due to alignment
+// constraints.
+
+#ifndef BYTE_POOL_TLSF_COLUMNS
+#define BYTE_POOL_TLSF_COLUMNS 8 /* 1,2,4, ... BITS_PER_UNSIGNED_LONG */
+#endif
+
+static void
+compute_tuning(BytePool *pool, size_t size, int columns)
+{
+    int log2_min_size;
+
+    pool->columns = columns;
+    pool->log2_columns = floor_log2(pool->columns);
+    pool->column_mask = (1 << pool->log2_columns) - 1;
+
+    log2_min_size = MAX(pool->log2_columns, floor_log2(sizeof(FreeByteBlock)));
+    pool->minimum_block_size = align(1 << log2_min_size, 1);
+}
+
+
+// Compute the size of a block
+
+static inline size_t
+block_size(ByteBlock *block)
+{
+    return (unsigned long)(block->next) - (unsigned long)block;
+}
+
+
+/// Return implementation information for a block
+///
+/// \param memory The memory block to query.  This pointer must have been
+/// returned by one of the byte_pool functions or derivitives, or may also be
+/// 0. 
+///
+/// \param actual_address : Returned as the address of the block header.
+///
+/// \param actual_size Returned as the size of the complete block, including
+/// the header.
+///
+/// \param useful_size : Returned as the actual amount of space available from
+/// \a memory to the end of the block. The \a useful_size may be useful to
+/// applications that allocate big blocks then carve them up into smaller
+/// structures.
+///
+/// Note that any of \a actual_address, \a actual_size and \a useful_size may
+/// be passed in as 0 if the caller does not require the information.
+
+void
+byte_pool_block_info(void* memory,
+                     void** actual_address, size_t* actual_size,
+                     size_t* useful_size)
+{
+    ByteBlock* block;
+
+    if (memory == 0) {
+
+        if (actual_address) *actual_address = 0;
+        if (actual_size) *actual_size = 0;
+        if (useful_size) *useful_size = 0;
+
+    } else {
+
+        // This implementation uses the convention that if the \a next pointer
+        // of the putative ByteBlock == 1, then this is actually an aligned
+        // allocation and the actual ByteBlock is located at the address
+        // contained in the \a previous field of the dummy header.
+
+        block = (ByteBlock *)(((unsigned long)memory) - sizeof(ByteBlock));
+        if ((int)(block->next) == 1) {
+            block = block->previous;
+        }
+
+        if (actual_address) *actual_address = block;
+        if (actual_size) *actual_size = block_size(block);
+        if (useful_size) 
+            *useful_size = 
+                (unsigned long)(block->next) - (unsigned long)memory;
+    }
+}
+
+
+// Mark a block as allocated by setting the low-order bit of the \a previous
+// pointer.
+
+static inline ByteBlock *
+allocated(ByteBlock *p)
+{
+    return (ByteBlock *)((unsigned long)p | 1ul);
+}
+
+
+static void
+mark_allocated(BytePool *pool, ByteBlock *block)
+{
+    size_t bytes = block_size(block);
+
+    pool->bytes_allocated += bytes;
+    pool->bytes_free -= bytes;
+    pool->blocks_allocated += 1;
+    pool->blocks_free -= 1;
+
+    block->previous = allocated(block->previous);
+}
+
+
+// Mark a block as free by clearing the low-order bit of the \a previous
+// pointer. 
+
+static inline ByteBlock *
+deallocated(ByteBlock *p)
+{
+    return (ByteBlock *)((unsigned long)p & ~1ul);
+}
+
+
+static void
+mark_free(BytePool *pool, ByteBlock *block)
+{
+    size_t bytes = block_size(block);
+
+    pool->bytes_allocated -= bytes;
+    pool->bytes_free += bytes;
+    pool->blocks_allocated -= 1;
+    pool->blocks_free += 1;
+
+    block->previous = deallocated(block->previous);
+}
+
+
+// Check for a block being free
+
+static inline int
+block_is_free(ByteBlock *block)
+{
+    return (((unsigned long)(block->previous)) & 1ul) == 0;
+}
+
+
+// Normalize a 'previous' pointer
+
+static inline ByteBlock *
+normalize_previous(ByteBlock *previous)
+{
+    return (ByteBlock *)((unsigned long)previous & ~1ul);
+}
+
+
+// Check for correct linkage.  This is such a critical check for application
+// memory corruption that it is always done.
+
+static int
+check_linkage(ByteBlock *block)
+{
+    if (normalize_previous(block->next->previous) != block) {
+        printk("byte_pool: Forward linkage error\n"
+               "    block                 : %p\n"
+               "    block->next           : %p\n"
+               "    block->next->previous : %p\n",
+               block,
+               block->next,
+               block->next->previous);
+        SSX_ERROR(BYTE_POOL_REVERSE_LINKAGE);
+    } else if (normalize_previous(block->previous)->next != block) {
+        printk("byte_pool:  linkage error\n"
+               "    block->previous       : %p\n"
+               "    block->pevious->next  : %p\n"
+               "    block                 : %p\n",
+               block->previous,
+               block->previous->next,
+               block);
+        SSX_ERROR(BYTE_POOL_FORWARD_LINKAGE);
+    } 
+    return 0;
+}
+
+
+// Mark a free list as empty
+
+static inline void
+mark_empty(BytePool *pool, int row, int column)
+{
+    pool->column_status[row] &= ~UL_BE_MASK(column);
+    if (pool->column_status[row] == 0) {
+	pool->row_status &= ~UL_BE_MASK(row);
+    }
+}
+
+
+// Mark a free list as non-empty
+
+static inline void
+mark_non_empty(BytePool *pool, int row, int column)
+{
+    pool->column_status[row] |= UL_BE_MASK(column);
+    pool->row_status |= UL_BE_MASK(row);
+}
+
+
+// Convert a size into row and column indices
+
+static inline void
+size2rc(BytePool *pool, size_t size, int *row, int *column)
+{
+    *row = floor_log2(size);
+    *column = (size >> (*row - pool->log2_columns)) & pool->column_mask;
+}    
+
+
+// Given a block size, find the free list that contains blocks of that size
+// (or greater, up to the next free list). When called during block freeing,
+// the block size is known to be valid.  When called during allocation, the
+// block size may be invalid (too big), in which case 0 is returned.
+
+static FreeByteBlock **
+find_free_list(BytePool *pool, size_t size, int *row, int *column)
+{
+    size2rc(pool, size, row, column);
+    if (*row > pool->last_row) {
+	return 0;
+    }
+    return &((pool->free[*row])[*column]);
+}
+
+
+// Remove an arbitrary block from its free list due to a merging operation.
+
+static void 
+unlink_free_block(BytePool *pool, ByteBlock *block)
+{
+    FreeByteBlock **free_list;
+    FreeByteBlock *free_block;
+    int row, column;
+
+    free_list = find_free_list(pool, block_size(block), &row, &column);
+
+    if (SSX_ERROR_CHECK_KERNEL) {
+	if (free_list == 0) {
+	    SSX_PANIC(BYTE_POOL_NULL_FREE_LIST);
+	}
+    }
+
+    // Unlink the block from the free list
+
+    free_block = (FreeByteBlock *)block;
+    *(free_block->previous) = free_block->next;
+    if (free_block->next) {
+	free_block->next->previous = free_block->previous;
+    }
+
+    // If the free list is now 0, mark the free list as empty.
+
+    if (*free_list == 0) {
+	mark_empty(pool, row, column);
+    }
+}
+
+
+// Link a block into the head of its free list due to freeing memory
+
+static void 
+link_free_block(BytePool *pool, ByteBlock *block)
+{
+    FreeByteBlock **free_list;
+    FreeByteBlock *free_block;
+    int row, column;
+
+    free_list = find_free_list(pool, block_size(block), &row, &column);
+
+    if (SSX_ERROR_CHECK_KERNEL) {
+	if (free_list == 0) {
+	    SSX_PANIC(BYTE_POOL_NULL_FREE_LIST);
+	}
+    }
+
+    // Link the block into the free list, and mark the free list as
+    // non-empty. 
+
+    free_block = (FreeByteBlock *)block;
+
+    free_block->next = *free_list;
+    if (*free_list) {
+	(*free_list)->previous = &(free_block->next);
+    }
+    *free_list = free_block;
+    free_block->previous = free_list;
+
+    mark_non_empty(pool, row, column);
+}
+
+
+// Round up the block size (if required) to the next column. Note that the
+// block_size input here is aligned, and remains aligned even after rounding.
+
+static size_t
+round_up_size(BytePool *pool, size_t block_size)
+{
+    size_t residue, column_span, column_mask;
+    int row = floor_log2(block_size);
+
+    column_span = 1 << (row - pool->log2_columns);
+    column_mask = column_span - 1;
+    residue = block_size & column_mask;
+
+    if (residue == 0) {
+    	return block_size;
+    } else {
+    	return block_size + (column_span - residue);
+    } 
+}
+
+
+// The implemenation of freeing a block of memory. When freed, a block is
+// immediately merged with its neighbors if possible, and the final merged
+// block is inserted into the proper free list.
+//
+// The linkage check is done here so that it can also protect internal uses of
+// this API (but only if SSX errors lead to panics, the expected default).
+
+static int
+byte_pool_free_block(BytePool *pool, ByteBlock *block)
+{
+    int rc;
+    SsxMachineContext ctx;
+
+    rc = check_linkage(block);
+    if (rc) return rc;
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    pool->free_calls++;
+
+    mark_free(pool, block);
+
+    if (block_is_free(block->next)) {
+
+	// Merge next block into current block
+
+	unlink_free_block(pool, block->next);
+
+	block->next = (ByteBlock *)((unsigned long)(block->next) +
+				    block_size(block->next));
+	block->next->previous = allocated(block);
+
+	pool->blocks_free--;
+    }
+
+    if (block_is_free(block->previous)) {
+
+	// Merge current block into previous block
+
+	unlink_free_block(pool, block->previous);
+
+	block->previous->next = 
+	    (ByteBlock *)((unsigned long)(block->previous->next) +
+			  block_size(block));
+	block = block->previous;
+	block->next->previous = allocated(block);
+
+	pool->blocks_free--;
+    }
+
+    // Finally, insert the block into the proper free list.
+
+    link_free_block(pool, block);
+
+    ssx_critical_section_exit(&ctx);
+
+    return 0;
+}
+
+
+/// Free a block of memory back to a byte pool
+///
+/// \param pool A pointer to the BytePool structure that allocated the memory.
+///
+/// \param memory A pointer to memory returned by byte_pool_alloc() or
+/// byte_pool_alloc_aligned() for the pool.  This pointer may be NULL (0), in
+/// which case the byte_pool_free() request succeeds immediately.
+///
+/// The part of this API that manipulates the \a pool runs as an
+/// SSX_NONCRITICAL critical section. byte_pool_free() uses a constant-time
+/// algorithm.
+///
+/// Return values other then SSX_OK (0) are errors; see \ref ssx_errors
+///
+/// \retval 0 Success
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a pool argument was NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT The block is not marked as being
+/// allocated, or does not appear to have been allocated from this byte_pool.
+///
+/// \retval -BYTE_POOL_LINKAGE_ERROR The block being freed is not linked
+/// correctly with the other blocks managed by the pool, most likely
+/// indicating that the memory being freed was not allocated by
+/// byte_pool_alloc(), or that memory corruption has occured.
+
+// This implementation uses the convention that if the \a next pointer of the
+// putative ByteBlock == 1, then this is actually an aligned allocation and
+// the actual ByteBlock is located at the address contained in the \a previous
+// field of the dummy header.
+
+int
+byte_pool_free(BytePool *pool, void *memory)
+{
+    ByteBlock *block;
+
+    if (memory == 0) {
+	return 0;
+    }
+
+    block = (ByteBlock *)(((unsigned long)memory) - sizeof(ByteBlock));
+    if ((int)(block->next) == 1) {
+        if (0) {
+            printk("byte_pool_free(%p, %p) [%p] : Aligned\n",
+                   pool, memory, block);
+        }
+        block = block->previous;
+    }
+
+    if (0) {
+	printk("byte_pool_free(%p, %p) [%p] : %d %d %d\n",
+               pool, memory, block,
+               block_is_free(block), 
+               block < pool->first_block,
+               block > pool->last_block);
+    }
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(pool == 0, BYTE_POOL_INVALID_OBJECT);
+	SSX_ERROR_IF(block_is_free(block)        ||
+		     (block < pool->first_block) ||
+		     (block > pool->last_block), 
+		     BYTE_POOL_INVALID_ARGUMENT);
+    }
+
+    return byte_pool_free_block(pool, block);
+}
+
+
+/// Create a BytePool with explicit specification of tuning parameters
+///
+/// This routine is the real body of byte_pool_create(), however this
+/// underlying interface is provided for testing and experimentation and allows
+/// the specification of non-default tuning parameters.  
+///
+/// There is actually only one tuning parameter for TLSF - the number of
+/// columns.  The number of columns must be an even power of two no larger
+/// than the number of bits in an unsigned long.
+///
+/// Return values other then SSX_OK (0) are errors; see \ref ssx_errors
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a pool pointer was NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT Either the \a memory pointer was NULL
+/// (0), the amount of memory was insufficient for the management overhead, or
+/// the parameterization was invalid.
+
+int
+byte_pool_create_tuned(BytePool *pool, void *memory, size_t size,
+		       int columns)
+{
+    size_t overhead, free_list_overhead;
+    unsigned long memory_ul, aligned_memory;
+    int i;
+    FreeByteBlock **free;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(pool == 0, BYTE_POOL_INVALID_OBJECT);
+	SSX_ERROR_IF((memory == 0) ||
+		     (columns < 1) ||
+		     ((columns & (columns - 1)) != 0) ||
+		     (floor_log2(columns) > floor_log2(BITS_PER_UNSIGNED_LONG)),
+		     BYTE_POOL_INVALID_ARGUMENT);
+    }
+
+    // Compute tuning parameters
+
+    compute_tuning(pool, size, columns);
+
+    // Clear free list vector pointers and column status
+    
+    for (i = 0; i < BITS_PER_UNSIGNED_LONG; i++) {
+	pool->free[i] = 0;
+	pool->column_status[i] = 0;
+    }
+
+    // Determine the first and last allocated rows. 
+
+    pool->first_row = floor_log2(pool->minimum_block_size);
+    pool->last_row = floor_log2(size);
+
+    // The dynamic overhead consists of aligment overhead, 2 sentinel nodes,
+    // the vectors of pointers to free lists, plus 2 alignments. There must
+    // also be enough room for at least 1 block to allocate.
+
+    memory_ul = (unsigned long)memory;
+    aligned_memory = align(memory_ul, 1);
+
+    free_list_overhead = 
+	(((pool->last_row - pool->first_row + 1) * pool->columns) * 
+	 sizeof(FreeByteBlock *));
+
+    overhead = 
+	(aligned_memory - memory_ul) +
+	(2 * sizeof(ByteBlock)) +
+	free_list_overhead +
+	(2 * ALIGNMENT) +
+	pool->minimum_block_size;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(overhead >= size, BYTE_POOL_INVALID_ARGUMENT);
+    }
+	
+    // Allocate the overhead items. The free list vectors and column status
+    // arrays are carved out and zeroed. For good measure we re-align after
+    // each of these operations. The sentinel blocks are carved off of either
+    // end of the remaining free space and marked allocated.  The remaining
+    // initial "big block" is also initialized (as if it were allocated).
+
+    size = size - (aligned_memory - memory_ul);
+    size = align(size, -1);
+    
+    pool->row_status = 0;
+
+    free = (FreeByteBlock **)aligned_memory;
+    memset((void *)free, 0, free_list_overhead);
+
+    aligned_memory += free_list_overhead;
+    size -= free_list_overhead;
+    aligned_memory = align(aligned_memory, 1);
+    size = align(size, -1);
+
+    for (i = pool->first_row; i <= pool->last_row; i++) {
+	pool->free[i] = free;
+	free += pool->columns;
+    }
+
+    pool->first_block = (ByteBlock *)aligned_memory;
+    aligned_memory += sizeof(ByteBlock);
+    size -= sizeof(ByteBlock);
+
+    pool->big_block = (ByteBlock *)aligned_memory;
+
+    pool->last_block = 
+	(ByteBlock *)(aligned_memory + size - sizeof(ByteBlock));
+    size -= sizeof(ByteBlock);
+
+    pool->first_block->next = pool->big_block;
+    pool->first_block->previous = 0;
+    mark_allocated(pool, pool->first_block);
+
+    pool->last_block->next = 0;
+    pool->last_block->previous = pool->big_block;
+    mark_allocated(pool, pool->last_block);
+
+    pool->big_block->previous = pool->first_block;
+    pool->big_block->next = pool->last_block;
+
+    // Initialize statistics
+
+    pool->bytes_allocated = 0;
+    pool->bytes_free = block_size(pool->big_block);
+    pool->initial_allocation = pool->bytes_free;
+    pool->blocks_allocated = 0;
+    pool->blocks_free = 1;
+    pool->alloc_calls = 0;
+    pool->free_calls = 0;
+
+    // Free the big block and we're ready to go.
+
+    mark_allocated(pool, pool->big_block);
+    byte_pool_free_block(pool, pool->big_block);
+
+    return 0;
+}
+
+
+/// Create a BytePool
+///
+/// \param pool A pointer to an uninitialized BytePool structure
+///
+/// \param memory A pointer to the memory to be managed by the BytePool
+///
+/// \param size The size of the managed area in bytes
+///
+/// byte_pool_create() sets up the \a memory area to be used as a memory pool
+/// for malloc()-style allocation using byte_pool_alloc() and
+/// byte_pool_free().  Note that the actual memory area available for
+/// allocation will be smaller than \a size due to alignment, and reservation
+/// of a portion of the area for management overhead.
+///
+/// Return values other then SSX_OK (0) are errors; see \ref ssx_errors
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a pool pointer was NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT Either the \a memory pointer was NULL
+/// (0), the amount of memory was insufficient for the management overhead, or
+/// the parameterization was invalid.
+
+int
+byte_pool_create(BytePool *pool, void *memory, size_t size)
+{
+    return byte_pool_create_tuned(pool, memory, size, BYTE_POOL_TLSF_COLUMNS);
+}
+
+
+/// Allocate memory from a byte pool
+///
+/// \param pool A pointer to an initialized BytePool
+///
+/// \param memory An address to recieve a pointer to the allocated memory.
+/// This address will be set to NULL (0) if the allocation request can not be
+/// satisfied (or the \a size is 0).
+///
+/// \param size The number of bytes to allocate.
+///
+/// The part of this API that manipulates the \a pool runs as an
+/// SSX_NONCRITICAL critical section. byte_pool_alloc() uses a constant-time
+/// algorithm.
+///
+/// Return values other than 0 are not necessarily errors; see \ref
+/// ssx_errors.   
+///
+/// The following return codes are not considered errors:
+///
+/// \retval 0 Success
+///
+/// \retval -BYTE_POOL_NO_MEMORY The allocation request could not be
+/// satisfied.  The memory pointer will also be NULL (0) in this case.
+///
+/// The following return codes are considered errors:
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a pool argument was NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT The \a memory argument is NULL (0).
+
+int
+byte_pool_alloc(BytePool *pool, void **memory, size_t size)
+{
+    SsxMachineContext ctx;
+    size_t request_size, actual_size;
+    int found, row, column;
+    unsigned long row_status, column_status;
+    FreeByteBlock **free_list;
+    FreeByteBlock *free_block;
+    ByteBlock *block;
+    ByteBlock *residue_block;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(pool == 0, BYTE_POOL_INVALID_OBJECT);
+	SSX_ERROR_IF(memory == 0, BYTE_POOL_INVALID_ARGUMENT);
+    }
+
+    // Quickly dispense with NULL requests
+
+    if (size == 0) {
+	*memory = 0;
+	return 0;
+    }
+
+    // Compute the requested block size (which includes the header).  If the
+    // size went down we overflowed due to a huge request (which can't be
+    // filled).  Otherwise if the request is small it is boosted up to the
+    // (aligned) minimum size.  To guarantee fast search, the requested size
+    // must then be rounded up to a size that is represented in the 2-D array
+    // of free list pointers.
+
+    request_size = align(size + sizeof(ByteBlock), 1);
+    if (request_size < size) {
+        *memory = 0;
+        return -BYTE_POOL_NO_MEMORY;
+    }
+
+    if (request_size < pool->minimum_block_size) {
+	request_size = pool->minimum_block_size;
+    }
+
+    request_size = round_up_size(pool, request_size);
+
+    // Up to this point, all accesses of the memory pool object have been to
+    // read only constants. Now we get serious.
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    pool->alloc_calls++;
+
+    // See if a block of the correct or larger size exists in the row.  The
+    // search is first via a single bit in the row_status. If that hits then
+    // we check for columns >= the target column.
+
+    found = 0;
+    size2rc(pool, request_size, &row, &column);
+
+    if (pool->row_status & UL_BE_MASK(row)) {
+
+	column_status = pool->column_status[row] &
+	    ((UL_BE_MASK(column) << 1) - 1);
+
+	if (column_status != 0) {
+	    column = __builtin_clzl(column_status);
+	    found = 1;
+	}
+    }
+
+    // If the block was not found in the 'optimum' row, look in all rows of
+    // larger size and take the first block that fits.
+
+    if (!found) {
+
+	row_status = pool->row_status & (UL_BE_MASK(row) - 1);
+
+	if (row_status != 0) {
+	    row = __builtin_clzl(row_status);
+	    column = __builtin_clzl(pool->column_status[row]);
+	    found = 1;
+	}
+    }
+
+    // Another out of memory case.
+
+    if (!found) {
+	ssx_critical_section_exit(&ctx);
+	*memory = 0;
+	return -BYTE_POOL_NO_MEMORY;
+    }
+
+    // Now we can get the pointer to the free list and take the block. 
+
+    free_list = &((pool->free[row])[column]);
+
+    if (SSX_ERROR_CHECK_KERNEL) {
+	if ((free_list == 0) || (*free_list == 0)) {
+	    SSX_PANIC(BYTE_POOL_INVALID_FREE_LIST);
+	}
+    }
+
+    free_block = *free_list;
+    *free_list = free_block->next;
+    if (free_block->next) {
+	free_block->next->previous = free_list;
+    } else {
+	mark_empty(pool, row, column);
+    }
+
+    // Mark the block as allocated
+
+    block = (ByteBlock *)free_block;
+    mark_allocated(pool, block);
+
+    // If there is enough residue, split the excess memory off of the end of
+    // the block.  This is a kind of dummy transaction for our statistical
+    // purposes.
+
+    actual_size = block_size(block);
+    if ((actual_size - request_size) >= pool->minimum_block_size) {
+
+	residue_block = (ByteBlock *)((unsigned long)block + request_size);
+
+	residue_block->next = block->next;
+	residue_block->previous = block;
+	residue_block->previous->next = residue_block;
+	residue_block->next->previous = allocated(residue_block);
+
+	pool->blocks_allocated++;
+	byte_pool_free_block(pool, residue_block);
+	pool->free_calls--;
+    }
+
+    // Set the memory pointer to the area to be used by the application and
+    // return.
+
+    *memory = (void *)((unsigned long)block + sizeof(ByteBlock));
+
+    ssx_critical_section_exit(&ctx);
+
+    if (0) {
+        ByteBlock* block = 
+            (ByteBlock*)((unsigned long)*memory - sizeof(ByteBlock));
+
+        printk("byte_pool_alloc(%p, -> %p, %zu)\n"
+               "    request_size = %u, Previous = %p, Next = %p\n",
+               pool, *memory, size,
+               request_size, block->previous, block->next);
+    }
+
+    return 0;
+}
+
+
+/// Allocate memory from a byte pool and clear
+///
+/// byte_pool_calloc() allocates memory using byte_pool_alloc() then clears
+/// the memory area using memset().  The arguments conform to the POSIX
+/// standard for calloc(). See byte_pool_alloc() for return codes and usage
+/// notes.
+
+int
+byte_pool_calloc(BytePool *pool, void **memory, size_t nmemb, size_t size)
+{
+    int rc;
+
+    rc = byte_pool_alloc(pool, memory, nmemb * size);
+    if (rc || (*memory == 0)) {
+	return rc;
+    }
+
+    memset(*memory, 0, nmemb * size);
+
+    return 0;
+}
+
+
+/// Allocate an aligned memory area
+///
+/// \param pool A pointer to an initialized BytePool
+///
+/// \param memory An address to recieve a pointer to the allocated memory.
+/// This address will be set to NULL (0) if the allocation request can not be
+/// satisfied (or the \a size is 0).
+///
+/// \param size The size of the memory area required (in bytes). This can be
+/// any size - it \e does \e not have to be a multiple of the aligned size (as
+/// is required by other common aligned memory allocators).
+///
+/// \param alignment The alignment constraint, specified as the base 2
+/// logarithm of the alignment.  For example, to align on a 128-byte boundary
+/// the \a alignment would be specified as 7.
+///
+/// byte_pool_alloc_aligned() is a convenience interface for allocating memory
+/// with a guaranteed alignment. The BytePool APIs do not normally do aligned
+/// allocation. byte_pool_alloc_aligned() first uses byte_pool_alloc() to
+/// allocate a block of memory large enough to satisfy the request and
+/// guarantee that a subset of the memory allocation will satisfy the
+/// alignment constraint plus the overhead of a dummy block header.  Note that
+/// it is space-inefficient to allocate many small aligned areas. If possble
+/// it would be better to allocate a single aligned area and then have the
+/// application partition the memory as required.
+///
+/// Memory areas allocated by byte_pool_alloc_aligned() can be freed with
+/// byte_pool_free(), just like any other dynamic memory allocation.
+///
+/// The part of this API that manipulates the \a pool runs as an
+/// SSX_NONCRITICAL critical section. The underlying call of byte_pool_alloc()
+/// uses a constant-time algorithm.
+///
+/// Return values other than 0 are not necessarily errors; see \ref
+/// ssx_errors.   
+///
+/// The following return codes are not considered errors:
+///
+/// \retval 0 Success
+///
+/// \retval -BYTE_POOL_NO_MEMORY The allocation request could not be
+/// satisfied.  The memory pointer will also be NULL (0) in this case.
+///
+/// The following return codes are considered errors:
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a pool argument was NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT The \a memory argument is NULL (0), or
+/// the \a alignment argument is invalid.
+
+// The allocation must be big enough for the size requested + the alignment
+// amount (to guarantee alignment) + room for a dummy ByteBlock.  The dummy
+// ByteBlock is marked by setting the \a next pointer to 1 to indicate that
+// this is an aligned allocation.  In this case the \a previous pointer of the
+// dummy ByteBlock points to the ByteBlock of the original allocation.
+
+int
+byte_pool_alloc_aligned(BytePool *pool, void **memory, size_t size, 
+			int alignment)
+{
+    int rc;
+    unsigned long pow2_alignment, mask, aligned;
+    void *unaligned_memory;
+    ByteBlock *dummy_block, *unaligned_block;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF((alignment < 1) || (alignment >= BITS_PER_UNSIGNED_LONG),
+		     BYTE_POOL_INVALID_ARGUMENT);
+    }
+
+    pow2_alignment = (unsigned long)1 << (unsigned long)alignment;
+    mask = pow2_alignment - 1;
+
+    rc = byte_pool_alloc(pool, &unaligned_memory, 
+			 size + pow2_alignment + sizeof(ByteBlock));
+
+    if (rc || (unaligned_memory == 0)) {
+	*memory = 0;
+	return rc;
+    }
+    unaligned_block = (ByteBlock *)(((unsigned long)unaligned_memory) - 
+                                    sizeof(ByteBlock));
+
+    aligned = (unsigned long)unaligned_memory + sizeof(ByteBlock);
+    if (aligned & mask) {
+	aligned += (pow2_alignment - (aligned & mask));
+    }
+    *memory = (void *)aligned;
+    
+    dummy_block = (ByteBlock *)(aligned - sizeof(ByteBlock));
+    dummy_block->previous = unaligned_block;
+    dummy_block->next = (ByteBlock*)1;
+
+    if (0) {
+        printk("byte_pool_alloc_aligned(%p, -> %p, %zu, %d)\n",
+               pool, *memory, size, alignment);
+    }
+
+    return 0;
+}
+
+
+/// Allocate aligned memory from a byte pool and clear
+///
+/// byte_pool_calloc_alligned() allocates memory using
+/// byte_pool_alloc_aligned() then clears the memory area using memset().  The
+/// arguments conform to the POSIX standard for calloc(). See
+/// byte_pool_alloc_aligned() for return codes and usage notes. In particular
+/// note that this memory must be freed with byte_pool_free_aligned().
+
+int
+byte_pool_calloc_aligned(BytePool *pool, void **memory, 
+			 size_t nmemb, size_t size, int alignment)
+{
+    int rc;
+
+    rc = byte_pool_alloc_aligned(pool, memory, nmemb * size, alignment);
+    if (rc || (*memory == 0)) return rc;
+
+    memset(*memory, 0, nmemb * size);
+
+    return 0;
+}
+
+
+/// malloc() allocates \a size bytes and returns a pointer to the allocated
+/// memory.  The memory is not cleared. The value returned is a pointer to the
+/// allocated memory, which is suitably aligned for any kind of variable, or
+/// NULL if the requested \a size is 0 or the request fails.
+///
+/// NB: The aplication must create and assign a BytePool object to the
+/// library variable _malloc_byte_pool in order for malloc() to work.
+
+void *
+malloc(size_t size)
+{
+    void *memory;
+
+    if (byte_pool_alloc(_malloc_byte_pool, &memory, size)) {
+	memory = 0;
+    }
+    return memory;
+}
+
+
+/// calloc() allocates memory for an array of \a nmemb elements of \a size
+/// bytes each and returns a pointer to the allocated memory.  The memory is
+/// set to zero. The value returned is a pointer to the allocated and cleared
+/// memory, which is suitably aligned for any kind of variable, or NULL if the
+/// requested \a size is 0 or the request fails.
+///
+/// NB: The aplication must create and assign a BytePool object to the
+/// library variable _malloc_byte_pool in order for calloc() to work.
+
+void *
+calloc(size_t nmemb, size_t size)
+{
+    void *memory;
+
+    if (byte_pool_calloc(_malloc_byte_pool, &memory, nmemb, size)) {
+	return 0;
+    }
+    return memory;
+}
+
+
+/// free() frees the memory space pointed to by \a ptr, which must have been
+/// returned by a previous call to malloc(), posix_memalign, calloc() or
+/// realloc().  Otherwise, or if free(ptr) has already been called before,
+/// undefined behavior occurs.  If \a ptr is NULL, no operation is performed.
+///
+/// NB: The aplication must create and assign a BytePool object to the
+/// library variable _malloc_byte_pool in order for free() to work.
+
+void
+free(void *ptr)
+{
+    byte_pool_free(_malloc_byte_pool, ptr);
+}
+
+
+/// realloc() changes the size of the memory block pointed to by \a ptr to \a
+/// size bytes.  The contents will be unchanged to the minimum of the old and
+/// new sizes; newly allocated memory will be uninitialized.  If \a ptr is
+/// NULL, the call is equivalent to malloc(size); if \a size is equal to zero,
+/// the call is equivalent to free(ptr).  Unless \a ptr is NULL, it must have
+/// been returned by an earlier call to malloc(), calloc() or realloc().  If
+/// the area pointed to was moved, a free(ptr) is done.
+///
+/// realloc() returns a pointer to the newly allocated memory, which is
+/// suitably aligned for any kind of variable and may be different from \a
+/// ptr, or NULL if the request fails.  If \a size was equal to 0, either NULL
+/// or a pointer suitable to be passed to free() is returned.  If realloc()
+/// fails the original block is left untouched; it is not freed or moved.
+
+void*
+realloc(void *ptr, size_t size)
+{
+    void *memory;
+    size_t useful_size;
+
+    // Handle simple case
+
+    if (ptr == 0) {
+
+        memory = malloc(size);
+
+    } else if (size == 0) {
+
+        free(ptr);
+        memory = 0;
+
+    } else {
+
+        // Find out the useful size of the block. If we need more than this we
+        // need to allocate a new block and memcpy() the old data to the new
+        // block and free the old block. If we need less then this we also
+        // need to allocate a new block and move the head of the current
+        // data. If the new size is the same as the current size we do nothing.
+
+        byte_pool_block_info(ptr, 0, 0, &useful_size);
+
+        if (size == useful_size) {
+
+            memory = ptr;
+
+        } else {
+
+            memory = malloc(size);
+            if (memory != 0) {
+                memcpy(memory, ptr, (size > useful_size) ? useful_size : size);
+                free(ptr);
+            }
+        }
+    }
+    return memory;
+}
+
+
+/// The posix_memalign() function allocates \a size bytes aligned on a
+/// boundary specified by \a alignment, and returns a pointer to the allocated
+/// memory in \a memptr. The value of \a alignment shall be a multiple of
+/// sizeof(void*), that is also a power of two. Upon successful completion,
+/// the value pointed to by \a memptr will be a multiple of alignment.
+///
+/// Note that memory allocated with posix_memalign() can be freed with
+/// free(). 
+///
+/// In the event of errors, the contents of \a memptr will be returned as 0.
+///
+/// The following return codes are mandated by POSIX, and are always returned
+/// in the event of the specified condition. 
+///
+/// \retval 0 Success
+///
+/// \retval -EINVAL The value of the \a alignment parameter is not a power of
+/// two multiple of sizeof(void*).
+///
+/// \retval -ENOMEM There is insufficient memory available with the requested
+/// alignment.
+///
+/// The following return codes are implementation-specific and may be
+/// configured to cause a kernel panic.
+///
+/// \retval -BYTE_POOL_INVALID_OBJECT The \a _malloc_byte_pool is NULL (0).
+///
+/// \retval -BYTE_POOL_INVALID_ARGUMENT The \a memptr argument is NULL (0).
+
+int
+posix_memalign(void** memptr, size_t alignment, size_t size)
+{
+    int rc;
+
+    if (((alignment & (alignment - 1)) != 0) ||
+        (alignment < sizeof(void*))) {
+        rc = -EINVAL;
+    } else {
+        rc = byte_pool_alloc_aligned(_malloc_byte_pool, memptr, size,
+                                     floor_log2(alignment));
+        if (!rc && (*memptr == 0)) {
+            rc = -ENOMEM;
+        }
+    }
+    if (rc && memptr) {
+        *memptr = 0;
+    }
+    return rc;
+}
+
+
+/// Print a dump of a byte pool, including the header and allocation report
+///
+/// \param stream The stream to receive the dump
+///
+/// \param pool The BytePool object to dump
+///
+/// \bug This routine is not thread safe.
+
+void
+byte_pool_report(FILE* stream, BytePool* pool)
+{
+    ByteBlock* block;
+    uint8_t* p8;
+    uint32_t* p32;
+    int i;
+
+    fprintf(stream, ">>> Byte Pool Report for Pool %p <<<\n", pool);
+
+    fprintf(stream, ">>> BytePool Object Dump <<<\n");
+
+#define DUMPIT(x, fmt)                                  \
+    fprintf(stream, "%20s : " #fmt "\n", #x, pool->x)
+
+    DUMPIT(first_row, %d);
+    DUMPIT(last_row, %d);
+    DUMPIT(columns, %d);
+    DUMPIT(log2_columns, %d);
+    DUMPIT(column_mask, 0x%08x);
+    DUMPIT(minimum_block_size, %d);
+    DUMPIT(free, %p);
+    DUMPIT(column_status, %p);
+    DUMPIT(row_status, %lu);
+    DUMPIT(first_block, %p);
+    DUMPIT(big_block, %p);
+    DUMPIT(last_block, %p);
+    DUMPIT(initial_allocation, %d);
+    DUMPIT(bytes_allocated, %d);
+    DUMPIT(bytes_free, %d);
+    DUMPIT(blocks_allocated, %d);
+    DUMPIT(blocks_free, %d);
+    DUMPIT(alloc_calls, %d);
+    DUMPIT(free_calls, %d);
+
+    fprintf(stream, ">>> Byte Pool Allocation Report <<<\n");
+    fprintf(stream, 
+            ">>> status :   address  :  size  :      binary[0:7]      : ASCII[0:7] <<<\n");
+
+    for (block = pool->first_block->next; 
+         block != pool->last_block;
+         block = block->next) {
+
+        fprintf(stream, "      %c    : %p : %6zu : ",
+                (block_is_free(block) ? 'F' : 'A'),
+                block, block_size(block));
+
+        p8 = (uint8_t*)((unsigned long)block + sizeof(ByteBlock));
+        p32 = (uint32_t*)p8;
+
+        fprintf(stream, "0x%08x 0x%08x : ", p32[0], p32[1]);
+        for (i = 0; i < 8; i++) {
+            if (isprint(p8[i])) {
+                fputc(p8[i], stream);
+            } else {
+                fputc('.', stream);
+            }
+        }                
+        fputc('\n', stream);
+    }
+
+    fprintf(stream, ">>> End Report <<<\n");
+}
diff --git a/src/lib/ppc405lib/byte_pool.h b/src/lib/ppc405lib/byte_pool.h
new file mode 100644
index 0000000..8766745
--- /dev/null
+++ b/src/lib/ppc405lib/byte_pool.h
@@ -0,0 +1,166 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/byte_pool.h $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __BYTE_POOL_H__
+#define __BYTE_POOL_H__
+
+// $Id$
+
+#ifndef __ASSEMBLER__
+
+#include "ssx_io.h"
+
+struct ByteBlock;
+struct FreeByteBlock;
+
+// A handy constant
+
+#define BITS_PER_UNSIGNED_LONG (8 * sizeof(unsigned long))
+
+
+/// A control structure for a byte pool. The application will never modify the
+/// structure fields directly, but some applications may be interested in
+/// reading the statistics.
+
+typedef struct {
+
+    // The index of the first allocated row of free list pointers
+    int first_row;
+
+    // The index of the last allocated row of free list pointers
+    int last_row;
+
+    // The number of columns in each row of free list pointers
+    int columns;
+
+    // The log2 of the number of columns in each row of free list pointers
+    int log2_columns;
+
+    // The shifted block size is ANDed with this mask to extract the column
+    // number. 
+    size_t column_mask;
+
+    // The minimum block size.
+    int minimum_block_size;
+
+    // The vectors of free list pointers
+    struct FreeByteBlock **free[BITS_PER_UNSIGNED_LONG];
+
+    // The array of column status bit masks
+    unsigned long column_status[BITS_PER_UNSIGNED_LONG];
+
+    // The row status bit mask
+    unsigned long row_status;
+
+    // A sentinel node - the first allocated block.  Kept for error checking
+    // purposes.
+    struct ByteBlock *first_block;
+
+    // The initial memory allocation. Kept here only for debugging purposes. 
+    struct ByteBlock *big_block;
+
+    // A sentinel node - the last allocated block.  Kept here for error
+    // checking purposes.
+    struct ByteBlock *last_block;
+
+    // The initial allocation. Kept here for debugging and statistics.
+    size_t initial_allocation;
+
+    // The total number of bytes currently allocated (excludes overhead)
+     size_t bytes_allocated;
+
+    // The total number of bytes currently free in the pool
+     size_t bytes_free;
+
+    // The total number of blocks allocated from the pool
+     size_t blocks_allocated;
+
+    // The total number of blocks free in the pool
+     size_t blocks_free;
+
+    // The number of calls to allocate memory
+     size_t alloc_calls;
+
+    // The number of calls to free memory
+     size_t free_calls;
+
+} BytePool;
+
+extern BytePool *_malloc_byte_pool;
+
+int
+byte_pool_create(BytePool *pool, void *memory, size_t size);
+
+int
+byte_pool_create_tuned(BytePool *pool, void *memory, size_t size,
+		       int columns);
+
+int
+byte_pool_alloc(BytePool *pool, void **memory, size_t size);
+
+int
+byte_pool_calloc(BytePool *pool, void **memory, size_t nmemb, size_t size);
+
+int
+byte_pool_free(BytePool *pool, void *memory);
+
+void
+byte_pool_block_info(void* memory,
+                     void** actual_address, size_t* actual_size,
+                     size_t* useful_size);
+
+int
+byte_pool_alloc_aligned(BytePool *pool, void **memory, size_t size, 
+			int alignment);
+
+void *
+malloc(size_t size);
+
+void *
+calloc(size_t nmemb, size_t size);
+
+void
+free(void *ptr);
+
+int
+posix_memalign(void** memptr, size_t alignment, size_t size);
+
+void
+byte_pool_report(FILE* stream, BytePool* pool);
+
+#endif	/* __ASSEMBLER__ */
+
+
+// Error/panic codes
+
+#define BYTE_POOL_INVALID_OBJECT    0x00b98e01
+#define BYTE_POOL_INVALID_ARGUMENT  0x00b98e02
+#define BYTE_POOL_REVERSE_LINKAGE   0x00b98e03
+#define BYTE_POOL_FORWARD_LINKAGE   0x00b98e04
+#define BYTE_POOL_NO_MEMORY         0x00b98e05
+
+#define BYTE_POOL_NULL_FREE_LIST    0x00b98e10
+#define BYTE_POOL_INVALID_FREE_LIST 0x00b98e11
+
+#endif	/* __BYTE_POOL_H__ */
diff --git a/src/lib/ppc405lib/chip_config.h b/src/lib/ppc405lib/chip_config.h
new file mode 100644
index 0000000..cc772e2
--- /dev/null
+++ b/src/lib/ppc405lib/chip_config.h
@@ -0,0 +1,109 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/chip_config.h $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __CHIP_CONFIG_H__
+#define __CHIP_CONFIG_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file chip_config.h
+/// \brief Chip configuration data structures for OCC procedures
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/// A bitmask defining a chip configuration
+///
+/// Since we are using the conventional big-endian notation, any use of these 
+/// bitmasks requires that the data being tested is of this type - otherwise
+/// the masks won't work.  
+///
+/// Layout: 
+///
+/// Bits 0:15  - Core chiplet 0..15 is configured
+/// Bits 16:23 - MCS 0..7 is configured
+/// Bits 24:31 - Centaur 0..7 is configured
+
+typedef uint64_t ChipConfig;
+typedef uint16_t ChipConfigCores;
+typedef uint8_t  ChipConfigMcs;
+typedef uint8_t  ChipConfigCentaur;
+
+
+/// Convert a ChipConfig into a mask suitable for use as the 32-bit chiplet
+/// mask argument of a PORE wakeup program.
+#if 0
+static inline uint32_t 
+pore_exe_mask(ChipConfig config)
+{
+    return (uint32_t)((config >> 32) & 0xffff0000);
+}
+#endif
+
+/// Left justify and mask core chiplet configuration into a uint32_t
+
+static inline uint32_t
+left_justify_core_config(ChipConfig config)
+{
+    return (uint32_t)((config >> 32) & 0xffff0000);
+}
+
+/// Left justify and mask MCS configuration into a uint32_t
+
+static inline uint32_t
+left_justify_mcs_config(ChipConfig config)
+{
+    return (uint32_t)((config >> 16) & 0xff000000);
+}
+
+/// Left justify and mask Centaur configuration into a uint32_t
+
+static inline uint32_t
+left_justify_centaur_config(ChipConfig config)
+{
+    return (uint32_t)((config >> 8) & 0xff000000);
+}
+
+#endif // __ASSEMBLER__
+
+
+#define CHIP_CONFIG_CORE_BASE 0
+#define CHIP_CONFIG_CORE(n) \
+    ((0x8000000000000000ull >> CHIP_CONFIG_CORE_BASE) >> (n))
+
+#define CHIP_CONFIG_MCS_BASE 16
+#define CHIP_CONFIG_MCS(n) \
+    ((0x8000000000000000ull >> CHIP_CONFIG_MCS_BASE) >> (n))
+
+#define CHIP_CONFIG_CENTAUR_BASE 24
+#define CHIP_CONFIG_CENTAUR(n) \
+    ((0x8000000000000000ull >> CHIP_CONFIG_CENTAUR_BASE) >> (n))
+
+
+#endif  /* __CHIP_CONFIG_H__ */
diff --git a/src/lib/ppc405lib/ctype.c b/src/lib/ppc405lib/ctype.c
new file mode 100644
index 0000000..5069590
--- /dev/null
+++ b/src/lib/ppc405lib/ctype.c
@@ -0,0 +1,46 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ctype.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: ctype.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/ctype.c,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ctype.c
+/// \brief Replacement for <ctype.h> functions
+///
+/// This file contains entry point equivalents for the "ctype.h" macros.
+/// These would only ever be used by assembler programs, therefore it's likely
+/// that the object file will never be linked into an image.
+
+#define __CTYPE_C__
+#include "ctype.h"
+#undef  __CTYPE_C__
+
+
+
+
diff --git a/src/lib/ctype.h b/src/lib/ppc405lib/ctype.h
index 9072c41..9e41e45 100755..100644
--- a/src/lib/ctype.h
+++ b/src/lib/ppc405lib/ctype.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ctype.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __CTYPE_H__
 #define __CTYPE_H__
 
diff --git a/src/lib/ctype_table.c b/src/lib/ppc405lib/ctype_table.c
index 6f3e576..01dd08a 100644
--- a/src/lib/ctype_table.c
+++ b/src/lib/ppc405lib/ctype_table.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ctype_table.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: ctype_table.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/ctype_table.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ppc405lib/errno.h b/src/lib/ppc405lib/errno.h
new file mode 100644
index 0000000..e5ac6a9
--- /dev/null
+++ b/src/lib/ppc405lib/errno.h
@@ -0,0 +1,49 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/errno.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __ERRNO_H__
+#define __ERRNO_H__
+
+// $Id: errno.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/errno.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file errno.h
+/// \brief Replacement for <errno.h>
+///
+/// SSX does not support a per-thread or global 'errno'.  The standard Unix
+/// errno values returned by library functions are defined here. The prefix
+/// code is the 'telephone code' for "errn".
+
+#define EINVAL 0x00377601
+#define EBADF  0x00377602
+#define EAGAIN 0x00377603
+#define ENXIO  0x00377604
+#define ENOMEM 0x00377605
+
+#endif  /* __ERRNO_H__ */
diff --git a/src/lib/fgetc.c b/src/lib/ppc405lib/fgetc.c
index e4e4a49..6e6a1f9 100755..100644
--- a/src/lib/fgetc.c
+++ b/src/lib/ppc405lib/fgetc.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/fgetc.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: fgetc.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/fgetc.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ppc405lib/initcall.c b/src/lib/ppc405lib/initcall.c
new file mode 100644
index 0000000..664fb6e
--- /dev/null
+++ b/src/lib/ppc405lib/initcall.c
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/initcall.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file initcall.c
+/// \brief An anonymous early initialization facility for SSX applications
+
+#include "ssx.h"
+#include "initcall.h"
+
+// These linker symbols must be defined if the initcall facility is used.  The
+// special ELF section .data.initcall contains an array of Initcall structures
+// for all declared initcalls.
+
+extern InitCall        _INITCALL_SECTION_BASE[];
+extern SsxLinkerSymbol _INITCALL_SECTION_SIZE;
+
+void
+_initcall_run(InitCall* initcall)
+{
+    void (*f)(void* arg);
+
+    f = initcall->initcall;
+    if (f) {
+        initcall->initcall = 0;
+        f(initcall->arg);
+    }
+}
+
+
+void
+initcall_run_all()
+{
+    InitCall* initcall;
+    size_t nCalls;
+
+    initcall = _INITCALL_SECTION_BASE;
+    nCalls = (size_t)(&_INITCALL_SECTION_SIZE) / sizeof(InitCall);
+
+    for (; nCalls--; initcall++) {
+        _initcall_run(initcall);
+    }
+}
+
+
+
+    
+    
diff --git a/src/lib/ppc405lib/initcall.h b/src/lib/ppc405lib/initcall.h
new file mode 100644
index 0000000..af8b53c
--- /dev/null
+++ b/src/lib/ppc405lib/initcall.h
@@ -0,0 +1,116 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/initcall.h $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __INITCALL_H__
+#define __INITCALL_H__
+
+// $Id$
+
+/// \file initcall.h
+/// \brief An early initialization facility for SSX applications
+///
+/// The C language standard does not define a generic load-time initialization
+/// method, unlike C++ which supports load-time initialization of static
+/// objects.  The \e initcall facility implements a simple method for SSX
+/// applications to declare early initialization functions that are executed
+/// prior to or during the invocation of main().
+///
+/// An \e initcall can be any function with the prototype
+///
+/// \code
+///
+/// void (*initcall)(void* arg)
+///
+/// \endcode
+///
+/// Initcalls are declared with the INITCALL() macro. An initcall is
+/// represented by a named structure, and typically an initcall will be
+/// declared static to the compilation unit that implements the initcall:
+///
+/// \code
+///
+/// void (*init_fn)(void* arg);
+/// void* init_data = ...;
+/// static INITCALL(init_var, init_fn, init_data);
+///
+/// \endcode
+///
+/// All INITCALLS loaded in the executable image are executed by the
+/// initcall_run_all() API.  An SSX application will typically call
+/// initcall_run_all() in the function declared as the \a ssx_main_hook, or in
+/// the main() routine itself.
+///
+/// Initcalls are run in an arbitrary order. However if initcall \a b is
+/// dependent on initcall \a a, then initcall \a b can execute
+/// initcall_run(&a) to guarantee that initcall \a a runs before \a b.
+/// Regardless, every initcall is run exectly once by the initcall facility,
+/// even if initcall_run() or initcall_run_all() were to be used multiple
+/// times.
+///
+/// Behind the scenes, initcalls are implemented by a special ELF section,
+/// .data.initcall, that records all declared initcalls.  The
+/// initcall_run_all() API simply runs all initcalls declared in
+/// .data.initcall.
+
+/// The structure representing an initcall
+
+typedef struct {
+
+    /// The initialization function
+    ///
+    /// Prior to running the initcall, this field is zeroed.  This guarantess
+    /// that each initcall is run at most 1 time.
+    void (*initcall)(void* arg);
+
+    /// The argument to the initialization function
+    void* arg;
+
+} InitCall;
+
+
+/// Declare an initcall
+///
+/// This macro generates C code and global data so must be placed at file
+/// scope in a C file, not in a header file or inside a C function
+/// body. Unless the initcall needs to be referenced by another initcall (to
+/// guarantee ordering), this declaration will normally be prepended with
+/// 'static'.
+#define INITCALL(_var, _initcall, _arg)                                 \
+    InitCall _var __attribute__ ((used, section (".data.initcall"))) = \
+    {.initcall = _initcall, .arg = _arg};
+
+
+/// Run the initcall represented by an InitCall structure, assuming it has not
+/// already run.
+///
+/// \param[in] i_initcall The address of the initcall structure to run
+void
+initcall_run(InitCall* i_initcall);
+
+
+/// Run all initcalls
+void
+initcall_run_all();
+
+#endif // __INITCALL_H__
diff --git a/src/lib/ppc405lib/lfsr.c b/src/lib/ppc405lib/lfsr.c
new file mode 100644
index 0000000..21ddb93
--- /dev/null
+++ b/src/lib/ppc405lib/lfsr.c
@@ -0,0 +1,50 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/lfsr.c $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file lfsr.c
+/// \brief 
+
+#include <stdint.h>
+#include "lfsr.h"
+
+// Parity for 4-bit numbers
+static uint8_t S_parity4[16] = {
+    0, 1, 1, 0,
+    1, 0, 0, 1,
+    1, 0, 0, 1,
+    0, 1, 1, 0
+};
+
+// 64, 63, 61, 60 LFSR.  The routine is coded with the uint8_t casting to help
+// the compiler generate more efficient code.
+
+void
+_lfsr64(uint64_t* io_seed)
+{
+    *io_seed = (*io_seed << 1) |
+        S_parity4[(uint8_t)((*io_seed >> 59) & 0x3) | 
+                  (uint8_t)((*io_seed >> 60) & 0xc)];
+}
diff --git a/src/lib/ppc405lib/lfsr.h b/src/lib/ppc405lib/lfsr.h
new file mode 100644
index 0000000..951ec45
--- /dev/null
+++ b/src/lib/ppc405lib/lfsr.h
@@ -0,0 +1,46 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/lfsr.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __LFSR_H__
+#define __LFSR_H__
+
+/// \file lfsr.h
+/// \brief Linear-Feedback Shift Register Implementations
+///
+/// The 32- and 64-bit pseudo-random number generators in this library are of
+/// the linear-conguential type. These maximal-length LFSR pseudo-random
+/// sequence generators are also provided.
+
+/// 64-bit LFSR
+///
+/// \param[in,out] io_seed The input seed is converted in one step to the
+/// output seed.
+///
+/// This 64-bit LFSR uses taps 64, 63, 61, and 60. In big-endian numbering
+/// these are bits 0, 1, 3 and 4.  This LFSR is also implemented for the PORE
+/// engines in the file pore_rand.pS.
+void
+_lfsr64(uint64_t* io_seed);
+
+#endif // __LFSR_H__
diff --git a/src/lib/ppc405lib/libppc405files.mk b/src/lib/ppc405lib/libppc405files.mk
new file mode 100644
index 0000000..59aa7a0
--- /dev/null
+++ b/src/lib/ppc405lib/libppc405files.mk
@@ -0,0 +1,74 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/lib/ppc405lib/libppc405files.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file libppc405files.mk
+#
+#  @brief mk for libppc405.a object files
+#
+#  @page ChangeLogs Change Logs
+#  @section libppc405files.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# INCLUDES
+##########################################################################
+
+C-SOURCES = \
+    assert.c \
+	byte_pool.c \
+	ctype.c \
+	ctype_table.c \
+	fgetc.c \
+	initcall.c \
+	lfsr.c \
+	mutex.c \
+	periodic_semaphore.c \
+	polling.c \
+	printf.c \
+	progress.c \
+	puts.c \
+	rtx_stdio.c \
+	simics_stdio.c \
+	sprintf.c \
+	ssx_dump.c \
+	ssx_io.c \
+	stdlib.c \
+	strcasecmp.c \
+	strdup.c \
+	string.c \
+	string_stream.c \
+	strtox.c \
+	sxlock.c \
+	time.c
+
+S-SOURCES =  
+
+LIBPPC405_OBJECTS = $(C-SOURCES:.c=.o) $(S-SOURCES:.S=.o)
diff --git a/src/lib/ppc405lib/libssx.h b/src/lib/ppc405lib/libssx.h
new file mode 100644
index 0000000..601eb00
--- /dev/null
+++ b/src/lib/ppc405lib/libssx.h
@@ -0,0 +1,44 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/libssx.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __LIBSSX_H__
+#define __LIBSSX_H__
+
+// $Id: libssx.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/libssx.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file libssx.h
+/// \brief Header definitions with no other obvious home
+
+// Kernel panics
+
+#define ASSERTION_FAILURE 0x00542701
+#define ERROR_EXIT        0x00542702
+
+#endif // __LIBSSX_H__
diff --git a/src/lib/ppc405lib/mutex.c b/src/lib/ppc405lib/mutex.c
new file mode 100644
index 0000000..db57f54
--- /dev/null
+++ b/src/lib/ppc405lib/mutex.c
@@ -0,0 +1,129 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/mutex.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file mutex.c
+/// \brief A ThreadX-style mutual exclusion object
+
+#include "mutex.h"
+
+int
+mutex_create(Mutex* i_mutex)
+{
+    int rc;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(i_mutex == 0, SSX_INVALID_OBJECT);
+    }
+
+    rc = ssx_semaphore_create(&(i_mutex->sem), 1, 1);
+    i_mutex->thread = 0;
+    i_mutex->count = 0;
+
+    return rc;
+}
+
+
+// If the current thread owns the Mutex we simply increment the count,
+// otherwise pend for the semaphore.
+//
+// Note: It's possible this doesn't need to be done in a critical section. The
+// fact that ssx_semaphore_pend() is atomic may be sufficient since it locks
+// the Mutex.
+
+int
+mutex_pend(Mutex* i_mutex, SsxInterval i_timeout)
+{
+    int rc;
+    SsxMachineContext ctx;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(i_mutex == 0, SSX_INVALID_OBJECT);
+        SSX_ERROR_UNLESS_THREAD_CONTEXT();
+    }
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    if (i_mutex->thread == ssx_current()) {
+
+        i_mutex->count++;
+        if (i_mutex->count == 0) {
+            rc = MUTEX_OVERFLOW;
+        } else {
+            rc = 0;
+        }
+
+    } else {
+
+        rc = ssx_semaphore_pend(&(i_mutex->sem), i_timeout);
+        if (rc == 0) {
+            i_mutex->thread = ssx_current();
+            i_mutex->count = 1;
+        }
+    }
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+// If the current thread owns the Mutex we decrement the count and free the
+// object when the count goes to 0.
+//
+// Note: It's possible this doesn't need to be done in a critical section. The
+// fact that ssx_semaphore_pend() is atomic may be sufficient since it locks
+// the Mutex.
+
+int
+mutex_post(Mutex* i_mutex)
+{
+    int rc;
+    SsxMachineContext ctx;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(i_mutex == 0, SSX_INVALID_OBJECT);
+        SSX_ERROR_UNLESS_THREAD_CONTEXT();
+    }
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    SSX_ERROR_IF(i_mutex->thread != ssx_current(), MUTEX_NOT_OWNED);
+
+    if (--i_mutex->count == 0) {
+        i_mutex->thread = 0;
+        rc = ssx_semaphore_post(&(i_mutex->sem));
+    } else {
+        rc = 0;
+    }
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+    
+
+    
diff --git a/src/lib/ppc405lib/mutex.h b/src/lib/ppc405lib/mutex.h
new file mode 100644
index 0000000..6d3a352
--- /dev/null
+++ b/src/lib/ppc405lib/mutex.h
@@ -0,0 +1,164 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/mutex.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __MUTEX_H__
+#define __MUTEX_H__
+
+// $Id$
+
+/// \file mutex.h
+/// \brief A ThreadX-style mutual exclusion object
+///
+/// A Mutex is a binary semaphore with the concept of thread ownership.  A
+/// thread first obtains the Mutex using the mutex_pend() API, which may block
+/// if the Mutex is currently owned by another thread.  Once a thread owns a
+/// Mutex, subsequent calls of mutex_pend() by the same thread simply
+/// increment an internal counter, but do not block. Once a thread has
+/// executed a matching mutex_post() call for every mutex_pend() call, the
+/// Mutex is free for another thread.
+///
+/// This type of mutual exclusion object is useful for example to control
+/// access to data structures that are manipulated by APIs with several common
+/// entry points. Each call of an API in the chain will 'lock' the data
+/// structure using mutex_pend()/mutex_post(). The Mutex semantics allows
+/// multiple "locks" by the same thread, but requires a corresponding "unlock"
+/// for every "lock".
+///
+/// The Mutex usage counter is a 32-bit unsigned integer. If a thread makes
+/// 2^32 calls to mutex_pend() without an intervening call of mutex_post(), an
+/// overflow is signalled. This error should be considered unrecoverable to
+/// the application.
+///
+/// Like the SSX semaphore, no record is kept in the thread of which Mutex
+/// objects are currently owned by the thread.  If a thread terminates or is
+/// deleted while holding a Mutex it is likely that the application will
+/// hang. Unlike the SSX semaphore, it is absolutely illegal to call
+/// mutex_pend() and mutex_post() from interrupt contexts. It is also illegal
+/// for a thread to call mutex_post() for a mutex it does not own.
+///
+/// Mutex objects are easily created with the static initialization macro
+/// MUTEX_INITIALIZATION as in the following example.
+///
+/// \code 
+///
+/// Mutex G_mutex = MUTEX_INITIALIZATION;
+///
+/// \endcode
+///
+/// The API mutex_create() is also provided for run-time initialization.
+
+#include "ssx.h"
+
+
+// Mutex error/panic codes
+
+#define MUTEX_OVERFLOW  0x00688901
+#define MUTEX_NOT_OWNED 0x00688902
+
+
+#ifndef __ASSEMBLER__
+
+/// Static initialization of a Mutex
+///
+/// For a full description of the Mutex please see the documentation fof the
+/// file mutex.h.
+#define MUTEX_INITIALIZATION {SSX_SEMAPHORE_INITIALIZATION(1, 1), 0, 0}
+
+
+/// The Mutex object
+
+typedef struct {
+
+    /// The binary semaphore
+    SsxSemaphore sem;
+
+    /// A pointer to the owning thread, or NULL (0)
+    SsxThread* thread;
+
+    /// The count of unmatched mutex_pend() calls made by the owning thread.
+    uint32_t count;
+
+} Mutex;
+
+
+/// Create (initialize) a Mutex
+///
+/// \param[in] i_mutex A pointer to the Mutex object to initialize.
+///
+/// For a full description of the Mutex please see the documentation for the
+/// file mutex.h.
+///
+/// \retval 0 Success
+///
+/// \retval 0 -SSX_INVALID_OBJECT The \a i_mutex is NULL (0).
+int
+mutex_create(Mutex* i_mutex);
+
+
+/// Pend on a Mutex with optional timeout
+///
+/// \param[in] i_mutex A pointer to the Mutex
+///
+/// \param[in] i_timeout Either the constant SSX_WAIT_FOREVER, or a timeout
+/// interval specification.
+///
+/// For a full description of the Mutex please see the documentation for the
+/// file mutex.h.
+///
+/// \retval 0 Success
+///
+/// \retval -SSX_INVALID_OBJECT The \a i_mutex is NULL (0).
+/// 
+/// \retval -SSX_ILLEGAL_CONTEXT The call was not made from a thread context.
+///
+/// \retval -SSX_SEMEPHORE_PEND_TIMED_OUT The thread was not able to obtain
+/// the Mutex before the timeout.
+///
+/// \retval -MUTEX_OVERFLOW The owning thread has made 2^32 unmatched calls of
+/// mutex_pend(). 
+int
+mutex_pend(Mutex* i_mutex, SsxInterval i_timeout);
+
+
+/// Post to a Mutex
+///
+/// \param[in] i_mutex A pointer to the Mutex
+///
+/// For a full description of the Mutex please see the documentation for the
+/// file mutex.h.
+///
+/// \retval 0 Success
+///
+/// \retval -SSX_INVALID_OBJECT The \a i_mutex is NULL (0).
+///
+/// \retval -SSX_ILLEGAL_CONTEXT The call was not made from a thread context.
+///
+/// \retval -MUTEX_NOT_OWNED The thread calling mutex_post() does not own the
+/// Mutex. 
+int
+mutex_post(Mutex* i_mutex);
+
+#endif // __ASSEMBLER__
+
+#endif // __MUTEX_H__
diff --git a/src/lib/ppc405lib/periodic_semaphore.c b/src/lib/ppc405lib/periodic_semaphore.c
new file mode 100644
index 0000000..dec9ea2
--- /dev/null
+++ b/src/lib/ppc405lib/periodic_semaphore.c
@@ -0,0 +1,114 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/periodic_semaphore.c $                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file perodic_semaphore.h
+/// \brief Periodic semphores
+
+#include "ssx.h"
+#include "periodic_semaphore.h"
+
+// The timer callback is created nonpreemptible, so noncritical interrupts are
+// disabled at entry.
+
+static void
+_periodic_semaphore_timeout(void* arg)
+{
+    PeriodicSemaphore* ps;
+
+    ps = (PeriodicSemaphore*)arg;
+
+    if (ps->sem.count != 1) {
+        ssx_semaphore_post(&(ps->sem));
+    }
+}
+
+
+int
+periodic_semaphore_create(PeriodicSemaphore* sem, SsxInterval period)
+{
+    int rc;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(sem == 0, SSX_INVALID_OBJECT);
+    }
+
+    do {
+        rc = ssx_semaphore_create(&(sem->sem), 0, 1);
+        if (rc) break;
+
+        rc = ssx_timer_create_nonpreemptible(&(sem->timer), 
+                                             _periodic_semaphore_timeout,
+                                             sem);
+        if (rc) break;
+
+        rc = ssx_timer_schedule(&(sem->timer),
+                                period,
+                                period);
+        if (rc) break;
+
+    } while (0);
+
+    return rc;
+}
+
+
+int
+periodic_semaphore_pend(PeriodicSemaphore* sem)
+{
+    int rc;
+    SsxMachineContext ctx;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(sem == 0, SSX_INVALID_OBJECT);
+    }
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    if (sem->sem.count == 0) {
+
+        rc = ssx_semaphore_pend(&(sem->sem), SSX_WAIT_FOREVER);
+        
+    } else {
+
+        sem->sem.count = 0;
+        rc = -PERIODIC_SEMAPHORE_OVERRUN;
+    }
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+int
+periodic_semaphore_cancel(PeriodicSemaphore* sem)
+{
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(sem == 0, SSX_INVALID_OBJECT);
+    }
+
+    return ssx_timer_cancel(&(sem->timer));
+}
diff --git a/src/lib/ppc405lib/periodic_semaphore.h b/src/lib/ppc405lib/periodic_semaphore.h
new file mode 100644
index 0000000..c3c2e53
--- /dev/null
+++ b/src/lib/ppc405lib/periodic_semaphore.h
@@ -0,0 +1,152 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/periodic_semaphore.h $                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PERIODIC_SEMAPHORE_H__
+#define __PERIODIC_SEMAPHORE_H__
+
+// $Id$
+
+/// \file perodic_semaphore.h
+/// \brief Periodic semphores
+///
+/// The PeriodicSemphore is a simple abstraction introduced to simplify coding
+/// peridic threads. A periodic thread creates the PeriodicSemaphore after
+/// thread initialization, but prior to the entry to the periodic infinite
+/// loop. This creates the periodicSemaphore with a count of 0. Once thread
+/// processing is finished, the thread pends on the PeriodicSemaphore. A
+/// periodic timer posts to the PeriodicSemaphore on a fixed, absolute period
+/// to reschedule the thread.
+///
+/// If the thread pends on the PeriodicSemaphore and the timer has already
+/// posted to the semaphore, the call of periodic_semaphore_pend() clears the
+/// semaphore and terminates immediately with the return code
+/// -PERIODIC_SEMAPHORE_OVERRUN, indicating that the thread has overrun its
+/// period. The thread can choose the appropriate action upon obtaining this
+/// return code.
+///
+/// The PeriodicSemaphore can also be cancelled, which simply cancels the
+/// periodic timer posting to the semaphore. If the thread needs to
+/// re-initialize the PeriodicSemaphore for any reason (e.g, to resynchronize
+/// after an overrun) it must be cancelled first.
+
+// Error/Panic codes
+
+#define PERIODIC_SEMAPHORE_OVERRUN 0x0077e601
+
+
+/// A periodic semaphore
+
+typedef struct {
+
+    /// The semaphore
+    SsxSemaphore sem;
+
+    /// The timer
+    SsxTimer timer;
+
+} PeriodicSemaphore;
+
+
+/// Create (initialize) a PeriodicSemaphore
+///
+/// \param sem A pointer to an uninitialized or inactive
+/// PeriodicSemaphore.
+///
+/// \param period The semaphore period
+///
+/// This API creates the embedded semaphore as a binary semaphore with an
+/// initial value of 0, and schedules a periodic timer to post to the
+/// semaphore.
+///
+/// \retval 0 Success
+///
+/// \retval -SSX_INVALID_OBJECT The \a sem was NULL (0) or otherwise invalid.
+///
+/// Other return codes are possible from the embedded calls of SSX APIs.
+int
+periodic_semaphore_create(PeriodicSemaphore* sem, SsxInterval period);
+
+
+/// Pend on a PeriodicSemaphore
+///
+/// \param sem A pointer to an initialized PeriodicSemaphore
+///
+/// Pend on a PeriodicSemaphore.  It is considered a non-fatal error if the
+/// semaphore has a non-0 count as this may indicate that a periodic thread
+/// has missed a deadline.
+///
+/// Return values other than SSX_OK (0) are not necessarily errors; see \ref
+/// ssx_errors 
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Success. In particular, the semaphore count was 0 at entry.
+///
+/// \retval -PERIODIC_SEMAPHORE_OVERRUN This return code indicates that the
+/// semaphore count was 1 at entry. This code is always returned (never causes
+/// a panic). 
+///
+/// The following return codes are  error codes:
+///
+/// \retval -SSX_IVALID_OBJECT The \a sem was NULL () or otherwise invalid at
+/// entry.
+///
+/// Other error return codes are possible from embedded calls of SSX APIs.
+int
+periodic_semaphore_pend(PeriodicSemaphore* sem);
+
+
+/// Cancel a periodic semaphore
+///
+/// \param sem A pointer to an initialized PeriodicSemaphore
+///
+/// Cancel the PeriodicSemaphore timeout. This is a required step if the
+/// PeriodicSemaphore is to be reinitialized. This is also required if the
+/// PeriodicSemaphore is created on the thread stack and the thread
+/// terminates.  PeriodicSemaphore can be canceled at any time.  It is never
+/// an error to call periodic_semaphore_cancel() on a PeriodicSemaphore object
+/// after it is created.
+///
+/// Return values other than SSX_OK (0) are not necessarily errors; see \ref
+/// ssx_errors 
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Successful completion
+///
+/// \retval -SSX_TIMER_NOT_ACTIVE The embedded timer is not currently
+/// scheduled, meaning that the PeriodicSemaphore was previosly
+/// cancelled.
+///
+/// The following return codes are  error codes:
+///
+/// \retval -SSX_IVALID_OBJECT The \a sem was NULL () or otherwise invalid at
+/// entry.
+///
+/// Other error return codes are possible from embedded calls of SSX APIs.
+int
+periodic_semaphore_cancel(PeriodicSemaphore* sem);
+
+
+#endif // __PERIODIC_SEMAPHORE_H__
diff --git a/src/lib/ppc405lib/polling.c b/src/lib/ppc405lib/polling.c
new file mode 100644
index 0000000..a013202
--- /dev/null
+++ b/src/lib/ppc405lib/polling.c
@@ -0,0 +1,97 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/polling.c $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: polling.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/polling.c,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file polling.c
+/// \brief Library APIs for polling
+
+#include "polling.h"
+
+int
+polling(int* o_rc,
+        int (*i_condition)(void* io_arg, int* o_satisfied),
+        void* io_arg,
+        SsxInterval i_timeout,
+        SsxInterval i_sleep)
+{
+    SsxTimebase start;
+    int rc, pollRc, timed_out, done;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF((i_condition == 0), POLLING_ERROR);
+    }
+    
+    start = ssx_timebase_get();
+    timed_out = 0;
+
+    do {
+        pollRc = i_condition(io_arg, &done);
+        if (pollRc) {
+            rc = POLLING_CONDITION;
+            break;
+        }
+        if (done) {
+            rc = 0;
+            break;
+        }
+        if (timed_out) {
+            rc = POLLING_TIMEOUT;
+            break;
+        }
+        if (i_sleep != 0) {
+            rc = ssx_sleep(i_sleep);
+            if (rc) {
+                break;
+            }
+        }
+        timed_out = 
+            ((i_timeout != SSX_WAIT_FOREVER) &&
+             ((ssx_timebase_get() - start) >= i_timeout));
+
+    } while (1);
+
+    if (o_rc) {
+        *o_rc = pollRc;
+    }
+
+    return rc;
+}
+
+
+void
+busy_wait(SsxInterval i_interval)
+{
+    SsxTimebase start;
+
+    start = ssx_timebase_get();
+    while ((ssx_timebase_get() - start) < i_interval);
+}
+
diff --git a/src/lib/polling.h b/src/lib/ppc405lib/polling.h
index b719ac6..99afbe7 100644
--- a/src/lib/polling.h
+++ b/src/lib/ppc405lib/polling.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/polling.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __POLLING_H__
 #define __POLLING_H__
 
diff --git a/src/lib/printf.c b/src/lib/ppc405lib/printf.c
index 96f08f3..d75cdf3 100755..100644
--- a/src/lib/printf.c
+++ b/src/lib/ppc405lib/printf.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/printf.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: printf.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/printf.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ppc405lib/progress.c b/src/lib/ppc405lib/progress.c
new file mode 100644
index 0000000..8d2cd30
--- /dev/null
+++ b/src/lib/ppc405lib/progress.c
@@ -0,0 +1,743 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/progress.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id
+
+/// \file progress.c
+/// \brief Programmable progress (hang) checking
+///
+/// This is a simple implementation of a progress (hang) checking
+/// facility. The application provides an array of \e pass \e counts that are
+/// expected to update/count over time.  For simplicity and generality all
+/// pass counts are defined to be \c uint64_t types.  The
+/// progress_checker_create() API initializes the checker, and as a
+/// convenience clears the pass counts.
+///
+/// The checker can be created with an optional \a callback function, which
+/// has the prototype
+///
+/// \code
+/// typedef int (*ProgressCheckerCallback)(struct ProgressChecker *checker,
+/// 				           void* arg,
+/// 				           size_t failed)
+/// \endcode
+///
+/// The checker callback is called \e every time a check is made by
+/// progress_checker_check().  In addition to a private void* argument, the
+/// parameter list of the callback includes a count of the number of counters
+/// that failed to make progress - this count will be 0 if the check was
+/// successful. The return value of the callback is passed back as the return
+/// value of progress_checker_check().  If the callback is specified as NULL
+/// (0), then a successful check returns 0, and any failure causes a return
+/// code of -PROGRESS_CHECKER_FAILED.
+///
+/// The application can dynamically mark counters as either \e exempt or \e
+/// required.  By default all counts are required to have increased
+/// each time a check is made for progress.  Counters marked \e exempt when a
+/// progress check is made are not checked for progress.
+///
+/// The application can also use the progress_checker_schedule() API to
+/// schedule either one-shot or periodic checks.  The
+/// progress_checker_cancel() API can be used to cancel any scheduled
+/// checks. It is never an error to call this API, even if no checks are
+/// currently scheduled. Note that each call of progress_checker_schedule()
+/// also cancels any outstanding scheduled requests before (re-) scheduling
+/// the checker.  If using the built-in timer mechanism, any calls of
+/// progress_checker_check that return a non-0 value will cause a kernel panic.
+///
+/// If failures are detected and caught, the ProgressChecker provides a
+/// primitive iteration facility for the callback or the applicaton to
+/// determine which counters have failed to update. Calling
+/// progress_checker_next_failure() returns either the index of the next
+/// failing counter, or -1 to indicate no more failures. This iteration
+/// facility is reset every time a check is made by progress_checker_check()
+/// (including those made implcitly by the timer-based mechanism). There is no
+/// API to reset the iteration.
+///
+/// The implemetation provides 2 standard callback functions:
+/// progess_checker_printk() and progress_checker_printk_dump().  The former
+/// callback uses printk() to print a simple report of failed counters, and if
+/// there were any failures it then returns its argument as a return code.  If
+/// the return code is non-zero then the lack of progress will cause a kernel
+/// panic (test failure). The later callback first calls
+/// progress_checker_printk(). If progress_checker_printk() returns a non-0
+/// value then progress_checker_printk_dump() enters an SSX_CRITICAL crictal
+/// section and prints a full kernel state dump that may be useful to help
+/// diagnose the hang.
+///
+/// \note We do not make the kernel dump the default or only behavior because
+/// it could take 1ms or more to produce the large quantity of formatted
+/// output required, which could be a significant amount of wall time in a
+/// logic simulation environment.
+///
+/// The progress_checker_create() API could be used in a couple of ways as
+/// illustrated below:
+///
+/// \code 
+///
+/// ProgressChecker progress;
+/// uint64_t counter;
+///
+/// progress_checker_create(&progress, "progress", counter, 1, 
+///                         progress_checker_printk,
+///                         (void*)-PROGRESS_CHECKER_FAILED);
+///
+/// OR
+///
+/// progress_checker_create(&progress, "progress", counter, 1, 
+///                         progress_checker_printk, 0);
+///
+/// \endcode
+///
+/// The first usage prints a report and panics the test if lack of progress is
+/// detected.  The second form simply prints a report in the event of a lack
+/// or progress.  The second form may be useful to report on counters that
+/// only have a statistical probability of making progress, however be aware
+/// that the report is generated in an interrupt context and all thread
+/// activity will be blocked until the formatted I/O is complete.
+///
+/// Notes:
+/// 
+/// This implementation requires the \c byte_pool facility and malloc() to be
+/// set up as the ProgressChecker allocates dynamic storage during
+/// initialization to store the previous pass counts.
+///
+/// It is probably not a good idea to use a single ProgressChecker for both
+/// manual and timer-based checking, since there is no protection in the
+/// implementation for mutiple accesses to the ProgressChecker.
+
+#include "progress.h"
+#include "ssx_dump.h"
+
+// The built-in timer callback
+
+static void
+progress_callback(void *arg)
+{
+    ProgressChecker *checker = (ProgressChecker *)arg;
+
+    if (progress_checker_check(checker)){
+	if (0) {
+	    progress_checker_dump(checker);
+	}
+	SSX_PANIC(PROGRESS_CHECKER_FAILED);
+    }
+}
+
+
+// Bit-vector operations manage the array of bits using little-endian
+// protocols 
+
+static inline void
+bit_vector_set(uint8_t *vector, size_t bit)
+{
+    vector[bit / 8] |= (1 << (bit % 8));
+}
+
+
+static inline void
+bit_vector_clear(uint8_t *vector, size_t bit)
+{
+    vector[bit / 8] &= ~(1 << (bit % 8));
+}
+
+
+static inline int
+bit_vector_is_set(uint8_t *vector, size_t bit)
+{
+    return ((vector[bit / 8] & (1 << (bit % 8))) != 0);
+}
+
+
+// NB: We don't have a bit-vector object with a size included.  For this
+// application we can only call this API if we know that there is at least 1
+// bit set in the vector.
+
+static size_t
+bit_vector_find_first_set(uint8_t *vector)
+{
+    size_t byte = 0;
+    
+    while (vector[byte] == 0) {
+	byte++;
+    }
+
+    return (8 * byte) + __builtin_ffs(vector[byte]) - 1;
+}
+
+
+/// Create a progress checker
+///
+/// \param checker A pointer to an uninitialized or idle ProgressChecker
+///
+/// \param name An optional character string associated with the checker
+///
+/// \param pass_counts An array of pass counters - the array will be cleared
+/// by this API.
+///
+/// \param counters The number of counters in the array
+///
+/// \param callback This function is called \e every time a check is
+/// completed.  
+///
+/// \param arg The private argument of the callback function
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// Return values other than 0 are errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// \retval -PROGRESS_CHECKER_INVALID_ARGUMENT A null (0) pointer was provided
+/// as the \a pass_counts argument, or the number of \a counters can not be
+/// represented as a signed integer.
+///
+/// \retval -PROGRESS_CHECKER_ALLOCATION_FAILED Memory allocation of dynamic
+/// memory failed.  This is treated as a fatal error here.
+///
+/// This API may also return or signal other errors from its implementation
+/// APIs. 
+
+int
+progress_checker_create(ProgressChecker *checker,
+			const char* name,
+			uint64_t *pass_counts,
+			size_t counters,
+			ProgressCheckerCallback callback,
+			void *arg)
+{
+    int rc, bytes;
+    void *memory;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF((checker == 0),
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+	SSX_ERROR_IF((pass_counts == 0) ||
+		     (counters != (int)counters),
+		     PROGRESS_CHECKER_INVALID_ARGUMENT);
+    }
+
+    // Install and clear the counters
+
+    checker->pass_counts = pass_counts;
+    memset((void *)pass_counts, 0, counters * sizeof(uint64_t));
+    checker->counters = counters;
+
+    // Allocate and clear dynamic memory
+
+    memory = calloc(counters, sizeof(uint64_t));
+    checker->saved_counts = (uint64_t *)memory;
+
+    bytes = (counters / 8) + (counters % 8 ? 1 : 0);
+    checker->bit_vector_bytes = bytes;
+
+    memory = calloc(bytes, 1);
+    checker->exempt = (uint8_t *)memory;
+    
+    memory = calloc(bytes, 1);
+    checker->failure = (uint8_t *)memory;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF((counters != 0) && 
+		     ((checker->saved_counts == 0) ||
+		      (checker->exempt == 0) ||
+		      (checker->failure == 0)),
+		     PROGRESS_CHECKER_ALLOCATION_FAILED);
+    }
+
+    // Initialize other fields
+
+    checker->name = name;
+    checker->callback = callback;
+    checker->arg = arg;
+    checker->failed = 0;
+    checker->checks = 0;
+
+    // Initialize the timer structure.
+
+    rc = ssx_timer_create(&(checker->timer), 
+			  progress_callback, 
+			  (void *)checker);
+    if (rc) return rc;
+
+    return 0;
+}
+
+
+/// Exempt a pass count from progress checking
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// \param counter The index of the counter to exempt
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// Return values other than 0 are errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// \retval -PROGRESS_CHECKER_INVALID_ARGUMENT The \a counter argument is not
+/// valid.
+
+int
+progress_checker_exempt(ProgressChecker *checker,
+			size_t counter)
+{
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+	SSX_ERROR_IF(counter >= checker->counters,
+		     PROGRESS_CHECKER_INVALID_ARGUMENT);
+    }
+
+    bit_vector_set(checker->exempt, counter);
+
+    return 0;
+}
+
+
+/// Exempt all pass counts from progress checking
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// This API is provided to support applications where pass-count-updating
+/// processes are added dynamically. This API coule typically be called
+/// immediately after progress_checker_create(). Them, as each process was
+/// created it would call progress_checker_require() for the pass count.
+///
+/// Return values other than 0 are errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+int
+progress_checker_exempt_all(ProgressChecker *checker)
+{
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+    }
+
+    memset(checker->exempt, -1, checker->bit_vector_bytes);
+
+    return 0;
+}
+
+
+/// Require a pass count to update for progress checking
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// \param counter The index of the counter to require
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// Return values other than 0 are errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// \retval -PROGRESS_CHECKER_INVALID_ARGUMENT The \a counter argument is not
+/// valid.
+
+int
+progress_checker_require(ProgressChecker *checker,
+			size_t counter)
+{
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+	SSX_ERROR_IF(counter >= checker->counters,
+		     PROGRESS_CHECKER_INVALID_ARGUMENT);
+    }
+
+    bit_vector_clear(checker->exempt, counter);
+
+    return 0;
+}
+
+
+/// Require a pass count to update for progress checking avoiding races
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// \param counter The index of the counter to require
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// If a pass counter is marked "exempt" but then later marked "required",
+/// there is a potential race between the update of the pass counter and the
+/// next check, particularly when the checker is scheduled periodically. This
+/// form of the progress_checker_require() marks the progress checker such
+/// that \e all checks are deferred on the next call of
+/// progress_checker_check() targeting the object in order to avoid the race.
+///
+/// Return values other than 0 are errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// \retval -PROGRESS_CHECKER_INVALID_ARGUMENT The \a counter argument is not
+/// valid.
+int
+progress_checker_require_defer(ProgressChecker *checker,
+                               size_t counter)
+{
+    int rc;
+    SsxMachineContext ctx;
+
+    ssx_critical_section_enter(SSX_CRITICAL, &ctx);
+
+    rc = progress_checker_require(checker, counter);
+    checker->defer = 1;
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+/// Check for progress in every required pass counter.
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c
+///
+/// Return values other than 0 are not necessarily errors; see \ref
+/// ssx_errors 
+///
+/// \retval various  Except for the error listed below,
+/// progress_checker_check() returns the code returned by the callback
+/// function. If no callback was provided when the checker was created, then 0
+/// is returned for success and -PROGRESS_CHECKER_FAILED is returned in the
+/// event of a lack of progress.
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+
+int
+progress_checker_check(ProgressChecker *checker)
+{
+    size_t i;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+    }
+
+    // Avoid doing this step unless necessary
+
+    if (checker->failed != 0) {
+	checker->failed = 0;
+	memset((void *)checker->failure, 0, checker->bit_vector_bytes);
+    }
+
+    // Check, unless checking has been deferred for 1 time by
+    // progress_checker_require_defer().
+
+    if (checker->defer) {
+
+        checker->defer = 0;
+
+    } else {
+
+        SSX_ATOMIC(SSX_CRITICAL, checker->start_check = ssx_timebase_get());
+
+        for (i = 0; i < checker->counters; i++) {
+	
+            if ((checker->pass_counts[i] <= checker->saved_counts[i]) && 
+                !(bit_vector_is_set(checker->exempt, i))) {
+
+                checker->failed++;
+                bit_vector_set(checker->failure, i);
+            }
+            checker->saved_counts[i] = checker->pass_counts[i];
+        }
+
+        SSX_ATOMIC(SSX_CRITICAL, checker->end_check = ssx_timebase_get());
+    }
+
+    checker->checks++;
+
+    if (checker->callback) {
+	return checker->callback(checker, checker->arg, checker->failed);
+    } else if (checker->failed != 0) {
+	return -PROGRESS_CHECKER_FAILED;
+    } else {
+	return 0;
+    }
+}
+
+
+/// Schedule progress checks (periodically) in the future.
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// \param interval The relative time of the (first) check
+///
+/// \param period If non-zero, checks will be made periodically with this
+/// period. 
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c. See the SSX documentation for a discussion of
+/// timer scheduling in SSX.
+///
+/// Return values other than 0 errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// This API may also return or signal other errors from its implementation
+/// APIs. 
+
+
+int
+progress_checker_schedule(ProgressChecker *checker,
+			  SsxInterval interval,
+			  SsxInterval period)
+{
+    int rc;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+    }
+
+    rc = ssx_timer_cancel(&(checker->timer));
+    if (rc != -SSX_TIMER_NOT_ACTIVE) return rc;
+
+    rc = ssx_timer_schedule(&(checker->timer), interval, period);
+    if (rc) return rc;
+
+    return 0;
+}
+
+    
+/// Cancel all future (periodic) progress checks
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c. See the SSX documentation for a discussion of
+/// timer scheduling in SSX.
+///
+/// Return values other than 0 errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+///
+/// This API may also return or signal other errors from its implementation
+/// APIs. 
+
+int
+progress_checker_cancel(ProgressChecker *checker)
+{
+    int rc;
+
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+    }
+
+    rc = ssx_timer_cancel(&(checker->timer));
+    if (rc) return rc;
+
+    return 0;
+}
+
+    
+/// Iterate over progress check failures
+///
+/// \param checker A pointer to an initialized ProgressChecker
+///
+/// \param counter Will return the index of the next failing counter, or -1 to
+/// indicate no more failing counters.
+///
+/// For an overview of the ProgressChecker and its APIs, see the documentation
+/// for the file progress.c. 
+///
+/// Return values other than 0 errors; see \ref ssx_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PROGRESS_CHECKER_INVALID_OBJECT A null (0) pointer was provided
+/// as the \a checker argument.
+
+int
+progress_checker_next_failure(ProgressChecker *checker, int *counter)
+{
+    if (SSX_ERROR_CHECK_API) {
+	SSX_ERROR_IF(checker == 0,
+		     PROGRESS_CHECKER_INVALID_OBJECT);
+    }
+
+    if (checker->failed == 0) {
+	*counter = -1;
+	return 0;
+    }
+
+    *counter = bit_vector_find_first_set(checker->failure);
+    bit_vector_clear(checker->failure, *counter);
+    checker->failed--;
+
+    return 0;
+}
+
+
+/// A standard way to print the results of a progress check failure, suitable
+/// for use as a ProgressChecker callback.
+///
+/// \param checker The checker - which may or may not have failed. If the
+/// checker did fail, then a failure report is printed using printk().
+///
+/// \param arg The value to return in case of failure.  In case of
+/// success, 0 is returned.
+///
+/// \param failed - The number of failed checks
+
+int
+progress_checker_printk(ProgressChecker *checker,
+			void *arg,
+			size_t failed)
+{
+    int counter;
+
+    if (!failed) {
+	return 0;
+    }
+
+    printk("---------------------------------------------------------------\n");
+    printk("-- Progress check failed for \"%s\" (%p).\n", 
+	   checker->name, checker);
+    printk("-- Check %zu over interval 0x%016llx - 0x%016llx\n",
+           checker->checks, checker->start_check, checker->end_check);
+    printk("-- %zu failed counter%s listed below\n", 
+	   failed, failed > 1 ? "s are" : " is");
+    printk("---------------------------------------------------------------\n");
+
+    do {
+	progress_checker_next_failure(checker, &counter);
+	if (counter < 0) {
+	    break;
+	}
+	printk("%4d. 0x%016llx\n", counter, checker->pass_counts[counter]);
+    } while (1);
+
+    printk("---------------------------------------------------------------\n");
+
+    return (int)arg;
+}    
+
+
+/// Call progress_checker_printk(), then create a kernel dump on failure
+///
+/// \param checker The checker - which may or may not have failed. If the
+/// checker did fail, then a failure report is printed using
+/// progress_checker_printk().
+///
+/// \param arg The value to return in case of failure.  In case of
+/// success, 0 is returned.
+///
+/// \param failed - The number of failed checks
+///
+/// If progress_checker_printk() fails with a non-0 return code then this API
+/// prints a full SSX kernel dump after the progress_checker_printk() report.
+int
+progress_checker_printk_dump(ProgressChecker *checker,
+                             void *arg,
+                             size_t failed)
+{
+    int rc;
+    SsxMachineContext ctx;
+    
+    rc = progress_checker_printk(checker, arg, failed);
+    if (rc != 0) {
+        ssx_critical_section_enter(SSX_CRITICAL, &ctx);
+        ssx_dump(ssxout, 0);
+        ssx_critical_section_exit(&ctx);
+    }
+
+    return rc;
+}    
+
+
+/// Dump a progress checker structure using printk()
+
+void
+progress_checker_dump(ProgressChecker *checker)
+{
+    size_t i;
+
+    printk("Dump of progress checker \"%s\" (%p)\n"
+	   "  Counters = %zu\n"
+	   "  Checks   = %zu\n"
+	   "  Failed   = %zu\n"
+	   "  Callback = %p(%p)\n",
+	   checker->name, checker, checker->counters, checker->checks,
+	   checker->failed, checker->callback, checker->arg);
+    
+    printk("  Pass Counts (%p) :\n", checker->pass_counts);
+    for (i = 0; i < checker->counters; i++) {
+    	printk("    %9d%c 0x%016llx\n", 
+    	       i, 
+    	       bit_vector_is_set(checker->exempt, i) ? '*' : ' ',
+    	       checker->pass_counts[i]);
+    }
+    printk("  Saved Counts (%p) :\n", checker->saved_counts);
+    for (i = 0; i < checker->counters; i++) {
+    	printk("    %9d   0x%016llx\n", 
+    	       i, checker->saved_counts[i]);
+    }
+}
+
+    
+    
+	   
+
+
+    
+
diff --git a/src/lib/ppc405lib/progress.h b/src/lib/ppc405lib/progress.h
new file mode 100644
index 0000000..3454a0f
--- /dev/null
+++ b/src/lib/ppc405lib/progress.h
@@ -0,0 +1,177 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/progress.h $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PROGRESS_H__
+#define __PROGRESS_H__
+
+// $Id$
+
+/// \file progress.h
+/// \brief Programmable progress (hang) checking
+
+#include <time.h>
+#include "ssx.h"
+#include "byte_pool.h"
+#include "ssx_io.h"
+
+#ifndef __ASSEMBLER__
+
+struct ProgressChecker;
+
+/// ProgressChecker callback type
+///
+/// \param checker The checker that has just been checked
+///
+/// \param arg The private argument provided when the checker was created
+///
+/// \param failed The number of failed pass counts - 0 indicates no failures
+
+typedef int (*ProgressCheckerCallback)(struct ProgressChecker* checker,
+				       void*  arg,
+				       size_t failed);
+
+
+/// A simple progress (hang) checker.  For API details see file progress.c
+
+typedef struct ProgressChecker {
+
+    /// The application provided pass-count array
+    uint64_t *pass_counts;
+
+    /// The number of pass-count counters in the array.
+    size_t counters;
+
+    /// The (optional) name of the checker for reporting purposes.
+    const char *name;
+
+    /// The (optional) checker callback.
+    ProgressCheckerCallback callback;
+
+    /// The checker callback private argument
+    void *arg;
+
+    /// The dynamically-allocated saved pass counts.
+    uint64_t *saved_counts;
+
+    /// The dynamically-allocated exemption bit-vector
+    ///
+    /// \todo Get or implement a generic unlimited-precision bit vector
+    uint8_t *exempt;
+
+    /// The dynamically-allocated failure bit-vector
+    uint8_t *failure;
+
+    /// The number of bytes in the bit vector
+    size_t bit_vector_bytes;
+
+    /// Defer all checking the next time progress_checker_check() is called.
+    ///
+    /// See progress_checker_require_defer()
+    int defer;
+
+    /// The number of failures present in the *failure vector 
+    size_t failed;
+
+    /// A timer object to support time-based checking.
+    SsxTimer timer;
+
+    /// The number of times progress_checker_check() has been called on the
+    /// object. 
+    size_t checks;
+
+    /// The time the last check started
+    SsxTimebase start_check;
+
+    /// The time the last check ended
+    SsxTimebase end_check;
+
+} ProgressChecker;
+
+
+int
+progress_checker_create(ProgressChecker *checker,
+			const char *name,
+			uint64_t *pass_counts,
+			size_t counters,
+			ProgressCheckerCallback callback,
+			void *arg);
+
+int
+progress_checker_exempt(ProgressChecker *checker,
+			size_t counter);
+
+int
+progress_checker_exempt_all(ProgressChecker *checker);
+
+int
+progress_checker_require(ProgressChecker *checker,
+			 size_t counter);
+
+int
+progress_checker_require_defer(ProgressChecker *checker,
+                               size_t counter);
+
+int
+progress_checker_check(ProgressChecker *checker);
+
+int
+progress_checker_schedule(ProgressChecker *checker,
+			  SsxInterval interval,
+			  SsxInterval period);
+
+int
+progress_checker_cancel(ProgressChecker *checker);
+
+int
+progress_checker_next_failure(ProgressChecker *checker, int *counter);
+
+int 
+progress_checker_delete(ProgressChecker *checker);
+
+int
+progress_checker_printk(ProgressChecker *checker,
+			void *arg,
+			size_t failed);
+
+int
+progress_checker_printk_dump(ProgressChecker *checker,
+                             void *arg,
+                             size_t failed);
+
+void
+progress_checker_dump(ProgressChecker *checker);
+
+
+#endif	/* __ASSEMBLER__ */
+
+// Error/Panic codes
+
+#define PROGRESS_CHECKER_INVALID_OBJECT    0x00776001
+#define PROGRESS_CHECKER_INVALID_ARGUMENT  0x00776002
+#define PROGRESS_CHECKER_FAILED            0x00776003
+#define PROGRESS_CHECKER_CALLBACK_PANIC    0x00776004
+#define PROGRESS_CHECKER_INVARIANT         0x00776005
+#define PROGRESS_CHECKER_ALLOCATION_FAILED 0x00776006
+
+#endif	/* __PROGRESS_H__ */
diff --git a/src/lib/puts.c b/src/lib/ppc405lib/puts.c
index ab24d6b..446671a 100755..100644
--- a/src/lib/puts.c
+++ b/src/lib/ppc405lib/puts.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/puts.c $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: puts.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/puts.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ppc405lib/rtx_stdio.c b/src/lib/ppc405lib/rtx_stdio.c
new file mode 100644
index 0000000..4bb1a18
--- /dev/null
+++ b/src/lib/ppc405lib/rtx_stdio.c
@@ -0,0 +1,149 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/rtx_stdio.c $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file rtx_stdio.c
+/// \brief SSX I/O drivers for RTX stdio streams
+///
+/// The RTX \a stdout and \a stderr components accept 1, 2 and 4-byte
+/// transactions on a 32-bit OCI address and write the data to the RTX
+/// job's \a stdout or \a stderr respectively.  The \a stdin device is not yet
+/// implemented.
+
+#include "ssx.h"
+#include "rtx_stdio.h"
+
+RtxStdio rtx_stdin;
+RtxStdio rtx_stdout;
+RtxStdio rtx_stderr;
+
+int
+rtx_stdio_sread(FILE *stream, void *buf, size_t count, size_t *read)
+{
+    SSX_PANIC(ENXIO);
+    return -ENXIO;
+}
+
+
+int
+rtx_stdio_swrite(FILE *stream, const void *buf,
+                    size_t count, size_t *written)
+{
+    RtxStdio *rtx = (RtxStdio *)stream;
+    size_t n;
+
+    n = count;
+    while (n) {
+        if (n >= 4) {
+            out32(rtx->address, *((uint32_t *)buf));
+            buf += 4;
+            n -= 4;
+        } else if (n >= 2) {
+            out16(rtx->address, *((uint16_t *)buf));
+            buf += 2;
+            n -= 2;
+        } else {
+            out8(rtx->address, *((uint8_t *)buf));
+            buf++;
+            n--;
+        }
+    }
+
+    if (written != 0) {
+        *written = count;
+    }
+
+    return 0;
+}
+
+
+ssize_t
+rtx_stdio_fflush(FILE *stream)
+{
+    RtxStdio *rtx = (RtxStdio *)stream;
+
+    out8(rtx->flush_address, 0);
+    return 0;
+}
+
+
+int
+rtx_stdin_create(RtxStdio *stream)
+{
+    FILE *base = (FILE *)stream;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(stream == 0, EBADF);
+    }
+
+    memset((void *)stream, 0, sizeof(RtxStdio));
+    base->sread = rtx_stdio_sread;
+
+    stream->address = RTX_STDIN;
+
+    return 0;
+}
+
+
+int
+rtx_stdout_create(RtxStdio *stream)
+{
+    FILE *base = (FILE *)stream;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(stream == 0, EBADF);
+    }
+
+    memset((void *)stream, 0, sizeof(RtxStdio));
+    base->swrite = rtx_stdio_swrite;
+    base->fflush = rtx_stdio_fflush;
+
+    stream->address = RTX_STDOUT;
+    stream->flush_address = RTX_STDOUT_FLUSH;
+
+    return 0;
+}
+
+
+int
+rtx_stderr_create(RtxStdio *stream)
+{
+    FILE *base = (FILE *)stream;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(stream == 0, ENXIO);
+    }
+
+    memset((void *)stream, 0, sizeof(RtxStdio));
+    base->swrite = rtx_stdio_swrite;
+    base->fflush = rtx_stdio_fflush;
+
+    stream->address = RTX_STDERR;
+    stream->flush_address = RTX_STDERR_FLUSH;
+
+    return 0;
+}
+
+
diff --git a/src/lib/ppc405lib/rtx_stdio.h b/src/lib/ppc405lib/rtx_stdio.h
new file mode 100644
index 0000000..cd2a439
--- /dev/null
+++ b/src/lib/ppc405lib/rtx_stdio.h
@@ -0,0 +1,74 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/rtx_stdio.h $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __RTX_STDIO_H__
+#define __RTX_STDIO_H__
+
+// $Id$
+
+/// \file rtx_stdio.h
+/// \brief SSX I/O implementations for RTX stdio streams
+
+#include "ssx_io.h"
+#include "rtx_stdio_addresses.h"
+
+/// A FILE structure for a RTX fake stdio stream
+
+typedef struct {
+
+    /// The base class
+    FILE stream;
+
+    /// The MMIO address of the RTX device for the stream
+    SsxAddress address;
+
+    /// The MMIO address of the RTX device for flushing the stream;
+    SsxAddress flush_address;
+
+} RtxStdio;
+
+extern RtxStdio rtx_stdin;
+extern RtxStdio rtx_stdout;
+extern RtxStdio rtx_stderr;
+
+int
+rtx_stdin_create(RtxStdio *stream);
+
+int
+rtx_stdout_create(RtxStdio *stream);
+
+int
+rtx_stderr_create(RtxStdio *stream);
+
+int
+rtx_stdio_sread(FILE *stream, void *buf, size_t count, size_t *read);
+
+int
+rtx_stdio_swrite(FILE *stream, const void *buf,
+                    size_t count, size_t *written);
+
+int
+rtx_stdio_sflush(FILE *stream);
+
+#endif /* __RTX_STDIO_H__ */
diff --git a/src/lib/ppc405lib/rtx_stdio_addresses.h b/src/lib/ppc405lib/rtx_stdio_addresses.h
new file mode 100644
index 0000000..5359f7f
--- /dev/null
+++ b/src/lib/ppc405lib/rtx_stdio_addresses.h
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/rtx_stdio_addresses.h $                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __RTX_STDIO_ADDRESSES_H__
+#define __RTX_STDIO_ADDRESSES_H__
+
+// $Id$
+
+/// \file rtx_stdio_addresses.h
+/// \brief MMIO addresses and offsets of the rtx fake stdio model
+///
+/// The RTX stdio module appears as OCI device #7?  Reading 1 byte from the
+/// stdin offset returns that byte from stdin. Writing 1, 2 or 4 bytes to the
+/// stdout or stderr offsets causes output on that stream.  Writing any single
+/// byte to the 'flush' offsets flush the stdout or stderr streams.
+///
+/// -*- This header is maintained as part of the PMX RTX model.    -*-
+/// -*- Do not edit in the SSX library as your edits will be lost. -*-
+
+#define RTX_STDIO_BASE          0x40060000
+
+#define RTX_STDIN_OFFSET        0x00
+#define RTX_STDOUT_OFFSET       0x04
+#define RTX_STDOUT_FLUSH_OFFSET 0x08
+#define RTX_STDERR_OFFSET       0x0c
+#define RTX_STDERR_FLUSH_OFFSET 0x10
+
+#define RTX_STDIN        (RTX_STDIO_BASE + RTX_STDIN_OFFSET)
+#define RTX_STDOUT       (RTX_STDIO_BASE + RTX_STDOUT_OFFSET)
+#define RTX_STDOUT_FLUSH (RTX_STDIO_BASE + RTX_STDOUT_FLUSH_OFFSET)
+#define RTX_STDERR       (RTX_STDIO_BASE + RTX_STDERR_OFFSET)
+#define RTX_STDERR_FLUSH (RTX_STDIO_BASE + RTX_STDERR_FLUSH_OFFSET)
+
+#endif /* __RTX_STDIO_ADDRESSES_H__ */
diff --git a/src/lib/simics_stdio.c b/src/lib/ppc405lib/simics_stdio.c
index 5c276a2..6ff1fa9 100755..100644
--- a/src/lib/simics_stdio.c
+++ b/src/lib/ppc405lib/simics_stdio.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/simics_stdio.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: simics_stdio.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/simics_stdio.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/simics_stdio.h b/src/lib/ppc405lib/simics_stdio.h
index abbfe26..b9ebfcf 100755..100644
--- a/src/lib/simics_stdio.h
+++ b/src/lib/ppc405lib/simics_stdio.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/simics_stdio.h $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SIMICS_STDIO_H__
 #define __SIMICS_STDIO_H__
 
diff --git a/src/lib/simics_stdio_addresses.h b/src/lib/ppc405lib/simics_stdio_addresses.h
index 9f7d886..4554bbf 100755..100644
--- a/src/lib/simics_stdio_addresses.h
+++ b/src/lib/ppc405lib/simics_stdio_addresses.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/simics_stdio_addresses.h $                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SIMICS_STDIO_ADDRESSES_H__
 #define __SIMICS_STDIO_ADDRESSES_H__
 
diff --git a/src/lib/sprintf.c b/src/lib/ppc405lib/sprintf.c
index 458cd39..0a95416 100755..100644
--- a/src/lib/sprintf.c
+++ b/src/lib/ppc405lib/sprintf.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/sprintf.c $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: sprintf.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/sprintf.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ssx_dump.c b/src/lib/ppc405lib/ssx_dump.c
index 93ce1ea..52334ab 100644
--- a/src/lib/ssx_dump.c
+++ b/src/lib/ppc405lib/ssx_dump.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ssx_dump.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: ssx_dump.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/ssx_dump.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ssx_dump.h b/src/lib/ppc405lib/ssx_dump.h
index 17455c0..a413214 100644
--- a/src/lib/ssx_dump.h
+++ b/src/lib/ppc405lib/ssx_dump.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ssx_dump.h $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_DUMP_H__
 #define __SSX_DUMP_H__
 
diff --git a/src/lib/ssx_io.c b/src/lib/ppc405lib/ssx_io.c
index e69dcbe..b517aeb 100755..100644
--- a/src/lib/ssx_io.c
+++ b/src/lib/ppc405lib/ssx_io.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ssx_io.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: ssx_io.c,v 1.2 2014/02/03 01:30:25 daviddu Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/ssx_io.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ssx_io.h b/src/lib/ppc405lib/ssx_io.h
index 794fe5d..b30b32f 100755..100644
--- a/src/lib/ssx_io.h
+++ b/src/lib/ppc405lib/ssx_io.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/ssx_io.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_IO_H__
 #define __SSX_IO_H__
 
diff --git a/src/lib/stdlib.c b/src/lib/ppc405lib/stdlib.c
index 2dcc009..a15308d 100755..100644
--- a/src/lib/stdlib.c
+++ b/src/lib/ppc405lib/stdlib.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/stdlib.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: stdlib.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/stdlib.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/strcasecmp.c b/src/lib/ppc405lib/strcasecmp.c
index 361a387..fc7585c 100644
--- a/src/lib/strcasecmp.c
+++ b/src/lib/ppc405lib/strcasecmp.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/strcasecmp.c $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: strcasecmp.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/strcasecmp.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/ppc405lib/strdup.c b/src/lib/ppc405lib/strdup.c
new file mode 100644
index 0000000..6d205c7
--- /dev/null
+++ b/src/lib/ppc405lib/strdup.c
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/strdup.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: strdup.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/strdup.c,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file strdup.c
+/// \brief Functions from <string.h> that require malloc()
+///
+/// These APIs are split from string.c for the benefit of applications like
+/// OCC FW that don't use malloc().
+
+#include <stdlib.h>
+#include <string.h>
+
+/// Duplicate a string
+///
+/// \param s The string to duplicate
+///
+/// The strdup() function returns a pointer to a new string which is a
+/// duplicate of the input string \a s.  Memory for the new string is obtained
+/// with malloc(), and can be freed with free().
+///
+/// \returns The strdup() function returns a pointer to the duplicated string,
+/// or NULL (0) if insufficient memory was available.
+
+char *
+strdup(const char* s)
+{
+    char* dup;
+
+    dup = (char*)malloc(strlen(s) + 1);
+    if (dup != 0) {
+        strcpy(dup, s);
+    }
+    return dup;
+}
diff --git a/src/lib/string_stream.c b/src/lib/ppc405lib/string_stream.c
index f3b1889..1dfc439 100755..100644
--- a/src/lib/string_stream.c
+++ b/src/lib/ppc405lib/string_stream.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/string_stream.c $                           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: string_stream.c,v 1.2 2014/02/03 01:30:25 daviddu Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/string_stream.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/string_stream.h b/src/lib/ppc405lib/string_stream.h
index 939489c..07891f5 100755..100644
--- a/src/lib/string_stream.h
+++ b/src/lib/ppc405lib/string_stream.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/string_stream.h $                           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __STRING_STREAM_H__
 #define __STRING_STREAM_H__
 
diff --git a/src/lib/strtox.c b/src/lib/ppc405lib/strtox.c
index d901158..56493fa 100755..100644
--- a/src/lib/strtox.c
+++ b/src/lib/ppc405lib/strtox.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/strtox.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: strtox.c,v 1.2 2014/02/03 01:30:25 daviddu Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/strtox.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/strtox.h b/src/lib/ppc405lib/strtox.h
index b005ca9..db2cef2 100755..100644
--- a/src/lib/strtox.h
+++ b/src/lib/ppc405lib/strtox.h
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/strtox.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __STRTOX_H__
 #define __STRTOX_H__
 
diff --git a/src/lib/ppc405lib/sxlock.c b/src/lib/ppc405lib/sxlock.c
new file mode 100644
index 0000000..35f9698
--- /dev/null
+++ b/src/lib/ppc405lib/sxlock.c
@@ -0,0 +1,494 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/sxlock.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id$
+
+/// \file sxlock.c
+/// \brief API for the SharedExclusiveLock
+///
+/// The APIs in this file implement a shared-exclusive lock for SSX
+/// applications.  This type of lock is also called a readers-writer lock. The
+/// lock is implemented in terms of SSX semaphores, so its use is limited to
+/// threads willing to block for access to a resource. 
+///
+/// The SharedExclusiveLock allows multiple threads shared access to a
+/// resource, while limiting exclusive access to a single thread. There are
+/// several ways that this type of lock might be specified. The specification
+/// implemented here is an "exclusive-biasing" lock. As long as the lock is
+/// held or requested in exclusive mode, all new shared-mode requests will
+/// block, and only exclusive accesses will be allowed. If multiple threads
+/// are blocked exclusive the requests are honored in priority order (as
+/// the underlying implementation is an SSX semaphore). Once the exclusive
+/// lock is cleared, any/all threads blocked for shared access are released
+/// simultaneously (using an SSX semaphore as a thread barrier).
+///
+/// The lock is created (initialized) by sxlock_create(), which allows
+/// specification of an initial value of the number of shared or exclusive
+/// accesses outstanding.  The lock/unlock APIs are as follows:
+///
+/// - sxlock_lock_shared(SharedExclusiveLock* sxlock, SsxInterval timeout)
+/// - sxlock_unlock_shared(SharedExclusiveLock* sxlock)
+/// - sxlock_lock_exclusive(SharedExclusiveLock* sxlock, SsxInterval timeout)
+/// - sxlock_unlock_exclusive(SharedExclusiveLock* sxlock)
+///
+/// Threads must always issue *_lock() and *_unlock() requests in matched
+/// pairs in order to avoid errors and deadlock. The *_lock() APIs allow
+/// specification of a timeout, which may be SSX_WAIT_FOREVER to indicate no
+/// timeout. The *_lock() APIs will return the code -SXLOCK_TIMED_OUT if the
+/// timeout occurs before the thread acquires the resource. If called from an
+/// interrupt context then the only legal timeout specification is
+/// SSX_NO_WAIT (0).  
+///
+/// If a *_lock() request times out then the thread \e has \e not acquired the
+/// resource and \e must \e not call *_unlock(). As with semaphores there is
+/// no record that a thread holds a lock, so if a thread completes or is
+/// deleted while holding a lock it is likely that the application will
+/// deadlock.
+
+#include "ssx.h"
+#include "sxlock.h"
+
+/// Create (initialize) a SharedExclusiveLock
+///
+/// \param sxlock A pointer to the SharedExclusiveLock object to
+/// initialize
+///
+/// \param shared The initial numbers of shared accesses
+///
+/// \param exclusive The initial numbers of exclusive accesses
+///
+/// Create (initialize) a SharedExclusiveLock and optionally specify an
+/// initial state. The initial number of shared or exclusive accesses can be
+/// specified, however at most one of \a nshared and \a exclusive can be
+/// non-0. If \a shared or \a exclusive are non-0 then eventually a
+/// thread(s) will need to issue unmatched *_unlock() call(s) to allow
+/// progress for other threads requiring the resource.
+///
+/// \retval 0 Success
+///
+/// \retval SXLOCK_INVALID_OBJECT The \a sxlock parameter is NULL (0) or
+/// otherwise invalid.
+///
+/// \retval SXLOCK_INVALID_ARGUMENT Both of the \a shared and \a exclusive
+/// parameters are non-0.
+///
+/// \retval others sxlock_create() may also return codes from
+/// ssx_semaphore_create(), which would indicate a serious bug.
+
+int
+sxlock_create(SharedExclusiveLock* sxlock, 
+              SsxSemaphoreCount shared, 
+              SsxSemaphoreCount exclusive)
+{
+    int rc;
+
+    rc = 0;
+    do {
+
+        if (SSX_ERROR_CHECK_API) {
+            SSX_ERROR_IF(sxlock == 0, 
+                         SXLOCK_INVALID_OBJECT);
+            SSX_ERROR_IF((shared != 0) && (exclusive != 0), 
+                         SXLOCK_INVALID_ARGUMENT);
+        }
+        
+        rc = ssx_semaphore_create(&(sxlock->shared_sem), 0, 0);
+        if (rc) break;
+
+        rc = ssx_semaphore_create(&(sxlock->exclusive_sem), 0, 0);
+        if (rc) break;
+
+        sxlock->running_shared = shared;
+        sxlock->running_exclusive = exclusive;
+        
+    } while (0);
+
+    return rc;
+}
+
+
+/// Lock a SharedExclusiveLock for shared access
+///
+/// \param sxlock A pointer to the SharedExclusiveLock object to lock
+///
+/// \param timeout The maximum amount of time to wait for access, or the
+/// constant SSX_WAIT_FOREVER to wait forever.
+///
+/// Acquire a SharedExclusiveLock for shared access, potentially blocking
+/// forever or until a specified timeout if access is not immediately
+/// granted. Access will be blocked as long as one or more threads request or
+/// control exclusive acesss to the resource. Once the access is granted, the
+/// thread maintains shared access to the resource until a subsequent call of
+/// sxlock_unlock_shared().
+///
+/// Return values other than SSX_OK (0) are not necessarily errors; see \ref
+/// ssx_errors 
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Successful completion
+///
+/// \retval -SXLOCK_TIMED_OUT Shared access was not acquired before the
+/// timeout expired.
+///
+/// The following return codes are error codes:
+///
+/// \retval -SXLOCK_INVALID_OBJECT The \a sxlock parameter was NULL (0) or
+/// otherwise invalid.
+///
+/// \retval -SSX_ILLEGAL_CONTEXT The API was called from a critical
+/// interrupt context.
+/// 
+/// \retval -SSX_SEMAPHORE_PEND_WOULD_BLOCK The call was made from an
+/// interrupt context (or before threads have been started), shared access was
+/// not immediately available and a non-zero timeout was specified.
+///
+/// \retval others This API may also return codes from SSX semaphore APIs,
+/// which should be considered as non-recoverable errors.
+
+
+int
+sxlock_lock_shared(SharedExclusiveLock* sxlock, SsxInterval timeout)
+{
+    SsxMachineContext ctx;
+    int rc, pending_exclusive;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(sxlock == 0, SXLOCK_INVALID_OBJECT);
+    }
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    rc = 0;
+    do {
+
+        // NB: This is the only way to correctly compute the number of threads
+        // pending exclusive, given that threads could be removed from the
+        // exclusive_sem by timeout.
+
+        rc = ssx_semaphore_info_get(&(sxlock->exclusive_sem),
+                                    0, &pending_exclusive);
+        if (rc) break;
+
+        if ((sxlock->running_exclusive == 0) && (pending_exclusive == 0)) {
+
+            // If no other thread has or is requesting exclusive access, the
+            // current thread gets immediate access.
+
+            sxlock->running_shared++;
+
+        } else {
+
+            // If threads are running or pending exclusive, this thread must
+            // pend shared. The thread will be unblocked by an exclusive
+            // unlock, which is responsible for adjusting
+            // sxlock->running_shared in this case.
+        
+            rc = ssx_semaphore_pend(&(sxlock->shared_sem), timeout);
+            if (rc == -SSX_SEMAPHORE_PEND_TIMED_OUT) {
+                rc = -SXLOCK_TIMED_OUT;
+            } 
+        }
+
+    } while (0);
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+/// Relase a SharedExclusiveLock from shared access
+///
+/// \param sxlock A pointer to the SharedExclusiveLock object to unlock
+///
+/// Release a SharedExclusiveLock from shared access, signalling that the
+/// thread no longer requires or expects shared access to the resource.  It is
+/// an error for a thread to use this API if it has not previously locked
+/// shared access by a call of sxlock_pend_shared() (or the thread is
+/// unlocking a lock initialized in the shared-locked state).
+///
+/// Return values other than SSX_OK (0) are errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -SSX_ILLEGAL_CONTEXT The API was called from a critical interrupt
+/// context.
+///
+/// \retval -SXLOCK_INVALID_OBJECT The \a sxlock parameter was NULL (0) or
+/// otherwise invalid.
+///
+/// \retval -SXLOCK_SHARED_UNDERFLOW There was apparently no matched call of
+/// sxlock_lock_shared() prior to this call.
+///
+/// \retval others This API may also return codes from SSX semaphore APIs,
+/// which should be considered as non-recoverable errors.
+
+int
+sxlock_unlock_shared(SharedExclusiveLock* sxlock)
+{
+    SsxMachineContext ctx;
+    int rc, pending_exclusive;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF_CRITICAL_INTERRUPT_CONTEXT();
+        SSX_ERROR_IF(sxlock == 0, SXLOCK_INVALID_OBJECT);
+        SSX_ERROR_IF(sxlock->running_shared == 0, SXLOCK_SHARED_UNDERFLOW);
+    }
+
+    if (SSX_ERROR_CHECK_KERNEL) {
+        SSX_PANIC_IF(sxlock->running_exclusive != 0, 
+                     SXLOCK_SHARED_EXCLUSIVE_INVARIANT);
+    }
+
+    rc = 0;
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    do {
+
+        // If this is the last shared thread running, and a thread wants
+        // exclusive access, grant it. Note that there may be shared requests
+        // pending on the shared_sem but we always give preference to
+        // exclusive requests.
+
+        sxlock->running_shared--;
+        if (sxlock->running_shared == 0) {
+
+            // Wake any single thread pending exclusive
+
+            rc = ssx_semaphore_info_get(&(sxlock->exclusive_sem),
+                                        0, &pending_exclusive);
+            if (rc) break;
+
+            if (pending_exclusive != 0) {
+                
+                sxlock->running_exclusive = 1;
+                rc = ssx_semaphore_post(&(sxlock->exclusive_sem));
+                if (rc) break;
+            }
+        }
+
+    } while(0);
+
+    ssx_critical_section_exit(&ctx);
+    
+    return rc;
+}
+
+
+/// Lock a SharedExclusiveLock for exclusive access
+///
+/// \param sxlock A pointer to the SharedExclusiveLock object to lock
+///
+/// \param timeout The maximum amount of time to wait for access, or the
+/// constant SSX_WAIT_FOREVER to wait forever.
+///
+/// Acquire a SharedExclusiveLock for exclusive access, potentially blocking
+/// forever or until a specified timeout if access is not immediately
+/// granted. Access will be blocked as long as one or more threads control
+/// shared acesss to the resource, however once the thread requests exclusive
+/// access all new shared access requests will block. Once the access is
+/// granted, the thread maintains exclusive access to the resource until a
+/// subsequent call of sxlock_unlock_exclusive().
+///
+/// Return values other than SSX_OK (0) are not necessarily errors; see \ref
+/// ssx_errors 
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Successful completion
+///
+/// \retval -SXLOCK_TIMED_OUT Exclusive access was not acquired before the
+/// timeout expired.
+///
+/// The following return codes are error codes:
+///
+/// \retval -SXLOCK_INVALID_OBJECT The \a sxlock parameter was NULL (0) or
+/// otherwise invalid.
+///
+/// \retval -SSX_ILLEGAL_CONTEXT The API was called from a critical
+/// interrupt context.
+/// 
+/// \retval -SSX_SEMAPHORE_PEND_WOULD_BLOCK The call was made from an
+/// interrupt context (or before threads have been started), exclusive access
+/// was not immediately available and a non-zero timeout was specified.
+///
+/// \retval others This API may also return codes from SSX semaphore APIs,
+/// which shoudl be considered as non-recoverable errors.
+
+
+int
+sxlock_lock_exclusive(SharedExclusiveLock* sxlock, SsxInterval timeout)
+{
+    SsxMachineContext ctx;
+    int rc, pending_exclusive, pending_shared;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(sxlock == 0, SXLOCK_INVALID_OBJECT);
+    }
+
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    rc = 0;
+    do {
+
+        if ((sxlock->running_shared == 0) &&
+            (sxlock->running_exclusive == 0)) {
+
+            // If no other thread has acquired the lock, this thread gets
+            // immediate access.
+
+            sxlock->running_exclusive = 1;
+
+        } else {
+
+            // Some other thread has acquired the lock.  This thread must pend
+            // exclusive. In this case the sxlock->running_exclusive must be
+            // set by the *_unlock() operation that unblocks the thread.
+        
+            rc = ssx_semaphore_pend(&(sxlock->exclusive_sem), timeout);
+            if (rc == -SSX_SEMAPHORE_PEND_TIMED_OUT) {
+
+                // This exclusive request timed out.  Since the request may
+                // have blocked shared requests, then if this is the only
+                // exclusive request or thread we need to unblock any pending
+                // shared requests.
+
+                if (sxlock->running_exclusive == 0) {
+
+                    rc = ssx_semaphore_info_get(&(sxlock->exclusive_sem),
+                                                0, &pending_exclusive);
+                    if (rc) break;
+
+                    if (pending_exclusive == 0) {
+
+                        rc = ssx_semaphore_info_get(&(sxlock->shared_sem),
+                                                    0, &pending_shared);
+                        if (rc) break;
+
+                        if (pending_shared != 0) {
+
+                            sxlock->running_shared += pending_shared;
+                            rc = ssx_semaphore_release_all(&(sxlock->shared_sem));
+                            if (rc) break;
+                        }
+                    }
+                }
+
+                rc = -SXLOCK_TIMED_OUT;
+            }
+        }
+
+    } while (0);
+
+    ssx_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+/// Release a SharedExclusiveLock from exclusive access
+///
+/// \param sxlock A pointer to the SharedExclusiveLock object to unlock
+///
+/// Release a SharedExclusiveLock from exclusive access, signalling that the
+/// thread no longer requires or expects exclusive access to the resource.  It
+/// is an error for a thread to use this API if it has not previously locked
+/// exclusive access by a call of sxlock_lock_exclusive() (or the thread is
+/// unlocking a lock initialized in the exclusive-locked state).
+///
+/// Return values other than SSX_OK (0) are errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -SSX_ILLEGAL_CONTEXT The API was called from a critical interrupt
+/// context.
+///
+/// \retval -SXLOCK_INVALID_OBJECT The \a sxlock parameter was NULL (0) or
+/// otherwise invalid.
+///
+/// \retval -SXLOCK_EXCLUSIVE_UNDERFLOW There was apparently no matched call of
+/// sxlock_lock_exclusive() prior to this call.
+///
+/// \retval others This API may also return codes from SSX semaphore APIs,
+/// which should be considered as non-recoverable errors.
+
+int
+sxlock_unlock_exclusive(SharedExclusiveLock* sxlock)
+{
+    SsxMachineContext ctx;
+    int rc, pending_exclusive, pending_shared;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF_CRITICAL_INTERRUPT_CONTEXT();
+        SSX_ERROR_IF(sxlock == 0, SXLOCK_INVALID_OBJECT);
+        SSX_ERROR_IF(sxlock->running_exclusive != 1, SXLOCK_SHARED_UNDERFLOW);
+    }
+
+    if (SSX_ERROR_CHECK_KERNEL) {
+        SSX_PANIC_IF(sxlock->running_shared != 0, 
+                     SXLOCK_SHARED_EXCLUSIVE_INVARIANT);
+    }
+
+    rc = 0;
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    do {
+
+        rc = ssx_semaphore_info_get(&(sxlock->exclusive_sem),
+                                    0, &pending_exclusive);
+        if (rc) break;
+
+        if (pending_exclusive != 0) {
+
+            // If there are other threads pending exclusive, make the
+            // highest-priority one of them
+            // runnable. sxlock->running_exclusive remains equal to 1.
+
+            rc = ssx_semaphore_post(&(sxlock->exclusive_sem));
+            if (rc) break;
+
+        } else {
+
+            // Otherwise unblock any/all threads pending shared
+
+            sxlock->running_exclusive = 0;
+
+            rc = ssx_semaphore_info_get(&(sxlock->shared_sem),
+                                        0, &pending_shared);
+            if (rc) break;
+
+            if (pending_shared != 0) {
+
+                sxlock->running_shared = pending_shared;
+                rc = ssx_semaphore_release_all(&(sxlock->shared_sem));
+                if (rc) break;
+            }
+        }
+    } while (0);
+
+    ssx_critical_section_exit(&ctx);
+    
+    return rc;
+}
diff --git a/src/lib/ppc405lib/sxlock.h b/src/lib/ppc405lib/sxlock.h
new file mode 100644
index 0000000..e0fa196
--- /dev/null
+++ b/src/lib/ppc405lib/sxlock.h
@@ -0,0 +1,108 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/sxlock.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SXLOCK_H__
+#define __SXLOCK_H__
+
+// $Id$
+
+/// \file sxlock.h
+/// \brief The implementation of a SharedExclusiveLock
+///
+/// The SharedExclusiveLock is documented in the comments for the file
+/// sxlock.c 
+
+// Error/panic codes
+
+#define SXLOCK_INVALID_OBJECT             0x00795501
+#define SXLOCK_INVALID_ARGUMENT           0x00795502
+#define SXLOCK_TIMED_OUT                  0x00795503
+#define SXLOCK_SHARED_UNDERFLOW           0x00795504
+#define SXLOCK_EXCLUSIVE_UNDERFLOW        0x00795505
+#define SXLOCK_SHARED_EXCLUSIVE_INVARIANT 0x00795506 
+
+/// A shared-exclusive lock object (also called a readers-write lock)
+///
+/// This facility is documented in the file sxlock.c
+
+typedef struct {
+
+    /// A semaphore for threads requesting shared access
+    SsxSemaphore shared_sem;
+
+    /// A semaphore for threads requesting exclusive access
+    SsxSemaphore exclusive_sem;
+
+    /// The number of threads running shared
+    SsxSemaphoreCount running_shared;
+
+    /// The number of threads running exclusive
+    SsxSemaphoreCount running_exclusive;
+
+} SharedExclusiveLock;
+
+
+/// Static initialization of a shared-exclusive lock object
+///
+/// \param[in] shared The number of threads running shared at static
+/// initialization
+///
+/// \param[in] exclusive The number of threads running exclusive at static
+/// initialization. 
+///
+/// Note that it is an error to specify both \a shared and \a exclusive as
+/// non-0.
+
+#define SXLOCK_INITIALIZATION(shared, exclusive)        \
+    {                                                   \
+        SSX_SEMAPHORE_INITIALIZATION(0, 0),             \
+            SSX_SEMAPHORE_INITIALIZATION(0, 0),         \
+            (shared), (exclusive)                       \
+            }
+
+/// Declare and initialize a shared-exclusive lock
+
+#define SXLOCK(sxlock, shared, exclusive)                               \
+    SharedExclusiveLock sxlock = SXLOCK_INITIALIZATION(shared, exclusive)
+
+
+
+int
+sxlock_create(SharedExclusiveLock* sxlock,
+              SsxSemaphoreCount shared,
+              SsxSemaphoreCount exclusive);
+
+int
+sxlock_lock_shared(SharedExclusiveLock* sxlock, SsxInterval timeout);
+
+int
+sxlock_unlock_shared(SharedExclusiveLock* sxlock);
+
+int
+sxlock_lock_exclusive(SharedExclusiveLock* sxlock, SsxInterval timeout);
+
+int
+sxlock_unlock_exclusive(SharedExclusiveLock* sxlock);
+
+#endif // __SXLOCK_H__
diff --git a/src/lib/time.c b/src/lib/ppc405lib/time.c
index bc1f2e7..39d005c 100755..100644
--- a/src/lib/time.c
+++ b/src/lib/ppc405lib/time.c
@@ -1,3 +1,27 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/lib/ppc405lib/time.c $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 // $Id: time.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/time.c,v $
 //-----------------------------------------------------------------------------
diff --git a/src/lib/pstates.c b/src/lib/pstates.c
deleted file mode 100755
index 958b9e1..0000000
--- a/src/lib/pstates.c
+++ /dev/null
@@ -1,410 +0,0 @@
-// $Id: pstates.c,v 1.2 2014/02/03 01:30:25 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pstates.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pstates.c
-/// \brief Pstate routines required by OCC product firmware
-
-#include "ssx.h"
-#include "pgp_common.h"
-#include "pstates.h"
-
-/// Validate a VRM11 VID code
-///
-/// \param vid A VRM11 VID
-///
-/// \retval 0 The VID is valid
-///
-/// \retval -VID11_UNDERFLOW_VID11_VALIDATE The Vid code is a low 'power off' 
-/// VID (0 or 1)
-///
-/// \retval -VID11_OVERFLOW_VID11_VALIDATE The Vid code is a high 'power off' 
-/// VID (0xfe or 0xff)
-
-int
-vid11_validate(Vid11 vid)
-{
-    int rc;
-
-    if (vid < VID11_MIN) {
-
-        rc = -VID11_UNDERFLOW_VID11_VALIDATE;
-
-    } else if (vid > VID11_MAX) {
-
-        rc = -VID11_OVERFLOW_VID11_VALIDATE;
-
-    } else {
-
-        rc = 0;
-
-    }
-    
-    return rc;
-}
-
-
-/// Bias a Pstate with saturation
-///
-/// \param pstate The initial Pstate to bias
-///
-/// \param bias The signed bias amount
-///
-/// \param biased_pstate The final biased Pstate
-///
-/// This API adds a signed bias to the \a pstate and returns the saturated sum
-/// as \a biased_pstate.  Any application that biases Pstates should use this
-/// API rather than simple addition/subtraction.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -PSTATE_OVERFLOW_BIAS_PS The biased Pstate saturated at PSTATE_MAX.
-///
-/// \retval -PSTATE_UNDERFLOW_BIAS_PS The biased Pstate saturated at PSTATE_MIN.
-
-int
-bias_pstate(Pstate pstate, int bias, Pstate* biased_pstate)
-{
-    int rc, int_pstate;
-
-    int_pstate = (int)pstate + bias; 
-    if (int_pstate != (Pstate)int_pstate) {
-        if (bias < 0) {
-            *biased_pstate = PSTATE_MIN;
-            rc = -PSTATE_UNDERFLOW_BIAS_PS;
-        } else {
-            *biased_pstate = PSTATE_MAX;
-            rc = -PSTATE_OVERFLOW_BIAS_PS;
-        }
-    } else {
-        *biased_pstate = int_pstate;
-        rc = 0;
-    }
-
-    return rc;
-}
-
-
-/// Bias a DPLL frequency code with saturation and bounds checking
-///
-/// \param fcode The initial frequency code to bias
-///
-/// \param bias The signed bias amount
-///
-/// \param biased_fcode The final biased frequency code
-///
-/// This API adds a signed bias to the \a fcode and returns the saturated and
-/// bounded sum as \a biased_fcode.  Any application that biases frequency
-/// codes should use this API rather than simple addition/subtraction.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -DPLL_OVERFLOW The biased frequency code saturated at DPLL_MAX.
-///
-/// \retval -DPLL_UNDERFLOW1 The biased frequency code saturated at DPLL_MIN.
-///
-/// \retval -DPLL_UNDERFLOW2 The biased frequency code saturated at DPLL_MIN.
-
-int
-bias_frequency(DpllCode fcode, int bias, DpllCode* biased_fcode)
-{
-    int rc;
-    unsigned uint_fcode;
-
-    uint_fcode = (unsigned)fcode + bias; 
-    if (uint_fcode != (DpllCode)uint_fcode) {
-        if (bias < 0) {
-            *biased_fcode = DPLL_MIN;
-            rc = -DPLL_UNDERFLOW1;
-        } else {
-            *biased_fcode = DPLL_MAX;
-            rc = -DPLL_OVERFLOW;
-        }
-    } else if (uint_fcode < DPLL_MIN) {
-        *biased_fcode = DPLL_MIN;
-        rc = -DPLL_UNDERFLOW2;
-    } else {
-        *biased_fcode = uint_fcode;
-        rc = 0;
-    }
-
-    return rc;
-}
-
-
-/// Bias a VRM11 VID code with saturation and bounds checking
-///
-/// \param vid The initial vid code to bias
-///
-/// \param bias The signed bias amount
-///
-/// \param biased_vid The final biased VID code
-///
-/// This API adds a signed bias to the \a vid and returns the saturated and
-/// bounded sum as \a biased_vid.  Any application that biases VID codes
-/// should use this API rather than simple addition/subtraction.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -VID11_OVERFLOW_BIAS_VID11 The biased VID code saturated 
-/// at VID11_MAX.
-///
-/// \retval -VID11_UNDERFLOW_BIAS_VID11 The biased VID code saturated 
-/// at VID11_MIN.
-
-int
-bias_vid11(Vid11 vid, int bias, Vid11* biased_vid)
-{
-    int rc;
-    unsigned uint_vid;
-
-    uint_vid = (unsigned)vid + bias; 
-    if (uint_vid != (DpllCode)uint_vid) {
-        if (bias < 0) {
-            *biased_vid = VID11_MIN;
-            rc = -VID11_UNDERFLOW_BIAS_VID11;
-        } else {
-            *biased_vid = VID11_MAX;
-            rc = -VID11_OVERFLOW_BIAS_VID11;
-        }
-    } else {
-
-        rc = vid11_validate(uint_vid);
-        *biased_vid = uint_vid;
-
-    }
-
-    return rc;
-}
-
-
-/// Retrieve an entry from the Global Pstate Table abstraction
-///
-/// \param gpst An initialized GlobalPstateTable structure.
-///
-/// \param pstate The Pstate index of the entry to fetch
-///
-/// \param bias This is a signed bias. The entry searched is the \a pstate +
-/// \a bias entry.
-///
-/// \param entry A pointer to a gpst_entry_t to hold the returned data.
-///
-/// This routine functions similar to PMC harwdare.  When a Pstate is
-/// requested the index is first biased (under/over-volted) and clipped to the
-/// defined bounds, then the Pstate entry is returned.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -GPST_PSTATE_CLIPPED_HIGH_GPST_ENTRY The requested Pstate does not 
-/// exist in the table. The maximum Pstate entry in the table has been returned.
-///
-/// \retval -GPST_PSTATE_CLIPPED_LOW_GPST_ENTRY The requested Pstate does not 
-/// exist in the table. The minimum Pstate entry in the table has been returned.
-///
-/// The following return codes are considered errors:
-///
-/// \retval -GPST_INVALID_OBJECT_GPST_ENTRY The Global Pstate Table is 
-/// either null (0) or otherwise invalid.
-
-int
-gpst_entry(const GlobalPstateTable *gpst, 
-           const Pstate pstate, 
-           int bias,
-           gpst_entry_t *entry)
-{
-    int rc, index;
-    Pstate biased_pstate;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(gpst == 0, GPST_INVALID_OBJECT_GPST_ENTRY);
-    }
-
-    rc = bias_pstate(pstate, bias, &biased_pstate);
-
-    if ((rc == -PSTATE_UNDERFLOW_BIAS_PS) || (pstate < gpst_pmin(gpst))) {
-
-        rc = -GPST_PSTATE_CLIPPED_LOW_GPST_ENTRY;
-        index = 0;
-
-    } else if ((rc == -PSTATE_OVERFLOW_BIAS_PS) || (pstate > gpst_pmax(gpst))) {
-
-        rc = -GPST_PSTATE_CLIPPED_HIGH_GPST_ENTRY;
-        index = gpst->entries - 1;
-
-    } else {
-
-        rc = 0;
-        index = pstate - gpst_pmin(gpst);
-
-    }
-
-    *entry = gpst->pstate[index];
-
-    return rc;
-}
-
-
-/// Translate a Vdd VID code to the closest Pstate in a Global Pstate table.
-///
-/// \param gpst The GlobalPstateTable to search
-///
-/// \param vdd A VID code representing an external VDD voltage
-///
-/// \param pstate The Pstate most closely matching the \a vid.
-///
-/// \param entry The GlobalPstateTable entry of the returned \a pstate.
-///
-/// This routine assumes that Pstate voltages increase monotonically from
-/// lower to higher Pstates.  The algorithm operates from lowest to highest
-/// voltage, scanning until the Pstate voltage is >= the VID voltage.  Thus
-/// the algorithm effectively rounds up voltage (unless clipped at the highest
-/// Pstate).
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -GPST_PSTATE_CLIPPED_HIGH_GPST_V2P The requested voltage does not 
-/// exist in the table. The highest legal Pstate is returned.
-///
-/// \retval -GPST_PSTATE_CLIPPED_LOW_GPST_V2P The requested voltage does not 
-/// exist in the table.  The lowest legal Pstate in the table is returned.
-///
-/// The following return codes are considered errors:
-///
-/// \retval -VRM_INVALID_VOLTAGE The \a vid is invalid.
-///
-/// \retval -GPST_INVALID_OBJECT_GPST_V2P The \a gpst argument is NULL (0).
-
-// Recall that VID codes _decrease_ as voltage _increases_
-
-int
-gpst_vdd2pstate(const GlobalPstateTable* gpst, 
-                const Vid11 vdd, 
-                Pstate* pstate,
-                gpst_entry_t* entry)
-{
-    size_t i;
-    int rc;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(gpst == 0, GPST_INVALID_OBJECT_GPST_V2P);
-    }
-
-    do {
-        rc =vid11_validate(vdd);
-        if (rc) break;
-
-        // Search for the Pstate that contains (close to) the requested
-        // voltage, then handle special cases.
-
-        for (i = 0; i < gpst->entries; i++) {
-            if (gpst->pstate[i].fields.evid_vdd <= vdd) {
-                break;
-            }
-        }
-
-        if (i == gpst->entries) {
-
-            *pstate = gpst_pmax(gpst);
-            *entry = gpst->pstate[i - 1];
-            rc = -GPST_PSTATE_CLIPPED_HIGH_GPST_V2P;
-
-        } else if ((i == 0) && (gpst->pstate[i].fields.evid_vdd < vdd)) {
-
-            *pstate = gpst_pmin(gpst);
-            *entry = gpst->pstate[0];
-            rc = -GPST_PSTATE_CLIPPED_LOW_GPST_V2P;
-
-        } else {
-
-            rc = bias_pstate(gpst_pmin(gpst), i, pstate);
-            if (rc) break;
-
-            *entry = gpst->pstate[i];
-        }
-    } while (0);
-    return rc;
-}
-
-
-/// Translate a frequency in KHz to the closest Pstate in a Global Pstate
-/// table.
-///
-/// \param gpst The GlobalPstateTable to search
-///
-/// \param frequency_khz The frequency in KHz
-///
-/// \param pstate The Pstate most closely matching the frequency, rounded down
-/// (towards lower Pstates).
-///
-///
-/// Note that the Pstate returned may or may not be represented in the Pstate
-/// table. This means that it may be higher that the highest legal frequency
-/// or lower than the lowest frequency represented in the Pstate table.
-///
-/// The following return codes are not considered errors:
-///
-/// \retval 0 Success
-///
-/// \retval -PSTATE_OVERFLOW_GPST_F2P The requested frequency translates to an
-/// unrepresentable Pstate. PSTATE_MAX (127) is returned.
-///
-/// \retval -PSTATE_UNDERFLOW_GPST_F2P The requested frequency translates to an
-/// unrepresentable Pstate. PSTATE_MIN (-128) is returned.
-int
-gpst_frequency2pstate(const GlobalPstateTable* gpst, 
-                      const uint32_t frequency_khz,
-                      Pstate* pstate)
-{
-    int rc;
-    int32_t intPstate;
-
-    // Compute the Pstate and round down
-
-    intPstate = 
-        (int32_t)(frequency_khz - gpst->pstate0_frequency_khz) / 
-        (int32_t)gpst->frequency_step_khz;
-
-    if (intPstate < 0) {
-
-        if (((int32_t)(frequency_khz - gpst->pstate0_frequency_khz) %
-             (int32_t)gpst->frequency_step_khz) != 0) {
-
-            intPstate--;
-        }
-    }
-
-
-    // Clip to legal Pstate type values
-
-    if (intPstate < PSTATE_MIN) {
-
-        *pstate = PSTATE_MIN;
-        rc = -PSTATE_UNDERFLOW_GPST_F2P;
-
-    } else if (intPstate > PSTATE_MAX) {
-
-        *pstate = PSTATE_MAX;
-        rc = -PSTATE_OVERFLOW_GPST_F2P;
-
-    } else {
-
-        *pstate = intPstate;
-        rc = 0;
-    }
-
-    return rc;
-}
diff --git a/src/lib/pstates.h b/src/lib/pstates.h
deleted file mode 100755
index 2aeb52c..0000000
--- a/src/lib/pstates.h
+++ /dev/null
@@ -1,835 +0,0 @@
-#ifndef __PSTATES_H__
-#define __PSTATES_H__
-
-// $Id: pstates.h,v 1.5 2015/05/18 15:56:07 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/pstates.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pstates.h
-/// \brief Pstate structures and support routines for OCC product firmware
-
-#include "pgp_common.h"
-
-////////////////////////////////////////////////////////////////////////////
-// Global and Local Pstate Tables
-////////////////////////////////////////////////////////////////////////////
-
-/// The Global Pstate Table must be 1KB-aligned in SRAM. The alignment is
-/// specified in the traditional log2 form.
-#define GLOBAL_PSTATE_TABLE_ALIGNMENT 10
-
-/// The Global Pstate table has 128 * 8-byte entries
-#define GLOBAL_PSTATE_TABLE_ENTRIES 128
-
-/// The Local Pstate table has 32 x 64-bit entries
-#define LOCAL_PSTATE_ARRAY_ENTRIES 32
-
-/// The VDS/VIN table has 32 x 64-bit entries
-#define VDSVIN_ARRAY_ENTRIES       64
-
-/// The VRM-11 VID base voltage in micro-Volts
-#define VRM11_BASE_UV 1612500
-
-/// The VRM-11 VID step as an unsigned number (micro-Volts)
-#define VRM11_STEP_UV 6250
-
-/// The iVID base voltage in micro-Volts
-#define IVID_BASE_UV 600000
-
-/// The iVID step as an unsigned number (micro-Volts)
-#define IVID_STEP_UV 6250
-
-///  CPM Inflection Points
-#define CPM_RANGES 8
-
-/// VPD #V Operating Points
-#define VPD_PV_POINTS 4
-#define VPD_PV_ORDER_STR {"PowerSave", "Nominal    ", "Turbo    ", "UltraTurbo"}
-#define POWERSAVE   0
-#define NOMINAL     1
-#define TURBO       2
-#define ULTRA       3
-
-/// IDDQ readings
-#define CORE_IDDQ_MEASUREMENTS 6
-#define CHIP_IDDQ_MEASUREMENTS 1
-
-#define CORE_IDDQ_ARRAY_VOLTAGES {0.80, 0.90, 1.00, 1.10, 1.20, 1.25}
-#define CHIP_IDDQ_ARRAY_VOLTAGES {1.10}
-
-/// Iddq LRPx and CRPx elements
-#define LRP_IDDQ_RECORDS    CORE_IDDQ_MEASUREMENTS
-#define CRP_IDDQ_RECORDS    CHIP_IDDQ_MEASUREMENTS
-#define IDDQ_READINGS_PER_IQ 2
-
-/// LRPx mapping to Core measurements      1      2      3      4      5       6
-///    Index                               0      1      2      3      4       5
-#define CORE_IDDQ_MEASUREMENTS_ORDER   {   1,     2,     3,     4,     5,      0}
-#define CORE_IDDQ_MEASUREMENT_VOLTAGES {"0.90", "1.00", "1.10", "1.20", "1.25", "0.80"}
-#define CORE_IDDQ_VALIDITY_CHECK       {   1,     1,     1,     1,     1,      0}
-#define CORE_IDDQ_VALID_SECOND         {   1,     1,     1,     1,     1,      0}
-
-// CRPx mapping to Chip measurements       0
-#define CHIP_IDDQ_MEASUREMENTS_ORDER    {  0 }
-#define CHIP_IDDQ_MEASUREMENT_VOLTAGES  {"1.10"}
-#define CHIP_IDDQ_VALID_SECOND          {  0 }
-
-/// WOF Items
-#define NUM_ACTIVE_CORES 12
-#define MAX_UT_PSTATES   64     // Oversized
-
-// Error/Panic codes for support routines
-
-#define VRM11_INVALID_VOLTAGE               0x00876101
-
-#define PSTATE_OVERFLOW_BIAS_PS             0x00778a01
-#define PSTATE_UNDERFLOW_BIAS_PS            0x00778a02
-#define PSTATE_OVERFLOW_GPST_F2P            0x00778a03
-#define PSTATE_UNDERFLOW_GPST_F2P           0x00778a04
-
-#define PSTATE_LT_PSTATE_MIN                0x00778a05
-#define PSTATE_GT_PSTATE_MAX                0x00778a06
-
-#define DPLL_OVERFLOW                       0x00d75501
-#define DPLL_UNDERFLOW1                     0x00d75502
-#define DPLL_UNDERFLOW2                     0x00d75503
-
-#define VID11_OVERFLOW_VID11_VALIDATE       0x00843101
-#define VID11_OVERFLOW_BIAS_VID11           0x00843102
-#define VID11_UNDERFLOW_VID11_VALIDATE      0x00843103
-#define VID11_UNDERFLOW_BIAS_VID11          0x00843104
-
-#define GPST_INVALID_OBJECT_GPST_ENTRY      0x00477801
-#define GPST_INVALID_OBJECT_GPST_V2P        0x00477802
-#define GPST_INVALID_ARGUMENT               0x00477803
-#define GPST_INVALID_ENTRY                  0x00477804
-#define GPST_PSTATE_CLIPPED_HIGH_GPSM_BGA   0x00477805
-#define GPST_PSTATE_CLIPPED_LOW_GPSM_BGA    0x00477806
-#define GPST_PSTATE_CLIPPED_HIGH_GPST_ENTRY 0x00477807
-#define GPST_PSTATE_CLIPPED_LOW_GPST_ENTRY  0x00477808
-#define GPST_PSTATE_CLIPPED_HIGH_GPST_V2P   0x00477809
-#define GPST_PSTATE_CLIPPED_LOW_GPST_V2P    0x0047780a
-#define GPST_BUG                            0x0047780b
-#define GPST_PSTATE_GT_GPST_PMAX            0x0047780c
-
-#define LPST_INVALID_OBJECT                 0x00477901
-#define LPST_GPST_WARNING                   0x00477902
-#define LPST_INCR_CLIP_ERROR                0x00477903
-
-/// PstateSuperStructure Magic Number
-///
-/// This magic number identifies a particular version of the
-/// PstateSuperStructure and its substructures.  The version number should be
-/// kept up to date as changes are made to the layout or contents of the
-/// structure.
-
-#define PSTATE_SUPERSTRUCTURE_MAGIC 0x5053544154453034ull /* PSTATE04 */
-#define PSTATE_SUPERSTRUCTURE_GOOD1 0x5053544154453031ull /* PSTATE01 */
-#define PSTATE_SUPERSTRUCTURE_GOOD2 0x5053544154453032ull /* PSTATE02 */
-#define PSTATE_SUPERSTRUCTURE_GOOD3 0x5053544154453033ull /* PSTATE03 */
-#define PSTATE_SUPERSTRUCTURE_GOOD4 0x5053544154453034ull /* PSTATE03 */
-
-
-/// \defgroup pstate_options Pstate Options
-///
-/// These are flag bits for the \a options field of the PstateOptions
-/// structure.
-///
-/// @{
-
-/// gpsm_gpst_install() - Bypass copying the Pstate table from the
-/// PstateSuperStructure into the aligned global location.
-#define PSTATE_NO_COPY_GPST       0x01
-
-/// gpsm_gpst_install() - Bypass Global Pstate Table installation and setup.
-#define PSTATE_NO_INSTALL_GPST    0x02
-
-/// gpsm_lpsa_install() - Bylass Local Pstate Array installation and setup
-#define PSTATE_NO_INSTALL_LPSA    0x04
-
-/// gpsm_resclk_install - Bypass resonant clocking Pstate limit setup
-#define PSTATE_NO_INSTALL_RESCLK  0x08
-
-/// gpsm_enable_pstates() - Force the system to the minimum Pstate at
-/// initialization
-///
-/// This mode is added as a workaround for the case that the SPIVID interface
-/// is not working correctly during initial bringup.  This forces Pstate mode
-/// to come up at a low frequency.
-#define PSTATE_FORCE_INITIAL_PMIN 0x10
-
-/// Flag to indicated that the 0.8V readings in the IDDQ Table are valid
-#define PSTATE_IDDQ_0P80V_VALID   0x20
-#define PSTATE_IDDQ_0P80V_INVALID ~PSTATE_IDDQ_0P80V_VALID
-
-/// @}
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/// A Global Pstate Table Entry, in the form of a packed 'firmware register'
-///
-/// Global Pstate table entries are referenced by OCC firmware, for example
-/// in procedures that do 'manual' Pstate manipulation.
-
-typedef union gpst_entry {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t evid_vdd     : 8;
-        uint64_t evid_vcs     : 8;
-        uint64_t reserved16   : 1;
-        uint64_t evid_vdd_eff : 7;
-        uint64_t reserved24   : 1;
-        uint64_t evid_vcs_eff : 7;
-        uint64_t reserved32   : 1;
-        uint64_t maxreg_vdd   : 7;
-        uint64_t reserved40   : 1;
-        uint64_t maxreg_vcs   : 7;
-        uint64_t reserved48   : 8;
-        uint64_t ecc          : 8;
-#else
-        uint64_t ecc          : 8;
-        uint64_t reserved48   : 8;
-        uint64_t maxreg_vcs   : 7;
-        uint64_t reserved40   : 1;
-        uint64_t maxreg_vdd   : 7;
-        uint64_t reserved32   : 1;
-        uint64_t evid_vcs_eff : 7;
-        uint64_t reserved24   : 1;
-        uint64_t evid_vdd_eff : 7;
-        uint64_t reserved16   : 1;
-        uint64_t evid_vcs     : 8;
-        uint64_t evid_vdd     : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-
-} gpst_entry_t;
-
-
-/// A Local Pstate Table Entry, in the form of a packed 'firmware register'
-///
-/// This structure is provided for reference only; Currently the OCC firmware
-/// does not manupulate Local Pstate table entries, however it is possible
-/// that future lab applications will require this.
-
-typedef union lpst_entry {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t ivid_vdd          : 7;
-        uint64_t ivid_vcs          : 7;
-        uint64_t vdd_core_pwrratio : 6;
-        uint64_t vcs_core_pwrratio : 6;
-        uint64_t vdd_eco_pwrratio  : 6;
-        uint64_t vcs_eco_pwrratio  : 6;
-        uint64_t ps1_vid_incr      : 3;
-        uint64_t ps2_vid_incr      : 3;
-        uint64_t ps3_vid_incr      : 3;
-        uint64_t reserved47        : 7;
-        uint64_t inc_step          : 3;
-        uint64_t dec_step          : 3;
-        uint64_t reserved60        : 4;
-#else
-        uint64_t reserved60        : 4;
-        uint64_t dec_step          : 3;
-        uint64_t inc_step          : 3;
-        uint64_t reserved47        : 7;
-        uint64_t ps3_vid_incr      : 3;
-        uint64_t ps2_vid_incr      : 3;
-        uint64_t ps1_vid_incr      : 3;
-        uint64_t vcs_eco_pwrratio  : 6;
-        uint64_t vdd_eco_pwrratio  : 6;
-        uint64_t vcs_core_pwrratio : 6;
-        uint64_t vdd_core_pwrratio : 6;
-        uint64_t ivid_vcs          : 7;
-        uint64_t ivid_vdd          : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-
-} lpst_entry_t;
-
-
-/// A VDS/VIN table Entry
-
-typedef union vdsvin_entry {
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivid0             : 7;
-    uint64_t ivid1             : 7;
-    uint64_t reserved14        : 2;
-    uint64_t pfet0             : 5;
-    uint64_t pfet1             : 5;
-    uint64_t pfet2             : 5;
-    uint64_t pfet3             : 5;
-    uint64_t pfet4             : 5;
-    uint64_t pfet5             : 5;
-    uint64_t pfet6             : 5;
-    uint64_t pfet7             : 5;
-    uint64_t reserved_56       : 8;
-#else
-    uint64_t reserved_56       : 8;
-    uint64_t pfet7             : 5;
-    uint64_t pfet6             : 5;
-    uint64_t pfet5             : 5;
-    uint64_t pfet4             : 5;
-    uint64_t pfet3             : 5;
-    uint64_t pfet2             : 5;
-    uint64_t pfet1             : 5;
-    uint64_t pfet0             : 5;
-    uint64_t reserved14        : 2;
-    uint64_t ivid1             : 7;
-    uint64_t ivid0             : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-} vdsvin_entry_t;
-
-/// Standard options controlling Pstate setup and GPSM procedures
-
-typedef struct {
-
-    /// Option flags; See \ref pstate_options
-    uint32_t options;
-
-    /// Pad structure to 8 bytes.  Could also be used for other options later.
-    uint32_t pad;
-
-} PstateOptions;
-
-
-/// An abstract Global Pstate table
-///
-/// The GlobalPstateTable is an abstraction of a set of voltage/frequency
-/// operating points along with hardware limits.  Besides the hardware global
-/// Pstate table, the abstract table contains enough extra information to make
-/// it the self-contained source for setting up and managing voltage and
-/// frequency in either Hardware or Firmware Pstate mode.
-///
-/// When installed in PMC, Global Pstate table indices are adjusted such that
-/// the defined Pstates begin with table entry 0. The table need not be full -
-/// the \a pmin and \a entries fields define the minimum and maximum Pstates
-/// represented in the table.  However at least 1 entry must be defined to
-/// create a legal table.
-///
-/// Note that Global Pstate table structures to be mapped into PMC hardware
-/// must be 1KB-aligned.  This requirement is fullfilled by ensuring that
-/// instances of this structure are 1KB-aligned.
-
-typedef struct {
-
-    /// The Pstate table
-    gpst_entry_t pstate[GLOBAL_PSTATE_TABLE_ENTRIES];
-
-    /// Pstate options
-    ///
-    /// The options are included as part of the GlobalPstateTable so that they
-    /// are available to all procedures after gpsm_initialize().
-    PstateOptions options;
-
-    /// The frequency associated with Pstate[0] in KHz
-    uint32_t pstate0_frequency_khz;
-
-    /// The frequency step in KHz
-    uint32_t frequency_step_khz;
-
-    /// The DPLL frequency code corresponding to Pstate 0
-    ///
-    /// This frequency code is installed in the PCB Slave as the DPLL Fnom
-    /// when the Pstate table is activated. Normally this frequency code is
-    /// computed as
-    ///
-    ///     pstate0_frequency_khz / frequency_step_khz
-    ///
-    /// however it may be replaced by any other code as a way to
-    /// transparently bias frequency on a per-core basis.
-    DpllCode pstate0_frequency_code[PGP_NCORES];
-
-    /// The DPLL Fmax bias
-    ///
-    /// This bias value (default 0, range -8 to +7 frequency ticks) is
-    /// installed when the Pstate table is installed.  The value is allowed to
-    /// vary per core.  This bias value will usually be set to a small
-    /// positive number to provide a small amount of frequency headroom for
-    /// the CPM-DPLL voltage control algorithm.
-    ///
-    /// \bug Hardware currently specifies this field as unsigned for the
-    /// computation of frequency stability in
-    /// dpll_freqout_mode_en. (HW217404).  This issue will be fixed in
-    /// Venice. Since we never plan to use this mode no workaround or
-    /// mitigation is provided by GPSM procedures.
-
-    int8_t dpll_fmax_bias[PGP_NCORES];
-
-    /// The number of entries defined in the table.
-    uint8_t entries;
-
-    /// The minimum Pstate in the table
-    ///
-    /// Note that gpsi_min = pmin - PSTATE_MIN, gpsi_max = pmin + entries - 1.
-    Pstate pmin;
-
-    /// The "Safe" Global Pstate
-    ///
-    /// This Pstate is installed in the PMC and represents the safe-mode
-    /// voltage.
-    Pstate pvsafe;
-
-    /// The "Safe" Local Pstate
-    ///
-    /// This Pstate is installed in the PCB Slaves and represents the
-    /// safe-mode frequency.
-    Pstate psafe;
-
-    /// Step size of Global Pstate steps
-    uint8_t pstate_stepsize;
-
-    /// The exponent of the exponential encoding of Pstate stepping delay
-    uint8_t vrm_stepdelay_range;
-
-    /// The significand of the exponential encoding of Pstate stepping delay
-    uint8_t vrm_stepdelay_value;
-
-    /// The Pstate for minimum core frequency in the system, defined by MRW
-    uint8_t pfloor;
-
-    /// The Pstate representing the Turbo VPD point
-    Pstate turbo_ps;
-
-    /// The Pstate representing the Nominal VPD point
-    Pstate nominal_ps;
-
-    /// The Pstate representing the PowerSave VPD point
-    Pstate powersave_ps;
-
-    /// The Pstate within the GPST which is the maximum for which iVRMs are
-    /// defined.  This allows WOF Pstate and iVRM Pstates to be non-overlapping
-    /// to simplify characterization.
-    Pstate ivrm_max_ps;
-
-    /// The number of entries over which iVRM enablement is possible.  The
-    /// starting entry is PMin.
-    uint8_t ivrm_entries;
-
-} GlobalPstateTable;
-
-
-/// This macro creates a properly-aligned Global Pstate table structure as a
-/// static initialization.
-
-#define GLOBAL_PSTATE_TABLE(x)                                  \
-    GlobalPstateTable x                                         \
-    ALIGNED_ATTRIBUTE(POW2_32(GLOBAL_PSTATE_TABLE_ALIGNMENT))   \
-        SECTION_ATTRIBUTE(".noncacheable")                      \
-        = {.entries = 0}
-
-
-/// An opaque Local Pstate Array
-///
-/// An array local to each core contains the Local Pstate Table, Vds table and
-/// Vin table. The array contents are presented to OCC firmware as an opaque
-/// set of 96 x 64-bit entries which are simply installed verbatim into each
-/// core. Every core stores the same table.
-///
-/// When installed in the core, Local Pstate table indices are adjusted such
-/// that the defined Pstates begin with table entry 0. The table need not be
-/// full - the \a pmin and \a entries fields define the minimum and maximum
-/// Pstates represented in the table.  However at least 1 entry must be
-/// defined to create a legal table.
-
-typedef struct {
-
-    /// The vdsvin table contents
-    vdsvin_entry_t vdsvin[VDSVIN_ARRAY_ENTRIES];
-
-    /// The local pstate table contents
-    lpst_entry_t pstate[LOCAL_PSTATE_ARRAY_ENTRIES];
-
-    /// The number of entries defined in the Local Pstate Table
-    uint8_t entries;
-
-    /// The minimum Pstate in the Local Pstate table
-    ///
-    /// Note that lpsi_min = pmin - PSTATE_MIN, lpsi_max = pmin + entries - 1.
-    Pstate pmin;
-
-    /// Pstate step delay for rising iVRM voltages
-    uint8_t stepdelay_rising;
-
-    /// Pstate step delay for falling iVRM voltages
-    uint8_t stepdelay_lowering;
-
-    /// Pad structure to 8-byte alignment
-    uint8_t pad[4];
-
-} LocalPstateArray;
-
-
-/// Resonant Clocking setup parameters
-///
-/// All Pstate parameters are specified in terms of Pstates as defined in the
-/// current PstateSuperStructure.
-
-typedef struct {
-
-    /// Full Clock Sector Buffer Pstate
-    Pstate full_csb_ps;
-
-    /// Low-Frequency Resonant Lower Pstate
-    Pstate res_low_lower_ps;
-
-    /// Low-Frequency Resonant Upper Pstate
-    Pstate res_low_upper_ps;
-
-    /// High-Frequency Resonant Lower Pstate
-    Pstate res_high_lower_ps;
-
-    /// High-Frequency Resonant Upper Pstate
-    Pstate res_high_upper_ps;
-
-    /// Pad structure to 8-byte alignment
-    uint8_t pad[3];
-
-} ResonantClockingSetup;
-
-/// CPM Pstate ranges per mode
-///
-/// These Pstate range specifications apply to all chiplets operating in the
-/// same mode.
-
-typedef union {
-
-    /// Forces alignment
-    uint64_t quad[2];
-
-    struct {
-
-        /// Lower limit of each CPM calibration range
-        ///
-        /// The entries in this table are Pstates representing the
-        /// lowest-numbered (lowest-voltage) Pstate of each range. This is the
-        /// inflection point between range N and range N+1.
-        Pstate inflectionPoint[CPM_RANGES];
-
-        /// The number of ranges valid in the \a inflectionPoint table
-        ///
-        /// Validity here is defined by the original characterization
-        /// data. Whether or not OCC will use any particular range is managed
-        /// by OCC.
-        uint8_t validRanges;
-
-        /// The Pstate corresponding to the upper limit of range 0.
-        ///
-        /// This is the "CPmax" for the mode. The "CPmin" for this
-        /// mode is the value of inflectionPoint[valid_ranges - 1].
-        Pstate pMax;
-
-        uint8_t pad[6];
-    };
-
-} CpmPstateModeRanges;
-
-
-/// A VPD operating point
-///
-/// VPD operating points are stored without load-line correction.  Frequencies
-/// are in MHz, voltages are specified in units of 5mV, and characterization
-/// currents are specified in units of 500mA.
-///
-/// \bug The assumption is that the 'maxreg' points for the iVRM will also be
-/// supplied in the VPD in units of 5mv.  If they are supplied in some other
-/// form then chip_characterization_create() will need to be modified.
-
-typedef struct {
-
-    uint32_t vdd_5mv;
-    uint32_t vcs_5mv;
-    uint32_t vdd_maxreg_5mv;
-    uint32_t vcs_maxreg_5mv;
-    uint32_t idd_500ma;
-    uint32_t ics_500ma;
-    uint32_t frequency_mhz;
-
-} VpdOperatingPoint;
-
-/// System Power Distribution Paramenters
-///
-/// Parameters set by system design that influence the power distribution
-/// for a rail to the processor module.  This values are typically set in the
-/// system machine readable workbook and are used in the generation of the
-/// Global Pstate Table.  This values are carried in the Pstate SuperStructure
-/// for use and/or reference by OCC firmware (eg the WOF algorithm)
-
-typedef struct {
-
-    /// Loadline
-    ///   Impedance (binary microOhms) of the load line from a processor VDD VRM
-    ///   to the Processor Module pins.
-    uint32_t loadline_uohm;
-
-    /// Distribution Loss
-    ///   Impedance (binary in microOhms) of the VDD distribution loss sense point
-    ///   to the circuit.
-    uint32_t distloss_uohm;
-
-    /// Distribution Offset
-    ///   Offset voltage (binary in microvolts) to apply to the rail VRM
-    ///   distribution to the processor module.
-    uint32_t distoffset_uv;
-
-} SysPowerDistParms;
-
-
-
-/// IDDQ Reading Type
-/// Each entry is 2 bytes. The values are in 10mA units; this allow for a
-/// maximum value of 655.36A represented.
-///
-typedef uint16_t iddq_entry_t;
-
-/// IDDQ Reading
-///
-/// Structure with "raw" and "temperature corrected" values.  See VPD
-/// documentation for the correction function that is applied to the raw
-/// value to load the corrected value.
-///
-typedef union {
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        iddq_entry_t iddq_raw_value;
-        iddq_entry_t iddq_corrected_value;
-#else
-        iddq_entry_t iddq_corrected_value;
-        iddq_entry_t iddq_raw_value;
-#endif // _BIG_ENDIAN
-    } fields;
-
-} IddqReading;
-
-/// Iddq Table
-///
-/// A set of arrays of leakage values (Iddq) collected at various voltage
-/// conditions during manufacturing test that will feed into the Workload
-/// Optimized Frequency algorithms on the OCC.  These values are not installed
-/// in any hardware facilities.
-///
-typedef struct {
-
-    /// IDDQ version
-    uint8_t     iddq_version;
-
-    /// VDD IDDQ readings
-    IddqReading iddq_vdd[CORE_IDDQ_MEASUREMENTS];
-
-    /// VCS IDDQ readings
-    IddqReading iddq_vcs[CORE_IDDQ_MEASUREMENTS];
-
-    /// VIO IDDQ readings
-    IddqReading iddq_vio[CHIP_IDDQ_MEASUREMENTS];
-
-} IddqTable;
-
-
-
-/// UltraTurbo Segment VIDs by Core Count
-typedef struct {
-
-    /// Number of Segment Pstates
-    uint8_t     ut_segment_pstates;
-
-    /// Maximum number of core possibly active
-    uint8_t     ut_max_cores;
-
-    /// VDD VID modification
-    ///      1 core active  = offset 0
-    ///      2 cores active = offset 1
-    ///         ...
-    ///      12 cores active = offset 11
-    uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
-
-    /// VCS VID modification
-    ///      1 core active  = offset 0
-    ///      2 cores active = offset 1
-    ///         ...
-    ///      12 cores active = offset 11
-    uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES];
-
-} VIDModificationTable;
-
-/// Workload Optimized Frequency (WOF) Elements
-///
-/// Structure defining various control elements needed by the WOF algorithm
-/// firmware running on the OCC.
-///
-typedef struct {
-
-    /// WOF Enablement
-    uint8_t wof_enabled;
-
-    /// Operating points
-    ///
-    /// VPD operating points are stored without load-line correction.  Frequencies
-    /// are in MHz, voltages are specified in units of 5mV, and currents are
-    /// in units of 500mA.
-    VpdOperatingPoint operating_points[VPD_PV_POINTS];
-
-    /// Loadlines and Distribution values for the VDD rail
-    SysPowerDistParms vdd_sysparm;
-
-    /// Loadlines and Distribution values for the VCS rail
-    SysPowerDistParms vcs_sysparm;
-
-    /// TDP<>RDP Current Factor
-    ///   Value read from ??? VPD
-    ///   Defines the scaling factor that converts current (amperage) value from
-    ///   the Thermal Design Point to the Regulator Design Point (RDP) as input
-    ///   to the Workload Optimization Frequency (WOF) OCC algorithm.
-    ///
-    ///   This is a ratio value and has a granularity of 0.01 decimal.  Data
-    ///   is held in hexidecimal (eg 1.22 is represented as 122 and then converted
-    ///   to hex 0x7A).
-    uint32_t tdp_rdp_factor;
-
-    /// UltraTurbo Segment VIDs by Core Count
-    VIDModificationTable ut_vid_mod;
-
-    uint8_t pad[4];
-
-} WOFElements;
-
-
-/// The layout of the data created by the Pstate table creation firmware
-///
-/// This structure is only used for passing Pstate data from the FSP into OCC,
-/// therefore there is no alignment requirement.  The \gpst member is copied
-/// to an aligned location, and the \a lpsa and \a resclk members are directly
-/// installed in hardware.
-///
-/// Both the master and slave OCCs (in DCM-mode) install their Pstate tables
-/// independently via the API gpsm_initialize().  At that point the
-/// PstateSuperStructure can be discarded.
-
-typedef struct {
-
-    /// Magic Number
-    uint64_t magic;
-
-    /// Global Pstate Table
-    GlobalPstateTable gpst;
-
-    /// Local Pstate Array
-    LocalPstateArray lpsa;
-
-    /// Resonant Clocking Setup
-    ResonantClockingSetup resclk;
-
-    /// CPM Pstate ranges
-    CpmPstateModeRanges cpmranges;
-
-    /// Iddq Table
-    IddqTable iddq;
-
-    /// WOF Controls
-    WOFElements wof;
-
-} PstateSuperStructure;
-
-
-int
-vid11_validate(Vid11 vid);
-
-int
-bias_pstate(Pstate pstate, int bias, Pstate* biased_pstate);
-
-int
-bias_frequency(DpllCode fcode, int bias, DpllCode* biased_fcode);
-
-int
-bias_vid11(Vid11 vid, int bias, Vid11* biased_fcode);
-
-int
-gpst_entry(const GlobalPstateTable* gpst,
-           const Pstate pstate,
-           const int bias,
-           gpst_entry_t* entry);
-
-int
-gpst_frequency2pstate(const GlobalPstateTable* gpst,
-                      const uint32_t frequency_khz,
-                      Pstate* pstate);
-
-int
-gpst_vdd2pstate(const GlobalPstateTable* gpst,
-                const uint8_t vdd,
-                Pstate* pstate,
-                gpst_entry_t* entry);
-
-
-/// Return the Pmin value associated with a GlobalPstateTable
-static inline Pstate
-gpst_pmin(const GlobalPstateTable* gpst)
-{
-    return gpst->pmin;
-}
-
-
-/// Return the Pmax value associated with a GlobalPstateTable
-static inline Pstate
-gpst_pmax(const GlobalPstateTable* gpst)
-{
-    return (int)(gpst->pmin) + (int)(gpst->entries) - 1;
-}
-
-/// Return the Pmin value associated with a LocalPstateTable
-static inline Pstate
-lpst_pmin(const LocalPstateArray* lpsa)
-{
-    return lpsa->pmin;
-}
-
-
-/// Return the Pmax value associated with a GlobalPstateTable
-static inline Pstate
-lpst_pmax(const LocalPstateArray* lpsa)
-{
-    return (int)(lpsa->pmin) + (int)(lpsa->entries) - 1;
-}
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __PSTATES_H__ */
diff --git a/src/lib/special_wakeup.c b/src/lib/special_wakeup.c
deleted file mode 100644
index 59e3274..0000000
--- a/src/lib/special_wakeup.c
+++ /dev/null
@@ -1,149 +0,0 @@
-// $Id: special_wakeup.c,v 1.4 2014/02/03 01:30:25 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/special_wakeup.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file special_wakeup.c
-/// \brief Container for special wakeup related procedures
-
-#include "special_wakeup.h"
-
-uint32_t G_special_wakeup_count[PGP_NCORES] = {0};
-
-/// Enter or clear special wakeup for a core
-///
-/// \param set 1 = set, 0 = clear, all other values will cause an error.
-///
-/// \param cores = mask of cores to set/clear special wakeup.
-///
-/// \param[out] o_timeouts.  Mask of cores that timed out before special wakeup
-/// complete was observed.
-///
-/// \retval 0 Success
-///
-/// \retval -SPWU_INVALID_ARGUMENT One of the arguments was invalid in some way
-///
-/// \retval others This API may also return non-0 codes from
-/// getscom()/putscom()
-///
-/// If getscom/putscom rc = 0, the state of the global special_wakeup counts
-/// may no longer be valid.
-///
-
-int
-occ_special_wakeup(int set,
-                   ChipConfigCores cores,
-                   int timeout_ms,
-                   ChipConfigCores *o_timeouts)
-
-{
-
-    pmc_core_deconfiguration_reg_t pcdr;
-    pcbs_pmgp0_reg_t pmgp0;
-    pcbs_pmspcwkupocc_reg_t ppr;
-    ChipConfigCores core_list;
-    ChipConfigCores awake_list = 0;
-    ChipConfigCores success_list = 0;
-    ChipConfigCores poll_list = 0;
-    ChipConfigCores timeout_list = 0;
-    int rc, poll_count, core;
-    int time = 0;
-    int bad_clear;
-
-    // get pmc deconfig vector
-    pcdr.value = in32(PMC_CORE_DECONFIGURATION_REG);
-
-    core_list = cores;
-    bad_clear = 0;
-    if (! set) {
-        for (core = 0; core < PGP_NCORES; core++, core_list <<=1) {
-            if (core_list & (0x1 << (PGP_NCORES - 1))) {
-                if (G_special_wakeup_count[core] == 0) {
-                    bad_clear = 1;
-                }
-            }
-        }
-    }
-
-    
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF( (set < 0) ||
-                      (set > 1) ||
-                      (bad_clear) ||
-                      (pcdr.fields.core_chiplet_deconf_vector & cores),
-                      SPWU_INVALID_ARGUMENT);
-    }
-
-    do {
-        ppr.value = 0;
-        if (set) {
-            // If count is currently zero, set the bit and increment count.
-            // Otherwise, just increment count
-            core_list = cores;
-            for (core = 0; core < PGP_NCORES; core++, core_list <<=1) {
-                if (core_list & (0x1 << (PGP_NCORES - 1))) {
-                    if (! G_special_wakeup_count[core]) {
-                        ppr.fields.occ_special_wakeup = 1;
-                        rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMSPCWKUPOCC_REG, core), ppr.value);
-                        poll_list |= (0x1 << (PGP_NCORES - 1 - core));  
-                    }
-                    if (rc) break;  // break for loop
-                    ++G_special_wakeup_count[core];
-                    success_list |= (0x1 << (PGP_NCORES - 1 - core)); 
-                }
-            }
-            if (rc) break;
-            
-            // poll special_wkup_done bit.
-            poll_count = 0;
-            while ((poll_list != awake_list) && (time < timeout_ms)) {
-                if (! poll_count) {
-                    ssx_sleep(SSX_MICROSECONDS(2));
-                    ++poll_count;
-                } else {
-                    ssx_sleep(SSX_MILLISECONDS(5));
-                    time += 5;
-                }
-                core_list = poll_list & (~awake_list);
-                for (core = 0; core < PGP_NCORES; core++, core_list <<=1) {
-                    if (core_list & (0x1 << (PGP_NCORES - 1))) {
-                        rc = getscom(CORE_CHIPLET_ADDRESS(PCBS_PMGP0_REG, core), &pmgp0.value);
-                        if (rc) break;
-                        if (pmgp0.fields.special_wkup_done) { 
-                            awake_list |= (0x1 << (PGP_NCORES - 1 - core));
-                        } else {
-                            if (time >= timeout_ms) {
-                                timeout_list |= (0x1<<(PGP_NCORES-1-core));
-                            }
-                        }
-                    }
-                }                   
-            }       
-        } else { // clear special wakeup
-            core_list = cores;
-            for (core = 0; core < PGP_NCORES; core++, core_list <<=1) {
-                if (core_list & (0x1 << (PGP_NCORES - 1))) {
-                    if (G_special_wakeup_count[core] == 1) {
-                        ppr.fields.occ_special_wakeup = 0;
-                        rc = putscom(CORE_CHIPLET_ADDRESS(PCBS_PMSPCWKUPOCC_REG, core), ppr.value);
-                    }
-                    if (rc) break;
-                    --G_special_wakeup_count[core];
-                    success_list |= (0x1 << (PGP_NCORES - 1 - core));     
-                }
-            }
-            if (rc) break;
-        }
-    } while (0);
-
-    // bad rc recovery (recovery of counts, etc?)
-
-    *o_timeouts = timeout_list;
-    return rc;
-
-}
-                         
-            
diff --git a/src/lib/special_wakeup.h b/src/lib/special_wakeup.h
deleted file mode 100644
index 88b8ec0..0000000
--- a/src/lib/special_wakeup.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __SPECIAL_WAKEUP_H__
-#define __SPECIAL_WAKEUP_H__
-
-// $Id: special_wakeup.h,v 1.2 2014/02/03 01:30:25 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/special_wakeup.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file special_wakeup.h
-/// \brief Container for special wakeup related procedures
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-#include "pgp_config.h"
-#include "ssx.h"
-
-#define SPWU_INVALID_ARGUMENT 0x00779801
-
-extern uint32_t G_special_wakeup_count[PGP_NCORES];
-
-int
-occ_special_wakeup(int set,
-                   ChipConfigCores cores,
-                   int timeout_ms,
-                   ChipConfigCores *o_timeouts);
-
-#endif  /* __ASEMBLER__ */
-#endif  /* __SPECIAL_WAKEUP_H__ */
diff --git a/src/lib/strdup.c b/src/lib/strdup.c
deleted file mode 100755
index c6ac04c..0000000
--- a/src/lib/strdup.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// $Id: strdup.c,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/strdup.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file strdup.c
-/// \brief Functions from <string.h> that require malloc()
-///
-/// These APIs are split from string.c for the benefit of applications like
-/// OCC FW that don't use malloc().
-
-#include <stdlib.h>
-#include <string.h>
-
-/// Duplicate a string
-///
-/// \param s The string to duplicate
-///
-/// The strdup() function returns a pointer to a new string which is a
-/// duplicate of the input string \a s.  Memory for the new string is obtained
-/// with malloc(), and can be freed with free().
-///
-/// \returns The strdup() function returns a pointer to the duplicated string,
-/// or NULL (0) if insufficient memory was available.
-
-char *
-strdup(const char* s)
-{
-    char* dup;
-
-    dup = (char*)malloc(strlen(s) + 1);
-    if (dup != 0) {
-        strcpy(dup, s);
-    }
-    return dup;
-}
diff --git a/src/lib/string.h b/src/lib/string.h
deleted file mode 100755
index 2376463..0000000
--- a/src/lib/string.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __STRING_H__
-#define __STRING_H__
-
-// $Id: string.h,v 1.1.1.1 2013/12/11 20:49:20 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/string.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file string.h
-/// \brief Replacement for <string.h>
-///
-/// The SSX library does not implement the entire <string.h> function.
-/// However the real reason for this header was the finding that under certain
-/// optimization modes, we were geting errors from the default <string.h>
-/// supplied with the MPC environment.  So we created this replacement that
-/// only calls out what is implemented, exactly as it is implemented for SSX.
-
-#ifndef __ASSEMBLER__
-
-#include <stddef.h>
-
-// APIs inmplemented by string.c
-
-size_t 
-strlen(const char *s);
-
-int
-strcmp(const char* s1, const char* s2);
-
-int 
-strncmp(const char* s1, const char* s2, size_t n);
-
-int
-strcasecmp(const char* s1, const char* s2);
-
-int 
-strncasecmp(const char* s1, const char* s2, size_t n);
-
-char *
-strcpy(char *dest, const char *src);
-
-char *
-strncpy(char *dest, const char *src, size_t n);
-
-void *
-memcpy(void *dest, const void *src, size_t n);
-
-void *
-memset(void *s, int c, size_t n);
-
-int
-memcmp(const void* s1, const void* s2, size_t n);
-
-// APIs implemented by strdup.c
-
-char *
-strdup(const char* s);
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __STRING_H__ */
diff --git a/src/lib/vrm.c b/src/lib/vrm.c
deleted file mode 100755
index 57f19fa..0000000
--- a/src/lib/vrm.c
+++ /dev/null
@@ -1,394 +0,0 @@
-// $Id: vrm.c,v 1.2 2014/02/03 01:30:26 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/vrm.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file vrm.c
-/// \brief PgP SPIVRM procedures
-
-#include "vrm.h"
-
-// The semaphore used to block threads waiting for o2s operations to complete
-
-static SsxSemaphore o2s_protocol_semaphore;
-
-
-/// o2s_initialize follows the steps for setting up the o2s bridge as outlined
-/// In the Energy Management spec (PMC section)
-int 
-o2s_initialize()
-{
-    pmc_o2s_ctrl_reg0a_t pocr0a;
-    pmc_o2s_ctrl_reg0b_t pocr0b;
-    pmc_o2s_ctrl_reg1_t pocr1;
-
-
-    ssx_semaphore_create(&o2s_protocol_semaphore, 0, 1);
-
-    ssx_irq_disable(PGP_IRQ_OCI2SPIVID_ONGOING);
-    
-    ssx_irq_setup(PGP_IRQ_OCI2SPIVID_ONGOING,
-                  SSX_IRQ_POLARITY_ACTIVE_LOW,
-                  SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
-
-    ssx_irq_handler_set(PGP_IRQ_OCI2SPIVID_ONGOING,
-                        ssx_semaphore_post_handler,
-                        (void *)(&o2s_protocol_semaphore),
-                        SSX_NONCRITICAL);
-
-    pocr0a.value = in32(PMC_O2S_CTRL_REG0A);
-    pocr0a.fields.o2s_frame_size = 32;
-    pocr0a.fields.o2s_out_count1 = 32;
-    pocr0a.fields.o2s_in_delay1 = 0x3F;
-    pocr0a.fields.o2s_in_count1 = 0;
-    out32(PMC_O2S_CTRL_REG0A, pocr0a.value);
-
-    pocr0b.value = in32(PMC_O2S_CTRL_REG0B);
-    pocr0b.fields.o2s_out_count2 = 0;
-    pocr0b.fields.o2s_in_delay2 = 0;
-    pocr0b.fields.o2s_in_count2 = 32;
-    out32(PMC_O2S_CTRL_REG0B, pocr0b.value);
-
-    pocr1.value = in32(PMC_O2S_CTRL_REG1);
-    pocr1.fields.o2s_bridge_enable = 1;
-    pocr1.fields.o2s_cpol = 0;
-    pocr1.fields.o2s_cpha = 0;
-    pocr1.fields.o2s_clock_divider = 29; // 10 MHz(?)
-    pocr1.fields.o2s_nr_of_frames = 1;  // 2 frames
-    out32(PMC_O2S_CTRL_REG1, pocr1.value);
-
-    return 0;
-
-}
-
-/// similar to o2s_intialize, but for the automated spivid fsm
-/// \param vrm_select A 3-bit vector of VRM selected for the operation.
-///
-/// NOTE:  The spivid is normally initialized by Host Boot
-///
-/// \retval 0 Success
-int
-spivid_initialize(int vrm_select)
-{
-    pmc_spiv_ctrl_reg0a_t pocr0a;
-    pmc_spiv_ctrl_reg0b_t pocr0b;
-    pmc_spiv_ctrl_reg1_t pocr1;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((vrm_select <= 0) ||
-                     (vrm_select > 0x7),
-                     VRM_INVALID_ARGUMENT_INIT);
-    }
-
-
-    pocr0a.value = in32(PMC_SPIV_CTRL_REG0A);
-    pocr0a.fields.spivid_frame_size = 32;
-    pocr0a.fields.spivid_out_count1 = 32;
-    pocr0a.fields.spivid_in_delay1 = 0x3F;
-    pocr0a.fields.spivid_in_count1 = 0;
-    out32(PMC_SPIV_CTRL_REG0A, pocr0a.value);
-
-    pocr0b.value = in32(PMC_SPIV_CTRL_REG0B);
-    pocr0b.fields.spivid_out_count2 = 0;
-    pocr0b.fields.spivid_in_delay2 = 0;
-    pocr0b.fields.spivid_in_count2 = 32;
-    out32(PMC_SPIV_CTRL_REG0B, pocr0b.value);
-
-    pocr1.value = in32(PMC_SPIV_CTRL_REG1);
-    pocr1.fields.spivid_fsm_enable = 1;
-    pocr1.fields.spivid_cpol = 0;
-    pocr1.fields.spivid_cpha = 0;
-    pocr1.fields.spivid_clock_divider = 29; // 10 MHz(?)
-    pocr1.fields.spivid_port_enable = vrm_select; 
-    out32(PMC_SPIV_CTRL_REG1, pocr1.value);
-
-    return 0;
-
-}
-
-
-// Start an O2S transaction and poll for completion.  Optionally return the
-// input data.
-
-static void
-o2s_start_poll(uint64_t out, uint64_t *in)
-{
-
-    out32(PMC_O2S_WDATA_REG, out >> 32);
-
-    if (!ssx_irq_status_get(PGP_IRQ_OCI2SPIVID_ONGOING)) {
-        ssx_irq_enable(PGP_IRQ_OCI2SPIVID_ONGOING);
-        ssx_semaphore_pend(&o2s_protocol_semaphore, SSX_WAIT_FOREVER);
-    }
-
-
-    if (in != 0) {
-        *in = in32(PMC_O2S_RDATA_REG);
-    }
-}
-
-
-/// Write a voltage using the O2S bridge
-///
-/// \param vrm_select A 3-bit vector of VRM selected for the operation.
-///
-/// \param vdd_vid The VRM-11 VID code for Vdd.
-///
-/// \param vcs_offset The signed offset (Vdiff) equal to Vcs - Vdd expressed
-/// in VRM-11 VID units.
-///
-/// \param phases The number of phases enabled.
-///
-/// This is a polling CPU procedure that writes a new voltage to a set of one
-/// or more VRM then does a status read to make sure it succeeded.
-///
-/// \retval 0 Success
-///
-/// \retval -VRM_INVALID_ARGUMENT_VWRITE One of the arguments was invalid in 
-/// some way.
-///
-/// \retval -O2S_BUSY_VRM_VOLTAGE_WRITE The O2S bridge is currently busy
-///
-/// \retval -O2S_READ_NOT_READY A 'read not ready' condition occurred on the
-/// status read.
-///
-/// \retval -O2S_WRITE_NOT_VALID The voltage write was invalid
-///
-/// \retval -O2S_ECC_ERROR An ECC error occurred
-///
-/// \todo We need to understand what the firmware is expected to do when the
-/// 'read not ready' or other error responses come back.  Here they will
-/// likely panic.
-
-int
-vrm_voltage_write(int vrm_select, 
-                  uint8_t vdd_vid, 
-                  int8_t vcs_offset, 
-                  int phases)
-{
-    int i, port;
-    uint64_t result;
-    pmc_o2s_ctrl_reg1_t pocr;
-    pmc_o2s_status_reg_t posr;
-    vrm_write_transaction_t vwt;
-    vrm_write_resp_t vwr;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((vrm_select <= 0) ||
-                     (vrm_select > 0x7) ||
-                     (phases < 0) ||
-                     (phases > 0xf),
-                     VRM_INVALID_ARGUMENT_VWRITE);
-    }
-
-    // Check for O2S busy
-
-    posr.value = in32(PMC_O2S_STATUS_REG);
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(posr.fields.o2s_ongoing, O2S_BUSY_VRM_VOLTAGE_WRITE);
-    }
-
-    // Use O2S to set voltage and read status, one port at a time.
-
-    for (i = 0; i < SPIVRM_NPORTS; i++) {
-        
-        port = vrm_select & SPIVRM_PORT(i);
-        if (port != 0) {
-
-            // Set the (singular) O2S port
-
-            pocr.value = in32(PMC_O2S_CTRL_REG1);
-            pocr.fields.o2s_port_enable = port;
-            out32(PMC_O2S_CTRL_REG1, pocr.value);
-
-            // Create and initiate a voltage write command
-
-            vwt.value = 0;
-            vwt.fields.command = VRM_WRITE_VOLTAGE;
-            vwt.fields.vdd_vid = vdd_vid;
-            vwt.fields.vcs_offset = vcs_offset;
-            vwt.fields.phase_enable = phases;
-
-
-            o2s_start_poll(vwt.value, &result);
-            // Check the status
-            vwr.value = result << 32;
-
-            // results are duplicated 3x, using first byte for checking
-
-            SSX_ERROR_IF(vwr.fields.write_status0 == 0x00, O2S_READ_NOT_READY);
-            SSX_ERROR_IF(vwr.fields.write_status0 == 0x55, O2S_WRITE_ECC_ERROR);
-            SSX_ERROR_IF(vwr.fields.write_status0 != 0xAA, O2S_WRITE_NOT_VALID);
-        }
-    }
-    return 0;
-}
-
-/// Read VRM state using the O2S bridge
-///
-/// \param vrm_select A 3-bit vector of VRM selected for the operation.
-/// This procedure only allows 1 VRM to be selected.
-///
-/// \param vrail A 4-bit value for selecting a voltage rail
-///
-/// \param[out] o_vid The resulting 8-bit VRM-11 encoded voltage ID
-///
-///
-/// \retval 0 Success
-///
-/// \retval -VRM_INVALID_ARGUMENT_SREAD One of the arguments was invalid in some
-/// way.
-///
-/// \retval -O2S_BUSY_VRM_READ_STATE The O2S bridge is currently busy
-///
-
-int
-vrm_read_state(int vrm_select, 
-                  int  *mnp1,
-                  int  *mn,
-                  int  *vfan,
-                  int  *vovertmp)
-{
-    int i, port;
-    uint64_t result;
-    pmc_o2s_status_reg_t posr;
-    pmc_o2s_ctrl_reg1_t pocr;
-    vrm_read_state_t vrs;
-    vrm_read_state_resp_t vrsr;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((!((vrm_select == SPIVRM_PORT(0)) ||
-                        (vrm_select == SPIVRM_PORT(1)) || 
-                        (vrm_select == SPIVRM_PORT(2)))),
-                        VRM_INVALID_ARGUMENT_SREAD);
-    }
-
-
-    // Check for O2S busy
-
-    posr.value = in32(PMC_O2S_STATUS_REG);
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(posr.fields.o2s_ongoing, O2S_BUSY_VRM_READ_STATE);
-    }
-
-    // Use O2S to read voltage for selected rail.
-
-    for (i = 0; i < SPIVRM_NPORTS; i++) {
-        
-        port = vrm_select & SPIVRM_PORT(i);
-        if (port != 0) {
-
-            // Set the (singular) O2S port
-
-            pocr.value = in32(PMC_O2S_CTRL_REG1);
-            pocr.fields.o2s_port_enable = port;
-            out32(PMC_O2S_CTRL_REG1, pocr.value);
-
-            // Create and initiate a voltage read command
-
-            vrs.value = 0;
-            vrs.fields.command = VRM_READ_STATE;
-
-
-            o2s_start_poll(vrs.value, &result);
-            // Check the status
-            vrsr.value = result << 32;
-
-            // results are duplicated 3x, returning first byte
-            *mnp1     = vrsr.fields.minus_nplus1_0;
-            *mn       = vrsr.fields.minus_n0;
-            *vfan     = vrsr.fields.vrm_fan0; 
-            *vovertmp = vrsr.fields.vrm_overtemp0;
-
-        }
-    }
-    return 0;
-}
-
-
-/// Read a voltage using the O2S bridge
-///
-/// \param vrm_select A 3-bit vector of VRM selected for the operation.
-/// This procedure only allows 1 VRM to be selected.
-///
-/// \param vrail A 4-bit value for selecting a voltage rail
-///
-/// \param[out] o_vid The resulting 8-bit VRM-11 encoded voltage ID
-///
-///
-/// \retval 0 Success
-///
-/// \retval -VRM_INVALID_ARGUMENT_VREAD One of the arguments was invalid in some
-/// way.
-///
-/// \retval -O2S_BUSY_VRM_VOLTAGE_READ The O2S bridge is currently busy
-///
-
-int
-vrm_voltage_read(int vrm_select, 
-                  uint8_t vrail, 
-                  uint8_t *o_vid)
-{
-    int i, port;
-    uint64_t result;
-    pmc_o2s_status_reg_t posr;
-    pmc_o2s_ctrl_reg1_t pocr;
-    vrm_read_voltage_t vrv;
-    vrm_read_voltage_resp_t vrvr;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((!((vrm_select == SPIVRM_PORT(0)) ||
-                        (vrm_select == SPIVRM_PORT(1)) || 
-                        (vrm_select == SPIVRM_PORT(2)))) ||
-                        (vrail > (SPIVRM_NRAILS - 1)),
-                        VRM_INVALID_ARGUMENT_VREAD);
-    }
-
-
-    // Check for O2S busy
-
-    posr.value = in32(PMC_O2S_STATUS_REG);
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(posr.fields.o2s_ongoing, O2S_BUSY_VRM_VOLTAGE_READ);
-    }
-
-    // Use O2S to read voltage for selected rail.
-
-    for (i = 0; i < SPIVRM_NPORTS; i++) {
-        
-        port = vrm_select & SPIVRM_PORT(i);
-        if (port != 0) {
-
-            // Set the (singular) O2S port
-
-            pocr.value = in32(PMC_O2S_CTRL_REG1);
-            pocr.fields.o2s_port_enable = port;
-            out32(PMC_O2S_CTRL_REG1, pocr.value);
-
-            // Create and initiate a voltage read command
-
-            vrv.value = 0;
-            vrv.fields.command = VRM_READ_VOLTAGE;
-            vrv.fields.rail    = vrail;
-
-
-            o2s_start_poll(vrv.value, &result);
-            // Check the status
-            vrvr.value = result << 32;
-
-            // results are duplicated 3x, returning first byte
-            *o_vid = vrvr.fields.vid0;
-        }
-    }
-    return 0;
-}
-
-
-
-
diff --git a/src/lib/vrm.h b/src/lib/vrm.h
deleted file mode 100755
index 2efea4d..0000000
--- a/src/lib/vrm.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __VRM_H__
-#define __VRM_H__
-
-// $Id: vrm.h,v 1.2 2014/02/03 01:30:26 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/lib/vrm.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file vrm.h
-/// \brief PgP SPIVRM procedures
-
-#include "ssx.h"
-
-#ifndef __ASSEMBLER__
-
-int
-o2s_initialize();
-
-int
-spivid_initialize();
-
-
-int
-vrm_voltage_write(int vrm_select, 
-                  uint8_t vdd_vid, 
-                  int8_t vcs_offset, 
-                  int phases);
-
-int
-vrm_read_state(int vrm_select, 
-                  int  *mnp1,
-                  int  *mn,
-                  int  *vfan,
-                  int  *vovertmp);
-
-int
-vrm_voltage_read(int vrm_select,
-                 uint8_t vrail,
-                 uint8_t *o_vid);
-
-#endif  /* __ASEMBLER__ */
-
-// Error/panic codes
-
-#define O2S_BUSY_VRM_VOLTAGE_READ   0x00627001
-#define O2S_BUSY_VRM_VOLTAGE_WRITE  0x00627002
-#define O2S_BUSY_VRM_READ_STATE     0x00627003
-#define O2S_READ_NOT_READY          0x00627004
-#define O2S_WRITE_NOT_VALID         0x00627005
-#define O2S_WRITE_ECC_ERROR         0x00627006
-#define VRM_INVALID_ARGUMENT_VREAD  0x00627007
-#define VRM_INVALID_ARGUMENT_VWRITE 0x00627008 
-#define VRM_INVALID_ARGUMENT_SREAD  0x00627009 
-#define VRM_INVALID_ARGUMENT_INIT   0x0062700a
-
-#endif  /* __VRM_H__ */
diff --git a/src/occ/Makefile b/src/occ_405/Makefile
index bba6075..bba6075 100755
--- a/src/occ/Makefile
+++ b/src/occ_405/Makefile
diff --git a/src/occ/amec/amec_amester.c b/src/occ_405/amec/amec_amester.c
index c565912..c565912 100755
--- a/src/occ/amec/amec_amester.c
+++ b/src/occ_405/amec/amec_amester.c
diff --git a/src/occ/amec/amec_amester.h b/src/occ_405/amec/amec_amester.h
index 8a3510f..8a3510f 100644
--- a/src/occ/amec/amec_amester.h
+++ b/src/occ_405/amec/amec_amester.h
diff --git a/src/occ/amec/amec_analytics.c b/src/occ_405/amec/amec_analytics.c
index 8b65f6d..8b65f6d 100755
--- a/src/occ/amec/amec_analytics.c
+++ b/src/occ_405/amec/amec_analytics.c
diff --git a/src/occ/amec/amec_analytics.h b/src/occ_405/amec/amec_analytics.h
index ed6bb19..b6a344e 100755
--- a/src/occ/amec/amec_analytics.h
+++ b/src/occ_405/amec/amec_analytics.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_analytics.h $                               */
+/* $Source: src/occ_405/amec/amec_analytics.h $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_controller.c b/src/occ_405/amec/amec_controller.c
index 610d325..0b8b7e1 100644
--- a/src/occ/amec/amec_controller.c
+++ b/src/occ_405/amec/amec_controller.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_controller.c $                              */
+/* $Source: src/occ_405/amec/amec_controller.c $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_controller.h b/src/occ_405/amec/amec_controller.h
index 8ce68e7..8b2c1b9 100644
--- a/src/occ/amec/amec_controller.h
+++ b/src/occ_405/amec/amec_controller.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_controller.h $                              */
+/* $Source: src/occ_405/amec/amec_controller.h $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_data.c b/src/occ_405/amec/amec_data.c
index 33142e1..33142e1 100755
--- a/src/occ/amec/amec_data.c
+++ b/src/occ_405/amec/amec_data.c
diff --git a/src/occ/amec/amec_data.h b/src/occ_405/amec/amec_data.h
index 93cfd6e..ee7fccf 100755
--- a/src/occ/amec/amec_data.h
+++ b/src/occ_405/amec/amec_data.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_data.h $                                    */
+/* $Source: src/occ_405/amec/amec_data.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_dps.c b/src/occ_405/amec/amec_dps.c
index e566b7d..ac6aff7 100755
--- a/src/occ/amec/amec_dps.c
+++ b/src/occ_405/amec/amec_dps.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_dps.c $                                     */
+/* $Source: src/occ_405/amec/amec_dps.c $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_dps.h b/src/occ_405/amec/amec_dps.h
index 06f8d5d..c342139 100755
--- a/src/occ/amec/amec_dps.h
+++ b/src/occ_405/amec/amec_dps.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_dps.h $                                     */
+/* $Source: src/occ_405/amec/amec_dps.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_external.h b/src/occ_405/amec/amec_external.h
index b4248c8..17fcd57 100755
--- a/src/occ/amec/amec_external.h
+++ b/src/occ_405/amec/amec_external.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_external.h $                                */
+/* $Source: src/occ_405/amec/amec_external.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_freq.c b/src/occ_405/amec/amec_freq.c
index 953bf27..953bf27 100755
--- a/src/occ/amec/amec_freq.c
+++ b/src/occ_405/amec/amec_freq.c
diff --git a/src/occ/amec/amec_freq.h b/src/occ_405/amec/amec_freq.h
index d09c3b6..b05277d 100644
--- a/src/occ/amec/amec_freq.h
+++ b/src/occ_405/amec/amec_freq.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_freq.h $                                    */
+/* $Source: src/occ_405/amec/amec_freq.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_health.c b/src/occ_405/amec/amec_health.c
index 75a3b2b..4efad15 100755
--- a/src/occ/amec/amec_health.c
+++ b/src/occ_405/amec/amec_health.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_health.c $                                  */
+/* $Source: src/occ_405/amec/amec_health.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_health.h b/src/occ_405/amec/amec_health.h
index 3b7b705..35271c0 100755
--- a/src/occ/amec/amec_health.h
+++ b/src/occ_405/amec/amec_health.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_health.h $                                  */
+/* $Source: src/occ_405/amec/amec_health.h $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_init.c b/src/occ_405/amec/amec_init.c
index 487c9ef..487c9ef 100644
--- a/src/occ/amec/amec_init.c
+++ b/src/occ_405/amec/amec_init.c
diff --git a/src/occ/amec/amec_master_smh.c b/src/occ_405/amec/amec_master_smh.c
index 8e20f07..c49ca06 100755
--- a/src/occ/amec/amec_master_smh.c
+++ b/src/occ_405/amec/amec_master_smh.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_master_smh.c $                              */
+/* $Source: src/occ_405/amec/amec_master_smh.c $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_master_smh.h b/src/occ_405/amec/amec_master_smh.h
index a12041a..59563f6 100755
--- a/src/occ/amec/amec_master_smh.h
+++ b/src/occ_405/amec/amec_master_smh.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_master_smh.h $                              */
+/* $Source: src/occ_405/amec/amec_master_smh.h $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_oversub.c b/src/occ_405/amec/amec_oversub.c
index 8e00c6e..beff792 100755
--- a/src/occ/amec/amec_oversub.c
+++ b/src/occ_405/amec/amec_oversub.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_oversub.c $                                 */
+/* $Source: src/occ_405/amec/amec_oversub.c $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_oversub.h b/src/occ_405/amec/amec_oversub.h
index 24a7229..238599a 100755
--- a/src/occ/amec/amec_oversub.h
+++ b/src/occ_405/amec/amec_oversub.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_oversub.h $                                 */
+/* $Source: src/occ_405/amec/amec_oversub.h $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_parm.c b/src/occ_405/amec/amec_parm.c
index ff927cc..a3dafd6 100755
--- a/src/occ/amec/amec_parm.c
+++ b/src/occ_405/amec/amec_parm.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_parm.c $                                    */
+/* $Source: src/occ_405/amec/amec_parm.c $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_parm.h b/src/occ_405/amec/amec_parm.h
index a6ef1fd..83104f9 100755
--- a/src/occ/amec/amec_parm.h
+++ b/src/occ_405/amec/amec_parm.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_parm.h $                                    */
+/* $Source: src/occ_405/amec/amec_parm.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_parm_table.c b/src/occ_405/amec/amec_parm_table.c
index 03c239f..c485484 100755
--- a/src/occ/amec/amec_parm_table.c
+++ b/src/occ_405/amec/amec_parm_table.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_parm_table.c $                              */
+/* $Source: src/occ_405/amec/amec_parm_table.c $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_part.c b/src/occ_405/amec/amec_part.c
index 216cfb4..86f1b7e 100755
--- a/src/occ/amec/amec_part.c
+++ b/src/occ_405/amec/amec_part.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_part.c $                                    */
+/* $Source: src/occ_405/amec/amec_part.c $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_part.h b/src/occ_405/amec/amec_part.h
index 151569c..b95909c 100755
--- a/src/occ/amec/amec_part.h
+++ b/src/occ_405/amec/amec_part.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_part.h $                                    */
+/* $Source: src/occ_405/amec/amec_part.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_pcap.c b/src/occ_405/amec/amec_pcap.c
index c742851..c742851 100755
--- a/src/occ/amec/amec_pcap.c
+++ b/src/occ_405/amec/amec_pcap.c
diff --git a/src/occ/amec/amec_pcap.h b/src/occ_405/amec/amec_pcap.h
index 213af5d..47a065b 100755
--- a/src/occ/amec/amec_pcap.h
+++ b/src/occ_405/amec/amec_pcap.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_pcap.h $                                    */
+/* $Source: src/occ_405/amec/amec_pcap.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_perfcount.c b/src/occ_405/amec/amec_perfcount.c
index 3a6cc4a..da37d40 100755
--- a/src/occ/amec/amec_perfcount.c
+++ b/src/occ_405/amec/amec_perfcount.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_perfcount.c $                               */
+/* $Source: src/occ_405/amec/amec_perfcount.c $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_perfcount.h b/src/occ_405/amec/amec_perfcount.h
index 38a9c7f..49eb20c 100755
--- a/src/occ/amec/amec_perfcount.h
+++ b/src/occ_405/amec/amec_perfcount.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_perfcount.h $                               */
+/* $Source: src/occ_405/amec/amec_perfcount.h $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_centaur.c b/src/occ_405/amec/amec_sensors_centaur.c
index 1e2d3a3..2679bc9 100644
--- a/src/occ/amec/amec_sensors_centaur.c
+++ b/src/occ_405/amec/amec_sensors_centaur.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_sensors_centaur.c $                         */
+/* $Source: src/occ_405/amec/amec_sensors_centaur.c $                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_centaur.h b/src/occ_405/amec/amec_sensors_centaur.h
index 64db6eb..ddc3132 100644
--- a/src/occ/amec/amec_sensors_centaur.h
+++ b/src/occ_405/amec/amec_sensors_centaur.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_sensors_centaur.h $                         */
+/* $Source: src/occ_405/amec/amec_sensors_centaur.h $                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_core.c b/src/occ_405/amec/amec_sensors_core.c
index bdea518..bdea518 100755
--- a/src/occ/amec/amec_sensors_core.c
+++ b/src/occ_405/amec/amec_sensors_core.c
diff --git a/src/occ/amec/amec_sensors_core.h b/src/occ_405/amec/amec_sensors_core.h
index adc24cd..e018925 100755
--- a/src/occ/amec/amec_sensors_core.h
+++ b/src/occ_405/amec/amec_sensors_core.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_sensors_core.h $                            */
+/* $Source: src/occ_405/amec/amec_sensors_core.h $                        */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_fw.c b/src/occ_405/amec/amec_sensors_fw.c
index 1b799c2..1bc3811 100644
--- a/src/occ/amec/amec_sensors_fw.c
+++ b/src/occ_405/amec/amec_sensors_fw.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_sensors_fw.c $                              */
+/* $Source: src/occ_405/amec/amec_sensors_fw.c $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_fw.h b/src/occ_405/amec/amec_sensors_fw.h
index 12fd571..015cc01 100755
--- a/src/occ/amec/amec_sensors_fw.h
+++ b/src/occ_405/amec/amec_sensors_fw.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_sensors_fw.h $                              */
+/* $Source: src/occ_405/amec/amec_sensors_fw.h $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
index 8d08db3..8d08db3 100755
--- a/src/occ/amec/amec_sensors_power.c
+++ b/src/occ_405/amec/amec_sensors_power.c
diff --git a/src/occ/amec/amec_sensors_power.h b/src/occ_405/amec/amec_sensors_power.h
index fd69ce8..fd69ce8 100755
--- a/src/occ/amec/amec_sensors_power.h
+++ b/src/occ_405/amec/amec_sensors_power.h
diff --git a/src/occ/amec/amec_service_codes.h b/src/occ_405/amec/amec_service_codes.h
index 511c09d..c93cc25 100755
--- a/src/occ/amec/amec_service_codes.h
+++ b/src/occ_405/amec/amec_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_service_codes.h $                           */
+/* $Source: src/occ_405/amec/amec_service_codes.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_slave_smh.c b/src/occ_405/amec/amec_slave_smh.c
index 1b5dbc0..1b5dbc0 100755
--- a/src/occ/amec/amec_slave_smh.c
+++ b/src/occ_405/amec/amec_slave_smh.c
diff --git a/src/occ/amec/amec_slave_smh.h b/src/occ_405/amec/amec_slave_smh.h
index 884d480..884d480 100755
--- a/src/occ/amec/amec_slave_smh.h
+++ b/src/occ_405/amec/amec_slave_smh.h
diff --git a/src/occ/amec/amec_smh.h b/src/occ_405/amec/amec_smh.h
index 6ec2990..e66c339 100755
--- a/src/occ/amec/amec_smh.h
+++ b/src/occ_405/amec/amec_smh.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_smh.h $                                     */
+/* $Source: src/occ_405/amec/amec_smh.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/amec/amec_sys.h b/src/occ_405/amec/amec_sys.h
index 0383701..0383701 100755
--- a/src/occ/amec/amec_sys.h
+++ b/src/occ_405/amec/amec_sys.h
diff --git a/src/occ/amec/amec_tasks.c b/src/occ_405/amec/amec_tasks.c
index 096fd0b..ce306a9 100755
--- a/src/occ/amec/amec_tasks.c
+++ b/src/occ_405/amec/amec_tasks.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/amec/amec_tasks.c $                                   */
+/* $Source: src/occ_405/amec/amec_tasks.c $                               */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/aplt/aplt_service_codes.h b/src/occ_405/aplt/aplt_service_codes.h
index 8ca0cdf..daa2273 100755
--- a/src/occ/aplt/aplt_service_codes.h
+++ b/src/occ_405/aplt/aplt_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/aplt/aplt_service_codes.h $                           */
+/* $Source: src/occ_405/aplt/aplt_service_codes.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/aplt/appletManager.c b/src/occ_405/aplt/appletManager.c
index e2e70df..e2e70df 100755
--- a/src/occ/aplt/appletManager.c
+++ b/src/occ_405/aplt/appletManager.c
diff --git a/src/occ/aplt/appletManager.h b/src/occ_405/aplt/appletManager.h
index beeea5d..4d42602 100755
--- a/src/occ/aplt/appletManager.h
+++ b/src/occ_405/aplt/appletManager.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/aplt/appletManager.h $                                */
+/* $Source: src/occ_405/aplt/appletManager.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/aplt/incl/appletId.h b/src/occ_405/aplt/incl/appletId.h
index 0ae310d..96bdba3 100755
--- a/src/occ/aplt/incl/appletId.h
+++ b/src/occ_405/aplt/incl/appletId.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/aplt/incl/appletId.h $                                */
+/* $Source: src/occ_405/aplt/incl/appletId.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/aplt/incl/cmdhDbugCmd.h b/src/occ_405/aplt/incl/cmdhDbugCmd.h
index 80a722c..10fc75f 100755
--- a/src/occ/aplt/incl/cmdhDbugCmd.h
+++ b/src/occ_405/aplt/incl/cmdhDbugCmd.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/aplt/incl/cmdhDbugCmd.h $                             */
+/* $Source: src/occ_405/aplt/incl/cmdhDbugCmd.h $                         */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/aplt/incl/sensorQueryList.h b/src/occ_405/aplt/incl/sensorQueryList.h
index 3e82028..e582633 100755
--- a/src/occ/aplt/incl/sensorQueryList.h
+++ b/src/occ_405/aplt/incl/sensorQueryList.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/aplt/incl/sensorQueryList.h $                         */
+/* $Source: src/occ_405/aplt/incl/sensorQueryList.h $                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/app.mk b/src/occ_405/app.mk
index 025b100..025b100 100755
--- a/src/occ/app.mk
+++ b/src/occ_405/app.mk
diff --git a/src/occ/arl_test.c b/src/occ_405/arl_test.c
index 5968bfa..d697c5b 100755
--- a/src/occ/arl_test.c
+++ b/src/occ_405/arl_test.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/arl_test.c $                                          */
+/* $Source: src/occ_405/arl_test.c $                                      */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/arl_test_data.h b/src/occ_405/arl_test_data.h
index 84a6f52..6e660b3 100755
--- a/src/occ/arl_test_data.h
+++ b/src/occ_405/arl_test_data.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/arl_test_data.h $                                     */
+/* $Source: src/occ_405/arl_test_data.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cent/centaur_control.c b/src/occ_405/cent/centaur_control.c
index 825de18..825de18 100755
--- a/src/occ/cent/centaur_control.c
+++ b/src/occ_405/cent/centaur_control.c
diff --git a/src/occ/cent/centaur_control.h b/src/occ_405/cent/centaur_control.h
index e346045..a92f7ad 100755
--- a/src/occ/cent/centaur_control.h
+++ b/src/occ_405/cent/centaur_control.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cent/centaur_control.h $                              */
+/* $Source: src/occ_405/cent/centaur_control.h $                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cent/centaur_data.c b/src/occ_405/cent/centaur_data.c
index 9be48e1..9be48e1 100755
--- a/src/occ/cent/centaur_data.c
+++ b/src/occ_405/cent/centaur_data.c
diff --git a/src/occ/cent/centaur_data.h b/src/occ_405/cent/centaur_data.h
index 2eec5fd..2eec5fd 100755
--- a/src/occ/cent/centaur_data.h
+++ b/src/occ_405/cent/centaur_data.h
diff --git a/src/occ/cent/centaur_data_service_codes.h b/src/occ_405/cent/centaur_data_service_codes.h
index 9fa764d..fa4f5b4 100755
--- a/src/occ/cent/centaur_data_service_codes.h
+++ b/src/occ_405/cent/centaur_data_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cent/centaur_data_service_codes.h $                   */
+/* $Source: src/occ_405/cent/centaur_data_service_codes.h $               */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cfiles.mk b/src/occ_405/cfiles.mk
index 8fc299d..8fc299d 100755
--- a/src/occ/cfiles.mk
+++ b/src/occ_405/cfiles.mk
diff --git a/src/occ/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index 2151e67..2151e67 100755
--- a/src/occ/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
diff --git a/src/occ/cmdh/cmdh_fsp.h b/src/occ_405/cmdh/cmdh_fsp.h
index 602d471..468a6ec 100755
--- a/src/occ/cmdh/cmdh_fsp.h
+++ b/src/occ_405/cmdh/cmdh_fsp.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_fsp.h $                                     */
+/* $Source: src/occ_405/cmdh/cmdh_fsp.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c
index 4796662..4796662 100755
--- a/src/occ/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c
diff --git a/src/occ/cmdh/cmdh_fsp_cmds.h b/src/occ_405/cmdh/cmdh_fsp_cmds.h
index ee3b59d..ee3b59d 100755
--- a/src/occ/cmdh/cmdh_fsp_cmds.h
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.h
diff --git a/src/occ/cmdh/cmdh_fsp_cmds_datacnfg.c b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
index bd97e7c..bd97e7c 100755
--- a/src/occ/cmdh/cmdh_fsp_cmds_datacnfg.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
diff --git a/src/occ/cmdh/cmdh_fsp_cmds_datacnfg.h b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.h
index 6affe10..6affe10 100755
--- a/src/occ/cmdh/cmdh_fsp_cmds_datacnfg.h
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.h
diff --git a/src/occ/cmdh/cmdh_mnfg_intf.c b/src/occ_405/cmdh/cmdh_mnfg_intf.c
index 9e59a5b..4717982 100755
--- a/src/occ/cmdh/cmdh_mnfg_intf.c
+++ b/src/occ_405/cmdh/cmdh_mnfg_intf.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_mnfg_intf.c $                               */
+/* $Source: src/occ_405/cmdh/cmdh_mnfg_intf.c $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_mnfg_intf.h b/src/occ_405/cmdh/cmdh_mnfg_intf.h
index 36f3876..db4c4d9 100755
--- a/src/occ/cmdh/cmdh_mnfg_intf.h
+++ b/src/occ_405/cmdh/cmdh_mnfg_intf.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_mnfg_intf.h $                               */
+/* $Source: src/occ_405/cmdh/cmdh_mnfg_intf.h $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_service_codes.h b/src/occ_405/cmdh/cmdh_service_codes.h
index 93d422c..93d422c 100755
--- a/src/occ/cmdh/cmdh_service_codes.h
+++ b/src/occ_405/cmdh/cmdh_service_codes.h
diff --git a/src/occ/cmdh/cmdh_snapshot.c b/src/occ_405/cmdh/cmdh_snapshot.c
index 0c24305..5d73174 100755
--- a/src/occ/cmdh/cmdh_snapshot.c
+++ b/src/occ_405/cmdh/cmdh_snapshot.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_snapshot.c $                                */
+/* $Source: src/occ_405/cmdh/cmdh_snapshot.c $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_snapshot.h b/src/occ_405/cmdh/cmdh_snapshot.h
index 8dad178..3388c25 100755
--- a/src/occ/cmdh/cmdh_snapshot.h
+++ b/src/occ_405/cmdh/cmdh_snapshot.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_snapshot.h $                                */
+/* $Source: src/occ_405/cmdh/cmdh_snapshot.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_thread.c b/src/occ_405/cmdh/cmdh_thread.c
index f2a6c14..79f0fe1 100644
--- a/src/occ/cmdh/cmdh_thread.c
+++ b/src/occ_405/cmdh/cmdh_thread.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_thread.c $                                  */
+/* $Source: src/occ_405/cmdh/cmdh_thread.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_tunable_parms.c b/src/occ_405/cmdh/cmdh_tunable_parms.c
index 23946b1..c491dc0 100755
--- a/src/occ/cmdh/cmdh_tunable_parms.c
+++ b/src/occ_405/cmdh/cmdh_tunable_parms.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_tunable_parms.c $                           */
+/* $Source: src/occ_405/cmdh/cmdh_tunable_parms.c $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/cmdh_tunable_parms.h b/src/occ_405/cmdh/cmdh_tunable_parms.h
index 5fc35c7..8070fa4 100755
--- a/src/occ/cmdh/cmdh_tunable_parms.h
+++ b/src/occ_405/cmdh/cmdh_tunable_parms.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/cmdh_tunable_parms.h $                           */
+/* $Source: src/occ_405/cmdh/cmdh_tunable_parms.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/ffdc.c b/src/occ_405/cmdh/ffdc.c
index a0f57af..ab7c478 100755
--- a/src/occ/cmdh/ffdc.c
+++ b/src/occ_405/cmdh/ffdc.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/ffdc.c $                                         */
+/* $Source: src/occ_405/cmdh/ffdc.c $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/ffdc.h b/src/occ_405/cmdh/ffdc.h
index 715f177..b616f4b 100755
--- a/src/occ/cmdh/ffdc.h
+++ b/src/occ_405/cmdh/ffdc.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/cmdh/ffdc.h $                                         */
+/* $Source: src/occ_405/cmdh/ffdc.h $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/cmdh/ll_ffdc.S b/src/occ_405/cmdh/ll_ffdc.S
index 9f1a728..08d5179 100644
--- a/src/occ/cmdh/ll_ffdc.S
+++ b/src/occ_405/cmdh/ll_ffdc.S
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/cmdh/ll_ffdc.S $
+# $Source: src/occ_405/cmdh/ll_ffdc.S $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/common.c b/src/occ_405/common.c
index e90515d..e90515d 100755
--- a/src/occ/common.c
+++ b/src/occ_405/common.c
diff --git a/src/occ/common.h b/src/occ_405/common.h
index 0f6810d..0f6810d 100644
--- a/src/occ/common.h
+++ b/src/occ_405/common.h
diff --git a/src/occ/dcom/dcom.c b/src/occ_405/dcom/dcom.c
index 5b9f112..5b9f112 100755
--- a/src/occ/dcom/dcom.c
+++ b/src/occ_405/dcom/dcom.c
diff --git a/src/occ/dcom/dcom.h b/src/occ_405/dcom/dcom.h
index 29b8aad..7aaf652 100755
--- a/src/occ/dcom/dcom.h
+++ b/src/occ_405/dcom/dcom.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcom.h $                                         */
+/* $Source: src/occ_405/dcom/dcom.h $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcomMasterRx.c b/src/occ_405/dcom/dcomMasterRx.c
index 752f744..b5da6b3 100644
--- a/src/occ/dcom/dcomMasterRx.c
+++ b/src/occ_405/dcom/dcomMasterRx.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcomMasterRx.c $                                 */
+/* $Source: src/occ_405/dcom/dcomMasterRx.c $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index 7d13000..69f45d4 100644
--- a/src/occ/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcomMasterTx.c $                                 */
+/* $Source: src/occ_405/dcom/dcomMasterTx.c $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcomSlaveRx.c b/src/occ_405/dcom/dcomSlaveRx.c
index a512c38..0eb6be3 100644
--- a/src/occ/dcom/dcomSlaveRx.c
+++ b/src/occ_405/dcom/dcomSlaveRx.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcomSlaveRx.c $                                  */
+/* $Source: src/occ_405/dcom/dcomSlaveRx.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcomSlaveTx.c b/src/occ_405/dcom/dcomSlaveTx.c
index f01461e..41a19cf 100755
--- a/src/occ/dcom/dcomSlaveTx.c
+++ b/src/occ_405/dcom/dcomSlaveTx.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcomSlaveTx.c $                                  */
+/* $Source: src/occ_405/dcom/dcomSlaveTx.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcom_service_codes.h b/src/occ_405/dcom/dcom_service_codes.h
index c3e90d8..4c210de 100755
--- a/src/occ/dcom/dcom_service_codes.h
+++ b/src/occ_405/dcom/dcom_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcom_service_codes.h $                           */
+/* $Source: src/occ_405/dcom/dcom_service_codes.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/dcom/dcom_thread.c b/src/occ_405/dcom/dcom_thread.c
index 2e11c66..b171e1d 100755
--- a/src/occ/dcom/dcom_thread.c
+++ b/src/occ_405/dcom/dcom_thread.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/dcom/dcom_thread.c $                                  */
+/* $Source: src/occ_405/dcom/dcom_thread.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/errl/errl.c b/src/occ_405/errl/errl.c
index cd75621..cd75621 100755
--- a/src/occ/errl/errl.c
+++ b/src/occ_405/errl/errl.c
diff --git a/src/occ/errl/errl.h b/src/occ_405/errl/errl.h
index 5097b94..107a3f3 100755
--- a/src/occ/errl/errl.h
+++ b/src/occ_405/errl/errl.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/errl/errl.h $                                         */
+/* $Source: src/occ_405/errl/errl.h $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/errl/test/Makefile b/src/occ_405/errl/test/Makefile
index e702394..77393f1 100755
--- a/src/occ/errl/test/Makefile
+++ b/src/occ_405/errl/test/Makefile
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/errl/test/Makefile $
+# $Source: src/occ_405/errl/test/Makefile $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/errl/test/app.mk b/src/occ_405/errl/test/app.mk
index f17074d..720b5c8 100755
--- a/src/occ/errl/test/app.mk
+++ b/src/occ_405/errl/test/app.mk
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/errl/test/app.mk $
+# $Source: src/occ_405/errl/test/app.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/errl/test/errltest.c b/src/occ_405/errl/test/errltest.c
index 0da6b90..42e8fa3 100755
--- a/src/occ/errl/test/errltest.c
+++ b/src/occ_405/errl/test/errltest.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/errl/test/errltest.c $                                */
+/* $Source: src/occ_405/errl/test/errltest.c $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/errl/test/gpefiles.mk b/src/occ_405/errl/test/gpefiles.mk
index 00b03d1..049a87c 100755
--- a/src/occ/errl/test/gpefiles.mk
+++ b/src/occ_405/errl/test/gpefiles.mk
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/errl/test/gpefiles.mk $
+# $Source: src/occ_405/errl/test/gpefiles.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/errl/test/parser.c b/src/occ_405/errl/test/parser.c
index 5e7e7f6..d0ad9f0 100755
--- a/src/occ/errl/test/parser.c
+++ b/src/occ_405/errl/test/parser.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/errl/test/parser.c $                                  */
+/* $Source: src/occ_405/errl/test/parser.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/errl/test/test.mk b/src/occ_405/errl/test/test.mk
index fd8278c..ebf84d8 100755
--- a/src/occ/errl/test/test.mk
+++ b/src/occ_405/errl/test/test.mk
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/errl/test/test.mk $
+# $Source: src/occ_405/errl/test/test.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/firdata/ecc.c b/src/occ_405/firdata/ecc.c
index 6696678..6696678 100644
--- a/src/occ/firdata/ecc.c
+++ b/src/occ_405/firdata/ecc.c
diff --git a/src/occ/firdata/ecc.h b/src/occ_405/firdata/ecc.h
index 12ffe4e..12ffe4e 100644
--- a/src/occ/firdata/ecc.h
+++ b/src/occ_405/firdata/ecc.h
diff --git a/src/occ/firdata/firData.c b/src/occ_405/firdata/firData.c
index b446e4a..b446e4a 100644
--- a/src/occ/firdata/firData.c
+++ b/src/occ_405/firdata/firData.c
diff --git a/src/occ/firdata/firData.h b/src/occ_405/firdata/firData.h
index f1475db..f1475db 100644
--- a/src/occ/firdata/firData.h
+++ b/src/occ_405/firdata/firData.h
diff --git a/src/occ/firdata/firDataConst_common.h b/src/occ_405/firdata/firDataConst_common.h
index 17952df..17952df 100644
--- a/src/occ/firdata/firDataConst_common.h
+++ b/src/occ_405/firdata/firDataConst_common.h
diff --git a/src/occ/firdata/fir_data_collect.c b/src/occ_405/firdata/fir_data_collect.c
index 1930fa5..1930fa5 100644
--- a/src/occ/firdata/fir_data_collect.c
+++ b/src/occ_405/firdata/fir_data_collect.c
diff --git a/src/occ/firdata/fir_data_collect.h b/src/occ_405/firdata/fir_data_collect.h
index c313956..c313956 100644
--- a/src/occ/firdata/fir_data_collect.h
+++ b/src/occ_405/firdata/fir_data_collect.h
diff --git a/src/occ/firdata/fsi.c b/src/occ_405/firdata/fsi.c
index 4bf105a..4bf105a 100644
--- a/src/occ/firdata/fsi.c
+++ b/src/occ_405/firdata/fsi.c
diff --git a/src/occ/firdata/fsi.h b/src/occ_405/firdata/fsi.h
index 870e47f..870e47f 100644
--- a/src/occ/firdata/fsi.h
+++ b/src/occ_405/firdata/fsi.h
diff --git a/src/occ/firdata/homerData_common.h b/src/occ_405/firdata/homerData_common.h
index 9dfa579..9dfa579 100644
--- a/src/occ/firdata/homerData_common.h
+++ b/src/occ_405/firdata/homerData_common.h
diff --git a/src/occ/firdata/lpc.c b/src/occ_405/firdata/lpc.c
index fe69efc..fe69efc 100644
--- a/src/occ/firdata/lpc.c
+++ b/src/occ_405/firdata/lpc.c
diff --git a/src/occ/firdata/lpc.h b/src/occ_405/firdata/lpc.h
index 11290cc..11290cc 100644
--- a/src/occ/firdata/lpc.h
+++ b/src/occ_405/firdata/lpc.h
diff --git a/src/occ/firdata/native.c b/src/occ_405/firdata/native.c
index 10ec524..10ec524 100644
--- a/src/occ/firdata/native.c
+++ b/src/occ_405/firdata/native.c
diff --git a/src/occ/firdata/native.h b/src/occ_405/firdata/native.h
index 242c5e3..242c5e3 100644
--- a/src/occ/firdata/native.h
+++ b/src/occ_405/firdata/native.h
diff --git a/src/occ/firdata/nor_micron.c b/src/occ_405/firdata/nor_micron.c
index 3d0329a..3d0329a 100644
--- a/src/occ/firdata/nor_micron.c
+++ b/src/occ_405/firdata/nor_micron.c
diff --git a/src/occ/firdata/norflash.h b/src/occ_405/firdata/norflash.h
index d41c878..d41c878 100644
--- a/src/occ/firdata/norflash.h
+++ b/src/occ_405/firdata/norflash.h
diff --git a/src/occ/firdata/pnorData_common.h b/src/occ_405/firdata/pnorData_common.h
index d73f937..d73f937 100644
--- a/src/occ/firdata/pnorData_common.h
+++ b/src/occ_405/firdata/pnorData_common.h
diff --git a/src/occ/firdata/pnor_util.c b/src/occ_405/firdata/pnor_util.c
index bf32480..bf32480 100644
--- a/src/occ/firdata/pnor_util.c
+++ b/src/occ_405/firdata/pnor_util.c
diff --git a/src/occ/firdata/pnor_util.h b/src/occ_405/firdata/pnor_util.h
index d8b5518..d8b5518 100644
--- a/src/occ/firdata/pnor_util.h
+++ b/src/occ_405/firdata/pnor_util.h
diff --git a/src/occ/firdata/scom_trgt.c b/src/occ_405/firdata/scom_trgt.c
index ec38122..ec38122 100644
--- a/src/occ/firdata/scom_trgt.c
+++ b/src/occ_405/firdata/scom_trgt.c
diff --git a/src/occ/firdata/scom_trgt.h b/src/occ_405/firdata/scom_trgt.h
index 4ffe8b5..4ffe8b5 100644
--- a/src/occ/firdata/scom_trgt.h
+++ b/src/occ_405/firdata/scom_trgt.h
diff --git a/src/occ/firdata/scom_util.c b/src/occ_405/firdata/scom_util.c
index 4f6a391..4f6a391 100644
--- a/src/occ/firdata/scom_util.c
+++ b/src/occ_405/firdata/scom_util.c
diff --git a/src/occ/firdata/scom_util.h b/src/occ_405/firdata/scom_util.h
index 039ac64..039ac64 100644
--- a/src/occ/firdata/scom_util.h
+++ b/src/occ_405/firdata/scom_util.h
diff --git a/src/occ/firdata/sfc_ast2400.c b/src/occ_405/firdata/sfc_ast2400.c
index fbdb0b3..fbdb0b3 100644
--- a/src/occ/firdata/sfc_ast2400.c
+++ b/src/occ_405/firdata/sfc_ast2400.c
diff --git a/src/occ/firdata/sfc_ast2400.h b/src/occ_405/firdata/sfc_ast2400.h
index 30a9052..30a9052 100644
--- a/src/occ/firdata/sfc_ast2400.h
+++ b/src/occ_405/firdata/sfc_ast2400.h
diff --git a/src/occ/gpefiles.mk b/src/occ_405/gpefiles.mk
index 4002836..5e51458 100755
--- a/src/occ/gpefiles.mk
+++ b/src/occ_405/gpefiles.mk
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/gpefiles.mk $
+# $Source: src/occ_405/gpefiles.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/homer.c b/src/occ_405/homer.c
index a0331ce..a0331ce 100755
--- a/src/occ/homer.c
+++ b/src/occ_405/homer.c
diff --git a/src/occ/homer.h b/src/occ_405/homer.h
index b4d94ee..b4d94ee 100755
--- a/src/occ/homer.h
+++ b/src/occ_405/homer.h
diff --git a/src/occ/incl/common_types.h b/src/occ_405/incl/common_types.h
index 51ea3ed..51ea3ed 100755
--- a/src/occ/incl/common_types.h
+++ b/src/occ_405/incl/common_types.h
diff --git a/src/occ/incl/comp_ids.h b/src/occ_405/incl/comp_ids.h
index 3125a52..fb6f5d5 100755
--- a/src/occ/incl/comp_ids.h
+++ b/src/occ_405/incl/comp_ids.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/incl/comp_ids.h $                                     */
+/* $Source: src/occ_405/incl/comp_ids.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/incl/occ_common.h b/src/occ_405/incl/occ_common.h
index 032683f..032683f 100755
--- a/src/occ/incl/occ_common.h
+++ b/src/occ_405/incl/occ_common.h
diff --git a/src/occ/linkocc.cmd b/src/occ_405/linkocc.cmd
index 0deabc5..0deabc5 100755
--- a/src/occ/linkocc.cmd
+++ b/src/occ_405/linkocc.cmd
diff --git a/src/occ/main.c b/src/occ_405/main.c
index ff41e9c..ff41e9c 100755
--- a/src/occ/main.c
+++ b/src/occ_405/main.c
diff --git a/src/occ/mode.c b/src/occ_405/mode.c
index 135556d..19338a3 100755
--- a/src/occ/mode.c
+++ b/src/occ_405/mode.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/mode.c $                                              */
+/* $Source: src/occ_405/mode.c $                                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/mode.h b/src/occ_405/mode.h
index b7b815f..6d69331 100755
--- a/src/occ/mode.h
+++ b/src/occ_405/mode.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/mode.h $                                              */
+/* $Source: src/occ_405/mode.h $                                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/occLinkInputFile b/src/occ_405/occLinkInputFile
index 892bcd4..892bcd4 100644
--- a/src/occ/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
diff --git a/src/occ/occ_service_codes.h b/src/occ_405/occ_service_codes.h
index f1f4c70..f1f4c70 100644
--- a/src/occ/occ_service_codes.h
+++ b/src/occ_405/occ_service_codes.h
diff --git a/src/occ/occ_sys_config.c b/src/occ_405/occ_sys_config.c
index 3754b0a..3754b0a 100755
--- a/src/occ/occ_sys_config.c
+++ b/src/occ_405/occ_sys_config.c
diff --git a/src/occ/occ_sys_config.h b/src/occ_405/occ_sys_config.h
index 5ca89f3..5ca89f3 100755
--- a/src/occ/occ_sys_config.h
+++ b/src/occ_405/occ_sys_config.h
diff --git a/src/occ/occbuildname.c b/src/occ_405/occbuildname.c
index 8a92609..8a92609 100755
--- a/src/occ/occbuildname.c
+++ b/src/occ_405/occbuildname.c
diff --git a/src/occ/proc/proc_data.c b/src/occ_405/proc/proc_data.c
index eb7fe31..8b0bda8 100755
--- a/src/occ/proc/proc_data.c
+++ b/src/occ_405/proc/proc_data.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_data.c $                                    */
+/* $Source: src/occ_405/proc/proc_data.c $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/proc_data.h b/src/occ_405/proc/proc_data.h
index 103725c..03dc6b2 100755
--- a/src/occ/proc/proc_data.h
+++ b/src/occ_405/proc/proc_data.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_data.h $                                    */
+/* $Source: src/occ_405/proc/proc_data.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/proc_data_control.c b/src/occ_405/proc/proc_data_control.c
index 8e8a3c2..8e8a3c2 100755
--- a/src/occ/proc/proc_data_control.c
+++ b/src/occ_405/proc/proc_data_control.c
diff --git a/src/occ/proc/proc_data_control.h b/src/occ_405/proc/proc_data_control.h
index 49a1fcd..6e151e8 100755
--- a/src/occ/proc/proc_data_control.h
+++ b/src/occ_405/proc/proc_data_control.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_data_control.h $                            */
+/* $Source: src/occ_405/proc/proc_data_control.h $                        */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/proc_data_service_codes.h b/src/occ_405/proc/proc_data_service_codes.h
index 608e860..82c5e51 100755
--- a/src/occ/proc/proc_data_service_codes.h
+++ b/src/occ_405/proc/proc_data_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_data_service_codes.h $                      */
+/* $Source: src/occ_405/proc/proc_data_service_codes.h $                  */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/proc_pstate.c b/src/occ_405/proc/proc_pstate.c
index 5bd296f..ab225e6 100755
--- a/src/occ/proc/proc_pstate.c
+++ b/src/occ_405/proc/proc_pstate.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_pstate.c $                                  */
+/* $Source: src/occ_405/proc/proc_pstate.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/proc_pstate.h b/src/occ_405/proc/proc_pstate.h
index 1d1562e..3ac8439 100755
--- a/src/occ/proc/proc_pstate.h
+++ b/src/occ_405/proc/proc_pstate.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/proc_pstate.h $                                  */
+/* $Source: src/occ_405/proc/proc_pstate.h $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/proc/test/Makefile b/src/occ_405/proc/test/Makefile
index ca563c6..5360629 100755
--- a/src/occ/proc/test/Makefile
+++ b/src/occ_405/proc/test/Makefile
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/proc/test/Makefile $
+# $Source: src/occ_405/proc/test/Makefile $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/proc/test/app.mk b/src/occ_405/proc/test/app.mk
index 3568dfb..754609a 100755
--- a/src/occ/proc/test/app.mk
+++ b/src/occ_405/proc/test/app.mk
@@ -1,19 +1,19 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/proc/test/app.mk $
+# $Source: src/occ_405/proc/test/app.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/proc/test/main.c b/src/occ_405/proc/test/main.c
index 67c0bda..314d87d 100755
--- a/src/occ/proc/test/main.c
+++ b/src/occ_405/proc/test/main.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/proc/test/main.c $                                    */
+/* $Source: src/occ_405/proc/test/main.c $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/apss.c b/src/occ_405/pss/apss.c
index 9ba0ed1..4c2cc59 100755
--- a/src/occ/pss/apss.c
+++ b/src/occ_405/pss/apss.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/pss/apss.c $                                              */
+/* $Source: src/occ_405/pss/apss.c $                                      */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/apss.h b/src/occ_405/pss/apss.h
index 8de0cf2..8abd42e 100644
--- a/src/occ/pss/apss.h
+++ b/src/occ_405/pss/apss.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/pss/apss.h $                                          */
+/* $Source: src/occ_405/pss/apss.h $                                      */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/dpss.c b/src/occ_405/pss/dpss.c
index aab3dcc..6db3cdc 100755
--- a/src/occ/pss/dpss.c
+++ b/src/occ_405/pss/dpss.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/pss/dpss.c $                                          */
+/* $Source: src/occ_405/pss/dpss.c $                                      */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/dpss.h b/src/occ_405/pss/dpss.h
index 687df30..6b42f72 100755
--- a/src/occ/pss/dpss.h
+++ b/src/occ_405/pss/dpss.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/pss/dpss.h $                                          */
+/* $Source: src/occ_405/pss/dpss.h $                                      */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/pss_service_codes.h b/src/occ_405/pss/pss_service_codes.h
index 99b8f87..a4eda54 100755
--- a/src/occ/pss/pss_service_codes.h
+++ b/src/occ_405/pss/pss_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/pss/pss_service_codes.h $                             */
+/* $Source: src/occ_405/pss/pss_service_codes.h $                         */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/pss/test/Makefile b/src/occ_405/pss/test/Makefile
index ecb922e..045693b 100755
--- a/src/occ/pss/test/Makefile
+++ b/src/occ_405/pss/test/Makefile
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/pss/test/Makefile $
+# $Source: src/occ_405/pss/test/Makefile $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/pss/test/app.mk b/src/occ_405/pss/test/app.mk
index fdb4a6d..c1cf490 100755
--- a/src/occ/pss/test/app.mk
+++ b/src/occ_405/pss/test/app.mk
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/pss/test/app.mk $
+# $Source: src/occ_405/pss/test/app.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/pss/test/apsstest.c b/src/occ_405/pss/test/apsstest.c
index 9104fb3..768bdbe 100755
--- a/src/occ/pss/test/apsstest.c
+++ b/src/occ_405/pss/test/apsstest.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/pss/test/apsstest.c $                                 */
+/* $Source: src/occ_405/pss/test/apsstest.c $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/reset.c b/src/occ_405/reset.c
index f99fc40..f99fc40 100755
--- a/src/occ/reset.c
+++ b/src/occ_405/reset.c
diff --git a/src/occ/rtls/rtls.c b/src/occ_405/rtls/rtls.c
index 3a1d08b..df303c9 100755
--- a/src/occ/rtls/rtls.c
+++ b/src/occ_405/rtls/rtls.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/rtls/rtls.c $                                         */
+/* $Source: src/occ_405/rtls/rtls.c $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/rtls/rtls.h b/src/occ_405/rtls/rtls.h
index d4e12f4..a685883 100755
--- a/src/occ/rtls/rtls.h
+++ b/src/occ_405/rtls/rtls.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/rtls/rtls.h $                                         */
+/* $Source: src/occ_405/rtls/rtls.h $                                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/rtls/rtls_service_codes.h b/src/occ_405/rtls/rtls_service_codes.h
index b724ac3..5aab728 100755
--- a/src/occ/rtls/rtls_service_codes.h
+++ b/src/occ_405/rtls/rtls_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/rtls/rtls_service_codes.h $                           */
+/* $Source: src/occ_405/rtls/rtls_service_codes.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c
index e0414a4..e0414a4 100755
--- a/src/occ/rtls/rtls_tables.c
+++ b/src/occ_405/rtls/rtls_tables.c
diff --git a/src/occ/rtls/test/Makefile b/src/occ_405/rtls/test/Makefile
index 42762e1..4a45da2 100755
--- a/src/occ/rtls/test/Makefile
+++ b/src/occ_405/rtls/test/Makefile
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/rtls/test/Makefile $
+# $Source: src/occ_405/rtls/test/Makefile $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/rtls/test/app.mk b/src/occ_405/rtls/test/app.mk
index a214b0b..b34b3f6 100755
--- a/src/occ/rtls/test/app.mk
+++ b/src/occ_405/rtls/test/app.mk
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/rtls/test/app.mk $
+# $Source: src/occ_405/rtls/test/app.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/rtls/test/main.c b/src/occ_405/rtls/test/main.c
index 5016758..f720580 100755
--- a/src/occ/rtls/test/main.c
+++ b/src/occ_405/rtls/test/main.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/rtls/test/main.c $                                    */
+/* $Source: src/occ_405/rtls/test/main.c $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/rtls/test/rtls_tables.c b/src/occ_405/rtls/test/rtls_tables.c
index 72117cd..316dd8e 100755
--- a/src/occ/rtls/test/rtls_tables.c
+++ b/src/occ_405/rtls/test/rtls_tables.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/rtls/test/rtls_tables.c $                             */
+/* $Source: src/occ_405/rtls/test/rtls_tables.c $                         */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/scom.c b/src/occ_405/scom.c
index 6beed14..c891dba 100644
--- a/src/occ/scom.c
+++ b/src/occ_405/scom.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/scom.c $                                              */
+/* $Source: src/occ_405/scom.c $                                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/scom.h b/src/occ_405/scom.h
index 0e6312c..5d500a0 100644
--- a/src/occ/scom.h
+++ b/src/occ_405/scom.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/scom.h $                                              */
+/* $Source: src/occ_405/scom.h $                                          */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/sensor/sensor.c b/src/occ_405/sensor/sensor.c
index 8229ec8..e63d34d 100755
--- a/src/occ/sensor/sensor.c
+++ b/src/occ_405/sensor/sensor.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/sensor/sensor.c $                                     */
+/* $Source: src/occ_405/sensor/sensor.c $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/sensor/sensor.h b/src/occ_405/sensor/sensor.h
index 6172cd0..4459e08 100755
--- a/src/occ/sensor/sensor.h
+++ b/src/occ_405/sensor/sensor.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/sensor/sensor.h $                                     */
+/* $Source: src/occ_405/sensor/sensor.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/sensor/sensor_enum.h b/src/occ_405/sensor/sensor_enum.h
index 03caf52..ec2fd9e 100755
--- a/src/occ/sensor/sensor_enum.h
+++ b/src/occ_405/sensor/sensor_enum.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/sensor/sensor_enum.h $                                */
+/* $Source: src/occ_405/sensor/sensor_enum.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/sensor/sensor_info.c b/src/occ_405/sensor/sensor_info.c
index d23f2aa..d23f2aa 100755
--- a/src/occ/sensor/sensor_info.c
+++ b/src/occ_405/sensor/sensor_info.c
diff --git a/src/occ/sensor/sensor_service_codes.h b/src/occ_405/sensor/sensor_service_codes.h
index aa5ae71..517d9e3 100755
--- a/src/occ/sensor/sensor_service_codes.h
+++ b/src/occ_405/sensor/sensor_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/sensor/sensor_service_codes.h $                       */
+/* $Source: src/occ_405/sensor/sensor_service_codes.h $                   */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/sensor/sensor_table.c b/src/occ_405/sensor/sensor_table.c
index 6ad0c8b..86786e0 100755
--- a/src/occ/sensor/sensor_table.c
+++ b/src/occ_405/sensor/sensor_table.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/sensor/sensor_table.c $                               */
+/* $Source: src/occ_405/sensor/sensor_table.c $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index 10a635a..d619f34 100755
--- a/src/occ/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/ssx_app_cfg.h $                                       */
+/* $Source: src/occ_405/ssx_app_cfg.h $                                   */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/state.c b/src/occ_405/state.c
index 716c10c..716c10c 100755
--- a/src/occ/state.c
+++ b/src/occ_405/state.c
diff --git a/src/occ/state.h b/src/occ_405/state.h
index 3bae6ab..b6d0d7e 100755
--- a/src/occ/state.h
+++ b/src/occ_405/state.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/state.h $                                             */
+/* $Source: src/occ_405/state.h $                                         */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/chom.c b/src/occ_405/thread/chom.c
index b75bda8..b75bda8 100755
--- a/src/occ/thread/chom.c
+++ b/src/occ_405/thread/chom.c
diff --git a/src/occ/thread/chom.h b/src/occ_405/thread/chom.h
index b899e9e..b899e9e 100755
--- a/src/occ/thread/chom.h
+++ b/src/occ_405/thread/chom.h
diff --git a/src/occ/thread/test/Makefile b/src/occ_405/thread/test/Makefile
index 19671d8..62863ba 100755
--- a/src/occ/thread/test/Makefile
+++ b/src/occ_405/thread/test/Makefile
@@ -1,12 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/thread/test/Makefile $
+# $Source: src/occ_405/thread/test/Makefile $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/thread/test/app.mk b/src/occ_405/thread/test/app.mk
index 34bf102..b5001d5 100755
--- a/src/occ/thread/test/app.mk
+++ b/src/occ_405/thread/test/app.mk
@@ -1,13 +1,11 @@
 # IBM_PROLOG_BEGIN_TAG
 # This is an automatically generated prolog.
 #
-# $Source: src/occ/thread/test/app.mk $
-#
+# $Source: src/occ_405/thread/test/app.mk $
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2015
 # [+] International Business Machines Corp.
 #
 #
@@ -15,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
diff --git a/src/occ/thread/test/threadtest.c b/src/occ_405/thread/test/threadtest.c
index bebc8d2..0aced6c 100755
--- a/src/occ/thread/test/threadtest.c
+++ b/src/occ_405/thread/test/threadtest.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/test/threadtest.c $                            */
+/* $Source: src/occ_405/thread/test/threadtest.c $                        */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/thread.h b/src/occ_405/thread/thread.h
index 90d051f..3106a7c 100755
--- a/src/occ/thread/thread.h
+++ b/src/occ_405/thread/thread.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/thread.h $                                     */
+/* $Source: src/occ_405/thread/thread.h $                                 */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/threadSch.c b/src/occ_405/thread/threadSch.c
index f72fd94..cfb996e 100755
--- a/src/occ/thread/threadSch.c
+++ b/src/occ_405/thread/threadSch.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/threadSch.c $                                  */
+/* $Source: src/occ_405/thread/threadSch.c $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/threadSch.h b/src/occ_405/thread/threadSch.h
index 6359a82..124d460 100755
--- a/src/occ/thread/threadSch.h
+++ b/src/occ_405/thread/threadSch.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/threadSch.h $                                  */
+/* $Source: src/occ_405/thread/threadSch.h $                              */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/thread_service_codes.h b/src/occ_405/thread/thread_service_codes.h
index b855b15..6d13baa 100755
--- a/src/occ/thread/thread_service_codes.h
+++ b/src/occ_405/thread/thread_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/thread_service_codes.h $                       */
+/* $Source: src/occ_405/thread/thread_service_codes.h $                   */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/thrm_thread.c b/src/occ_405/thread/thrm_thread.c
index 408672d..13d9423 100755
--- a/src/occ/thread/thrm_thread.c
+++ b/src/occ_405/thread/thrm_thread.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/thrm_thread.c $                                */
+/* $Source: src/occ_405/thread/thrm_thread.c $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/thread/thrm_thread.h b/src/occ_405/thread/thrm_thread.h
index da44abd..21a8b8e 100755
--- a/src/occ/thread/thrm_thread.h
+++ b/src/occ_405/thread/thrm_thread.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/thread/thrm_thread.h $                                */
+/* $Source: src/occ_405/thread/thrm_thread.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/timer/timer.c b/src/occ_405/timer/timer.c
index 5a89b89..a85eaf8 100755
--- a/src/occ/timer/timer.c
+++ b/src/occ_405/timer/timer.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/timer/timer.c $                                       */
+/* $Source: src/occ_405/timer/timer.c $                                   */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/timer/timer.h b/src/occ_405/timer/timer.h
index e47ebd6..777a626 100755
--- a/src/occ/timer/timer.h
+++ b/src/occ_405/timer/timer.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/timer/timer.h $                                       */
+/* $Source: src/occ_405/timer/timer.h $                                   */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/timer/timer_service_codes.h b/src/occ_405/timer/timer_service_codes.h
index 906ee16..820ba88 100755
--- a/src/occ/timer/timer_service_codes.h
+++ b/src/occ_405/timer/timer_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/timer/timer_service_codes.h $                         */
+/* $Source: src/occ_405/timer/timer_service_codes.h $                     */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/trac/trac.h b/src/occ_405/trac/trac.h
index 87f669b..87f669b 100755
--- a/src/occ/trac/trac.h
+++ b/src/occ_405/trac/trac.h
diff --git a/src/occ/trac/trac_interface.c b/src/occ_405/trac/trac_interface.c
index ba3040c..56a7cfb 100755
--- a/src/occ/trac/trac_interface.c
+++ b/src/occ_405/trac/trac_interface.c
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/trac/trac_interface.c $                               */
+/* $Source: src/occ_405/trac/trac_interface.c $                           */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/trac/trac_interface.h b/src/occ_405/trac/trac_interface.h
index d448a0e..d448a0e 100755
--- a/src/occ/trac/trac_interface.h
+++ b/src/occ_405/trac/trac_interface.h
diff --git a/src/occ/trac/trac_service_codes.h b/src/occ_405/trac/trac_service_codes.h
index 74c782d..f7a278a 100755
--- a/src/occ/trac/trac_service_codes.h
+++ b/src/occ_405/trac/trac_service_codes.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/trac/trac_service_codes.h $                           */
+/* $Source: src/occ_405/trac/trac_service_codes.h $                       */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/gpe/apss_altitude.pS b/src/occ_gpe0/apss_altitude.pS
index df72fcc..df72fcc 100755
--- a/src/occ/gpe/apss_altitude.pS
+++ b/src/occ_gpe0/apss_altitude.pS
diff --git a/src/occ/gpe/apss_composite.pS b/src/occ_gpe0/apss_composite.pS
index 9e03c08..9e03c08 100755
--- a/src/occ/gpe/apss_composite.pS
+++ b/src/occ_gpe0/apss_composite.pS
diff --git a/src/occ/gpe/apss_constants.h b/src/occ_gpe0/apss_constants.h
index 413fdb1..5c6a28b 100755
--- a/src/occ/gpe/apss_constants.h
+++ b/src/occ_gpe0/apss_constants.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/gpe/apss_constants.h $                                */
+/* $Source: src/occ_405/gpe/apss_constants.h $                            */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/gpe/apss_init.pS b/src/occ_gpe0/apss_init.pS
index 23dfdd7..23dfdd7 100755
--- a/src/occ/gpe/apss_init.pS
+++ b/src/occ_gpe0/apss_init.pS
diff --git a/src/occ/gpe/apss_meas_read_complete.pS b/src/occ_gpe0/apss_meas_read_complete.pS
index 3967034..3967034 100755
--- a/src/occ/gpe/apss_meas_read_complete.pS
+++ b/src/occ_gpe0/apss_meas_read_complete.pS
diff --git a/src/occ/gpe/apss_meas_read_cont.pS b/src/occ_gpe0/apss_meas_read_cont.pS
index 0bd44b5..0bd44b5 100755
--- a/src/occ/gpe/apss_meas_read_cont.pS
+++ b/src/occ_gpe0/apss_meas_read_cont.pS
diff --git a/src/occ/gpe/apss_meas_read_start.pS b/src/occ_gpe0/apss_meas_read_start.pS
index c0b2393..c0b2393 100755
--- a/src/occ/gpe/apss_meas_read_start.pS
+++ b/src/occ_gpe0/apss_meas_read_start.pS
diff --git a/src/occ/gpe/gpe_export.h b/src/occ_gpe0/gpe_export.h
index f1673c6..6922638 100755
--- a/src/occ/gpe/gpe_export.h
+++ b/src/occ_gpe0/gpe_export.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/gpe/gpe_exports.h $                                   */
+/* $Source: src/occ_405/gpe/gpe_export.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/gpe/gpe_macros.h b/src/occ_gpe0/gpe_macros.h
index 9a34f98..b5f605c 100755
--- a/src/occ/gpe/gpe_macros.h
+++ b/src/occ_gpe0/gpe_macros.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/gpe/gpe_macros.h $                                    */
+/* $Source: src/occ_405/gpe/gpe_macros.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/gpe/pore_nop.pS b/src/occ_gpe0/pore_nop.pS
index bbe5e25..bbe5e25 100755
--- a/src/occ/gpe/pore_nop.pS
+++ b/src/occ_gpe0/pore_nop.pS
diff --git a/src/occ/gpe/pore_test.pS b/src/occ_gpe0/pore_test.pS
index 2534d4b..2534d4b 100755
--- a/src/occ/gpe/pore_test.pS
+++ b/src/occ_gpe0/pore_test.pS
diff --git a/src/occ/gpe/pore_test_error.pS b/src/occ_gpe0/pore_test_error.pS
index 58d7135..58d7135 100755
--- a/src/occ/gpe/pore_test_error.pS
+++ b/src/occ_gpe0/pore_test_error.pS
diff --git a/src/occ/gpe/pore_test_pss.pS b/src/occ_gpe0/pore_test_pss.pS
index f49bdac..f49bdac 100755
--- a/src/occ/gpe/pore_test_pss.pS
+++ b/src/occ_gpe0/pore_test_pss.pS
diff --git a/src/occ/gpe/pss_constants.h b/src/occ_gpe0/pss_constants.h
index bdeeb2b..31521ea 100755
--- a/src/occ/gpe/pss_constants.h
+++ b/src/occ_gpe0/pss_constants.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/gpe/pss_constants.h $                                 */
+/* $Source: src/occ_405/gpe/pss_constants.h $                             */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/occ/gpe/pss_macros.h b/src/occ_gpe0/pss_macros.h
index 9de29be..8cbcf0b 100755
--- a/src/occ/gpe/pss_macros.h
+++ b/src/occ_gpe0/pss_macros.h
@@ -1,14 +1,14 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ/gpe/pss_macros.h $                                    */
+/* $Source: src/occ_405/gpe/pss_macros.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] Google Inc.                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
+/*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
 /* You may obtain a copy of the License at                                */
diff --git a/src/ssx/occhw/Makefile b/src/ssx/occhw/Makefile
new file mode 100644
index 0000000..c16da5b
--- /dev/null
+++ b/src/ssx/occhw/Makefile
@@ -0,0 +1,77 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/occhw/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile compiles all of the SSX code required for the OCC port
+# of SSX.  See the "img_defs.mk" file in the top directory.
+
+#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/ssx
+export SUB_OBJDIR = /ssx
+
+include img_defs.mk
+include ssxocchwfiles.mk
+
+ifeq "$(SSX_TIMER_SUPPORT)" "1"
+OCCHW_OBJECTS += ${OCCHW-TIMER-C-SOURCES:.c=.o} ${OCCHW-TIMER-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(SSX_THREAD_SUPPORT)" "1"
+OCCHW_OBJECTS += ${OCCHW-THREAD-C-SOURCES:.c=.o} ${OCCHW-THREAD-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(OCCHW_ASYNC_SUPPORT)" "1"
+OCCHW_OBJECTS += ${OCCHW-ASYNC-C-SOURCES:.c=.o} ${OCCHW-ASYNC-S-SOURCES:.S=.o}
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(OCCHW_OBJECTS))
+
+libssx.a: ssx ppc405 ppc32 trace occhw
+	$(AR) crs $(OBJDIR)/libssx.a $(OBJDIR)/*.o
+
+.PHONY: clean occhw ssx ppc405 ppc32 trace
+
+occhw: $(OBJS)
+
+trace:
+	$(MAKE) -I $(IMAGE_SRCDIR) -C ../trace
+
+ssx:
+	$(MAKE) -I $(IMAGE_SRCDIR) -C ../ssx
+
+ppc405:
+	$(MAKE) -I $(IMAGE_SRCDIR) -C ../ppc405
+
+ppc32:
+	$(MAKE) -I $(IMAGE_SRCDIR) -C ../ppc32
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
diff --git a/src/ssx/pgp/pgp.h b/src/ssx/occhw/occhw.h
index fb99e4f..b0ddda8 100755..100644
--- a/src/ssx/pgp/pgp.h
+++ b/src/ssx/occhw/occhw.h
@@ -1,70 +1,79 @@
-#ifndef __PGP_H__
-#define __PGP_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw.h $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_H__
+#define __OCCHW_H__
 
-// $Id: pgp.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp.h
-/// \brief The PgP environment for SSX.
+/// \file occhw.h
+/// \brief The OCCHW environment for SSX.
 
 // This is a 'circular' reference in SSX, but included here to simplify PGAS
 // programming. 
 
-#ifndef CHIP_PGP
-#define CHIP_PGP
+#ifndef HWMACRO_OCC
+#define HWMACRO_OCC
 #include "ppc405.h"
 #endif  
 
 // Can't include this here due to ordering issues.  It's included in
 // ppc405_irq.h.
-// #include "pgp_irq.h"
+// #include "occhw_irq.h"
 
 // Required for MMU Map declarations
 #include "ppc405_mmu.h"
 
-#include "pgp_common.h"
-#include "pgp_core.h"
-#include "pgp_trace.h"
-#include "pgp_ocb.h"
-#include "pgp_pba.h"
-#include "pgp_pore.h"
-#include "pgp_pmc.h"
-#include "pgp_sramctl.h"
-#include "pgp_vrm.h"
-#include "pgp_id.h"
-#include "pgp_centaur.h"
+#include "occhw_common.h"
+#include "occhw_core.h"
+#include "occhw_ocb.h"
+#include "occhw_pba.h"
+#include "occhw_scom.h"
+#include "occhw_sramctl.h"
+//#include "occhw_vrm.h"
+#include "occhw_id.h"
+//#include "occhw_centaur.h"
 
-#include "pcbs_register_addresses.h"
-#include "pcbs_firmware_registers.h"
+//#include "pcbs_register_addresses.h"
+//#include "pcbs_firmware_registers.h"
 
-#include "tod_register_addresses.h"
-#include "tod_firmware_registers.h"
+//#include "tod_register_addresses.h"
+//#include "tod_firmware_registers.h"
 
-#include "plb_arbiter_register_addresses.h"
-#include "plb_arbiter_firmware_registers.h"
+//#include "mcs_register_addresses.h"
+//#include "mcs_firmware_registers.h"
 
-#include "mcs_register_addresses.h"
-#include "mcs_firmware_registers.h"
-
-#include "centaur_firmware_registers.h"
-#include "centaur_register_addresses.h"
+//#include "centaur_firmware_registers.h"
+//#include "centaur_register_addresses.h"
 
 #include "tpc_register_addresses.h"
 #include "tpc_firmware_registers.h"
 
-#include "oha_register_addresses.h"
-#include "oha_firmware_registers.h"
-
-
-// Include other driver headers
-
-#include "pgp_async.h"
-
 /// \defgroup memory_map Real-mode memory map setup for SRAM-resident applications
 ///
 /// Below are the interpretations of the default settings of the real-mode
@@ -112,11 +121,11 @@
 /// @}
 
 
-/// PgP always runs from a memory image
+/// OCCHW always runs from a memory image
 
 #define SSX_RUN_FROM_MEMORY 1
 
-/// This is the initial value of Cache Control Register 0 (CCR0) for PgP.
+/// This is the initial value of Cache Control Register 0 (CCR0) for OCCHW.
 /// This definition can be overridden by the application.
 ///
 /// The default setting:
@@ -128,7 +137,7 @@
 ///   performance evaluation).  Non-cacheable regions are not prefetched.
 ///
 /// - Gives highest PLB priority to ICU fetches.  This setting can be
-///   overriden by scan-only dials in the PgP design which force a fixed
+///   overriden by scan-only dials in the OCCHW design which force a fixed
 ///   priority on the ICU.
 ///
 /// - Sets priority bit 1 to '1' for DCU operations.  The DCU sets priority
@@ -148,7 +157,7 @@
 
 #ifndef __ASSEMBLER__
 
-/// \page noncacheable_support Non-cacheable modes for PgP
+/// \page noncacheable_support Non-cacheable modes for OCCHW 
 ///
 /// In order to support evaluation of cache management strategies on
 /// performance, DMA buffers read/written by DMA devices can be declared as
@@ -164,7 +173,7 @@
 /// sections are enforced only if PPC405_MMU_SUPPORT is also configured.
 /// Writethrogh sections are assumed to be read-write.
 ///
-/// PGP_HIGH_MEMORY_LOAD
+/// OCCHW_HIGH_MEMORY_LOAD
 ///
 ///     cacheable    : 0xfff8000 - 0xffffffff
 ///     noncacheable : 0xf7f8000 - 0xf7ffffff [cacheable - 128MB]
@@ -318,11 +327,11 @@ extern Ppc405MmuMap G_applet1_mmu_map;
 
 #endif  /* __ASSEMBLER__ */
 
-// PgP defines a private version of dcache_flush_all() that uses the undefined
-// OCI space at 0x80000000; See dcache_flush_all() in pgp_cache.S.
+// OCCHW defines a private version of dcache_flush_all() that uses the undefined
+// OCI space at 0x20000000; See dcache_flush_all() in occhw_cache.S.
 
 #define USE_GENERIC_DCACHE_FLUSH_ALL 0
-#define PGP_FLUSH_ZERO_ADDRESS       0x80000000
-#define PGP_FLUSH_ZERO_DCCR          0x00008000
+#define OCCHW_FLUSH_ZERO_ADDRESS       0x20000000
+#define OCCHW_FLUSH_ZERO_DCCR          0x08000000
 
-#endif  /* __PGP_H__ */
+#endif  /* __OCCHW_H__ */
diff --git a/src/ssx/pgp/pgp_async.c b/src/ssx/occhw/occhw_async.c
index f9c446f..f0fbbca 100755..100644
--- a/src/ssx/pgp/pgp_async.c
+++ b/src/ssx/occhw/occhw_async.c
@@ -1,12 +1,34 @@
-// $Id: pgp_async.c,v 1.4 2014/02/14 12:18:05 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_async.c $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_async.c
+/// \file occhw_async.c
 /// \brief Support for asynchronous request queuing and callback mechanisms
 ///
 /// This file implements device drivers for asynchronous requests.  The model
@@ -74,9 +96,9 @@
 /// request using the API async_request_timestamps_get().
 ///
 /// This is largely a generic implementation, designed to reduce code space by
-/// allowing the PORE, PBA and OCB drivers to use the same generic data
+/// allowing the GPE, PBA and OCB drivers to use the same generic data
 /// structures and code.  This is supported by the 'single-inheritence class
-/// hierarchy' described in the comments for pgp_async.h.
+/// hierarchy' described in the comments for occhw_async.h.
 ///
 /// <b> Request Completion and Callback States </b>
 ///
@@ -126,16 +148,19 @@
 /// handling to fast-mode assembler routines.
 
 #include "ssx.h"
-
+#include "occhw_async.h"
 
 ////////////////////////////////////////////////////////////////////////////
 // Global Data
 ////////////////////////////////////////////////////////////////////////////
 
-/// Queue of deferred callbacks
+/// Queue of deferred async callbacks
 
 static SsxDeque G_async_callback_queue;
 
+/// Queue of deferred IPC callbacks
+
+SsxDeque G_ipc_deferred_queue;
 
 ////////////////////////////////////////////////////////////////////////////
 // FFDC 
@@ -155,18 +180,19 @@ static SsxDeque G_async_callback_queue;
 void
 oci_ffdc(OciFfdc* ffdc, int master_id)
 {
-    uint32_t pesr_lock_mask;
-
-    ffdc->pearl.value = mfdcr(PLB_PEARL);
-    ffdc->pesr.value = mfdcr(PLB_PESR);
-
-    pesr_lock_mask = 0x30000000 >> (4 * master_id);
-    if (ffdc->pesr.value & pesr_lock_mask) {
-        ffdc->mine = 1;
-        mtdcr(PLB_PESR, pesr_lock_mask);
-    } else {
-        ffdc->mine = 0;
-    }
+// \todo, fix new pib access to dcr registers
+//    uint32_t oesr_lock_mask;
+
+//    ffdc->oear.value = mfdcr(OCB_OEAR);
+//    ffdc->oesr.value = mfdcr(OCB_OESR);
+
+//    oesr_lock_mask = 0x30000000 >> (4 * master_id);
+//    if (ffdc->oesr.value & oesr_lock_mask) {
+//        ffdc->mine = 1;
+//        mtdcr(OCB_OESR, oesr_lock_mask);
+//    } else {
+//        ffdc->mine = 0;
+//    }
 }
 
 
@@ -294,7 +320,7 @@ async_request_complete(AsyncRequest *request)
         }
 
         ssx_critical_section_exit(&ctx);
-        ssx_irq_status_set(PGP_IRQ_ASYNC_IPI, 1);
+        ssx_irq_status_set(OCCHW_IRQ_ASYNC_IPI, 1);
     }
 }
 
@@ -757,12 +783,12 @@ async_request_latency(AsyncRequest* request, SsxTimebase* latency)
 
 
 // Dump an AsyncRequest
-
+#if 0
 void
 async_request_printk(AsyncRequest *request)
 {
     printk("----------------------------------------\n");
-    printk("-- AsyncRequest @@ %p\n", request);
+    printk("-- AsyncRequest @ %p\n", request);
     printk("--   deque            = %p\n", &(request->deque));
     printk("--   start_time       = 0x%016llx\n", request->start_time);
     printk("--   end_time         = 0x%016llx\n", request->end_time);
@@ -777,7 +803,7 @@ async_request_printk(AsyncRequest *request)
     printk("--   options          = 0x%04x\n", request->options);
     printk("----------------------------------------\n");
 }
-
+#endif
 
 ////////////////////////////////////////////////////////////////////////////
 // Callback Queue
@@ -855,18 +881,17 @@ void
 async_callback_handler_full(void *arg, SsxIrqId irq, int priority)
 {
     SsxMachineContext ctx;
-    SsxDeque *queue = (SsxDeque *)arg;
     AsyncRequest *request;
+    ipc_msg_t *msg;
 
     ssx_irq_disable(irq);
 
+    //Check for any async callbacks first
     do {
 
         ssx_critical_section_enter(SSX_CRITICAL, &ctx);
-
-        request = (AsyncRequest *)ssx_deque_pop_front(queue);
+        request = (AsyncRequest *)ssx_deque_pop_front(&G_async_callback_queue);
         if (!request) {
-            ssx_irq_status_clear(irq);
             break;
         }
 
@@ -877,6 +902,28 @@ async_callback_handler_full(void *arg, SsxIrqId irq, int priority)
     } while (1);
 
     ssx_critical_section_exit(&ctx);
+
+    //Next, check for any deferred IPC messages
+    do {
+
+        ssx_critical_section_enter(SSX_CRITICAL, &ctx);
+
+        msg = (ipc_msg_t *)ssx_deque_pop_front(&G_ipc_deferred_queue);
+        if (!msg) {
+            ssx_irq_status_clear(irq);
+            break;
+        }
+
+        ssx_critical_section_exit(&ctx);
+
+void ipc_process_msg(ipc_msg_t* msg);
+
+        //handle the command or response message in a noncritical context
+        ipc_process_msg(msg);
+
+    } while (1);
+
+    ssx_critical_section_exit(&ctx);
     ssx_irq_enable(irq);
 }
 
@@ -924,17 +971,18 @@ async_level_handler_setup(SsxIrqHandler handler,
 
 
 void
-async_callbacks_initialize(SsxDeque *queue, SsxIrqId irq)
+async_callbacks_initialize(SsxIrqId irq)
 {
-    ssx_deque_sentinel_create(queue);
+    ssx_deque_sentinel_create(&G_async_callback_queue);
+    ssx_deque_sentinel_create(&G_ipc_deferred_queue);
     async_edge_handler_setup(async_callback_handler,
-                             (void *)queue,
+                             0,
                              irq, SSX_NONCRITICAL);
     ssx_irq_enable(irq);
 }
 
 
-/// Create all of the PgP asynchronous request structures and install and
+/// Create all of the asynchronous request structures and install and
 /// activate the interrupt handlers.
 
 void
@@ -943,30 +991,26 @@ async_initialize()
     // This is the callback queue used e.g. when critical interrupts need to
     // run non-critical callbacks.
 
-    async_callbacks_initialize(&G_async_callback_queue, PGP_IRQ_ASYNC_IPI);
+    async_callbacks_initialize(OCCHW_IRQ_ASYNC_IPI);
 
-    // PORE
+    async_gpe_initialize(&G_async_gpe_queue0, ASYNC_ENGINE_GPE0);
+    async_gpe_initialize(&G_async_gpe_queue1, ASYNC_ENGINE_GPE1);
+    async_gpe_initialize(&G_async_gpe_queue2, ASYNC_ENGINE_GPE2);
+    async_gpe_initialize(&G_async_gpe_queue3, ASYNC_ENGINE_GPE3);
 
-    async_pore_initialize(&G_pore_gpe0_queue, ASYNC_ENGINE_PORE_GPE0);
-    async_pore_initialize(&G_pore_gpe1_queue, ASYNC_ENGINE_PORE_GPE1);
-
-
-#if CONFIGURE_PTS
-    // PTS
-
-    async_pts_initialize(&G_pts_gpe0_queue, ASYNC_ENGINE_PORE_GPE0);
-    async_pts_initialize(&G_pts_gpe1_queue, ASYNC_ENGINE_PORE_GPE1);
-#endif
 
+    // TODO: add these back in as they are ported to P9
+#if 0
     // BCE
 
     async_bce_initialize(&G_pba_bcde_queue,
                          ASYNC_ENGINE_BCDE,
-                         PGP_IRQ_PBA_BCDE_ATTN);
+                         OCCHW_IRQ_PBA_BCDE_ATTN);
 
     async_bce_initialize(&G_pba_bcue_queue,
                          ASYNC_ENGINE_BCUE,
-                         PGP_IRQ_PBA_BCUE_ATTN);
+                         OCCHW_IRQ_PBA_BCUE_ATTN);
+#endif
 
     // OCB
 
@@ -988,6 +1032,12 @@ async_initialize()
                          OCB_READ2_LENGTH,
                          OCB_READ2_PROTOCOL);
 
+    async_ocb_initialize(&(G_ocb_read_queue[3]),
+                         ASYNC_ENGINE_OCB_PUSH3,
+                         G_ocb_read3_buffer,
+                         OCB_READ3_LENGTH,
+                         OCB_READ3_PROTOCOL);
+
     async_ocb_initialize(&(G_ocb_write_queue[0]),
                          ASYNC_ENGINE_OCB_PULL0,
                          G_ocb_write0_buffer,
@@ -1006,19 +1056,27 @@ async_initialize()
                          OCB_WRITE2_LENGTH,
                          OCB_WRITE2_PROTOCOL);
 
+    async_ocb_initialize(&(G_ocb_write_queue[3]),
+                         ASYNC_ENGINE_OCB_PULL3,
+                         G_ocb_write3_buffer,
+                         OCB_WRITE3_LENGTH,
+                         OCB_WRITE3_PROTOCOL);
+
+#if 0
     // PBAX
 
     async_pbax_initialize(&G_pbax_read_queue[0],
                           ASYNC_ENGINE_PBAX_PUSH0,
-                          PGP_IRQ_PBA_OCC_PUSH0,
+                          OCCHW_IRQ_PBAX_OCC_PUSH0,
                           G_pbax_read0_buffer,
                           PBAX_READ0_LENGTH,
                           PBAX_READ0_PROTOCOL);
 
     async_pbax_initialize(&G_pbax_read_queue[1],
                           ASYNC_ENGINE_PBAX_PUSH1,
-                          PGP_IRQ_PBA_OCC_PUSH1,
+                          OCCHW_IRQ_PBAX_OCC_PUSH1,
                           G_pbax_read1_buffer,
                           PBAX_READ1_LENGTH,
                           PBAX_READ1_PROTOCOL);
+#endif
 }
diff --git a/src/ssx/pgp/pgp_async.h b/src/ssx/occhw/occhw_async.h
index ecd3ae2..e2bbf0a 100755..100644
--- a/src/ssx/pgp/pgp_async.h
+++ b/src/ssx/occhw/occhw_async.h
@@ -1,15 +1,37 @@
-#ifndef __PGP_ASYNC_H__
-#define __PGP_ASYNC_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_async.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_ASYNC_H__
+#define __OCCHW_ASYNC_H__
 
-// $Id: pgp_async.h,v 1.2 2014/02/03 01:30:34 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_async.h
+/// \file occhw_async.h
 /// \brief Support for asynchronous request/callback mechanisms
 ///
 /// The data structures defined here provide a 'C' implementation of multiple
@@ -17,53 +39,52 @@
 /// 'superclass' as the initial element of the structure, allowing subclass
 /// pointers to be safely cast to the superclass, and vice-versa (assuming
 /// that the subclass is known). One benefit of this approach is that it
-/// allows code sharing between requests targeting PORE-GPE, PORE-SW,
+/// allows code sharing between requests targeting GPE,
 /// PBA-BCDE, PBA-BCUE and the deferred callback queue.
 ///
 /// The 'class hierarchy' :
 ///
 /// SsxDeque
 ///        AsyncRequest
-///              PoreRequest
-///                      PoreFixed
-///                      PoreFlex
+///              GpeRequest
 ///              BceRequest
 ///              OcbRequest
 ///              Pbaxrequest
 ///
 /// AsyncQueue
-///        PoreQueue
+///        GpeQueue
 ///        BceQueue
 ///        OcbQueue
 ///        PbaxQueue
 ///
-/// \bug We may need to redo how we start jobs since writing the EXE-TRIGGER
-/// does not guarantee a restart from a good state, although if we get our CCB
-/// request through it will.
 
+#include "ipc_async_cmd.h"
+#include "occhw_xir_dump.h"
 
-// PgP Execution engines for the purposes of the generic request mechanism.
+// OCCHW Execution engines for the purposes of the generic request mechanism.
 
 #define ASYNC_ENGINE_ANONYMOUS 0x00
 
-#define ASYNC_ENGINE_PORE      0x10
-#define ASYNC_ENGINE_PORE_GPE0 0x10
-#define ASYNC_ENGINE_PORE_GPE1 0x11
-#define ASYNC_ENGINE_PORE_SLW  0x12
+#define ASYNC_ENGINE_GPE       0x10
+#define ASYNC_ENGINE_GPE0      0x10
+#define ASYNC_ENGINE_GPE1      0x11
+#define ASYNC_ENGINE_GPE2      0x12
+#define ASYNC_ENGINE_GPE3      0x13
 
 #define ASYNC_ENGINE_BCE       0x20
 #define ASYNC_ENGINE_BCDE      0x20
 #define ASYNC_ENGINE_BCUE      0x21
 
-// Indirect channel 3 no longer supports push/pull queues and they have been
-// removed.
+// Indirect channel 3 is now back online to support push/pull queues in P9.
 #define ASYNC_ENGINE_OCB       0x40
 #define ASYNC_ENGINE_OCB_PUSH0 0x41
 #define ASYNC_ENGINE_OCB_PUSH1 0x42
 #define ASYNC_ENGINE_OCB_PUSH2 0x43
+#define ASYNC_ENGINE_OCB_PUSH3 0x44
 #define ASYNC_ENGINE_OCB_PULL0 0x45
 #define ASYNC_ENGINE_OCB_PULL1 0x46
 #define ASYNC_ENGINE_OCB_PULL2 0x47
+#define ASYNC_ENGINE_OCB_PULL3 0x48
 
 #define ASYNC_ENGINE_PBAX       0x80
 #define ASYNC_ENGINE_PBAX_PUSH0 0x81
@@ -94,17 +115,17 @@ typedef uint8_t AsyncEngine;
 
 typedef struct {
 
-    /// PLB arbiter Error Address Register Low
+    /// PLB arbiter Error Address Register
     ///
     /// This is the address of the last PLB timeout or other error recorded in
-    /// the PEARL.  This is an error for the unit in question only if the
+    /// the PEAR.  This is an error for the unit in question only if the
     /// \a mine data member is non-zero.
-    plb_pearl_t pearl;
+    ocb_oear_t oear;
 
     /// PLB arbiter Error Status Register
     ///
     /// The PESR at the time of the error.
-    plb_pesr_t pesr;
+    ocb_oesr_t oesr;
 
     /// Is the unit in question responsible for the error address recorded in
     /// the PEARL?
@@ -493,160 +514,66 @@ async_level_handler_setup(SsxIrqHandler handler,
                           int polarity);
 
 void
-async_callbacks_initialize(SsxDeque *queue, SsxIrqId irq);
+async_callbacks_initialize(SsxIrqId irq);
 
 
 #endif // __ASSEMBLER__
 
-
 ////////////////////////////////////////////////////////////////////////////
-// PoreRequest
+// GpeRequest
 ////////////////////////////////////////////////////////////////////////////
 
 #ifndef __ASSEMBLER__
 
-struct PoreQueue;
-
-/// PORE FFDC
-///
-/// The PORE engine has 208 bytes of programmer-visible state - too much to
-/// allocate in every PoreRequest on the off-chance that a request may fail.
-/// This PoreFfdc structure is designed to capture a reasonble amount of data
-/// in the case of failure of a PoreFlex request, which does not include any
-/// PORE error handlers.  This structure is currently 48 bytes.
-///
-/// The most common recoverable errors are expected to be erroneous PIB
-/// responses from deconfigured (garded) cores.  These will show up as Error
-/// event 0 and can be debugged from the debug registers.  We also include the
-/// instruction buffer registers to help debug error 2 - instruction
-/// fetch/decode errors.
-///
-/// To get a full picture in the event of OCI execution phase errors (error
-/// 1), the PORE memory-space address registers are captured.  We also capture
-/// FFDC from the PLB arbiter, which can be used to debug illegal address-type
-/// problems. 
-
-typedef struct {
-
-    /// FFDC from the PLB (OCI) arbiter
-    OciFfdc oci_ffdc;
-
-    /// PORE Debug Registers
-    /// 
-    /// - [0] Contains PIB address and PIB return code
-    /// - [1] Contains failing PC and error status bits
-    uint64_t debug[2];
-
-    /// PORE Memory-space address registers.  
-    ///
-    /// We only save the low-order 32 bits of each - the high-order bits are
-    /// implied/ignored for OCI-attached engines.  If OCC managed the SBE then
-    /// we would require the high-order bits in an FFDC dump.
-    uint32_t address[2];
-
-    /// PORE Instruction buffer 0-2
-    ///
-    /// - [0] Contains the opcode and register/short operands
-    /// - [1:2] Contain the 64-bit immediate
-    uint32_t ibuf[3];
-
-} PoreFfdc;
-
+struct GpeQueue;
 
-/// A PORE branch immediate address instruction, used in PORE jump tables.
+/// GPE FFDC
 typedef struct {
-    uint32_t word[3];
-} PoreBraia;
-
-
-void
-pore_braia_create(PoreBraia* instr, uint32_t address);
+    uint32_t            func_id;
+    int32_t             ipc_rc;
+    int                 xir_dump_rc;
+    occhw_xir_dump_t    xir_dump;
+} GpeFfdc;
 
-
-/// A request to run a PORE program
+/// A request to run a GPE command
 ///
-/// A PORE request extends the generic AsyncRequest request by the addition of
-/// several fields required to be set up in the engine before the job is run,
-/// including the program parameter for the routine.  The PoreRequest is an
-/// internal class that is re-typed to create the PoreFixed and PoreFlex
-/// request classes, which differ only slightly in their behavior.
+/// A GPE request extends the generic AsyncRequest request by the addition of
+/// several fields required for running a job on a GPE
+/// including the program parameter for the routine.
 ///
 /// As long as the request is known to be idle the application is free to
-/// change the \a parameter value between executions of the PORE program,
+/// change the \a parameter value between executions of the GPE command,
 /// e.g., to do ping-pong buffer management.  None of the other fields should
 /// be directly modified by the application.
 
 typedef struct {
 
     /// The generic request
-    AsyncRequest request;
-
-    /// Error information
-    PoreFfdc ffdc;
-
-    /// The PORE Jump Table
-    PoreBraia* table;
-
-    /// The initial value of the high-order 32 bits of the ERROR_MASK register
-    uint32_t error_mask;
-
-    /// The entry point address of the routine.
-    ///
-    /// For PoreFlex this entry point will be non-0 and will be inserted into
-    /// D0, as PoreFlex jobs are kicked off by BRAD.  For PoreFixed this
-    /// parameter will be zero and ignored.
-    uint32_t entry_point;
-
-    /// The single parameter of the PORE program - EXE-Trigger[32:63]
-    uint32_t parameter;
-
-    /// The high-order 32 bits of EXE-Trigger used to kick off the program.
-    ///
-    /// For PoreFlex this field is always 0, as PoreFlex only uses table entry
-    /// 0 which contains a BRAD.  For PoreFixed this encodes the address of
-    /// the table entry to kick off.
-    uint32_t exe_trigger;
+    AsyncRequest    request;
 
-} PoreRequest;
+    /// Error information collected by the 405
+    GpeFfdc         ffdc;
 
+    /// The targeted IPC function ID for this request
+    ipc_func_enum_t targeted_func_id;
 
-typedef PoreRequest PoreFlex;
+    /// A pointer to any command data that is used by the GPE or
+    /// returned by the GPE.
+    void*           cmd_data;
 
-typedef PoreRequest PoreFixed;
+} GpeRequest;
 
 int
-pore_run_method(AsyncRequest* request);
+gpe_run_method(AsyncRequest* request);
 
 int
-pore_error_method(AsyncRequest* request);
-
-#endif  /* __ASSEMBLER__ */
-
-/// The (fixed) number of PORE jump table error handler slots
-#define PORE_ERROR_SLOTS 5
-
-/// The maximum number of PORE jump table EXE_TRIGGER slots
-#define PORE_TRIGGER_SLOTS 16
-
-/// Compute the address of error handler BRAIA entry n of a PORE branch table
-#define PORE_ERROR_BRANCH(table, n) ((table) + ((n) * 12))
-
-/// Compute the address of entry point BRAIA entry n of a PORE branch table
-#define PORE_ENTRY_BRANCH(table, n) \
-    ((table) + (((PORE_ERROR_SLOTS) + (n)) * 12))
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreFlex
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
+gpe_error_method(AsyncRequest* request);
 
 int
-pore_flex_create(PoreFlex* request,
-                 struct PoreQueue* queue,
-                 PoreEntryPoint entry_point,
-                 uint32_t parameter,
+gpe_request_create(GpeRequest* request,
+                 struct GpeQueue* queue,
+                 ipc_func_enum_t func_id,
+                 void* cmd_data,
                  SsxInterval timeout,
                  AsyncRequestCallback callback,
                  void *arg,
@@ -655,85 +582,41 @@ pore_flex_create(PoreFlex* request,
 
 /// See async_request_schedule() for documentation.
 static inline int
-pore_flex_schedule(PoreFlex* request)
-{
-    return async_request_schedule((AsyncRequest *)request);
-}
-
-#endif  /* __ASSEMBLER__ */
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreFixed
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-int
-pore_fixed_create(PoreFixed *request,
-                  struct PoreQueue *queue,
-                  PoreBraia* table,
-                  uint32_t error_mask,
-                  int start_vector,
-                  uint32_t parameter,
-                  SsxInterval timeout,
-                  AsyncRequestCallback callback,
-                  void *arg,
-                  int options);
-
-/// See async_request_schedule() for documentation.
-static inline int
-pore_fixed_schedule(PoreFixed *request)
+gpe_request_schedule(GpeRequest* request)
 {
     return async_request_schedule((AsyncRequest *)request);
 }
 
-#endif  /* __ASSEMBLER__ */
-
-
 ////////////////////////////////////////////////////////////////////////////
-// PoreQueue
+// GpeQueue
 ////////////////////////////////////////////////////////////////////////////
 
-#ifndef __ASSEMBLER__
 
-/// A PORE engine queue
+/// A GPE engine queue
 ///
-/// A PORE queue consists of a generic AsyncQueue to manage jobs on the
-/// engine, the OCI base address of the PORE control register space of the
-/// engine, and interrupt information.
+/// A GPE queue consists of a generic AsyncQueue to manage jobs on the
+/// engine.
 
-typedef struct PoreQueue {
+typedef struct GpeQueue {
 
     /// The generic request queue - the "base class"
     AsyncQueue queue;
 
-    /// The base address of the OCI control register space for this engine.
-    uint32_t oci_base;
+    /// The IPC target_id
+    uint8_t         ipc_target_id;
 
-    /// The IRQ associated with normal completion on the engine
-    ///
-    /// \todo Due to header reference ordering we can't define this as SsxIrqId
-    uint8_t irq;
+    /// Pointer to an IPC command message
+    ipc_async_cmd_t *ipc_cmd;
 
-    /// The IRQ associated with error completion on the engine
-    ///
-    /// \todo Due to header reference ordering we can't define this as SsxIrqId
-    uint8_t error_irq;
-
-    /// The OCI master number of this engine; See pore_error_method()
-    uint8_t oci_master;
-
-} PoreQueue;
+} GpeQueue;
 
 
 int
-pore_queue_create(PoreQueue *queue,
+gpe_queue_create(GpeQueue *queue,
                   int engine);
 
 #endif  /* ASSEMBLER */
 
-
 ////////////////////////////////////////////////////////////////////////////
 // PBA FFDC Structures
 ////////////////////////////////////////////////////////////////////////////
@@ -1102,7 +985,7 @@ pbax_request_schedule(PbaxRequest *request);
 ////////////////////////////////////////////////////////////////////////////
 
 // NB: This assignment ordering is assumed by static initialization code in
-// pgp_async.c - these constants are used as array indices.
+// occhw_async.c - these constants are used as array indices.
 
 #define PBAX_ENGINE_PUSH0 0
 #define PBAX_ENGINE_PUSH1 1
@@ -1339,7 +1222,7 @@ ocb_request_schedule(OcbRequest *request);
 ////////////////////////////////////////////////////////////////////////////
 
 // NB: This assignment ordering is assumed by static initialization code in
-// pgp_async.c - these constants are used as array indices.  The code also
+// occhw_async.c - these constants are used as array indices.  The code also
 // assumes this ordering for the access of G_ocb_ocbsesn[], and for
 // determining whether the engine is a PUSH or PULL queue.
 // Note:  push/pull queues for channel 3 have been deleted 
@@ -1350,8 +1233,10 @@ ocb_request_schedule(OcbRequest *request);
 #define OCB_ENGINE_PULL1 3
 #define OCB_ENGINE_PUSH2 4
 #define OCB_ENGINE_PULL2 5
+#define OCB_ENGINE_PUSH3 6
+#define OCB_ENGINE_PULL3 7
 
-#define OCB_ENGINES 6
+#define OCB_ENGINES 8
 
 #ifndef __ASSEMBLER__
 
@@ -1411,13 +1296,8 @@ ocb_queue_create(OcbQueue *queue,
 #define ASYNC_INVALID_OBJECT_PBAX_QUEUE      0x00279606
 #define ASYNC_INVALID_OBJECT_BCE_REQUEST     0x00279607
 #define ASYNC_INVALID_OBJECT_BCE_QUEUE       0x00279608
-#define ASYNC_INVALID_OBJECT_PORE_REQUEST    0x00279609
-#define ASYNC_INVALID_OBJECT_PORE_QUEUE      0x0027960a
-#define ASYNC_INVALID_OBJECT_PTS_REQUEST     0x0027960b
-#define ASYNC_INVALID_OBJECT_PTS_THREAD      0x0027960c
-#define ASYNC_INVALID_OBJECT_PTS_QUEUE       0x0027960d
-#define ASYNC_INVALID_OBJECT_PTS_START       0x0027960e
-#define ASYNC_INVALID_OBJECT_PTS_SCHEDULE    0x0027960f
+#define ASYNC_INVALID_OBJECT_GPE_REQUEST     0x00279609
+#define ASYNC_INVALID_OBJECT_GPE_QUEUE       0x0027960a
 #define ASYNC_INVALID_ARGUMENT               0x00279610
 #define ASYNC_INVALID_ARGUMENT_OCB_READ      0x00279611
 #define ASYNC_INVALID_ARGUMENT_OCB_WRITE     0x00279612
@@ -1430,19 +1310,15 @@ ocb_queue_create(OcbQueue *queue,
 #define ASYNC_INVALID_ARGUMENT_PBAX_REQUEST  0x00279619
 #define ASYNC_INVALID_ARGUMENT_PBAX_SCHEDULE 0x0027961a
 #define ASYNC_INVALID_ARGUMENT_PBAX_QUEUE    0x0027961b
-#define ASYNC_INVALID_ARGUMENT_PORE_REQUEST  0x0027961c
-#define ASYNC_INVALID_ARGUMENT_PTS_THREAD    0x0027961d
-#define ASYNC_INVALID_ARGUMENT_PTS_REQUEST   0x0027961e
+#define ASYNC_INVALID_ARGUMENT_GPE_REQUEST   0x0027961c
 #define ASYNC_INVALID_ENGINE_OCB             0x0027961f
 #define ASYNC_INVALID_ENGINE_PBAX            0x00279620
 #define ASYNC_INVALID_ENGINE_BCE             0x00279621
-#define ASYNC_INVALID_ENGINE_PORE            0x00279622
-#define ASYNC_INVALID_ENGINE_PTS             0x00279623
+#define ASYNC_INVALID_ENGINE_GPE             0x00279622
 #define ASYNC_INVALID_OPTIONS                0x00279624
 #define ASYNC_INVALID_ASSIGNMENT             0x00279625
 #define ASYNC_CALLBACK_PROTOCOL_UNSPECIFIED  0x00279626
 #define ASYNC_REQUEST_NOT_IDLE               0x00279627
-#define ASYNC_REQUEST_NOT_IDLE_PTS           0x00279628
 #define ASYNC_REQUEST_COMPLETE               0x00279629
 #define ASYNC_INVALID_TIMESTAMPS             0x0027962a
 #define ASYNC_OCB_ERROR_READ_OLD             0x0027962b
@@ -1452,11 +1328,10 @@ ocb_queue_create(OcbQueue *queue,
 #define ASYNC_PBAX_ERROR_OLD                 0x0027962f
 #define ASYNC_PBAX_ERROR_NEW                 0x00279630
 #define ASYNC_REQUEST_NOT_COMPLETE           0x00279631
-#define ASYNC_REQUEST_NOT_COMPLETE_PTS       0x00279632
 
 // Panic codes
 
-#define ASYNC_PORE_FIXED_INVARIANT           0x00279633
+#define ASYNC_GPE_FIXED_INVARIANT            0x00279633
 #define ASYNC_PHANTOM_INTERRUPT              0x00279634
 #define ASYNC_PHANTOM_INTERRUPT_OCB          0x00279635
 #define ASYNC_PHANTOM_INTERRUPT_BCE          0x00279636
@@ -1465,9 +1340,7 @@ ocb_queue_create(OcbQueue *queue,
 #define ASYNC_TIMEOUT_BUG                    0x00279639
 #define ASYNC_INVALID_STATE                  0x0027963a
 #define ASYNC_PHANTOM_ERROR                  0x0027963b
-#define ASYNC_BUG_PORE_AT_CREATE             0x0027963c
-#define ASYNC_BUG_PTS_AT_CREATE              0x0027963d
-#define ASYNC_BUG_PTS_AT_RUN                 0x0027963e
+#define ASYNC_BUG_GPE_AT_CREATE              0x0027963c
 
 ////////////////////////////////////////////////////////////////////////////
 // Global Data and Constants
@@ -1475,31 +1348,12 @@ ocb_queue_create(OcbQueue *queue,
 
 #ifndef __ASSEMBLER__
 
-// PORE Queues
-
-extern PoreQueue G_pore_gpe0_queue;
-extern PoreQueue G_pore_gpe1_queue;
-extern PoreQueue G_pore_slw_queue;
-
-/// Define a PORE branch table.  All error slots are always defined, but space
-/// can be saved if not all of the entry points are required.
-#define PORE_TABLE(var, slots) PoreBraia var[PORE_ERROR_SLOTS + (slots)]
-
-
-// PTS Queues
-//
-// These queues are only defined if CONFIGURE_PTS is non-zero. CONFIGURE_PTS
-// is 0 by default.
-
-#ifndef CONFIGURE_PTS
-#define CONFIGURE_PTS 0
-#endif
+// GPE Queues
 
-#if CONFIGURE_PTS
-#include "pgp_async_pts.h"
-extern PtsQueue G_pts_gpe0_queue;
-extern PtsQueue G_pts_gpe1_queue;
-#endif
+extern GpeQueue G_async_gpe_queue0;
+extern GpeQueue G_async_gpe_queue1;
+extern GpeQueue G_async_gpe_queue2;
+extern GpeQueue G_async_gpe_queue3;
 
 
 // OCB Queues and FFDC
@@ -1533,18 +1387,22 @@ extern PtsQueue G_pts_gpe1_queue;
 #define OCB_READ0_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 #define OCB_READ1_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 #define OCB_READ2_LENGTH OCB_PUSH_PULL_LENGTH_MAX
+#define OCB_READ3_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 
 #define OCB_WRITE0_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 #define OCB_WRITE1_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 #define OCB_WRITE2_LENGTH OCB_PUSH_PULL_LENGTH_MAX
+#define OCB_WRITE3_LENGTH OCB_PUSH_PULL_LENGTH_MAX
 
 #define OCB_READ0_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE
 #define OCB_READ1_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE
 #define OCB_READ2_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE
+#define OCB_READ3_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE
 
 #define OCB_WRITE0_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY
 #define OCB_WRITE1_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY
 #define OCB_WRITE2_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY
+#define OCB_WRITE3_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY
 
 extern OcbUnitFfdc G_ocb_ffdc;
 
@@ -1554,10 +1412,12 @@ extern OcbQueue G_ocb_write_queue[];
 extern uint64_t G_ocb_read0_buffer[];
 extern uint64_t G_ocb_read1_buffer[];
 extern uint64_t G_ocb_read2_buffer[];
+extern uint64_t G_ocb_read3_buffer[];
 
 extern uint64_t G_ocb_write0_buffer[];
 extern uint64_t G_ocb_write1_buffer[];
 extern uint64_t G_ocb_write2_buffer[];
+extern uint64_t G_ocb_write3_buffer[];
 
 
 // PBA Queues
@@ -1630,7 +1490,7 @@ extern uint64_t G_pbax_read1_buffer[];
 // Initialization APIs
 
 void
-async_pore_initialize(PoreQueue *queue, int engine);
+async_gpe_initialize(GpeQueue *queue, int engine);
 
 void
 async_bce_initialize(BceQueue *queue, int engine, SsxIrqId irq);
@@ -1651,4 +1511,4 @@ async_initialize();
 
 #endif  /* __ASSEMBLER__ */
 
-#endif  /* __PGP_ASYNC_H__ */
+#endif  /* __OCCHW_ASYNC_H__ */
diff --git a/src/ssx/occhw/occhw_async_gpe.c b/src/ssx/occhw/occhw_async_gpe.c
new file mode 100644
index 0000000..524411d
--- /dev/null
+++ b/src/ssx/occhw/occhw_async_gpe.c
@@ -0,0 +1,309 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_async_gpe.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_async_gpe.c
+/// \brief Async driver code for GPE
+
+#include "ssx.h"
+#include "occhw_async.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// Global Data
+///////////////////////////////////////////////////////////////////////////////
+#define ASYNC_NUM_GPE_QUEUES 4
+#define ASYNC_ENG2GPE(eng) ((eng) & 0x0000000f)
+
+// The GPE queue objects.
+GpeQueue G_async_gpe_queue0;
+GpeQueue G_async_gpe_queue1;
+GpeQueue G_async_gpe_queue2;
+GpeQueue G_async_gpe_queue3;
+
+// Each GPE queue gets one IPC command.  These are allocated separately so that
+// they can be allocated in a non-cacheable section.
+ipc_async_cmd_t G_async_ipc_cmd[ASYNC_NUM_GPE_QUEUES] SECTION_ATTRIBUTE(".noncacheable");
+
+///////////////////////////////////////////////////////////////////////////////
+/// GpeQueue
+///////////////////////////////////////////////////////////////////////////////
+
+/// Create (initialize) a GpeQueue
+///
+/// \param queue An uninitialized or otherwise idle GpeeQueue
+///
+/// \param engine The identifier of a GPE engine associated with this queue.
+///
+/// This API initializes the GpeQueue structure.
+///
+/// \retval 0 Success
+///
+/// \retval -ASYNC_INVALID_OBJECT_PORE_QUEUE The \a queue was NULL (0).
+///
+/// \retval -ASYNC_INVALID_ENGINE_GPE The \a engine is not a (valid) 
+/// GPE engine.
+
+int
+gpe_queue_create(GpeQueue *queue, int engine)
+{
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(queue == 0, ASYNC_INVALID_OBJECT_GPE_QUEUE);
+        SSX_ERROR_IF(!(engine & ASYNC_ENGINE_GPE), ASYNC_INVALID_ENGINE_GPE);
+        SSX_ERROR_IF((ASYNC_ENG2GPE(engine) >= ASYNC_NUM_GPE_QUEUES), ASYNC_INVALID_ENGINE_GPE);
+    }
+
+    //initialize the base async queue
+    async_queue_create(&queue->queue, engine);
+
+    //assign an IPC message to be used with the queue
+    //This is kept as a pointer so that the message can kept in a
+    //cache-inhibited section of SRAM.
+    queue->ipc_cmd = &G_async_ipc_cmd[ASYNC_ENG2GPE(engine)];
+
+    //The IPC target ID that all messages on this queue will be sent to
+    queue->ipc_target_id = ASYNC_ENG2GPE(engine);
+
+    return 0;
+}
+
+////////////////////////////////////////////////////////////////////////////
+// async_ipc_callback
+////////////////////////////////////////////////////////////////////////////
+
+/// Internal function that handles aysnc IPC command responses
+
+void
+gpe_async_handler(ipc_msg_t* rsp, void* arg)
+{
+    // check for errors detected by the GPE code
+    if(rsp->ipc_rc != IPC_RC_SUCCESS)
+    {
+        //calls gpe_error_method before calling async_handler
+        async_error_handler((AsyncQueue *)arg, ASYNC_REQUEST_STATE_FAILED);
+    }
+    else
+    {
+
+        //handle async callbacks and process the next gpe request in the queue
+        //(if any)
+        async_handler((AsyncQueue *) arg);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////
+// GpeRequest
+////////////////////////////////////////////////////////////////////////////
+
+/// Create (initialize) the GpeRequest base class
+///
+/// \param request An uninitialized or otherwise idle GpeRequest.
+///
+/// \param queue An initialized GpeQueue.
+///
+/// \param func_id The IPC function ID of the GPE command.
+///
+/// \param cmd_data A pointer to command-specific input and output data.
+///
+/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request
+/// will be governed by a private watchdog timer that will cancel a queued job
+/// or kill a running job if the hardware operation does not complete before
+/// it times out.
+///
+/// \param callback The callback to execute when the GPE command completes,
+/// or NULL (0) to indicate no callback.
+///
+/// \param arg The parameter to the callback routine; ignored if the \a
+/// callback is NULL.
+///
+/// \param options Options to control request priority and callback context.
+///
+/// This routine has no way to know if the GpeRequest structure is currently
+/// in use, so this API should only be called on uninitialized or otherwise
+/// idle GpeRequest structures.
+///
+/// \retval 0 Success
+///
+/// \retval -ASYNC_INVALID_OBJECT_GPE_REQUEST The \a request was NULL (0) 
+/// or the \a queue was NULL (0) or not a GpeQueue.
+///
+/// \retval IPC_RC_INVALID_FUNC_ID The func_id has an invalid target id
+/// for the specified GPE queue.
+///
+/// See async_request_create() for other errors that may be returned by this
+/// call.
+
+int
+gpe_request_create(GpeRequest *request,
+                   GpeQueue *queue,
+                   ipc_func_enum_t func_id,
+                   void* cmd_data,
+                   SsxInterval timeout,
+                   AsyncRequestCallback callback,
+                   void *arg,
+                   int options)
+{
+    AsyncQueue  *async_queue = (AsyncQueue *)queue;
+    uint32_t    targeted_func_id;
+    int         rc;
+
+    if (SSX_ERROR_CHECK_API) {
+        SSX_ERROR_IF(!(async_queue->engine & ASYNC_ENGINE_GPE),
+                     ASYNC_INVALID_OBJECT_GPE_REQUEST);
+    }
+
+    //initialize the base async request
+    rc = async_request_create(&(request->request),
+                              async_queue,
+                              gpe_run_method,
+                              gpe_error_method,
+                              timeout,
+                              callback,
+                              arg,
+                              options);
+    if(!rc)
+    {
+
+        //If this is a multi-target function ID we need to set the target id.
+        if(IPC_FUNCID_IS_MT(func_id))
+        {
+            //This macro will set the target to an invalid target id if this
+            //function id is not a multi-target function ID and this condition
+            //will be caught when we check that the target id for the request
+            //matches the target id for the queue.
+            targeted_func_id = IPC_SET_MT_TARGET(func_id, queue->ipc_target_id);
+        }
+        else
+        {
+            //single target function IDs already have a target
+            targeted_func_id = func_id;
+        }
+    
+        //check that target id of the command matches the target id
+        //of the queue.
+        if (IPC_GET_TARGET_ID(targeted_func_id) != queue->ipc_target_id)
+        {
+            rc = IPC_RC_INVALID_FUNC_ID;
+        }
+        else
+        {
+            //initialize data that will be used when sending the command
+            request->cmd_data = cmd_data;
+            request->targeted_func_id = targeted_func_id;
+        }
+    }
+
+    return rc;
+}
+
+
+// Start a GpeRequest on a GPE
+//
+// \param async_request A GpeRequest upcast to an AsyncRequest.
+//
+// This is an internal API.
+//
+// This routine sends an async_request to a GPE.
+//
+ 
+int
+gpe_run_method(AsyncRequest *async_request)
+{
+    GpeQueue        *queue = (GpeQueue*)(async_request->queue);
+    GpeRequest      *request = (GpeRequest*)async_request;
+    ipc_async_cmd_t *ipc_cmd = queue->ipc_cmd;
+    int rc;
+
+    //Initialize the IPC command message
+    ipc_init_msg(&ipc_cmd->cmd,
+                 request->targeted_func_id,
+                 gpe_async_handler,
+                 queue);
+    ipc_cmd->cmd_data = request->cmd_data;
+
+    //Send the IPC command
+    rc = ipc_send_cmd(&ipc_cmd->cmd);
+
+    //If there's an error in the send, collect ffdc and mark it as
+    //having failed.
+    if(rc)
+    {
+        gpe_error_method(async_request);
+        async_request->completion_state = ASYNC_REQUEST_STATE_FAILED;
+        rc = -ASYNC_REQUEST_COMPLETE;
+    }
+
+    return rc;
+}
+
+
+// GPE FFDC collection
+//
+// \param async_request A GpeRequest upcast to an AsyncRequest
+//
+// This is an internal API, called from the async base code when an async
+// request times out.
+//
+// GPE async error handling procedure:
+//
+// - Collect FFDC from the failing engine
+//
+// Currently all GPE errors are treated as recoverable
+
+
+int
+gpe_error_method(AsyncRequest *async_request)
+{
+    GpeQueue *queue = (GpeQueue*)(async_request->queue);
+    GpeRequest *request = (GpeRequest*)async_request;
+
+    // Collect data that could explain why a GPE command
+    // couldn't be sent or timed out on the response and save it
+    // in the ffdc fields
+    
+    //retrieve IPC data
+    request->ffdc.func_id = queue->ipc_cmd->cmd.func_id.word32;
+    request->ffdc.ipc_rc = queue->ipc_cmd->cmd.ipc_rc;
+    
+    //retrieve XIR data
+    request->ffdc.xir_dump_rc = 
+        occhw_xir_dump(queue->ipc_target_id, &request->ffdc.xir_dump);
+
+    return 0;
+}
+
+
+////////////////////////////////////////////////////////////////////////////
+// Initialization
+////////////////////////////////////////////////////////////////////////////
+
+void
+async_gpe_initialize(GpeQueue *queue,int engine)
+{
+    gpe_queue_create(queue, engine);
+}
diff --git a/src/ssx/pgp/pgp_async_ocb.c b/src/ssx/occhw/occhw_async_ocb.c
index b9ef4b8..1a0abef 100755..100644
--- a/src/ssx/pgp/pgp_async_ocb.c
+++ b/src/ssx/occhw/occhw_async_ocb.c
@@ -1,16 +1,38 @@
-// $Id: pgp_async_ocb.c,v 1.2 2014/02/03 01:30:34 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_ocb.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_async_ocb.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_async_ocb.c
+/// \file occhw_async_ocb.c
 /// \brief Async driver code for OCB
 
 #include "ssx.h"
-
+#include "occhw_async.h"
 
 ////////////////////////////////////////////////////////////////////////////
 // Global Data
@@ -54,10 +76,12 @@ OcbQueue G_ocb_write_queue[OCB_INDIRECT_CHANNELS];
 OCB_CQ_READ_BUFFER(G_ocb_read0_buffer, OCB_READ0_LENGTH);
 OCB_CQ_READ_BUFFER(G_ocb_read1_buffer, OCB_READ1_LENGTH);
 OCB_CQ_READ_BUFFER(G_ocb_read2_buffer, OCB_READ2_LENGTH);
+OCB_CQ_READ_BUFFER(G_ocb_read3_buffer, OCB_READ3_LENGTH);
 
 OCB_CQ_WRITE_BUFFER(G_ocb_write0_buffer, OCB_WRITE0_LENGTH);
 OCB_CQ_WRITE_BUFFER(G_ocb_write1_buffer, OCB_WRITE1_LENGTH);
 OCB_CQ_WRITE_BUFFER(G_ocb_write2_buffer, OCB_WRITE2_LENGTH);
+OCB_CQ_WRITE_BUFFER(G_ocb_write3_buffer, OCB_WRITE3_LENGTH);
 
 
 ////////////////////////////////////////////////////////////////////////////
@@ -72,14 +96,16 @@ OCB_CQ_WRITE_BUFFER(G_ocb_write2_buffer, OCB_WRITE2_LENGTH);
 static const SsxAddress G_ocb_ocbsxcsn[OCB_ENGINES] =
     {OCB_OCBSHCS0, OCB_OCBSLCS0, 
      OCB_OCBSHCS1, OCB_OCBSLCS1, 
-     OCB_OCBSHCS2, OCB_OCBSLCS2};
+     OCB_OCBSHCS2, OCB_OCBSLCS2,
+     OCB_OCBSHCS3, OCB_OCBSLCS3};
 
 /// OCB Stream Push/Pull Base Register addresses
 
 static const SsxAddress G_ocb_ocbsxbrn[OCB_ENGINES] =
     {OCB_OCBSHBR0, OCB_OCBSLBR0, 
      OCB_OCBSHBR1, OCB_OCBSLBR1,
-     OCB_OCBSHBR2, OCB_OCBSLBR2};
+     OCB_OCBSHBR2, OCB_OCBSLBR2,
+     OCB_OCBSHBR3, OCB_OCBSLBR3};
 
 
 /// OCB Stream Push/Pull Increment Register addresses
@@ -87,13 +113,14 @@ static const SsxAddress G_ocb_ocbsxbrn[OCB_ENGINES] =
 static const SsxAddress G_ocb_ocbsxin[OCB_ENGINES] =
     {OCB_OCBSHI0, OCB_OCBSLI0, 
      OCB_OCBSHI1, OCB_OCBSLI1,
-     OCB_OCBSHI2, OCB_OCBSLI2};
+     OCB_OCBSHI2, OCB_OCBSLI2,
+     OCB_OCBSHI3, OCB_OCBSLI3};
 
 
 /// OCB Stream Error Status; There is only one register per OCB channel
 
 const SsxAddress G_ocb_ocbsesn[OCB_ENGINES / 2] =
-    {OCB_OCBSES0, OCB_OCBSES1, OCB_OCBSES2};
+    {OCB_OCBSES0, OCB_OCBSES1, OCB_OCBSES2, OCB_OCBSES3};
 
 
 ////////////////////////////////////////////////////////////////////////////
@@ -123,6 +150,8 @@ static void
 ocb_ffdc(int channel)
 {
     OcbFfdc* ffdc;
+    ocb_ocbshcsn_t ocbshcsn;
+    ocb_ocbslcsn_t ocbslcsn;
 
     if (channel < 0) {
         ffdc = &(G_ocb_ffdc.bridge);
@@ -145,10 +174,12 @@ ocb_ffdc(int channel)
             ffdc->slbr.value = in32(OCB_OCBSLBRN(channel));
             ffdc->slcs.value = in32(OCB_OCBSLCSN(channel));
 
-            out32(OCB_OCBSHCSN(channel), 
-                  ffdc->shcs.value & ~OCB_OCBSHCSN_PUSH_ENABLE);
-            out32(OCB_OCBSLCSN(channel), 
-                  ffdc->slcs.value & ~OCB_OCBSLCSN_PULL_ENABLE);
+            ocbshcsn.value = ffdc->shcs.value;
+            ocbshcsn.fields.push_enable = 0;
+            out32(OCB_OCBSHCSN(channel), ocbshcsn.value);
+            ocbslcsn.value = ffdc->slcs.value;
+            ocbslcsn.fields.pull_enable = 0;
+            out32(OCB_OCBSLCSN(channel), ocbslcsn.value);
 
         }
 
@@ -540,12 +571,14 @@ ocb_request_create(OcbRequest *request,
     case ASYNC_ENGINE_OCB_PULL0:
     case ASYNC_ENGINE_OCB_PULL1:
     case ASYNC_ENGINE_OCB_PULL2:
+    case ASYNC_ENGINE_OCB_PULL3:
         run_method = ocb_write_method;
         break;
 
     case ASYNC_ENGINE_OCB_PUSH0:
     case ASYNC_ENGINE_OCB_PUSH1:
     case ASYNC_ENGINE_OCB_PUSH2:
+    case ASYNC_ENGINE_OCB_PUSH3:
         run_method = ocb_read_method;
         break;
     }
@@ -766,20 +799,25 @@ ocb_queue_create(OcbQueue *queue,
         // These are the read engines from OCC's perspective.
 
     case ASYNC_ENGINE_OCB_PUSH0:
-        queue->irq = PGP_IRQ_STRM0_PUSH;
+        queue->irq = OCCHW_IRQ_STRM0_PUSH;
         queue->engine = OCB_ENGINE_PUSH0;
         goto read_engine;
 
     case ASYNC_ENGINE_OCB_PUSH1:
-        queue->irq = PGP_IRQ_STRM1_PUSH;
+        queue->irq = OCCHW_IRQ_STRM1_PUSH;
         queue->engine = OCB_ENGINE_PUSH1;
         goto read_engine;
 
     case ASYNC_ENGINE_OCB_PUSH2:
-        queue->irq = PGP_IRQ_STRM2_PUSH;
+        queue->irq = OCCHW_IRQ_STRM2_PUSH;
         queue->engine = OCB_ENGINE_PUSH2;
         goto read_engine;
 
+    case ASYNC_ENGINE_OCB_PUSH3:
+        queue->irq = OCCHW_IRQ_STRM3_PUSH;
+        queue->engine = OCB_ENGINE_PUSH3;
+        goto read_engine;
+
     read_engine:
         align_mask = CACHE_LINE_SIZE - 1;
         async_queue_create(async_queue, engine);
@@ -789,20 +827,25 @@ ocb_queue_create(OcbQueue *queue,
         // These are the write engines from OCC's perspective.
 
     case ASYNC_ENGINE_OCB_PULL0:
-        queue->irq = PGP_IRQ_STRM0_PULL;
+        queue->irq = OCCHW_IRQ_STRM0_PULL;
         queue->engine = OCB_ENGINE_PULL0;
         goto write_engine;
 
     case ASYNC_ENGINE_OCB_PULL1:
-        queue->irq = PGP_IRQ_STRM1_PULL;
+        queue->irq = OCCHW_IRQ_STRM1_PULL;
         queue->engine = OCB_ENGINE_PULL1;
         goto write_engine;
 
     case ASYNC_ENGINE_OCB_PULL2:
-        queue->irq = PGP_IRQ_STRM2_PULL;
+        queue->irq = OCCHW_IRQ_STRM2_PULL;
         queue->engine = OCB_ENGINE_PULL2;
         goto write_engine;
 
+    case ASYNC_ENGINE_OCB_PULL3:
+        queue->irq = OCCHW_IRQ_STRM3_PULL;
+        queue->engine = OCB_ENGINE_PULL3;
+        goto write_engine;
+
     write_engine:
         align_mask = 8 - 1;
         async_queue_create(async_queue, engine);
@@ -898,15 +941,18 @@ void
 ocb_error_handler_full(void *arg, SsxIrqId irq, int priority)
 {
     ocb_occlfir_t fir;
+    ocb_occlfir_t fir_temp;
     int channel;
     AsyncQueue* queue;
 
     ssx_irq_status_clear(irq);
 
     getscom(OCB_OCCLFIR, &(fir.value));
-    
+  
+    fir_temp.value = 0;
+    fir_temp.fields.ocb_idc0_error = 1;  
     for (channel = 0; channel < OCB_INDIRECT_CHANNELS; channel++) {
-        if (fir.value & (OCB_OCCLFIR_OCB_IDC0_ERROR >> channel)) {
+        if (fir.value & (fir_temp.value >> channel)) {
 
             queue = (AsyncQueue*)(&(G_ocb_read_queue[channel]));
             if (queue->state == ASYNC_QUEUE_STATE_RUNNING) {
diff --git a/src/ssx/pgp/pgp_async_pba.c b/src/ssx/occhw/occhw_async_pba.c
index 14b5619..3a03a17 100755..100644
--- a/src/ssx/pgp/pgp_async_pba.c
+++ b/src/ssx/occhw/occhw_async_pba.c
@@ -1,15 +1,38 @@
-// $Id: pgp_async_pba.c,v 1.2 2014/02/03 01:30:34 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_pba.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_async_pba.c $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_async_pba.c
+/// \file occhw_async_pba.c
 /// \brief Async device drivers for the PBA block copy engines and PBAX
 
 #include "ssx.h"
+#include "occhw_async.h"
 
 ////////////////////////////////////////////////////////////////////////////
 // Global Data
@@ -958,12 +981,12 @@ pbax_queue_create(PbaxQueue *queue,
     switch (engine) {
 
     case ASYNC_ENGINE_PBAX_PUSH0:
-        queue->irq = PGP_IRQ_PBA_OCC_PUSH0;
+        queue->irq = OCCHW_IRQ_PBAX_OCC_PUSH0;
         queue->engine = PBAX_ENGINE_PUSH0;
         break;
 
     case ASYNC_ENGINE_PBAX_PUSH1:
-        queue->irq = PGP_IRQ_PBA_OCC_PUSH1;
+        queue->irq = OCCHW_IRQ_PBAX_OCC_PUSH1;
         queue->engine = PBAX_ENGINE_PUSH1;
         break;
 
diff --git a/src/ssx/pgp/pgp_cache.S b/src/ssx/occhw/occhw_cache.S
index 4208f59..052021b 100755..100644
--- a/src/ssx/pgp/pgp_cache.S
+++ b/src/ssx/occhw/occhw_cache.S
@@ -1,13 +1,35 @@
-// $Id: pgp_cache.S,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_cache.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_cache.S $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
         
-/// \file pgp_cache.S
-/// \brief Cache-management specific to PGP
+/// \file occhw_cache.S
+/// \brief Cache-management specific to OCCHW
 
 #include "ssx.h"
 
@@ -23,12 +45,12 @@
 /// valid before flushing the entry.
 ///
 /// This algorithm works by filling the cache with 0s to displace any dirty
-/// lines.  Then the cache is invalidated.  In PgP the first 16 KB of the
+/// lines.  Then the cache is invalidated.  In OCCHW the first 16 KB of the
 /// 0x80000000 address range are used as the zero-fill range.  This memory is
 /// not mapped on the OCI so these lines must never escape the D-cache.
 ///
 /// Note: Our Simics model includes this 16K memory area since Simics does not
-/// default to having a cache.  Since we run PgP with the MMU enabled and we
+/// default to having a cache.  Since we run OCCHW with the MMU enabled and we
 /// don't MMU-map this area, memory addressing bugs should not be able to slip
 /// through. 
 #ifdef DOXYGEN_ONLY
@@ -57,7 +79,7 @@ dcache_flush_all:
         ## DCBZ to work.
 
         mfdccr  %r11
-        _liwa   %r3, PGP_FLUSH_ZERO_DCCR
+        _liwa   %r3, OCCHW_FLUSH_ZERO_DCCR
         or      %r3, %r3, %r11
         mtdccr  %r3
         isync
@@ -66,7 +88,7 @@ dcache_flush_all:
 
         li      %r3, DCACHE_LINES
         mtctr   %r3
-        _liwa   %r3, PGP_FLUSH_ZERO_ADDRESS
+        _liwa   %r3, OCCHW_FLUSH_ZERO_ADDRESS
 1:      
         dcbz    %r0, %r3
         addi    %r3, %r3, CACHE_LINE_SIZE
@@ -78,7 +100,7 @@ dcache_flush_all:
 
         li      %r3, DCACHE_LINES
         mtctr   %r3
-        _liwa   %r3, PGP_FLUSH_ZERO_ADDRESS
+        _liwa   %r3, OCCHW_FLUSH_ZERO_ADDRESS
 1:      
         dcbi    %r0, %r3
         addi    %r3, %r3, CACHE_LINE_SIZE
diff --git a/src/ssx/occhw/occhw_core.h b/src/ssx/occhw/occhw_core.h
new file mode 100644
index 0000000..b576e40
--- /dev/null
+++ b/src/ssx/occhw/occhw_core.h
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_core.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_CORE_H__
+#define __OCCHW_CORE_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_core.h
+/// \brief processor core units header.  Local and mechanically generated macros.
+
+//#include "pc_register_addresses.h"
+//#include "pc_firmware_registers.h"
+//#include "sensors_register_addresses.h"
+//#include "sensors_firmware_registers.h"
+
+#endif  /* __OCCHW_CORE_H__ */
diff --git a/src/ssx/pgp/pgp_id.c b/src/ssx/occhw/occhw_id.c
index 0b4d4d7..ab6f5bc 100644
--- a/src/ssx/pgp/pgp_id.c
+++ b/src/ssx/occhw/occhw_id.c
@@ -1,16 +1,38 @@
-// $Id: pgp_id.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_id.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_id.c $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_id.h
-/// \brief PgP chip and EC-level identification + chip configuration
+/// \file occhw_id.h
+/// \brief processor chip and EC-level identification + chip configuration
 
 #include "ssx.h"
-#include "pgp_config.h"
+#include "chip_config.h"
 
 
 // Note: These cached variables are all declared as 64 bits, noncacheable so
@@ -23,7 +45,7 @@ uint64_t G_cfam_chip_type SECTION_ATTRIBUTE(".noncacheable") = 0;
 uint64_t G_cfam_ec_level SECTION_ATTRIBUTE(".noncacheable") = 0;
 
 void
-_pgp_get_ids(void)
+_occhw_get_ids(void)
 {
     tpc_gp0_t gp0;
     tpc_device_id_t deviceId;
@@ -91,7 +113,7 @@ uint64_t G_core_configuration SECTION_ATTRIBUTE(".noncacheable") = 0;
 /// pending Simics support for the base pervasive functionality
 
 void
-_pgp_get_chip_configuration(void)
+_occhw_get_chip_configuration(void)
 {
     if (SIMICS_ENVIRONMENT) {
 
@@ -107,14 +129,14 @@ _pgp_get_chip_configuration(void)
         int rc;
     
         rc = getscom(0x000f0008, &select); /* TP CHIPLET SELECT */
-        if (rc) SSX_PANIC(PGP_ID_SCOM_ERROR_SELECT);
-        if (select != 0) SSX_PANIC(PGP_ID_SELECT_ERROR);
+        if (rc) SSX_PANIC(OCCHW_ID_SCOM_ERROR_SELECT);
+        if (select != 0) SSX_PANIC(OCCHW_ID_SELECT_ERROR);
     
         rc = getscom(MC_ADDRESS(0x000f0012, 
                                 MC_GROUP_EX_CORE, 
                                 PCB_MULTICAST_SELECT), 
                      &configuration);
-        if (rc) SSX_PANIC(PGP_ID_SCOM_ERROR_CONFIG);
+        if (rc) SSX_PANIC(OCCHW_ID_SCOM_ERROR_CONFIG);
     
         G_chip_configuration = (configuration << 16) & 0xffff000000000000ull;
     }
diff --git a/src/ssx/pgp/pgp_id.h b/src/ssx/occhw/occhw_id.h
index 2b0ecab..d591f6a 100644
--- a/src/ssx/pgp/pgp_id.h
+++ b/src/ssx/occhw/occhw_id.h
@@ -1,16 +1,38 @@
-#ifndef __PGP_ID_H__
-#define __PGP_ID_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_id.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_ID_H__
+#define __OCCHW_ID_H__
 
-// $Id: pgp_id.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_id.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_id.h
-/// \brief PgP chip and EC-level identification + chip configuration
+/// \file occhw_id.h
+/// \brief chip and EC-level identification + chip configuration
 ///
 /// During initialization the device identification SCOM registers are read
 /// and cached.
@@ -43,21 +65,20 @@
 
 // Error/Panic Codes
 
-#define PGP_ID_SCOM_ERROR_SELECT   0x00747401
-#define PGP_ID_SCOM_ERROR_CONFIG   0x00747402
-#define PGP_ID_SELECT_ERROR        0x00747403
+#define OCCHW_ID_SCOM_ERROR_SELECT   0x00747401
+#define OCCHW_ID_SCOM_ERROR_CONFIG   0x00747402
+#define OCCHW_ID_SELECT_ERROR        0x00747403
 
 
 #ifndef __ASSEMBLER__
 
 #include <stdint.h>
 #include "tpc_firmware_registers.h"
-#include "pgp_config.h"
 
 
-/// Get TPC device identification (internal API, called once from __pgp_setup().
+/// Get TPC device identification (internal API, called once from __occhw_setup().
 void
-_pgp_get_ids(void);
+_occhw_get_ids(void);
 
 /// Get the TPC Node Id
 uint8_t node_id(void);
@@ -68,13 +89,13 @@ uint8_t chip_id(void);
 /// Get the CFAM Chip Id
 /// 
 /// \returns A 32-bit value to be compared against the enumeration of known
-/// CFAM ids.  See \ref pgp_cfam_chip_ids.
+/// CFAM ids.  See \ref cfam_chip_ids.
 uint32_t cfam_id(void);
 
 /// Get the CFAM Chip Type
 /// 
 /// \returns An 8-bit value to be compared against the enumeration of known
-/// CFAM chip types.  See \ref pgp_cfam_chip_types.
+/// CFAM chip types.  See \ref cfam_chip_types.
 uint8_t cfam_chip_type(void);
 
 /// Get the CFAM Chip EC Level
@@ -85,9 +106,9 @@ uint8_t cfam_chip_type(void);
 uint8_t cfam_ec_level(void);
 
 
-/// Compute the chip configuration (internal API, called once from __pgp_setup().
+/// Compute the chip configuration (internal API, called once from __occhw_setup().
 void
-_pgp_get_chip_configuration(void);
+_occhw_get_chip_configuration(void);
 
 /// Get the core configuration
 ///
@@ -100,7 +121,7 @@ core_configuration(void);
 #endif // __ASSEMBLER__
 
 
-/// \defgroup pgp_cfam_chip_types PGP CFAM Chip Types (Including Centaur)
+/// \defgroup cfam_chip_types CFAM Chip Types (Including Centaur)
 ///
 /// The CFAM Chip Type is an 8-bit value that uniquely identfies a chip
 /// architecture.
@@ -114,7 +135,7 @@ core_configuration(void);
 /// @}
 
 
-/// \defgroup pgp_cfam_chip_ids PGP CFAM Chip Ids (Including Centaur)
+/// \defgroup cfam_chip_ids CFAM Chip Ids (Including Centaur)
 ///
 /// The CFAM Chip ID is a 32-bit value that uniquely identfies a chip and its
 /// EC level. 
@@ -180,4 +201,4 @@ typedef union {
 
 /// @}
 
-#endif // __PGP_ID_H__
+#endif // __OCCHW_ID_H__
diff --git a/src/ssx/pgp/pgp_init.c b/src/ssx/occhw/occhw_init.c
index 4e28014..f3383b4 100755..100644
--- a/src/ssx/pgp/pgp_init.c
+++ b/src/ssx/occhw/occhw_init.c
@@ -1,20 +1,44 @@
-// $Id: pgp_init.c,v 1.2 2014/03/14 16:34:34 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_init.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_init.c
-/// \brief SSX initialization for PgP
+/// \file occhw_init.c
+/// \brief SSX initialization for OCCHW
 ///
 /// The entry points in this routine are used during initialization.  This
 /// code space can be deallocated and reassigned after application
 /// initialization if required.
 
 #include "ssx.h"
-#include "pgp_vrm.h"
+#include "occhw_async.h"
+
+//#include "occhw_vrm.h"
 #include "simics_stdio.h"
 #include "string_stream.h"
 
@@ -24,7 +48,7 @@
 #endif
 
 // We need to make sure that the PLB arbiter is set up correctly to obtain
-// highest performance in the PgP environment, and that PLB error reporting is
+// highest performance in the OCCHW environment, and that PLB error reporting is
 // appropriate.
 
 // The PLB arbiter is configured to support fair arbitration of equal-priority
@@ -37,19 +61,22 @@
 static void
 plb_arbiter_setup()
 {
-    plb_pacr_t pacr;
+    //TODO: enable this once OCB support is present in simics
+#if 0
+    ocb_oacr_t oacr;
     ocb_ocichsw_t oo;
 
-    pacr.value = 0;
-    pacr.fields.ppm = 1;        /* Fair arbitration */
-    pacr.fields.hbu = 1;        /* High bus utilization */
-    pacr.fields.rdp = 1;        /* 2-deep read pipelining */
-    pacr.fields.wrp = 1;        /* 2-deep write pipelining */
-    mtdcr(PLB_PACR, pacr.value);
+    oacr.value = 0;
+    oacr.fields.oci_priority_mode = 1;          /* Fair arbitration */
+    oacr.fields.oci_hi_bus_mode = 1;            /* High bus utilization */
+    oacr.fields.oci_read_pipeline_control = 1;  /* 2-deep read pipelining */
+    oacr.fields.oci_write_pipeline_control = 1; /* 2-deep write pipelining */
+    mtdcr(OCB_OACR, oacr.value);
 
     oo.value = in32(OCB_OCICHSW);
     oo.fields.plbarb_lockerr = 1;
     out32(OCB_OCICHSW, oo.value);
+#endif
 }
 
 
@@ -162,7 +189,7 @@ static const MmuRegion mmu_regions[] = {
      0, TLBLO_WR | TLBLO_I | TLBLO_G, 0} ,
 };
 
-/// PgP MMU setup
+/// OCCHW MMU setup
 ///
 /// Run down the mmu_regions[] array and map all regions with non-0 sizes.
 /// These are direct maps, setting the effective address to the physical
@@ -173,7 +200,7 @@ static const MmuRegion mmu_regions[] = {
 /// to access main memory from the OCC.
 
 static void
-pgp_mmu_setup()
+occhw_mmu_setup()
 {
     int i, regions;
 
@@ -272,39 +299,93 @@ io_setup()
     stderr = (FILE *)(&simics_stderr);
     ssxout = (FILE *)(&simics_stdout);
 
+    printf("Initialize the Simics stdio.\n");
+
 #endif // I/O Configuration
 }
 
-
-/// PgP environment initial setup.
+/// OCCHW environment initial setup.
 ///
-/// This is setup common to all PgP applications.  This setup takes place
+/// This is setup common to all OCCHW applications.  This setup takes place
 /// during boot, before main() is called.
 
 void
-__pgp_setup()
+__occhw_setup()
 {
-    // All OCB interrupts are masked.  The SSX/PPC405 Boot code masks PPC405
-    // PIT, FIT, and Watchdog interrupts.  All interrupts are also initially
-    // set up as noncritical, non-debugged, edge-triggered, active-high, and
-    // their status is cleared.  This clarifies IPL debugging as it eliminates
-    // spurious "asserted" interrupts until the firmware comes in and actually
-    // sets up the interrupt.
-
-    out32(OCB_OIMR0, 0xffffffff);  /* Masked */
-    out32(OCB_OIMR1, 0xffffffff);
-    out32(OCB_OITR0, 0xffffffff);  /* Edge */
-    out32(OCB_OITR1, 0xffffffff);
-    out32(OCB_OIEPR0, 0xffffffff); /* Active High */
-    out32(OCB_OIEPR1, 0xffffffff);
-    out32(OCB_OCIR0, 0);           /* Noncritical */
-    out32(OCB_OCIR1, 0);
-    out32(OCB_OISR0_AND, 0);       /* Clear Status */
-    out32(OCB_OISR1_AND, 0);
-    out32(OCB_OUDER0, 0);          /* No Unconditional Debug Event */
-    out32(OCB_OUDER1, 0);
-    out32(OCB_ODHER0, 0);          /* No Debug Halt Event */
-    out32(OCB_ODHER1, 0);
+    uint64_t oirrA;
+    uint64_t oirrB;
+    uint64_t oirrC;
+    uint64_t owned_actual;
+    uint64_t reverse_polarity;
+
+#if (APPCFG_OCC_INSTANCE_ID == OCCHW_IRQ_ROUTE_OWNER)
+    //If this instance is the owner of the interrupt routting registers
+    //then write the routing registers for all OCC interrupts.
+    //This instance must be the first instance to run within the OCC
+    //This will be done while all external interrupts are masked.
+    out32(OCB_OIMR0_OR, 0xffffffff);
+    out32(OCB_OIMR1_OR, 0xffffffff);
+    out32(OCB_OIRR0A, (uint32_t)(g_ext_irqs_routeA >> 32));
+    out32(OCB_OIRR1A, (uint32_t)g_ext_irqs_routeA);
+    out32(OCB_OIRR0B, (uint32_t)(g_ext_irqs_routeB >> 32));
+    out32(OCB_OIRR1B, (uint32_t)g_ext_irqs_routeB);
+    out32(OCB_OIRR0C, (uint32_t)(g_ext_irqs_routeC >> 32));
+    out32(OCB_OIRR1C, (uint32_t)g_ext_irqs_routeC);
+
+    //Note: all interrupts are left in the masked state at this point
+#endif
+
+    //Determine from the routing registers which irqs are owned by this instance
+    //NOTE: If a bit is not set in the routeA register, it is not owned by a GPE
+
+    oirrA = ((uint64_t)in32(OCB_OIRR0A)) << 32;
+    oirrA |= in32(OCB_OIRR1A);
+    oirrB = ((uint64_t)in32(OCB_OIRR0B)) << 32;
+    oirrB |= in32(OCB_OIRR1B);
+    oirrC = ((uint64_t)in32(OCB_OIRR0C)) << 32;
+    oirrC |= in32(OCB_OIRR1C);
+
+    //All interrupts owned by the 405 will not have a bit set in routeA
+    owned_actual = ~oirrA;
+
+    //Panic if we don't own the irqs we were expecting
+    //NOTE: we don't panic if we are given more IRQ's than expected
+    if((owned_actual & g_ext_irqs_owned) != g_ext_irqs_owned)
+    {
+        //IRQ's were not routed to us correctly.
+        SSX_PANIC(OCCHW_IRQ_ROUTING_ERROR);
+    }
+
+    //Mask all external interrupts owned by this instance
+    //(even the ones given to us that we weren't expecting)
+    out32(OCB_OIMR0_OR, (uint32_t)(owned_actual >> 32));
+    out32(OCB_OIMR1_OR, (uint32_t)owned_actual);
+
+    //Set the interrupt type for all interrupts owned by this instance
+    out32(OCB_OITR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32));
+    out32(OCB_OITR1_CLR, (uint32_t)g_ext_irqs_owned);
+    out32(OCB_OITR0_OR, (uint32_t)(g_ext_irqs_type >> 32));
+    out32(OCB_OITR1_OR, (uint32_t)g_ext_irqs_type);
+
+    //Set the interrupt polarity for all interrupts owned by this instance
+    out32(OCB_OIEPR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32));
+    out32(OCB_OIEPR1_CLR, (uint32_t)g_ext_irqs_owned);
+    out32(OCB_OIEPR0_OR, (uint32_t)(g_ext_irqs_polarity >> 32));
+    out32(OCB_OIEPR1_OR, (uint32_t)g_ext_irqs_polarity);
+
+    //clear the status of all external interrupts owned by this instance
+    out32(OCB_OISR0_CLR, ((uint32_t)(g_ext_irqs_owned >> 32)));
+    out32(OCB_OISR1_CLR, ((uint32_t)g_ext_irqs_owned));
+
+    //set the status for interrupts that have reverse polarity
+    reverse_polarity = ~g_ext_irqs_polarity & g_ext_irqs_owned;
+    out32(OCB_OISR0_OR, ((uint32_t)(reverse_polarity >> 32)));
+    out32(OCB_OISR1_OR, ((uint32_t)reverse_polarity));
+
+    //Unmask the interrupts owned by this instance that are to be enabled by default
+    out32(OCB_OIMR0_CLR, (uint32_t)(g_ext_irqs_enable >> 32));
+    out32(OCB_OIMR1_CLR, (uint32_t)g_ext_irqs_enable);
+
 
     // Setup requires SCOM, which requires a timeout. Therefore we need to set
     // up a default timebase frequency, which may be overridden during
@@ -319,9 +400,12 @@ __pgp_setup()
 
     io_setup();
 
+    // TODO: enable once chip id support is present
+#if 0
     // Cache the device identification and chip configuration
-    _pgp_get_ids();
-    _pgp_get_chip_configuration();
+    _occhw_get_ids();
+    _occhw_get_chip_configuration();
+#endif
 
     // Set up the PLB arbiter
 
@@ -331,10 +415,9 @@ __pgp_setup()
     // MMU is activated.
 
 #if PPC405_MMU_SUPPORT
-    pgp_mmu_setup();
+    occhw_mmu_setup();
 #endif
 
-    // The PgP Async drivers are initialized.
-
+    // The Async drivers are initialized.
     async_initialize();
 }
diff --git a/src/ssx/pgp/pgp_irq.h b/src/ssx/occhw/occhw_irq.h
index f45ed52..b5c25c0 100755..100644
--- a/src/ssx/pgp/pgp_irq.h
+++ b/src/ssx/occhw/occhw_irq.h
@@ -1,31 +1,53 @@
-#ifndef __PGP_IRQ_H__
-#define __PGP_IRQ_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_irq.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_IRQ_H__
+#define __OCCHW_IRQ_H__
 
-// $Id: pgp_irq.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_irq.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_irq.h
-/// \brief PPC405-PgP Interrupt handling for SSX
+/// \file occhw_irq.h
+/// \brief PPC405-OCCHW Interrupt handling for SSX
 ///
-/// The PgP interrupt controller supports a maximum of 64 interrupts, split
+/// The OCCHW interrupt controller supports a maximum of 64 interrupts, split
 /// into 2 x 32-bit non-cascaded interrupt controllers with simple OR
 /// combining of the interrupt signals.
 ///
-/// The PGP interrupt controller allows interrupt status to be set directly by
+/// The OCB interrupt controller allows interrupt status to be set directly by
 /// software, as well as providing a mode that causes an enabled pending
-/// interrupt to trigger an Unconditional Debug Event. The PGP interrupt
+/// interrupt to trigger an Unconditional Debug Event. The OCB interrupt
 /// controller contains a 'mask' register, unlike other 405 interrupt
-/// controllers that have an 'enable' register.  The PgP mask and status
-/// registers also have atomic AND/OR function so that it is never necessary
+/// controllers that have an 'enable' register.  The OCCHW mask and status
+/// registers also have atomic CLR/OR function so that it is never necessary
 /// to enter a critical section to enable/disable/clear interrupts and
 /// interrupt status.
 
-#include "pgp_common.h"
+#include "occhw_common.h"
 #include "ocb_register_addresses.h"
 
 #ifndef __ASSEMBLER__
@@ -36,7 +58,7 @@ UNLESS__PPC405_IRQ_CORE_C__(extern)
 inline void
 ssx_irq_enable(SsxIrqId irq)
 {
-    out32(OCB_OIMR_AND(irq), ~PGP_IRQ_MASK32(irq));
+    out32(OCCHW_OIMR_CLR(irq), OCCHW_IRQ_MASK32(irq));
 }
 
 
@@ -46,18 +68,18 @@ UNLESS__PPC405_IRQ_CORE_C__(extern)
 inline void
 ssx_irq_disable(SsxIrqId irq)
 {
-    out32(OCB_OIMR_OR(irq), PGP_IRQ_MASK32(irq));
+    out32(OCCHW_OIMR_OR(irq), OCCHW_IRQ_MASK32(irq));
 }
 
 
-/// Clear interrupt status with an AND mask.  Only meaningful for
+/// Clear interrupt status with an CLR mask.  Only meaningful for
 /// edge-triggered interrupts.
 
 UNLESS__PPC405_IRQ_CORE_C__(extern)
 inline void
 ssx_irq_status_clear(SsxIrqId irq)
 {
-    out32(OCB_OISR_AND(irq), ~PGP_IRQ_MASK32(irq));
+    out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq));
 }
 
 
@@ -67,7 +89,7 @@ UNLESS__PPC405_IRQ_CORE_C__(extern)
 inline int
 ssx_irq_status_get(SsxIrqId irq)
 {
-    return (in32(OCB_OISR(irq)) & PGP_IRQ_MASK32(irq)) != 0;
+    return (in32(OCCHW_OISR(irq)) & OCCHW_IRQ_MASK32(irq)) != 0;
 }
 
 
@@ -78,9 +100,9 @@ inline void
 ssx_irq_status_set(SsxIrqId irq, int value)
 {
     if (value) {
-        out32(OCB_OISR_OR(irq), PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OISR_OR(irq), OCCHW_IRQ_MASK32(irq));
     } else {
-        out32(OCB_OISR_AND(irq), ~PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq));
     }
 }
 
@@ -90,9 +112,9 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
 
 #endif  /* __ASSEMBLER__ */
 
-/// \page pgp_irq_macros PgP IRQ API Assembler Macros
+/// \page occhw_irq_macros OCCHW IRQ API Assembler Macros
 ///
-/// These macros encapsulate the SSX API for the PgP interrupt
+/// These macros encapsulate the SSX API for the OCCHW interrupt
 /// controller. These macros require 2 scratch registers in addition to the \c
 /// irq parameter register passed into the handler from SSX interrupt
 /// dispatch. These macros also modift CR0.
@@ -156,16 +178,15 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
         .endm
 
 
-        .macro  _pgp_irq_or_mask, rirq:req, rmask:req
+        .macro  _occhw_irq_or_mask, rirq:req, rmask:req
         .two_unique \rirq, \rmask
         lis     \rmask, 0x8000
         srw     \rmask, \rmask, \rirq
         .endm
 
-        .macro  _pgp_irq_and_mask, rirq:req, rmask:req
+        .macro  _occhw_irq_clr_mask, rirq:req, rmask:req
         .two_unique \rirq, \rmask
-        _pgp_irq_or_mask \rirq, \rmask
-        not     \rmask, \rmask
+        _occhw_irq_or_mask \rirq, \rmask
         .endm
 
 
@@ -174,12 +195,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
         
         andi.   \raddr, \rirq, 0x20
         clrlwi  \raddr, \rirq, 27
-        _pgp_irq_and_mask \raddr, \rmask
+        _occhw_irq_clr_mask \raddr, \rmask
         bne-    888f
-        _stwi   \rmask, \raddr, OCB_OIMR0_AND
+        _stwi   \rmask, \raddr, OCB_OIMR0_CLR
         b       999f
 888:    
-        _stwi   \rmask, \raddr, OCB_OIMR1_AND
+        _stwi   \rmask, \raddr, OCB_OIMR1_CLR
 999:            
         eieio
         .endm
@@ -190,7 +211,7 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
         
         andi.   \raddr, \rirq, 0x20
         clrlwi  \raddr, \rirq, 27
-        _pgp_irq_or_mask \raddr, \rmask
+        _occhw_irq_or_mask \raddr, \rmask
         bne-    888f
         _stwi   \rmask, \raddr, OCB_OIMR0_OR
         b       999f
@@ -206,12 +227,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
         
         andi.   \raddr, \rirq, 0x20
         clrlwi  \raddr, \rirq, 27
-        _pgp_irq_and_mask \raddr, \rmask
+        _occhw_irq_clr_mask \raddr, \rmask
         bne-    888f
-        _stwi   \rmask, \raddr, OCB_OISR0_AND
+        _stwi   \rmask, \raddr, OCB_OISR0_CLR
         b       999f
 888:
-        _stwi   \rmask, \raddr, OCB_OISR1_AND
+        _stwi   \rmask, \raddr, OCB_OISR1_CLR
 999:            
         eieio
         .endm
@@ -224,7 +245,7 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
         clrlwi  \raddr, \rirq, 27
         
         .if     \imm
-        _pgp_irq_or_mask \raddr, \rmask
+        _occhw_irq_or_mask \raddr, \rmask
         bne-    888f
         _stwi   \rmask, \raddr, OCB_OISR0_OR
         b       999f
@@ -233,12 +254,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
 
         .else
         
-        _pgp_irq_and_mask \raddr, \rmask
+        _occhw_irq_clr_mask \raddr, \rmask
         bne-    888f
-        _stwi   \rmask, \raddr, OCB_OISR0_AND
+        _stwi   \rmask, \raddr, OCB_OISR0_CLR
         b       999f
 888:
-        _stwi   \rmask, \raddr, OCB_OISR1_AND
+        _stwi   \rmask, \raddr, OCB_OISR1_CLR
         .endif
 
 999:    
@@ -249,4 +270,4 @@ ssx_irq_debug_set(SsxIrqId irq, int value);
 
 /// \endcond
 
-#endif /* __PGP_IRQ_H__ */
+#endif /* __OCCHW_IRQ_H__ */
diff --git a/src/ssx/pgp/pgp_irq_init.c b/src/ssx/occhw/occhw_irq_init.c
index 6719766..da10cda 100755..100644
--- a/src/ssx/pgp/pgp_irq_init.c
+++ b/src/ssx/occhw/occhw_irq_init.c
@@ -1,13 +1,35 @@
-// $Id: pgp_irq_init.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_irq_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_irq_init.c $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_irq_init.c
-/// \brief PGP IRQ initialization code for SSX
+/// \file occhw_irq_init.c
+/// \brief OCCHW IRQ initialization code for SSX
 ///
 ///  The entry points in this file are initialization rotines that could be
 ///  eliminated/deallocated by the application to free up storage if they are
@@ -39,10 +61,10 @@ ssx_irq_setup(SsxIrqId irq,
               int      trigger)
 {
     SsxMachineContext ctx;
-    uint32_t oitr, oeipr;
 
     if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(!PGP_IRQ_VALID(irq) ||
+        SSX_ERROR_IF(!OCCHW_IRQ_VALID(irq) ||
+                     !OCCHW_IRQ_OWNED(irq) ||
                      !((polarity == SSX_IRQ_POLARITY_ACTIVE_HIGH) ||
                        (polarity == SSX_IRQ_POLARITY_ACTIVE_LOW)) ||
                      !((trigger == SSX_IRQ_TRIGGER_LEVEL_SENSITIVE) ||
@@ -52,18 +74,16 @@ ssx_irq_setup(SsxIrqId irq,
 
     ssx_critical_section_enter(SSX_CRITICAL, &ctx);
 
-    oeipr = in32(OCB_OIEPR(irq));
     if (polarity == SSX_IRQ_POLARITY_ACTIVE_HIGH) {
-        out32(OCB_OIEPR(irq), oeipr | PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OIEPR_OR(irq), OCCHW_IRQ_MASK32(irq));
     } else {
-        out32(OCB_OIEPR(irq), oeipr & ~PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OIEPR_CLR(irq), OCCHW_IRQ_MASK32(irq));
     }
 
-    oitr = in32(OCB_OITR(irq));
     if (trigger == SSX_IRQ_TRIGGER_EDGE_SENSITIVE) {
-        out32(OCB_OITR(irq), oitr | PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OITR_OR(irq), OCCHW_IRQ_MASK32(irq));
     } else {
-        out32(OCB_OITR(irq), oitr & ~PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OITR_CLR(irq), OCCHW_IRQ_MASK32(irq));
     }
 
     ssx_critical_section_exit(&ctx);
@@ -92,10 +112,10 @@ ssx_irq_handler_set(SsxIrqId      irq,
                     int           priority)
 {
     SsxMachineContext ctx;
-    uint32_t ocir;
 
     if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(!PGP_IRQ_VALID(irq) ||
+        SSX_ERROR_IF(!OCCHW_IRQ_VALID(irq) ||
+                     !OCCHW_IRQ_OWNED(irq) ||
                      (handler == 0) ||
                      !((priority == SSX_NONCRITICAL) ||
                        (priority == SSX_CRITICAL)),
@@ -104,11 +124,15 @@ ssx_irq_handler_set(SsxIrqId      irq,
 
     ssx_critical_section_enter(SSX_CRITICAL, &ctx);
 
-    ocir = in32(OCB_OCIR(irq));
+    //Regardless of priority, OIRRA & OIRRB will be cleared
+    out32(OCCHW_OIRRA_CLR(irq), OCCHW_IRQ_MASK32(irq));
+    out32(OCCHW_OIRRB_CLR(irq), OCCHW_IRQ_MASK32(irq));
+
+    //Critical priority needs a 1 in OIRRC
     if (priority == SSX_CRITICAL) {
-        out32(OCB_OCIR(irq), ocir | PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OIRRC_OR(irq), OCCHW_IRQ_MASK32(irq));
     } else {
-        out32(OCB_OCIR(irq), ocir & ~PGP_IRQ_MASK32(irq));
+        out32(OCCHW_OIRRC_CLR(irq), OCCHW_IRQ_MASK32(irq));
     }
 
     __ppc405_irq_handlers[irq].handler = handler;
@@ -126,15 +150,16 @@ void
 ssx_irq_debug_set(SsxIrqId irq, int value)
 {
     SsxMachineContext ctx;
-    uint32_t ouder;
+    //uint32_t ouder;
 
     ssx_critical_section_enter(SSX_CRITICAL, &ctx);
 
-    ouder = in32(OCB_OUDER(irq));
+    //TODO: port this over to using the OIRR instead of the OUDER
+    //ouder = in32(OCCHW_OUDER(irq));
     if (value) {
-        out32(OCB_OUDER(irq), ouder | PGP_IRQ_MASK32(irq));
+        //out32(OCCHW_OUDER(irq), ouder | OCCHW_IRQ_MASK32(irq));
     } else {
-        out32(OCB_OUDER(irq), ouder & ~PGP_IRQ_MASK32(irq));
+        //out32(OCCHW_OUDER(irq), ouder & ~OCCHW_IRQ_MASK32(irq));
     }
 
     ssx_critical_section_exit(&ctx);
diff --git a/src/ssx/pgp/pgp_ocb.c b/src/ssx/occhw/occhw_ocb.c
index e39475e..237c333 100755..100644
--- a/src/ssx/pgp/pgp_ocb.c
+++ b/src/ssx/occhw/occhw_ocb.c
@@ -1,13 +1,35 @@
-// $Id: pgp_ocb.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_ocb.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_ocb.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_ocb.c
-/// \brief OCB-related drivers for PgP
+/// \file occhw_ocb.c
+/// \brief OCB-related drivers for OCCHW
 
 #include "ssx.h"
 
@@ -140,20 +162,20 @@ ocb_timer_setup(int timer,
         //       timer, auto_reload, timeout_ns,
         //       handler, arg, priority);
     
-        ssx_irq_disable(PGP_IRQ_OCC_TIMER0 + timer);
+        ssx_irq_disable(OCCHW_IRQ_OCC_TIMER0 + timer);
 
-        ssx_irq_setup(PGP_IRQ_OCC_TIMER0 + timer,
+        ssx_irq_setup(OCCHW_IRQ_OCC_TIMER0 + timer,
                   SSX_IRQ_POLARITY_ACTIVE_HIGH,
                   SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
 
-        ssx_irq_handler_set(PGP_IRQ_OCC_TIMER0 + timer,
+        ssx_irq_handler_set(OCCHW_IRQ_OCC_TIMER0 + timer,
                         handler,
                         arg,
                         priority);
 
         rc = ocb_timer_reset(timer, auto_reload, timeout_ns);
 
-        ssx_irq_enable(PGP_IRQ_OCC_TIMER0 + timer);
+        ssx_irq_enable(OCCHW_IRQ_OCC_TIMER0 + timer);
     }while(0);
 
     return rc;
@@ -181,7 +203,7 @@ ocb_core_interrupt()
 
     oo.value = 0;
     oo.fields.core_ext_intr = 1;
-    out32(OCB_OCCMISC_AND, ~oo.value);
+    out32(OCB_OCCMISC_CLR, oo.value);
     out32(OCB_OCCMISC_OR, oo.value);
 
     return 0;
@@ -227,7 +249,7 @@ ocb_linear_window_initialize(int channel, uint32_t base, int log_size)
 
     if (SSX_ERROR_CHECK_API) {
         SSX_ERROR_IF((channel < 0) || 
-                     (channel > 2) ||
+                     (channel > 3) ||
                      (log_size < OCB_LW_LOG_SIZE_MIN) || 
                      (log_size > OCB_LW_LOG_SIZE_MAX) ||
                      ((base & mask) != 0),
@@ -238,19 +260,17 @@ ocb_linear_window_initialize(int channel, uint32_t base, int log_size)
     mask = ~mask;
 
 
-    // Configure OCB Linear Write Control Register    
+    // Enable LW mode
     ocblwcrn.fields.linear_window_enable = 1;
-    // base 13:28 (16 bits) 
-    ocblwcrn.fields.linear_window_bar = (base >> 3) & 0xFFFF;
-    // mask 17:28 (12 bits)
+    // Select bits(12:28) of OCI addr for the LW bar
+    ocblwcrn.fields.linear_window_bar = (base >> 3) & 0x1FFFF;
     ocblwcrn.fields.linear_window_mask = (mask >> 3) & 0xFFF;
     out32(OCB_OCBLWCRN(channel), ocblwcrn.value);
 
-    // Configure OCB Linear Window Write Base Register
-    ocblwsbrn.fields.linear_window_region = 3;  // SRAM only
-    // \todo:  Are there constants for the OCI regions?
-        // base 2:9 (8 bits)
-    ocblwsbrn.fields.linear_window_base = (base >> 19) & 0xFF;
+    // Configure LW region for SRAM access
+    ocblwsbrn.fields.linear_window_region = 7;
+    // Select bits(5:11) of OCI addr for the LW base
+    ocblwsbrn.fields.linear_window_base = (base >> 20) & 0x7F;
     out32(OCB_OCBLWSBRN(channel), ocblwsbrn.value);
 
     return 0 ;
@@ -276,12 +296,12 @@ ocb_linear_window_disable(int channel)
  
     if (SSX_ERROR_CHECK_API) {
         SSX_ERROR_IF((channel < 0) || 
-                     (channel > 2),
+                     (channel > 3),
                      OCB_INVALID_ARGUMENT_LW_DISABLE);
     }
 
     ocblwcrn.value = in32(OCB_OCBLWCRN(channel));
-    // Configure OCB Linear Write Control Register    
+    // Disable LW mode   
     ocblwcrn.fields.linear_window_enable = 0;
     out32(OCB_OCBLWCRN(channel), ocblwcrn.value);
 
@@ -314,6 +334,9 @@ ocb_linear_window_disable(int channel)
 ///
 
 
+//NOTE: The OCBICR register seems to have gone away in P9 and we didn't ever
+//      call this function in P8 so I'm removing this function for now. (grm)
+#if 0
 int
 ocb_allow_untrusted_initialize(int channel, int allow_untrusted)
 {
@@ -333,3 +356,4 @@ ocb_allow_untrusted_initialize(int channel, int allow_untrusted)
 
     return 0 ;
 }
+#endif
diff --git a/src/ssx/occhw/occhw_ocb.h b/src/ssx/occhw/occhw_ocb.h
new file mode 100644
index 0000000..9a780b4
--- /dev/null
+++ b/src/ssx/occhw/occhw_ocb.h
@@ -0,0 +1,113 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_ocb.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_OCB_H__
+#define __OCCHW_OCB_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_ocb.h
+/// \brief OCB unit header.  Local and mechanically generated macros and APIs.
+
+#include "ssx.h"
+#include "ppc32.h"
+
+#include "occhw_common.h"
+#include "ocb_register_addresses.h"
+#include "ocb_firmware_registers.h"
+
+#include "ppc405_irq.h"
+
+#define OCB_TIMER0 0
+#define OCB_TIMER1 1
+
+#define OCB_TIMERS 2
+
+#define OCB_TIMER_ONE_SHOT    0
+#define OCB_TIMER_AUTO_RELOAD 1
+
+#define OCB_LW_LOG_SIZE_MIN 3
+#define OCB_LW_LOG_SIZE_MAX 15
+
+#define OCB_INVALID_ARGUMENT_TIMER         0x00622001
+#define OCB_INVALID_ARGUMENT_LW_INIT       0x00622002
+#define OCB_INVALID_ARGUMENT_LW_DISABLE    0x00622003
+#define OCB_INVALID_ARGUMENT_UNTRUST       0x00622004
+
+#ifndef __ASSEMBLER__
+
+int 
+ocb_timer_reset(int timer, 
+                int auto_reload,
+                int timeout_ns);
+
+#ifdef OCC
+int
+ocb_timer_setup(int timer, 
+                int auto_reload,
+                int timeout_ns,
+                SsxIrqHandler handler,
+                void *arg,
+                int priority) INIT_SECTION;
+#else
+int
+ocb_timer_setup(int timer,
+        int auto_reload,
+        int timeout_ns,
+        SsxIrqHandler handler,
+        void *arg,
+        int priority);
+#endif
+
+/// Clear OCB timer status based on the IRQ
+///
+/// This API can be called from OCB timer interrupt handlers, using the IRQ
+/// provided to the handler.  No error checks are provided.
+
+static inline void
+ocb_timer_status_clear(SsxIrqId irq)
+{
+    ocb_otrn_t otrn_reg;
+    otrn_reg.value = 0;
+    otrn_reg.fields.timeout = 1;
+    out32(OCB_OTRN(irq - OCCHW_IRQ_OCC_TIMER0), otrn_reg.value);
+}
+
+int
+ocb_linear_window_initialize(int channel, uint32_t base, int log_size);
+
+int
+ocb_linear_window_disable(int channel);
+
+int
+ocb_allow_untrusted_initialize(int channel, int allow_untrusted);
+    
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __OCCHW_OCB_H__ */
diff --git a/src/ssx/pgp/pgp_pba.c b/src/ssx/occhw/occhw_pba.c
index 0f5d2d9..4c21bb8 100755..100644
--- a/src/ssx/pgp/pgp_pba.c
+++ b/src/ssx/occhw/occhw_pba.c
@@ -1,18 +1,40 @@
-// $Id: pgp_pba.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pba.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_pba.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_pba.c
+/// \file occhw_pba.c
 /// \brief procedures for pba setup and operation.
 
 #include "ssx.h"
-#include "pgp_pba.h"
-#include "pgp_pmc.h"
-#include "pgp_common.h"
+#include "occhw_pba.h"
+#include "occhw_scom.h"
+#include "occhw_common.h"
 #include "polling.h"
 
 
diff --git a/src/ssx/pgp/pgp_pba.h b/src/ssx/occhw/occhw_pba.h
index 647c334..c962936 100755..100644
--- a/src/ssx/pgp/pgp_pba.h
+++ b/src/ssx/occhw/occhw_pba.h
@@ -1,15 +1,37 @@
-#ifndef __PGP_PBA_H__
-#define __PGP_PBA_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_pba.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_PBA_H__
+#define __OCCHW_PBA_H__
 
-// $Id: pgp_pba.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pba.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_pba.h
+/// \file occhw_pba.h
 /// \brief PBA unit header.  Local and mechanically generated macros.
 
 /// \todo Add Doxygen grouping to constant groups
@@ -355,4 +377,4 @@ pbax_clear_receive_error(void)
 
 #endif /* __ASSEMBLER__ */
 
-#endif  /* __PGP_PBA_H__ */
+#endif  /* __OCCHW_PBA_H__ */
diff --git a/src/ssx/pgp/pgp_pmc.c b/src/ssx/occhw/occhw_scom.c
index bf3673b..743d0dc 100755..100644
--- a/src/ssx/pgp/pgp_pmc.c
+++ b/src/ssx/occhw/occhw_scom.c
@@ -1,21 +1,39 @@
-// $Id: pgp_pmc.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pmc.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_scom.c $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_pmc.c
-/// \brief PgP procedures and support for PMC operations
+/// \file occhw_scom.c
+/// \brief procedures and support for scom operations
 ///
 /// <b> SCOM Operations </b>
 ///
-/// The PMC provides an indirect bridge from the OCI to the PIB/PCB.  OCC
-/// firmware therefore has the ability to do immediate putscom()/getscom()
-/// operations in addition to the capabilities provided by the PORE-GPE
-/// engines. In PgP, SCOM latency from OCC is expected to be in the range of
-/// 150 - 1000 ns.  The maximum latency of a PIB operation has a hard upper
+/// The maximum latency of a PIB operation has a hard upper
 /// bound derived from the hardware implementation.  The putscom()/getscom()
 /// drivers here take advantage of this upper bound and implement tight
 /// timeouts, enforced by polling the timebase while waiting for the SCOM
@@ -62,8 +80,8 @@
 /// \bug Implement and use a generic poll_with_timeout(f, arg, t)
 
 #include "ssx.h"
-#include "pgp_pmc.h"
-
+#include "occhw_scom.h"
+#include "occhw_shared_data.h"
 
 ////////////////////////////////////////////////////////////////////////////
 // SCOM
@@ -73,27 +91,28 @@
 // at least twice to guarantee that we always poll once after a timeout.
 
 static int 
-poll_scom(SsxInterval timeout, pmc_o2p_ctrl_status_reg_t *cs)
+poll_scom(SsxInterval timeout)
 {
     SsxTimebase start;
     int timed_out;
+    int rc;
 
     start = ssx_timebase_get();
     timed_out = 0;
     do {
-        cs->value = in32(PMC_O2P_CTRL_STATUS_REG);
-        if (!(cs->fields.o2p_ongoing)) {
+        rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); 
+        if (!rc) {
             break;
         }
         if (timed_out) {
-            return -SCOM_TIMEOUT_ERROR;
+            rc = -SCOM_TIMEOUT_ERROR;
+            break;
         }
         timed_out = 
             ((timeout != SSX_WAIT_FOREVER) &&
              ((ssx_timebase_get() - start) > timeout));
     } while (1);
-
-    return 0;
+    return rc;
 }
 
 
@@ -132,44 +151,65 @@ poll_scom(SsxInterval timeout, pmc_o2p_ctrl_status_reg_t *cs)
 int
 _getscom(uint32_t address, uint64_t *data, SsxInterval timeout)
 {
-    pmc_o2p_addr_reg_t addr;
-    pmc_o2p_ctrl_status_reg_t cs;
-    SsxMachineContext ctx;
-    Uint64 data64;
-    int rc;
-
-    ssx_critical_section_enter(SSX_CRITICAL, &ctx);
+    SsxMachineContext   ctx;
+    int                 rc;
+    occhw_scom_cmd_t    *scom_cmd = &OSD_PTR->scom_cmd;
+    occhw_scom_status_t scom_status;
+
+    do
+    {
+        if(address & OCCHW_SCOM_READ_MASK)
+        {
+            rc = -SCOM_INVALID_ADDRESS;
+            break;
+        }
 
-    // Check for a transaction already ongoing
+        ssx_critical_section_enter(SSX_CRITICAL, &ctx);
 
-    cs.value = in32(PMC_O2P_CTRL_STATUS_REG);
-    if (cs.fields.o2p_ongoing) {
-        ssx_critical_section_exit(&ctx);
-        return -SCOM_PROTOCOL_ERROR_GETSCOM_BUSY;
-    }
+        // Check for a transaction already ongoing
+        rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); 
+        if (rc) {
+            ssx_critical_section_exit(&ctx);
+            rc = -SCOM_PROTOCOL_ERROR_GETSCOM_BUSY;
+            break;
+        }
 
-    // Start the read.  The 'read' bit is forced into the address.  Writing
-    // the PMC_O2P_ADDR_REG starts the read.
+        // Setup the write.  The 'read' bit is set in the address.
+        scom_cmd->scom_status.status32 = OCCHW_SCOM_PENDING;
+        scom_cmd->scom_addr = address | OCCHW_SCOM_READ_MASK;
 
-    addr.value = address;
-    addr.fields.o2p_read_not_write = 1;
-    out32(PMC_O2P_ADDR_REG, addr.value);
+        // Notify the GPE (by raising an interrupt) that a request is pending
+        ssx_irq_status_set(OCCHW_IRQ_IPI_SCOM, 1);
 
-    // Polling and return.
+        // Poll until completed or timed out
+        rc = poll_scom(timeout);
 
-    rc = poll_scom(timeout, &cs);
+        // Extract the data and status out of the scom command block
+        *data = scom_cmd->scom_data;
+        scom_status.status32 = scom_cmd->scom_status.status32;
 
-    data64.word[0] = in32(PMC_O2P_RECV_DATA_HI_REG);
-    data64.word[1] = in32(PMC_O2P_RECV_DATA_LO_REG);
-    *data = data64.value;
+        ssx_critical_section_exit(&ctx);
 
-    ssx_critical_section_exit(&ctx);
+        if(!rc)
+        {
+            //check that the GPE updated the scom status.  Normally,
+            //the gpe won't clear the interrupt until it has updated
+            //the status field.  The exception is if the GPE gets
+            //reset.
+            if(scom_status.status32 == OCCHW_SCOM_PENDING)
+            {
+                rc = -SCOM_PROTOCOL_ERROR_GETSCOM_RST;
+            }
+            else
+            {
+                //The SIBRC field of the MSR is where we get the status for
+                //the last scom operation.
+                rc = scom_status.sibrc;
+            }
+        }
 
-    if (rc) {
-        return rc;
-    } else {
-        return cs.fields.o2p_scresp;
-    }
+    }while(0);
+    return rc;
 }
 
 
@@ -211,8 +251,8 @@ getscom(uint32_t address, uint64_t *data)
         *data = 0;
     } else {
 
-        printk("getscom(0x%08x, %p) : Failed with error %d\n",
-               address, data, rc);
+        //printk("getscom(0x%08x, %p) : Failed with error %d\n",
+        //       address, data, rc);
 
         if (rc > 0) {
             switch (rc) {
@@ -268,44 +308,62 @@ getscom(uint32_t address, uint64_t *data)
 int
 _putscom(uint32_t address, uint64_t data, SsxInterval timeout)
 {
-    pmc_o2p_addr_reg_t addr;
-    pmc_o2p_ctrl_status_reg_t cs;
-    SsxMachineContext ctx;
-    Uint64 data64;
-    int rc;
-
-    ssx_critical_section_enter(SSX_CRITICAL, &ctx);
-
-    // Check for a transaction already ongoing
-
-    cs.value = in32(PMC_O2P_CTRL_STATUS_REG);
-    if (cs.fields.o2p_ongoing) {
-        ssx_critical_section_exit(&ctx);
-        return -SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY;
-    }
+    SsxMachineContext   ctx;
+    int                 rc;
+    occhw_scom_cmd_t    *scom_cmd = &OSD_PTR->scom_cmd;
+    occhw_scom_status_t scom_status;
+
+    do
+    {
+        if(address & OCCHW_SCOM_READ_MASK)
+        {
+            rc = -SCOM_INVALID_ADDRESS;
+            break;
+        }
 
-    // Start the write.  The 'write' bit is cleared in the address. Here the
-    // PIB write starts when the PMC_O2P_SEND_DATA_LO_REG is written.
+        ssx_critical_section_enter(SSX_CRITICAL, &ctx);
 
-    addr.value = address;
-    addr.fields.o2p_read_not_write = 0;
-    out32(PMC_O2P_ADDR_REG, addr.value);
+        // Check for a transaction already ongoing
+        rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); 
+        if (rc) {
+            ssx_critical_section_exit(&ctx);
+            rc = -SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY;
+            break;
+        }
 
-    data64.value = data;
-    out32(PMC_O2P_SEND_DATA_HI_REG, data64.word[0]);
-    out32(PMC_O2P_SEND_DATA_LO_REG, data64.word[1]);
-    
-    // Poll and return.
+        // Setup the write.  The 'read' bit is cleared in the address.
+        scom_cmd->scom_status.status32 = OCCHW_SCOM_PENDING;
+        scom_cmd->scom_addr = address;
+        scom_cmd->scom_data = data;
 
-    rc = poll_scom(timeout, &cs);
+        // Notify the GPE (by raising an interrupt) that a request is pending
+        ssx_irq_status_set(OCCHW_IRQ_IPI_SCOM, 1);
 
-    ssx_critical_section_exit(&ctx);
+        // Poll until completed or timed out
+        rc = poll_scom(timeout);
+        scom_status.status32 = scom_cmd->scom_status.status32;
 
-    if (rc) {
-        return rc;
-    } else {
-        return cs.fields.o2p_scresp;
-    }
+        ssx_critical_section_exit(&ctx);
+        
+        if(!rc)
+        {
+            //check that the GPE updated the scom status.  Normally,
+            //the gpe won't clear the interrupt until it has updated
+            //the status field.  The exception is if the GPE gets
+            //reset.
+            if(scom_status.status32 == OCCHW_SCOM_PENDING)
+            {
+                rc = -SCOM_PROTOCOL_ERROR_PUTSCOM_RST;
+            }
+            else
+            {
+                //The SIBRC field of the MSR is where we get the status for
+                //the last scom operation.
+                rc = scom_status.sibrc;
+            }
+        }
+    }while(0);
+    return rc;
 }
 
 
@@ -343,8 +401,8 @@ putscom(uint32_t address, uint64_t data)
         return rc;
     }
 
-    printk("putscom(0x%08x, 0x%016llx) : Failed with error %d\n",
-           address, data, rc);
+    //printk("putscom(0x%08x, 0x%016llx) : Failed with error %d\n",
+    //       address, data, rc);
 
     if (rc > 0) {
         switch (rc) {
diff --git a/src/ssx/pgp/pgp_pmc.h b/src/ssx/occhw/occhw_scom.h
index 1b372db..847fa90 100755..100644
--- a/src/ssx/pgp/pgp_pmc.h
+++ b/src/ssx/occhw/occhw_scom.h
@@ -1,20 +1,42 @@
-#ifndef __PGP_PMC_H__
-#define __PGP_PMC_H__
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_scom.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_SCOM_H__
+#define __OCCHW_SCOM_H__
 
-// $Id: pgp_pmc.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pmc.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
 
-/// \file pgp_pmc.h
-/// \brief PgP procedures and support for PMC operations
+/// \file occhw_scom.h
+/// \brief procedures and support for SCOM operations
 
 #include "ssx.h"
 
-#include "pgp_common.h"
+#include "occhw_common.h"
 #include "pmc_register_addresses.h"
 #include "pmc_firmware_registers.h"
 
@@ -62,6 +84,9 @@ putscom(uint32_t address, uint64_t data);
 #define SCOM_PROTOCOL_ERROR_PUTSCOM      0x00726614
 #define SCOM_PROTOCOL_ERROR_GETSCOM_BUSY 0x00726615
 #define SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY 0x00726616
+#define SCOM_PROTOCOL_ERROR_PUTSCOM_RST  0x00726617
+#define SCOM_PROTOCOL_ERROR_GETSCOM_RST  0x00726618
+#define SCOM_INVALID_ADDRESS             0x00726619
 
 
 /// The default timeout for getscom()/putscom()
@@ -69,7 +94,7 @@ putscom(uint32_t address, uint64_t data);
 /// This timeout is enforced by the firmware to guarantee a timeout regardless
 /// of the hardware setup.  
 ///
-/// The expectation is that the PgP hardware will be set up to enforce a PCB
+/// The expectation is that the hardware will be set up to enforce a PCB
 /// timeout of 8K cycles, or 16.384us @ 500 MHz. A timeout only occurs if
 /// someone erroneously issues a SCOM for a chiplet that does not exist. If
 /// this happens, then all other SCOMS waiting for the timed-out SCOM to
@@ -102,4 +127,4 @@ putscom(uint32_t address, uint64_t data);
 #define SCOM_ERROR_LIMIT PCB_ERROR_CHIPLET_OFFLINE
 #endif
 
-#endif // __PGP_PMC_H__
+#endif // __OCCHW_SCOM_H__
diff --git a/src/ssx/occhw/occhw_sramctl.h b/src/ssx/occhw/occhw_sramctl.h
new file mode 100644
index 0000000..7f1b1e5
--- /dev/null
+++ b/src/ssx/occhw/occhw_sramctl.h
@@ -0,0 +1,40 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/occhw_sramctl.h $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __OCCHW_SRAMCTL_H__
+#define __OCCHW_SRAMCTL_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_sramctl.h
+/// \brief SRAMCTL unit header.  Local and mechanically generated macros.
+
+#include "sramctl_register_addresses.h"
+#include "sramctl_firmware_registers.h"
+
+#endif  /* __OCCHW_SRAMCTL_H__ */
diff --git a/src/ssx/occhw/ssx_port.h b/src/ssx/occhw/ssx_port.h
new file mode 100644
index 0000000..81a52aa
--- /dev/null
+++ b/src/ssx/occhw/ssx_port.h
@@ -0,0 +1,40 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/occhw/ssx_port.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SSX_PORT_H__
+#define __SSX_PORT_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_port.h
+/// \brief The top-level OCCHW environment header for SSX.
+
+#define HWMACRO_OCC
+
+#include "ppc405.h"
+
+#endif /* __SSX_PORT_H__ */
diff --git a/src/ssx/occhw/ssxocchwfiles.mk b/src/ssx/occhw/ssxocchwfiles.mk
new file mode 100644
index 0000000..3559ae7
--- /dev/null
+++ b/src/ssx/occhw/ssxocchwfiles.mk
@@ -0,0 +1,58 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/occhw/ssxocchwfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file ssxoccwhfiles.mk
+#
+#  @brief mk for including occwh object files
+#
+#  @page ChangeLogs Change Logs
+#  @section ssxoccwhfiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Object Files
+##########################################################################
+OCCHW-C-SOURCES = occhw_init.c occhw_irq_init.c occhw_scom.c occhw_ocb.c occhw_pba.c \
+	occhw_id.c occhw_centaur.c
+OCCHW-S-SOURCES = occhw_cache.S
+
+OCCHW-TIMER-C-SOURCES = 
+OCCHW-TIMER-S-SOURCES = 
+
+OCCHW-THREAD-C-SOURCES = 
+OCCHW-THREAD-S-SOURCES = 
+
+OCCHW-ASYNC-C-SOURCES = occhw_async.c occhw_async_ocb.c \
+	occhw_async_pba.c occhw_async_gpe.c
+OCCHW-ASYNC-S-SOURCES =
+
+OCCHW_OBJECTS += $(OCCHW-C-SOURCES:.c=.o) $(OCCHW-S-SOURCES:.S=.o)
+
diff --git a/src/ssx/pgp/Makefile b/src/ssx/pgp/Makefile
deleted file mode 100755
index 417a452..0000000
--- a/src/ssx/pgp/Makefile
+++ /dev/null
@@ -1,38 +0,0 @@
-# $Id: Makefile,v 1.2 2013/12/12 16:12:28 bcbrock Exp $
-
-# This Makefile compiles all of the SSX code required for the PgP port
-# of SSX.  See the "ssx.mk" file in this directory.
-
-include ssx.mk
-include ssxpgpfiles.mk
-
-
-ifeq "$(SSX_TIMER_SUPPORT)" "1"
-PGP_OBJECTS += ${PGP-TIMER-C-SOURCES:.c=.o} ${PGP-TIMER-S-SOURCES:.S=.o}
-endif
-
-ifeq "$(SSX_THREAD_SUPPORT)" "1"
-PGP_OBJECTS += ${PGP-THREAD-C-SOURCES:.c=.o} ${PGP-THREAD-S-SOURCES:.S=.o}
-endif
-
-ifeq "$(PGP_ASYNC_SUPPORT)" "1"
-PGP_OBJECTS += ${PGP-ASYNC-C-SOURCES:.c=.o} ${PGP-ASYNC-S-SOURCES:.S=.o}
-endif
-
-
-all: local
-	$(MAKE) -I ../pgp -C ../ssx
-	$(MAKE) -I ../pgp -C ../ppc405
-
-local: $(PGP_OBJECTS)
-
-
-.PHONY : clean
-clean:
-	rm -f *.o *.d *.d.* *.ps *.pdf
-	$(MAKE) -I ../pgp -C ../ssx    clean
-	$(MAKE) -I ../pgp -C ../ppc405 clean
-
-ifneq ($(MAKECMDGOALS),clean)
-include $(PGP_OBJECTS:.o=.d) 
-endif
diff --git a/src/ssx/pgp/linkssx.cmd b/src/ssx/pgp/linkssx.cmd
deleted file mode 100755
index 0556a03..0000000
--- a/src/ssx/pgp/linkssx.cmd
+++ /dev/null
@@ -1,499 +0,0 @@
-// $Id: linkssx.cmd,v 1.2 2014/03/14 16:33:45 bcbrock Exp $
-
-// This linker script creates SRAM images of SSX applications for PgP. This
-// script is processed through the C proprocessor to create
-// configuration-dependent images.
-//
-// All sections with different MMU protection properties are 1KB-aligned, even
-// when linked in real-addressing mode.
-//
-// NB: According to *info* manual for ld, it should not be necessary to specify
-// the '.' in the section commands, e.g., 
-//
-//     .data.startup . : { *(.data.startup) } > sram
-//
-// However without these the sections are not aligned properly, as the linker
-// seems to ignore the LC and move the section 'backwards' until it abuts
-// (aligned) with the previous one.
-//
-// Info on PPC binaries:
-//     http://devpit.org/wiki/Debugging_PowerPC_ELF_Binaries
-
-// Need to do this so that elf32-powerpc is not modified!
-#undef powerpc
-
-#ifndef INITIAL_STACK_SIZE
-#define INITIAL_STACK_SIZE 2000
-#endif
-
-OUTPUT_FORMAT(elf32-powerpc);
-
-//  Define the beginning of SRAM, the location of the PowerPC exception
-//  vectors (must be 64K-aligned) and the location of the boot branch. 
-
-//  512 KB SRAM at the top of the 32-bit address space
-
-#define origin            0xfff80000
-#define vectors           0xfff80000
-#define reset             0xffffffec
-#define sram_available    (reset - origin)
-#define sram_size         0x00080000
-
-// The SRAM controller aliases the SRAM at 8 x 128MB boundaries to support
-// real-mode memory attributes using DCCR, ICCR etc.  Noncacheable access is
-// the next-to-last 128MB PPC405 region. Write-though access is the
-// next-to-next-to-last 128MB PPC405 region
-
-#define noncacheable_offset 0x08000000
-#define noncacheable_origin (origin - 0x08000000)
-
-#define writethrough_offset 0x10000000
-#define writethrough_origin (origin - 0x10000000)
-
-//  Define SSX kernel text sections to be packed into nooks and crannies of
-//  the exception vector area.  An option is provided _not_ to pack, to help
-//  better judge the best way to pack. Note that any code eligible for packing
-//  is considered 'core' code that will be needed by the application at
-//  runtime.  Any header data is _always_ packed into .vectors_0000 however.
-//
-//  Note that in order to support MMU protection, we can't pack data along
-//  with the text.  All of the packed data sections are thus left empty.
-
-
-// .vectors_0000
-
-#define text_0000 \
-*(.vectors_0000)
-
-#define data_0000
-
-
-// .vectors_0100
-
-#define text_0100 \
-ppc405_core.o(.text) \
-ppc405_irq_core.o(.text)
-
-#define data_0100
-
-
-// .vectors_0c00
-
-#if SSX_TIMER_SUPPORT 
-#define text_0c00_conditional
-#else
-#define text_0c00_conditional
-#endif
-
-
-#define text_0c00 \
-text_0c00_conditional \
-ppc405_cache_core.o(.text)
-
-#define data_0c00
-
-
-// .vectors_0f00
-
-#if SSX_TIMER_SUPPORT 
-
-#if SSX_THREAD_SUPPORT 
-#define text_0f00_conditional \
-ssx_timer_init.o(.text) \
-ssx_timer_core.o(.text) \
-ssx_semaphore_core.o(.text)
-#endif  /* SSX_THREAD_SUPPORT */
-
-#if !SSX_THREAD_SUPPORT
-#define text_0f00_conditional \
-ssx_timer_init.o(.text) \
-ssx_timer_core.o(.text)
-#endif  /* !SSX_THREAD_SUPPORT */
-
-#else  /* SSX_TIMER_SUPPORT */
-
-#define text_0f00_conditional
-#endif  /* SSX_TIMER_SUPPORT */
-
-#define text_0f00 \
-text_0f00_conditional
-
-#define data_0f00
-
-// .vectors_2000
-
-#if SSX_THREAD_SUPPORT
-#define thread_text \
-ssx_thread_init.o(.text) \
-ssx_thread_core.o(.text) \
-ppc405_irq_init.o(.text) \
-ppc405_thread_init.o(.text) \
-ssx_semaphore_init.o(.text)
-#else
-#define thread_text
-#endif
-
-#if PPC405_MMU_SUPPORT
-#define mmu_text \
-ppc405_mmu.o(.text)\
-ppc405_mmu_asm.o(.text)
-#else
-#define mmu_text
-#endif
-
-#define text_2000 \
-pgp_irq_init.o(.text) \
-ppc405_cache_init.o(.text) \
-ppc405_breakpoint.o(.text) \
-pgp_cache.o(.text) \
-ssx_stack_init.o(.text) \
-thread_text \
-mmu_text \
-pgp_async.o(.text) \
-pgp_async_pore.o(.text) \
-pgp_async_ocb.o(.text) \
-pgp_async_pba.o(.text) \
-pgp_pmc.o(.text) \
-pgp_ocb.o(.text) \
-pgp_pba.o(.text) \
-pgp_id.o(.text) \
-pgp_centaur.o(.text) \
-ppc405_lib_core.o(.text) \
-ssx_core.o(.text) \
-
-#define data_2000
-
-// .vectors_0000 is always packed with header information
-
-#define pack_0000 text_0000 data_0000
-#define nopack_0000
-
-#ifndef NO_PACK_SSX
-
-#define pack_0100 text_0100 data_0100
-#define nopack_0100
-
-#define pack_0c00 text_0c00 data_0c00
-#define nopack_0c00
-
-#define pack_0f00 text_0f00 data_0f00
-#define nopack_0f00
-
-#define pack_2000 text_2000 data_2000
-#define nopack_2000
-
-#else
-
-#define pack_0100
-#define nopack_0100 text_0100 data_0100
-
-#define pack_0c00
-#define nopack_0c00 text_0c00 data_0c00
-
-#define pack_0f00
-#define nopack_0f00 text_0f00 data_0f00
-
-#define pack_2000
-#define nopack_2000 text_2000 data_2000
-
-#endif
-
-#define init_text \
-ssx_init.o(.text) \
-ppc405_boot.o(.text) \
-ppc405_init.o(.text) \
-pgp_init.o(.text)       
-
-// Define memory areas.
-
-MEMORY
-{
- sram         : ORIGIN = origin, LENGTH = sram_available
- noncacheable : ORIGIN = noncacheable_origin, LENGTH = sram_available
- writethrough : ORIGIN = writethrough_origin, LENGTH = sram_available
- boot         : ORIGIN = reset,  LENGTH = 20
-}
-
-// NB: The code that sets up the MMU assumes that the linker script provides a
-// standard set of symbols that define the base address and size of each
-// expected section. Any section with a non-0 size will be mapped in the MMU
-// using protection attributes appropriate for the section.  All sections
-// requiring different MMU attributes must be 1KB-aligned.
-
-SECTIONS
-{       
-    . = origin;
-    . = vectors;
-
-    _MEMORY_ORIGIN = .;
-    _MEMORY_SIZE = sram_size;
-    
-    ////////////////////////////////
-    // Text0 
-    ////////////////////////////////
-
-    // Low-memory kernel code and any other code that would benefit from being
-    // resident in lower-latency SRAM
-
-    _TEXT0_SECTION_BASE = .;
-    _PPC405_VECTORS_BASE = .;
-    
-    .exceptions . : {
-         ___vectors = .;
-         ppc405_exceptions.o(.vectors_0000)
-         pack_0000
-         . = ___vectors + 0x0100;
-         ppc405_exceptions.o(.vectors_0100)
-         pack_0100
-         . = ___vectors + 0x0c00;
-         ppc405_exceptions.o(.vectors_0c00)
-         pack_0c00
-         . = ___vectors + 0x0f00;
-         ppc405_exceptions.o(.vectors_0f00)
-         pack_0f00
-         . = ___vectors + 0x2000;
-         ppc405_exceptions.o(.vectors_2000)
-         pack_2000
-    } > sram
-
-    // If we're not packing, then place 'core' code immediately after the
-    // exception vectors.
-    
-   .nopack . : { nopack_0000 nopack_0100 nopack_0c00 nopack_0f00 nopack_2000 } > sram
-
-    . = ALIGN(1024);
-    _TEXT0_SECTION_SIZE = . - _TEXT0_SECTION_BASE;
-
-    ////////////////////////////////
-    // Noncacheable and Write-through Data
-    ////////////////////////////////
-
-    // Non-cacheable and write-through data is placed in low memory to
-    // improve latency.  PORE-private text and data is also placed here. PORE
-    // text and data are segregated to enable relocated PORE disassembly of
-    //.text.pore. PORE text is read-only to OCC, however PORE data is writable
-    // by OCC to allow shared data structures (e.g., PTS).
-
-    // When running without the MMU we need to carefully arrange things such
-    // that the noncacheable and writethrough data is linked at the correct 
-    // aliased VMA while remaining loaded in contiguous LMA addresses.
-
-#if PPC405_MMU_SUPPORT
-
-#define ALIASED_SECTION(s) s . : {*(s)} > sram
-
-#else
-
-#define ALIASED_SECTION(s) \
-	_LMA = . + _lma_offset; \
-	s . : AT (_LMA) {*(s)}
-    
-#endif
-
-#if !PPC405_MMU_SUPPORT
-    . = . - noncacheable_offset;
-    _lma_offset = noncacheable_offset;
-#endif
-
-    _NONCACHEABLE_RO_SECTION_BASE = .;
-
-    ALIASED_SECTION(.noncacheable_ro)
-    ALIASED_SECTION(.text.pore)
-
-    . = ALIGN(1024);
-    _NONCACHEABLE_RO_SECTION_SIZE = . - _NONCACHEABLE_RO_SECTION_BASE;
-    
-
-    _NONCACHEABLE_SECTION_BASE = .;   
-
-    ALIASED_SECTION(.noncacheable)
-    ALIASED_SECTION(.data.pore)
-
-    . = ALIGN(1024);
-    _NONCACHEABLE_SECTION_SIZE = . - _NONCACHEABLE_SECTION_BASE;
-
-
-#if !PPC405_MMU_SUPPORT
-    . = . + noncacheable_offset - writethrough_offset;
-    _lma_offset = writethrough_offset;
-#endif
-
-
-    _WRITETHROUGH_SECTION_BASE = .;   
-
-    ALIASED_SECTION(.writethrough)
-
-    . = ALIGN(1024);
-    _WRITETHROUGH_SECTION_SIZE = . - _WRITETHROUGH_SECTION_BASE;
-
-#if !PPC405_MMU_SUPPORT
-    . = . + writethrough_offset;
-#endif
-
-
-    ////////////////////////////////
-    // Read-only Data
-    ////////////////////////////////
-
-    // Accesses of read-only data may or may not benefit from being in fast
-    // SRAM - we'll give it the benefit of the doubt.
-
-    _RODATA_SECTION_BASE = .;
-
-    // SDA2 constant sections .sdata2 and .sbss2 must be adjacent to each
-    // other.  Our SDATA sections are small so we'll use strictly positive
-    // offsets. 
-
-    _SDA2_BASE_ = .;
-   .sdata2 . : { *(.sdata2) } > sram
-   .sbss2  . : { *(.sbss2) } > sram
-
-   // The .rodata.vclcommand section contains read-only VclCommandRecord for
-   // the benefit of the vcl_console() command interpreter.
-   
-   _VCL_COMMAND_SECTION_BASE = .;
-   .rodata.vclcommand . : { *(.rodata.vclcommand) } > sram
-   _VCL_COMMAND_SECTION_SIZE = . - _VCL_COMMAND_SECTION_BASE;
-
-   // The .rodata.vclthread section contains read-only VclThreadRecord for the 
-   // benefit of the thread command.
-   
-   _VCL_THREAD_SECTION_BASE = .;
-   .rodata.vclthread . : { *(.rodata.vclthread) } > sram
-   _VCL_THREAD_SECTION_SIZE = . - _VCL_THREAD_SECTION_BASE;
-
-   // The .rodata.vclpackage section contains read-only char* pointers for the 
-   // benefit of the package command.
-   
-   _VCL_PACKAGE_SECTION_BASE = .;
-   .rodata.vclpackage . : { *(.rodata.vclpackage) } > sram
-   _VCL_PACKAGE_SECTION_SIZE = . - _VCL_PACKAGE_SECTION_BASE;
-
-   // Other read-only data.  
-
-   .rodata . : { *(.rodata*) *(.got2) } > sram
-
-    . = ALIGN(1024);
-    _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE;
-
-    ////////////////////////////////
-    // Text1
-    ////////////////////////////////
-
-    // The default text section
-
-    _TEXT1_SECTION_BASE = .;
-    
-    // Initialization text.  If we ever do a scheme to get rid of
-    // initialization text then this will have to be moved if we're also doing
-    // MMU protection.
-
-   .itext . : { init_text } > sram
-
-    // Other text
-    // It's not clear why boot.S is generating empty .glink,.iplt
-
-   .otext . : { *(.text) *(.text.startup)} > sram
-   .glink . : { *(.glink) } > sram
-
-    . = ALIGN(1024);
-    _TEXT1_SECTION_SIZE = . - _TEXT1_SECTION_BASE;
-
-    ////////////////////////////////
-    // Read-write Data
-    ////////////////////////////////
-
-    _DATA_SECTION_BASE = .;
-
-    // SDA sections .sdata and .sbss must be adjacent to each
-    // other.  Our SDATA sections are small so we'll use strictly positive
-    // offsets. 
-
-    _SDA_BASE_ = .;
-    .sdata  . : { *(.sdata)  } > sram
-    .sbss   . : { *(.sbss)   } > sram
-
-    // Other read-write data
-    // It's not clear why boot.S is generating empty .glink,.iplt
-
-   .rela   . : { *(.rela*) } > sram
-   .rwdata . : { *(.data) *(.bss) } > sram
-   .iplt . : { *(.iplt) } > sram
-
-
-   // Initialization-only data.  This includes the stack of main, the data
-   // structures declared by INITCALL, and any other data areas that can be
-   // reclaimed to the heap after initialization. 
-   //
-   // NB: If we ever do reclaim this space, we need to modify the concept of
-   // executable free space.
-
-   _INIT_ONLY_DATA_BASE = .;
-
-   _SSX_INITIAL_STACK_LIMIT = .;
-   . = . + INITIAL_STACK_SIZE;
-   _SSX_INITIAL_STACK = . - 1;
-
-   _INITCALL_SECTION_BASE = .;
-   .data.initcall . : { *(.data.initcall) } > sram
-   _INITCALL_SECTION_SIZE = . - _INITCALL_SECTION_BASE;
-
-   .data.startup . : { *(.data.startup) } > sram
-
-   _INIT_ONLY_DATA_SIZE = . - _INIT_ONLY_DATA_BASE;
-
-    ////////////////////////////////
-    // Free Space
-    ////////////////////////////////
-
-    // If the configuration allows executing from free space - i.e.,
-    // malloc()-ing a buffer and loading and executing code from it - then the
-    // free space is separated and aligned so that it can be marked executable.
-    // Otherwise it is simply read/write like the normal data sections.
-
-#ifndef EXECUTABLE_FREE_SPACE
-#define EXECUTABLE_FREE_SPACE 0
-#endif
-
-#if PPC405_MMU_SUPPORT && EXECUTABLE_FREE_SPACE
-    . = ALIGN(1024);
-#endif
-
-    // The free space available to the program starts here.  This space does
-    // not include the initial stack used by the boot loader and main().  The
-    // initial stack space is considered part of the free 'section' for MMU
-    // purposes.  Free space is always 8-byte aligned.  
-    //
-    // Note that there is no data after _SSX_FREE_START.  When binary images
-    // are created they can be padded to _SSX_FREE_START to guarantee
-    // that .bss and COMMON data are zeroed, and that the images contain an
-    // even multiple of 8 bytes (required for HW loaders).
-
-    . = ALIGN(8);
-    _EX_FREE_SECTION_BASE = .;
-    _SSX_FREE_START = .;
-
-#if EXECUTABLE_FREE_SPACE
-    _DATA_SECTION_SIZE = . - _DATA_SECTION_BASE;     
-    _EX_FREE_SECTION_SIZE = 0 - _EX_FREE_SECTION_BASE;
-#else
-    _DATA_SECTION_SIZE = 0 - _DATA_SECTION_BASE;     
-    _EX_FREE_SECTION_SIZE = 0;
-#endif
-
-    ////////////////////////////////
-    // Applet areas
-    ////////////////////////////////
-
-    // These symbols are currently unused, but required to be defined.
-    
-    _APPLET0_SECTION_BASE = 0;
-    _APPLET0_SECTION_SIZE = 0;
-    _APPLET1_SECTION_BASE = 0;
-    _APPLET1_SECTION_SIZE = 0;
-
-    // The final 16 bytes of memory are reserved for the hardware boot branch
-
-    _SSX_FREE_END = reset - 1;
-}
-
diff --git a/src/ssx/pgp/pgp_async_pore.c b/src/ssx/pgp/pgp_async_pore.c
deleted file mode 100755
index 5f9b425..0000000
--- a/src/ssx/pgp/pgp_async_pore.c
+++ /dev/null
@@ -1,644 +0,0 @@
-// $Id: pgp_async_pore.c,v 1.5 2014/05/14 13:35:43 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_pore.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_async_pore.c
-/// \brief PgP "async" drivers for PORE engines
-
-#include "ssx.h"
-
-////////////////////////////////////////////////////////////////////////////
-// Global Data
-////////////////////////////////////////////////////////////////////////////
-
-// The PORE queue objects.
-
-PoreQueue G_pore_gpe0_queue;
-PoreQueue G_pore_gpe1_queue;
-PoreQueue G_pore_slw_queue;
-
-
-////////////////////////////////////////////////////////////////////////////
-// Local Data
-////////////////////////////////////////////////////////////////////////////
-
-/// PoreFlex entry point - See G_pore_flex_table.
-
-static uint32_t G_pore_flex_entry0 = PORE_BRAD_D0;
-
-
-/// Entry 0 of the PoreFlex branch table
-///
-/// This variable is the only thing we represent of the branch table for PORE
-/// flex requests.  PoreFlex requests are forbidden from using PORE error
-/// handlers. Therefore they don't require the 60 redundant bytes of error
-/// handler entry points.  They also only run trigger slot 0, and begin
-/// execution with a BRAD D0, so the only thing we represent is a single BRAD
-/// D0 instruction.
-
-static uint32_t* G_pore_flex_table = &G_pore_flex_entry0 - (PORE_ERROR_SLOTS * 3);
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreQueue
-////////////////////////////////////////////////////////////////////////////
-
-/// Create (initialize) a PoreQueue
-///
-/// \param queue An uninitialized of otherwise idle PoreQueue
-///
-/// \param engine The identifier of a PORE engine associated with this queue.
-///
-/// This API initializes the PoreQueue structure and also initializes the
-/// underlying PORE hardware to run in the OCC environment.  Neither the
-/// branch table nor the error modes are specified here - those are considered
-/// application-specific functions that are set up each time a job is run on
-/// the engine.
-///
-/// \retval 0 Success
-///
-/// \retval -ASYNC_INVALID_OBJECT_PORE_QUEUE The \a queue was NULL (0).
-///
-/// \retval -ASYNC_INVALID_ENGINE_PORE The \a engine is not a (valid) 
-/// PORE engine.
-
-int
-pore_queue_create(PoreQueue *queue, int engine)
-{
-    pore_control_t control;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(queue == 0, ASYNC_INVALID_OBJECT_PORE_QUEUE);
-        SSX_ERROR_IF(!(engine & ASYNC_ENGINE_PORE), ASYNC_INVALID_ENGINE_PORE);
-    }
-
-    async_queue_create(&(queue->queue), engine);
-
-    switch (engine) {
-
-    case ASYNC_ENGINE_PORE_GPE0:
-        queue->oci_base = PORE_GPE0_OCI_BASE;
-        queue->irq = PGP_IRQ_PORE_GPE0_COMPLETE;
-        queue->error_irq = PGP_IRQ_PORE_GPE0_ERROR;
-        queue->oci_master = OCI_MASTER_ID_PORE_GPE;
-        break;
-
-    case ASYNC_ENGINE_PORE_GPE1:
-        queue->oci_base = PORE_GPE1_OCI_BASE;
-        queue->irq = PGP_IRQ_PORE_GPE1_COMPLETE;
-        queue->error_irq = PGP_IRQ_PORE_GPE1_ERROR;
-        queue->oci_master = OCI_MASTER_ID_PORE_GPE;
-        break;
-
-    case ASYNC_ENGINE_PORE_SLW:
-        queue->oci_base = PORE_SLW_OCI_BASE;
-        queue->irq = PGP_IRQ_PORE_SW_COMPLETE;
-        queue->error_irq = PGP_IRQ_PORE_SW_ERROR;
-        queue->oci_master = OCI_MASTER_ID_PORE_SLW;
-        break;
-
-    default:
-        SSX_PANIC(ASYNC_BUG_PORE_AT_CREATE);
-    }
-
-    // PORE engine setup
-    //
-    // Force the PORE to stop and set it up for OCC control.  Neither the
-    // breakpoint address nor the trap enable setting are modified in case
-    // they are being controlled from Simics or a hardware debugger ab initio.
-    //
-    // Register field settings:
-    //
-    // The scanclk ratio is not modified.
-    // The EXE-Trigger register is unlocked
-    // The freeze action is not modified
-    // Instruction parity is ignored
-    // The PIB parity checking setting is not modified
-    // The TRAP enable is not modified
-    // The breakpoint address is not modified
-
-    control.value = in64(queue->oci_base + PORE_CONTROL_OFFSET);
-
-    control.fields.start_stop = 1;
-    control.fields.lock_exe_trig= 0;
-    control.fields.check_parity = 0;
-
-    out64(queue->oci_base + PORE_CONTROL_OFFSET, control.value);
-
-    return 0;
-}
-
-
-// The interrupt handler for asynchronous PORE errors
-//
-// The PORE interrupts are disabled here, then cleared and re-enabled when the
-// next job runs.  This is to protect against "phantom" interrupts caused by
-// PORE freeze-on-checkstop behavior.
-
-SSX_IRQ_FAST2FULL(pore_async_error_handler, pore_async_error_handler_full);
-
-void
-pore_async_error_handler_full(void *arg, SsxIrqId irq, int priority)
-{
-    PoreQueue* queue = (PoreQueue*)arg;
-
-    ssx_irq_disable(queue->irq);
-    ssx_irq_disable(queue->error_irq);
-
-    async_error_handler((AsyncQueue *)arg, ASYNC_REQUEST_STATE_FAILED);
-}
-
-
-// The interrupt handler for asynchronous PORE requests
-//
-// The PORE interrupts are disabled here, then cleared and re-enabled when the
-// next job runs.  This is to protect against "phantom" interrupts caused by
-// PORE freeze-on-checkstop behavior.
-//
-// Note that if the system checkstops and freezes the PORE we will get a
-// normal completion interrupt.  Therefore we have to check to see if the
-// completion is associated with a freeze, and if so, fail the job.
-
-SSX_IRQ_FAST2FULL(pore_async_handler, pore_async_handler_full);
-
-void
-pore_async_handler_full(void *arg, SsxIrqId irq, int priority)
-{
-    PoreQueue* queue = (PoreQueue*)arg;
-    pore_status_t status;
-
-    status.value = in64(queue->oci_base + PORE_STATUS_OFFSET);
-    if (status.fields.freeze_action) {
-
-        pore_async_error_handler_full(arg, irq, priority);
-
-    } else {
-
-        ssx_irq_disable(queue->irq);
-        ssx_irq_disable(queue->error_irq);
-
-        async_handler((AsyncQueue *)arg);
-    }
-}
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreRequest
-////////////////////////////////////////////////////////////////////////////
-
-/// Create (initialize) the PoreRequest base class
-///
-/// \param request An uninitialized or otherwise idle PoreRequest.
-///
-/// \param queue An initialized PoreQueue
-///
-/// \param table The PORE branch table to install prior to kicking off the
-/// engine. All PoreFlex jobs use a common (stubbed) table.  PoreFixed jobs
-/// must supply a fully-formed table.
-///
-/// \param error_mask The initial value of the PORE ERROR_MASK register to be
-/// installed before kicking off the engine.
-///
-/// \param entry_point The entry point address of the routine.  For PoreFlex
-/// this entry point will be non-0 and will be inserted into D0, as PoreFlex
-/// jobs are kicked off by BRAD D0.  For PoreFixed this parameter will be zero
-/// and ignored.
-///
-/// \param start_vector The TBAR start vector to execute. This will always be
-/// 0 for PoreFlex.
-///
-/// \param parameter The single 32-bit parameter to the PORE program.  This
-/// value is stored in the low-order part of the \c EXE_TRIGGER register
-/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER
-/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as
-/// this is the hardware usage for hardware-initiated PORE-SLW routines.)
-///
-/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request
-/// will be governed by a private watchdog timer that will cancel a queued job
-/// or kill a running job if the hardware operation does not complete before
-/// it times out.
-///
-/// \param callback The callback to execute when the PORE program completes,
-/// or NULL (0) to indicate no callback.
-///
-/// \param arg The parameter to the callback routine; ignored if the \a
-/// callback is NULL.
-///
-/// \param options Options to control request priority and callback context.
-///
-/// This routine has no way to know if the PoreRequest structure is currently
-/// in use, so this API should only be called on uninitialized or otherwise
-/// idle PoreRequest structures.
-///
-/// \retval 0 Success
-///
-/// \retval -ASYNC_INVALID_OBJECT_PORE_REQUEST The \a request was NULL (0) 
-/// or the \a queue was NULL (0) or not a PoreQueue.
-///
-/// \retval -ASYNC_INVALID_ARGUMENT_PORE_REQUEST The \a start_vector is invalid or any of
-/// the parameters that represent OCI addresses are not 4-byte aligned, , or
-/// the \a table was null.
-///
-/// See async_request_create() for other errors that may be returned by this
-/// call.
-
-int
-pore_request_create(PoreRequest *request,
-                    PoreQueue *queue,
-                    PoreBraia* table,
-                    uint32_t error_mask,
-                    uint32_t entry_point,
-                    int start_vector,
-                    uint32_t parameter,
-                    SsxInterval timeout,
-                    AsyncRequestCallback callback,
-                    void *arg,
-                    int options)
-{
-    AsyncQueue *async_queue = (AsyncQueue *)queue;
-    int rc;
-    pore_exe_trigger_t etr;
-
-    if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF(!(async_queue->engine & ASYNC_ENGINE_PORE),
-                     ASYNC_INVALID_OBJECT_PORE_REQUEST);
-        SSX_ERROR_IF((start_vector < 0) ||
-                     (start_vector >= PORE_TRIGGER_SLOTS) ||
-                     ((uint32_t) table % 4) ||
-                     (entry_point % 4) ||
-                     (table == 0),
-                     ASYNC_INVALID_ARGUMENT_PORE_REQUEST);
-    }
-
-    rc = async_request_create(&(request->request),
-                              async_queue,
-                              pore_run_method,
-                              pore_error_method,
-                              timeout,
-                              callback,
-                              arg,
-                              options);
-
-    if (!rc) {
-        request->table = table;
-        request->error_mask = error_mask;
-        request->entry_point = entry_point;
-        request->parameter = parameter;
-        etr.value = 0;
-        etr.fields.start_vector = start_vector;
-        request->exe_trigger = etr.words.high_order;
-    }
-
-    return rc;
-}
-
-
-// Start a PoreRequest on a PORE
-//
-// \param async_request A PoreRequest upcast to an AsyncRequest.
-//
-// This is an internal API. At entry both the completion and error interrupts
-// are disabled and may show status that needs to be cleared before they are
-// re-enabled.
-//
-// This routine implements a simple procedure:
-//
-// - Check to make sure the PORE is not frozen due to a checkstop, and if so,
-//   collect FFDC and immediately fail the job.
-//
-// Otherwise:
-//
-// - Reset the PORE engine to clear up any error status that may remain from
-//   the last job .
-// - Install the TBAR (Table Base Address Register) from the request as an OCI
-//   address
-// - Set the EMR (Error Mask Register) from the request
-// - Install the parameter (ETR[32:63])
-// - If the entry point is non-0 then this is a PoreFlex job that is kicked
-//   off by a BRAD D0, and the entry point is installed in D0 as a full OCI
-//   address. 
-// - Clear pending interrupt status
-// - Hit ETR[0:31] to start the job.
-// - Enable interrupts.
-//
-// If the PORE is frozen due to a system checkstop we fail the job immediately
-// right here.  Note that there is still a small window where the system may
-// checkstop and the PORE may freeze after this check. Unfortunately the PORE
-// design locks out register writes while frozen, and instead of reporting
-// write access attempts as bus errors, silently ignores them and simply sets
-// a FIR bit. Originally the "frozen" check was done last to shrink the
-// window, however this practically guarantees these FIRs in a checkstopped
-// system (which the FW team finds problematic), so the check was moved to the
-// front of the procedure. (SW256621).
-//
-// Note that PORE interrupts remain masked unless the job starts successfully.
-
-int
-pore_run_method(AsyncRequest *async_request)
-{
-    PoreQueue *queue = (PoreQueue*)(async_request->queue);
-    PoreRequest *request = (PoreRequest*)async_request;
-    pore_status_t status;
-    pore_reset_t reset;
-    uint32_t oci_base;
-    int rc;
-
-    oci_base = queue->oci_base;
-
-    status.value = in64(oci_base + PORE_STATUS_OFFSET);
-    if (status.fields.freeze_action) {
-
-        pore_error_method(async_request);
-        async_request->completion_state = ASYNC_REQUEST_STATE_FAILED;
-        rc = -ASYNC_REQUEST_COMPLETE;
-
-    } else {
-
-        reset.value = 0;
-        reset.fields.fn_reset = 1;
-        out32(oci_base + PORE_RESET_OFFSET, reset.value);
-
-        out32(oci_base + PORE_TABLE_BASE_ADDR_OFFSET, PORE_ADDRESS_SPACE_OCI);
-        out32(oci_base + PORE_TABLE_BASE_ADDR_OFFSET + 4,
-              (uint32_t)(request->table));
-        out32(oci_base + PORE_ERROR_MASK_OFFSET, request->error_mask);
-        out32(oci_base + PORE_EXE_TRIGGER_OFFSET + 4, request->parameter);
-
-        if (request->entry_point != 0) {
-            out32(oci_base + PORE_SCRATCH1_OFFSET, PORE_ADDRESS_SPACE_OCI);
-            out32(oci_base + PORE_SCRATCH1_OFFSET + 4, request->entry_point);
-        }
-
-        ssx_irq_status_clear(queue->irq);
-        ssx_irq_status_clear(queue->error_irq);
-
-        out32(oci_base + PORE_EXE_TRIGGER_OFFSET, request->exe_trigger);
-
-        ssx_irq_enable(queue->irq);
-        ssx_irq_enable(queue->error_irq);
-        rc = 0;
-    }
-
-    return rc;
-}
-
-
-// PORE FFDC collection
-//
-// \param async_request A PoreRequest upcast to an AsyncRequest
-//
-// This is an internal API, called from an interrupt context when a PORE
-// engine signals an error interrupt.  See the comments for PoreFfdc for a
-// description of why this particular set of data is collected.
-//
-// PORE error handling procedure:
-//
-// - Collect FFDC from the PLB arbiter
-//
-// - Collect FFDC from the failing engine
-//
-// Currently all PORE errors are treated as recoverable
-
-/// \todo Consider analyzing the errors to determine if the error should be
-/// considered fatal.
-
-int
-pore_error_method(AsyncRequest *async_request)
-{
-    PoreQueue *queue = (PoreQueue*)(async_request->queue);
-    PoreRequest *request = (PoreRequest*)async_request;
-    uint32_t oci_base;
-    PoreFfdc* ffdc;
-
-    oci_base = queue->oci_base;
-    ffdc = &(request->ffdc);
- 
-    oci_ffdc(&(ffdc->oci_ffdc), queue->oci_master);
-
-    ffdc->debug[0] = in64(oci_base + PORE_DBG0_OFFSET);
-    ffdc->debug[1] = in64(oci_base + PORE_DBG1_OFFSET);
-    ffdc->address[0] = in32(oci_base + PORE_OCI_BASE_ADDRESS0_OFFSET + 4);
-    ffdc->address[1] = in32(oci_base + PORE_OCI_BASE_ADDRESS1_OFFSET + 4);
-    ffdc->ibuf[0] = in32(oci_base + PORE_IBUF_01_OFFSET);
-    ffdc->ibuf[1] = in32(oci_base + PORE_IBUF_01_OFFSET + 4);
-    ffdc->ibuf[2] = in32(oci_base + PORE_IBUF_2_OFFSET);
-
-    return 0;
-}
-
-
-/// Create (initialize) a PoreBraia branch table entry
-///
-/// \param instr  A pointer to the BRAIA instruction to initialize. Use the
-/// macros PORE_ERROR_BRANCH(table, n) and PORE_ENTRY_BRANCH(table, n) to
-/// select one of 5 error branches or one of 16 entry point branches in a PORE
-/// branch table.
-///
-/// \param address The 32-bit OCI address of the error routine or entry point.
-///
-/// This routine initializes the given entry of a PORE branch table with an
-/// OCI-based BRAIA instruction, them flushes the entry from the D-Cache.
-
-// Note that we don't know the alignment of the jump table, so we need to
-// flush both the first and last jump address to ensure that the BRAI is
-// completely flushed. This assumes (correctly) that uint32_t are at least
-// 4-byte aligned.
-
-void
-pore_braia_create(PoreBraia* instr, uint32_t address) {
-    instr->word[0] = PORE_BRAI;
-    instr->word[1] = PORE_ADDRESS_SPACE_OCI;
-    instr->word[2] = address;
-    dcache_flush_line(&(instr->word[0]));
-    dcache_flush_line(&(instr->word[2]));
-}
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreFlex
-////////////////////////////////////////////////////////////////////////////
-
-/// Create (initialize) a flex-mode PORE request
-///
-/// \param request An uninitialized or otherwise idle PoreFlex.
-///
-/// \param queue A pointer to a PoreQueue
-///
-/// \param entry_point The entry point of the PORE program. This must be a
-/// 32-bit, 4-byte aligned byte address in OCI space. The PoreEntryPoint
-/// typedef is provided to declare external PORE entry points. Note that an \a
-/// entry_point of 0 is considered an error - although it \e is conceivably a
-/// legal OCI address in mainstore via the PBA.
-///
-/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request
-/// will be governed by a private watchdog timer that will cancel a queued job
-/// or kill a running job if the hardware operation does not complete before
-/// it times out.
-///
-/// \param parameter The single 32-bit parameter to the PORE program.  This
-/// value is stored in the high-order part of the \c EXE_TRIGGER register
-/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER
-/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as
-/// this is the hardware usage for hardware-initiated PORE-SLW routines.)
-///
-/// \param callback The callback to execute when the PORE program completes,
-/// or NULL (0) to indicate no callback.
-///
-/// \param arg The parameter to the callback routine; ignored if the \a
-/// callback is NULL.
-///
-/// \param options Options to control request priority and callback context.
-///
-/// This routine has no way to know if the PoreFlex structure is currently
-/// in use, so this API should only be called on uninitialized or
-/// otherwise idle PoreFlex structures.
-///
-/// \retval 0 Success
-///
-/// See pore_request_create() for error return codes that may be returned by
-/// this call.
-
-int
-pore_flex_create(PoreFlex *request,
-                 PoreQueue *queue,
-                 PoreEntryPoint entry_point,
-                 uint32_t parameter,
-                 SsxInterval timeout,
-                 AsyncRequestCallback callback,
-                 void *arg,
-                 int options)
-{
-    uint32_t emr;
-
-    // PoreFlex jobs run w/o error handlers, and ignore sleeping cores. All
-    // errors are signalled on both error outputs of all PORE engines.
-
-    emr = (PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0       |
-           PORE_ERROR_MASK_ENABLE_ERR_OUTPUT1       |
-           PORE_ERROR_MASK_ENABLE_ERR_OUTPUT2       |
-           PORE_ERROR_MASK_ENABLE_ERR_OUTPUT3       |
-           PORE_ERROR_MASK_ENABLE_ERR_OUTPUT4       |
-           PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 |
-           PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 |
-           PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 |
-           PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 |
-           PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 |
-           PORE_ERROR_MASK_STOP_EXE_ON_ERROR0       |
-           PORE_ERROR_MASK_STOP_EXE_ON_ERROR1       |
-           PORE_ERROR_MASK_STOP_EXE_ON_ERROR2       |
-           PORE_ERROR_MASK_STOP_EXE_ON_ERROR3       |
-           PORE_ERROR_MASK_STOP_EXE_ON_ERROR4) >> 32;
-
-    return pore_request_create((PoreRequest*)request,
-                               queue,
-                               (PoreBraia*)G_pore_flex_table,
-                               emr,
-                               (uint32_t)entry_point,
-                               0,
-                               parameter,
-                               timeout,
-                               callback,
-                               arg,
-                               options);
-}
-
-
-////////////////////////////////////////////////////////////////////////////
-// PoreFixed
-////////////////////////////////////////////////////////////////////////////
-
-/// Create (initialize) a fixed-mode PORE request
-///
-/// \param request An uninitialized or otherwise idle PoreFixed request.
-///
-/// \param queue A PoreQueue capable of running fixed requests.
-///
-/// \param table A PORE branch table containing all of the error handler and
-/// entry point assignments required for the request.
-///
-/// \param error_mask A value that will be loaded into the high-order 32-bits
-/// of the PORE Error Mask Register to control error behavior.
-///
-/// \param start_vector The branch table slot reserved for this request.
-///
-/// \param parameter The single 32-bit parameter to the PORE program.  This
-/// value is stored in the high-order part of the \c EXE_TRIGGER register
-/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER
-/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as
-/// this is the hardware usage for hardware-initiated PORE-SLW routines.)
-///
-/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request
-/// will be governed by a private watchdog timer that will cancel a queued job
-/// or kill a running job if the hardware operation does not complete before
-/// it times out.
-///
-/// \param callback The callback to execute when the PORE program completes,
-/// or NULL (0) to indicate no callback.
-///
-/// \param arg The parameter to the callback routine; ignored if the \a
-/// callback is NULL.
-///
-/// \param options Options to control request priority and callback context.
-///
-/// This routine has no way to know if the PoreFixed structure is currently
-/// in use, so this API should only be called on uninitialized or
-/// otherwise idle PoreFlex structures.
-///
-/// \retval 0 Success
-///
-/// See pore_request_create() for error return codes that may be returned by
-/// this call.
-
-int
-pore_fixed_create(PoreFixed *request,
-                  PoreQueue *queue,
-                  PoreBraia* table,
-                  uint32_t error_mask,
-                  int start_vector,
-                  uint32_t parameter,
-                  SsxInterval timeout,
-                  AsyncRequestCallback callback,
-                  void *arg,
-                  int options)
-{
-    return pore_request_create((PoreRequest*)request,
-                               queue,
-                               table,
-                               error_mask,
-                               0,
-                               start_vector,
-                               parameter,
-                               timeout,
-                               callback,
-                               arg,
-                               options);
-}
-
-
-////////////////////////////////////////////////////////////////////////////
-// Initialization
-////////////////////////////////////////////////////////////////////////////
-
-// Due to the fact that PORE signals a "complete" interrupt on a freeze event
-// (i.e., a checkstop, even if PORE is not running), we can not enable PORE
-// interrupts globally.  They need to be carefully managed to avoid "phantom
-// interrupt" panics from async_handler().
-
-void
-async_pore_initialize(PoreQueue *queue,int engine)
-{
-    pore_queue_create(queue, engine);
-    async_edge_handler_setup(pore_async_handler,
-                             (void *)queue,
-                             queue->irq, SSX_CRITICAL);
-    async_edge_handler_setup(pore_async_error_handler,
-                             (void *)queue,
-                             queue->error_irq, SSX_CRITICAL);
-}
-
-
-
diff --git a/src/ssx/pgp/pgp_centaur.c b/src/ssx/pgp/pgp_centaur.c
deleted file mode 100644
index 85a0dd3..0000000
--- a/src/ssx/pgp/pgp_centaur.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/ssx/pgp/pgp_centaur.c $                                   */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: pgp_centaur.c,v 1.6 2015/01/27 17:56:26 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_centaur.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_centaur.c
-/// \brief Support for Centaur access and configuration from OCC.
-///
-/// Generic PBA generated PowerBus Address in pictures and words:
-/// 
-/// \code
-///
-///           1         2         3         4         5         6
-/// 0123456789012345678901234567890123456789012345678901234567890123
-///    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
-///                                                                 
-/// ..............B-------BX------------XO-----OA------------------A
-/// 
-/// .: Unused
-/// B: Direct from PBA BAR, bits 14:22
-/// X: If PBA BAR MASK 23:36 == 0, then PBA BAR 23:36
-///    Else Extended Address 0:13
-/// O: If PBA BAR MASK 37:43 == 0, then PBA BAR 37:43
-///    Else OCI Address 5:11
-/// A: OCI Address 12:31
-///
-/// \endcode
-///
-/// The OCI address always selects the low-order 20 bits of the PowerBus
-/// address, i.e., the window size is always a multiple of 1MB. The PBA BAR
-/// mask allows up to a 128MB window into main memory without using the
-/// extended address. The extended address allows OCC to address up to 2^41
-/// bytes by manipulating the extended address, assuming PHYP sets up the mask
-/// correctly.
-/// 
-/// 
-/// Centaur in-band SCOM, sensor cache and SYNC addressing in pictures and words:
-///
-/// \code
-/// 
-///           1         2         3         4         5         6
-/// 0123456789012345678901234567890123456789012345678901234567890123
-///    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
-///                                                                 
-/// ..............B-------BX------------XO-----OA------------------A - See Above
-/// ..............M-----------M10S------------------------------S000 - SCOM
-/// ..............M-----------M1100000000000000000000000000000000000 - Sensor cache
-/// ..............M-----------M1110000000000000000000000000000000000 - Sync
-/// 
-/// .: Unused
-/// M: The base address of the Centaur, taken from the MCS MCFGPR.
-/// O: 1 Signifies that this access comes from the OCC.
-/// S: The 32-bit SCOM address
-/// 0: Zero
-/// 
-/// \endcode
-///
-/// In order to access the Centaur for in-band SCOM, the PBA BAR MASK must
-/// extend at least from bit 29 down to bit 43, in order to allow the OCC to
-/// generate these addresses. In practice the mask must allow all configured
-/// Centaur to be accessed. This means that all Centaur in-band address bits
-/// not controllable by OCC through the mask must be equal.
-/// 
-/// Note that the SCOM address must be split between the extended address and
-/// the OCI address.
-/// 
-/// We assume (and verify) that MCMODE0(36) will always be set which means
-/// that bit 27 is a flag indicating whether an access comes from FSP or
-/// OCC. All OCC (GPE) accesses set this flag to 1.
-
-#include "ssx.h"
-#include "gpe_scom.h"
-
-#if defined(VERIFICATION) || defined(LAB_VALIDATION)
-#define PRINTD(...) printk(__VA_ARGS__)
-#else
-#define PRINTD(...)
-#endif
-
-CentaurConfiguration G_centaurConfiguration
-SECTION_ATTRIBUTE(".noncacheable_ro") = {.configRc = CENTAUR_NOT_CONFIGURED};
-
-const uint16_t _pgp_mcs_offset[PGP_NMCS] = {
-    0x0800, 0x0880, 0x0900, 0x0980, 0x0c00, 0x0c80, 0x0d00, 0x0d80
-};
-
-
-// All GpeScomParms structures are required to be noncacheable, so we have to
-// allocate a static instance rather than using the stack. For simplicity the
-// single-entry scomList_t required to collect the Centaur device IDs is
-// allocated statically as well.
-
-static GpeScomParms S_parms SECTION_ATTRIBUTE(".noncacheable") = {0};
-static scomList_t S_scomList SECTION_ATTRIBUTE(".noncacheable") = {{{0}}};
-
-int
-_centaur_configuration_create(int i_bar, int i_slave, int i_setup)
-{
-    CentaurConfiguration config;
-    int i, designatedSync, diffInit;
-    int64_t rc;                 /* Must be copied to global struct. */
-    mcfgpr_t mcfgpr;
-    mcifir_t mcifir;
-    mcsmode0_t mcsmode0;
-    pba_slvctln_t slvctl;
-    uint64_t diffMask, addrAccum, bar, mask, base;
-    PoreFlex request;
-
-    // Start by clearing the local structure and setting the error flag.
-    memset(&config, 0, sizeof(config));
-    config.configRc = CENTAUR_NOT_CONFIGURED;
-
-    designatedSync = -1;
-
-    do {
-        // Basic consistency checks
-
-        if ((i_bar < 0) || (i_bar >= PBA_BARS) ||
-            (i_slave < 0) || (i_slave >= PBA_SLAVES)) {
-            
-            rc = CENTAUR_INVALID_ARGUMENT;
-            break;
-        }
-
-        
-        // Create the setups for the GPE procedures. The 'dataParms' are the
-        // setup for accessing the Centaur sensor cache.  The 'scomParms' are
-        // the setup for accessing Centaur SCOMs. 
-
-        rc = gpe_pba_parms_create(&(config.dataParms),
-                                  PBA_SLAVE_PORE_GPE,
-                                  PBA_WRITE_TTYPE_CI_PR_W,
-                                  PBA_WRITE_TTYPE_DC,
-                                  PBA_READ_TTYPE_CL_RD_NC);
-        if (rc) {
-            rc = CENTAUR_DATA_SETUP_ERROR;
-            break;
-        }
-
-        rc = gpe_pba_parms_create(&(config.scomParms),
-                                  PBA_SLAVE_PORE_GPE,
-                                  PBA_WRITE_TTYPE_CI_PR_W,
-                                  PBA_WRITE_TTYPE_DC,
-                                  PBA_READ_TTYPE_CI_PR_RD);
-        if (rc) {
-            rc = CENTAUR_SCOM_SETUP_ERROR;
-            break;
-        }
-
-
-        // Go into each MCS on the chip, and for all enabled MCS get a couple
-        // of SCOMs and check configuration items for correctness. If any of
-        // the Centaur are configured, exactly one of the MCS must be
-        // designated to receive the SYNC commands.
-
-        // Note that the code uniformly treats SCOM failures of the MCFGPR
-        // registers as an unconfigured Centaur. This works both for Murano,
-        // which only defines the final 4 MCS, as well as for our VBU models
-        // where some of the "valid" MCS are not in the simulation models.
-
-        for (i = 0; i < PGP_NCENTAUR; i++) {
-
-            // SW273928: New function added for FW820, when centaur has channel
-            // checkstop, we consider centaur is not usable so treat it as 
-            // deconfigured. Note that the current implementation assumes when 
-            // centaur is dead, its mcs is also dead, which is wrong. However,
-            // it only concerns when MCS happens to be the SYNC master because 
-            // the gpe procedure only tries to talk to centaurs regardless what 
-            // MCS status it knows about. In this particular case,
-            // the procedure will turn on SYNC on a different MCS with
-            // valid centaur. According to Eric Retter, it would be ok for 
-            // HW to have more MCS turned on as SYNC master as long as FW
-            // only send SYNC command to one of them. 
-
-            rc = _getscom(MCS_ADDRESS(MCIFIR, i), &(mcifir.value),
-                          SCOM_TIMEOUT);
-            if (rc) {
-                rc = 0;
-                config.baseAddress[i] = 0;
-                continue;
-            }
-
-            if (mcifir.fields.channel_fail_signal_active) continue;
-
-            rc = _getscom(MCS_ADDRESS(MCFGPR, i), &(mcfgpr.value),
-                          SCOM_TIMEOUT);
-            if (rc) {
-                rc = 0;
-                config.baseAddress[i] = 0;
-                continue;
-            }
-
-            if (!mcfgpr.fields.mcfgprq_valid) continue;
-
-            rc = _getscom(MCS_ADDRESS(MCSMODE0, i), &(mcsmode0.value),
-                          SCOM_TIMEOUT);
-            if (rc) {
-                PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n",
-                       (uint32_t)rc, i);
-                rc = CENTAUR_MCSMODE0_SCOM_FAILURE;
-                break;
-            }
-
-
-            // We require that the MCFGRP_19_IS_HO_BIT be set in the mode
-            // register.  We do not support the option of this bit not being
-            // set, and all of our procedures will set bit 19 of the PowerBus
-            // address to indicate that OCC is making the access.
-
-            if (!mcsmode0.fields.mcfgrp_19_is_ho_bit) {
-
-                PRINTD("MCSMODE0(%d).mcfgrp_19_is_ho_bit == 0\n", i);
-                rc = CENTAUR_MCSMODE0_19_FAILURE;
-                break;
-            }
-                
-
-            // The 14-bit base-address is moved to begin at bit 14 in the
-            // 64-bit PowerBus address. The low-order bit of this address (bit
-            // 19 mentioned above which is bit 27 as an address bit) must be 0
-            // - otherwise there is confusion over who's controlling this
-            // bit.
-
-            config.baseAddress[i] = 
-                ((uint64_t)(mcfgpr.fields.mcfgprq_base_address)) << 
-                (64 - 14 - 14);
-
-            if (config.baseAddress[i] & 0x0000001000000000ull) {
-
-                PRINTD("Centaur base address %d has bit 27 set\n", i);
-                rc = CENTAUR_ADDRESS_27_FAILURE;
-                break;
-            }
-
-
-            // If this MCS is configured to be the designated SYNC unit, it
-            // must be the only one. 
-
-            if (mcsmode0.fields.enable_centaur_sync) {
-
-                if (designatedSync > 0) {
-
-                    PRINTD("Both MCS %d and %d are designated "
-                           "for Centaur Sync\n",
-                           designatedSync, i);
-                    rc = CENTAUR_MULTIPLE_DESIGNATED_SYNC;
-                    break;
-
-                } else {
-
-                    designatedSync = i;
-                }
-            }
-
-
-            // Add the Centaur to the configuration
-
-            config.config |= (CHIP_CONFIG_MCS(i) | CHIP_CONFIG_CENTAUR(i));
-        }
-
-        if (rc) break;
-
-
-        // If Centaur are configured, make sure at least one of the MCS will
-        // handle the SYNC. If so, convert its base address into an address
-        // for issuing SYNC commands by setting bits 27 (OCC) 28 and 29
-        // (Sync), then insert this address into the extended address field of
-        // a PBA slave control register image. gsc_scom_centaur() then merges
-        // this extended address into the PBA slave control register (which
-        // has been set up for Centaur SCOM) to do the SYNC.
-
-        // In the override mode (i_setup > 1) we tag the first valid MCS
-        // to recieve the sync if the firmware has not set it up correctly.
-
-        if (config.config) {
-
-            if (designatedSync < 0) {
-
-                if (i_setup <= 1) {
-
-                    PRINTD("No MCS is designated for Centaur SYNC\n");
-                    rc = CENTAUR_NO_DESIGNATED_SYNC;
-                    break;
-
-                } else {
-
-                    designatedSync = 
-                        cntlz32(left_justify_mcs_config(config.config));
-
-                    rc = _getscom(MCS_ADDRESS(MCSMODE0, designatedSync), 
-                                  &(mcsmode0.value),
-                                  SCOM_TIMEOUT);
-                    if (rc) {
-                        PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n",
-                               (uint32_t)rc, designatedSync);
-                        rc = CENTAUR_MCSMODE0_SCOM_FAILURE;
-                        break;
-                    }
-
-                    mcsmode0.fields.enable_centaur_sync = 1;
-
-                    rc = _putscom(MCS_ADDRESS(MCSMODE0, designatedSync), 
-                                  mcsmode0.value,
-                                  SCOM_TIMEOUT);
-                    if (rc) {
-                        PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n",
-                               (uint32_t)rc, designatedSync);
-                        rc = CENTAUR_MCSMODE0_SCOM_FAILURE;
-                        break;
-                    }
-                }
-            }
-
-            base = config.baseAddress[designatedSync] | 0x0000001c00000000ull;
-
-            slvctl.value = 0;
-            slvctl.fields.extaddr = (base & 0x000001fff8000000ull) >> 27;
-
-            config.syncSlaveControl = slvctl.value;
-        }
-
-        
-        // At this point we have one or more enabled MCS and they pass the
-        // initial configuration sniff test. We can now implement the option
-        // to configure the PBA BAR and BAR MASK correctly to allow access to
-        // these Centaur. We do this by computing the minimum BAR mask that
-        // covers all of the Centaur base addresses. This is done by
-        // accumulating a difference mask of the base addresses and finding
-        // the first set bit in the mask.
-        //
-        // Note that we do the configuration here on demand, but always do the
-        // correctness checking as the next step.
-
-        if (i_setup && (config.config != 0)) {
-
-            diffInit = 0;
-            diffMask = 0;       /* GCC happiness */
-            addrAccum = 0;      /* GCC happiness */
-            
-            for (i = 0; i < PGP_NCENTAUR; i++) {
-
-                if (config.baseAddress[i] != 0) {
-
-                    if (!diffInit) {
-
-                        diffInit = 1;
-                        diffMask = 0;
-                        addrAccum = config.baseAddress[i];
-
-                    } else {
-
-                        diffMask |= 
-                            (config.baseAddress[i] ^ addrAccum);
-                        addrAccum |= config.baseAddress[i];
-                    }
-
-                    if (0) {
-
-                        // Debug
-
-                        printk("i:%d baseAddress: 0x%016llx "
-                               "diffMask: 0x%016llx, addrAccum: 0x%016llx\n",
-                               i, config.baseAddress[i], diffMask, addrAccum);
-                    }
-                }
-            }
-
-            // The mask must cover all differences - and must also have at
-            // least bit 27 set. The mask register contains only the mask. The
-            // BAR is set to the accumulated address outside of the mask. The
-            // BAR also contains a scope field which defaults to 0 (Nodal
-            // Scope) for Centaur inband access.
-
-            diffMask |= 0x0000001000000000ull;            
-            mask = 
-                ((1ull << (64 - cntlz64(diffMask))) - 1) &
-                PBA_BARMSKN_MASK_MASK;
-
-            rc = _putscom(PBA_BARMSKN(i_bar), mask, SCOM_TIMEOUT);
-            if (rc) {
-                PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n",
-                       (uint32_t)rc, i_bar);
-                rc = CENTAUR_BARMSKN_PUTSCOM_FAILURE;
-                break;
-            }
-
-            rc = _putscom(PBA_BARN(i_bar), addrAccum & ~mask, SCOM_TIMEOUT);
-            if (rc) {
-                PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n",
-                       (uint32_t)rc, i_bar);
-                rc = CENTAUR_BARN_PUTSCOM_FAILURE;
-                break;
-            }
-        }
-
-
-        // Do an independent check that every Centaur base address
-        // can be generated by the combination of the current BAR and
-        // BAR Mask, along with the initial requirement that the mask must
-        // include at least bits 27:43.
-
-        if (config.config != 0) {
-
-            rc = _getscom(PBA_BARN(i_bar), &bar, SCOM_TIMEOUT);
-            if (rc) {
-                PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n",
-                       (uint32_t)rc, i_bar);
-                rc = CENTAUR_BARN_GETSCOM_FAILURE;
-                break;
-            }
-
-            rc = _getscom(PBA_BARMSKN(i_bar), &mask, SCOM_TIMEOUT);
-
-            if (rc) {
-                PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n",
-                       (uint32_t)rc, i_bar);
-                rc = CENTAUR_BARMSKN_GETSCOM_FAILURE;
-                break;
-            }
-
-            bar = bar & PBA_BARN_ADDR_MASK;
-            mask = mask & PBA_BARMSKN_MASK_MASK;
-
-            if ((mask & 0x0000001ffff00000ull) != 0x0000001ffff00000ull) {
-
-                PRINTD("PBA BAR mask (%d) does not cover bits 27:43\n", i_bar);
-                rc = CENTAUR_MASK_ERROR;
-                break;
-            }
-
-            for (i = 0; i < PGP_NCENTAUR; i++) {
-
-                if (config.baseAddress[i] != 0) {
-
-                    if ((config.baseAddress[i] & ~mask) != 
-                        (bar & ~mask)) {
-
-                        PRINTD("BAR/Mask (%d) error for MCS/Centaur %d\n"
-                               "    base = 0x%016llx\n"
-                               "    bar  = 0x%016llx\n"
-                               "    mask = 0x%016llx\n",
-
-                               i_bar, i, config.baseAddress[i], bar, mask);
-                        rc = CENTAUR_BAR_MASK_ERROR;
-                        break;
-                    }
-                }
-            }
-
-            if (rc) break;
-        }
-
-
-        // At this point the structure is initialized well-enough that it can
-        // be used by gpe_scom_centaur(). We run gpe_scom_centaur() to collect
-        // the CFAM ids of the chips.  Prior to this we copy our local copy
-        // into the global read-only data structure. (Note that GPE can DMA
-        // under the OCC TLB memory protection.) In order for
-        // gpe_scom_centaur() to run the global configuration must be valid
-        // (configRc == 0) - so we provisionally mark it valid (and will
-        // invalidate it later if errors occur here).
-
-        // Note however that if no Centaur are present then we're already
-        // done.
-
-        // It's assumed that this procedure is being run before threads have
-        // started, therefore we must poll for completion of the GPE program.
-        // Assuming no contention for GPE1 this procedure should take a few
-        // microseconds at most to complete.
-
-        if (0) {
-
-            // Debug for Simics - only enable MCS 5
-
-            config.baseAddress[0] =
-                config.baseAddress[1] =
-                config.baseAddress[2] =
-                config.baseAddress[3] =
-                config.baseAddress[4] =
-                config.baseAddress[6] =
-                config.baseAddress[7] = 0;
-        }
-
-
-        config.configRc = 0;
-        memcpy_real(&G_centaurConfiguration, &config, sizeof(config));
-
-        if (config.config == 0) break;
-
-        S_scomList.scom = CENTAUR_DEVICE_ID;
-        S_scomList.commandType = GPE_SCOM_READ_VECTOR;
-        S_scomList.pData = G_centaurConfiguration.deviceId;
-
-        S_parms.scomList = CAST_POINTER(uint64_t, &S_scomList);
-        S_parms.entries = 1;
-        S_parms.options = 0;
-        
-        pore_flex_create(&request,
-                         &G_pore_gpe1_queue,
-                         gpe_scom_centaur,
-                         (uint32_t)(&S_parms),
-                         SSX_MILLISECONDS(10), /* Timeout */
-                         0, 0, 0);
-
-        rc = pore_flex_schedule(&request);
-
-        if (rc) break;
-
-        while (!async_request_is_idle((AsyncRequest*)(&request)));
-
-        if (!async_request_completed((AsyncRequest*)(&request)) ||
-            (S_parms.rc != 0)) {
-
-            PRINTD("gpe_scom_centaur() for CENTAUR_DEVICE_ID failed:\n"
-                   "    Async state                   = 0x%02x\n"
-                   "    gpe_scom_centaur() rc         = %u\n"
-                   "    gpe_scom_centaur() errorIndex = %d\n",
-                   ((AsyncRequest*)(&request))->state,
-                   S_parms.rc, S_parms.errorIndex);
-                   
-            rc = CENTAUR_READ_TPC_ID_FAILURE;
-        }
-
-        if (0) {
-
-            // Debug
-
-            slvctl.value = G_gsc_lastSlaveControl;
-            
-            PRINTD("centaur_configuration_create:Debug\n"
-                   "    Last SCOM (PowerBus) address  = 0x%016llx\n"
-                   "    Last Slave Control            = 0x%016llx\n"
-                   "    Extended Address (positioned) = 0x%016llx\n"
-                   "    Last OCI Address              = 0x%016llx\n",
-                   G_gsc_lastScomAddress,
-                   G_gsc_lastSlaveControl,
-                   (unsigned long long)(slvctl.fields.extaddr) <<
-                   (64 - 23 - 14),
-                   G_gsc_lastOciAddress);
-        }
-
-    } while (0);
-
-    // Copy the final RC into the global structure and done.
-
-    memcpy_real(&(G_centaurConfiguration.configRc), &rc, sizeof(rc));
-
-    return rc;
-}
-
-
-// For now we have to handle configuring the PBA BAR and mask, and designating
-// a SYNC if the firmware forgot to.
-
-int
-centaur_configuration_create(void)
-{
-    return _centaur_configuration_create(PBA_BAR_CENTAUR, 
-                                         PBA_SLAVE_PORE_GPE,
-                                         2);
-}
-
-
-uint32_t mb_id(int i_mb)
-{
-    uint32_t rv;
-    centaur_device_id_t id;
-
-    if ((i_mb < 0) || (i_mb >= PGP_NCENTAUR) ||
-        (G_centaurConfiguration.configRc != 0)) {
-
-        rv = (uint32_t)-1;
-
-    } else {
-
-        id.value = G_centaurConfiguration.deviceId[i_mb];
-        rv = id.fields.cfam_id;
-    }
-
-    return rv;
-}
-
-
-uint8_t mb_chip_type(int i_mb)
-{
-    uint8_t rv;
-    cfam_id_t id;
-
-    if ((id.value = mb_id(i_mb)) == -1) {
-
-        rv = (uint8_t)-1;
-
-    } else {
-
-        rv = id.chipType;
-    }
-
-    return rv;
-}
-
-
-uint8_t mb_ec_level(int i_mb)
-{
-    uint8_t rv;
-    cfam_id_t id;
-
-    if ((id.value = mb_id(i_mb)) == -1) {
-
-        rv = (uint8_t)-1;
-
-    } else {
-
-        rv = (id.majorEc << 4) | id.minorEc;
-    }
-
-    return rv;
-}
diff --git a/src/ssx/pgp/pgp_centaur.h b/src/ssx/pgp/pgp_centaur.h
deleted file mode 100644
index 8c2ccee..0000000
--- a/src/ssx/pgp/pgp_centaur.h
+++ /dev/null
@@ -1,254 +0,0 @@
-#ifndef __PGP_CENTAUR_H__
-#define __PGP_CENTAUR_H__
-
-// $Id: pgp_centaur.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_centaur.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_centaur.h
-/// \brief Support for Centaur access and configuration from OCC.
-
-#include "gpe_pba.h"
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/// Compute the address of an MCS unit register from an index
-///
-/// The MCS units have a bizarre PIB addressing scheme.  This macro generates
-/// MCS unit PIB addresses from a register name (w/o unit/index prefix),
-/// assuming a valid index in the range 0:7. In the big sceheme of things it
-/// probably saves space and time to do this with a table lookup rather than
-/// generating the code to compute the address modification. (If we ever need
-/// these in assembler code we'll have to implement a macro).
-
-#define MCS_ADDRESS(reg, index) (MCS0_##reg | _pgp_mcs_offset[index])
-
-extern const uint16_t _pgp_mcs_offset[PGP_NMCS];
-
-
-/// A description of the current Centaur configuration
-///
-/// \note Because this structure is read by the GPE engine it is strongly
-/// recommended to allocate instances of this structure in non-cacheable data
-/// sections, with the caveat that data structures assigned to non-default
-/// data sections must always be initialized. For example:
-///
-/// \code
-///
-/// CentaurConfiguration G_centaurConfiguration
-/// SECTION_ATTRIBUTE(".noncacheable_ro") = 
-/// {.configRc = CENTAUR_NOT_CONFIGURED};
-///
-/// \endcode
-
-typedef struct {
-
-    /// Centaur base addresses for in-band operations
-    ///
-    /// These base addresses are used by GPE programs so it is most convenient
-    /// to store the entire 64 bits, even though only bits 23:26 of the base
-    /// address can be manipulated through the PBA BARs and BAR masks. A 0
-    /// value indicates an unconfigured Centaur (MCS).
-    uint64_t baseAddress[PGP_NCENTAUR];
-
-    /// Contents of Centaur device id registers
-    ///
-    /// These are the device ID SCOMs (0x000f000f) read from configured
-    /// Centaur during initialization. A 0 value indicates an unconfigured
-    /// Centaur.  These values are deconstructed by the memory buffer (mb)
-    /// APIs mb_id(), mb_chip_type() and mb_ec_level().
-    uint64_t deviceId[PGP_NCENTAUR];
-
-    /// A "chip configuration" bit mask denoting valid Centaur
-    ///
-    /// It shoud always be true that a bit denoting a configured Centaur is
-    /// associated with a non-0 \a baseAddress and vice-versa.
-    ChipConfig config;
-
-    /// The image of the PBA slave control register to use for the SYNC command
-    ///
-    /// The PowerBus address used to accomplish a Centaur SYNC is
-    /// constant. To simplify the procedures the PBA slave control register
-    /// (containing the extended address portion of the address) is
-    /// pre-computed and stored here.
-    ///
-    /// \note One and Only one of the MCS units can be targeted with SYNC
-    /// commands. The design includes a private bus connecting all MCS on the
-    /// chip that allows this "SYNC master" to broadcast the SYNC to all other
-    /// MCS on the chip.
-    uint64_t syncSlaveControl;
-
-    /// A GpePbaParms parameter block for gpe_mem_data()
-    ///
-    /// This parameter block is set up in advance and used by the GPE
-    /// procedure gpe_mem_data(). Given the complexity of accessing Centaur
-    /// sensors and SCOM through the PBA it is simpler to set these up ahead
-    /// of time and simply have the GPE procedures access preconfigured global
-    /// data. The \a dataParms and \a scomParms members are distinguished by
-    /// the different way the PBA slave needs to be configured to access
-    /// either the Centaur sensor cache or Centaur SCOMs.
-    GpePbaParms dataParms;
-
-    /// A GpePbaParms parameter block for gpe_scom_centaur().
-    GpePbaParms scomParms;
-
-    /// The final return code from centaur_configuration_create().
-    ///
-    /// If initialization fails then this value can be used to diagnose what
-    /// happend. This field should be statically initialized to a non-0 value
-    /// (CENTAUR_NOT_CONFIGURED) and can then be checked against 0 to
-    /// determine if the structure has been correctly initialized.
-    int64_t configRc;
-
-} CentaurConfiguration;
-
-/// The global CentaurConfiguration created during initialization
-extern CentaurConfiguration G_centaurConfiguration;
-
-#else // __ASSEMBLER__
-
-        .set    CENTAUR_CONFIGURATION_BASE_ADDRESS, 0x0
-
-        .set    CENTAUR_CONFIGURATION_DEVICE_ID, \
-                (CENTAUR_CONFIGURATION_BASE_ADDRESS + (8 * PGP_NCENTAUR))
-
-        .set    CENTAUR_CONFIGURATION_CONFIG, \
-                (CENTAUR_CONFIGURATION_DEVICE_ID + (8 * PGP_NCENTAUR))
-
-        .set    CENTAUR_CONFIGURATION_SYNC_SLAVE_CONTROL, \
-                (CENTAUR_CONFIGURATION_CONFIG + 8)  
-
-        .set    CENTAUR_CONFIGURATION_DATA_PARMS, \
-                (CENTAUR_CONFIGURATION_SYNC_SLAVE_CONTROL + 8)  
-
-        .set     CENTAUR_CONFIGURATION_SCOM_PARMS, \
-                (CENTAUR_CONFIGURATION_DATA_PARMS + SIZEOF_GPEPBAPARMS)
-
-        .set     CENTAUR_CONFIGURATION_CONFIG_RC, \
-                (CENTAUR_CONFIGURATION_SCOM_PARMS + SIZEOF_GPEPBAPARMS)
-
-        .set    SIZEOF_CENTAUR_CONFIGURATION, \
-                (CENTAUR_CONFIGURATION_CONFIG_RC + 8)
-
-#endif // __ASSEMBLER__
-
-
-#ifndef __ASSEMBLER__
-
-/// Error return codes set/returned by centaur_configuration_create()
-
-enum CentaurConfigurationCreateRc{
-
-    CENTAUR_INVALID_ARGUMENT         = 0x007ccc01,
-    CENTAUR_MCSMODE0_SCOM_FAILURE    = 0x007ccc02,
-    CENTAUR_MCSMODE0_19_FAILURE      = 0x007ccc03,
-    CENTAUR_ADDRESS_27_FAILURE       = 0x007ccc04,
-    CENTAUR_MULTIPLE_DESIGNATED_SYNC = 0x007ccc05,
-    CENTAUR_NO_DESIGNATED_SYNC       = 0x007ccc06,
-    CENTAUR_BAR_MASK_ERROR           = 0x007ccc07,
-    CENTAUR_CONFIGURATION_FAILED     = 0x007ccc08,
-    CENTAUR_DATA_SETUP_ERROR         = 0x007ccc09,
-    CENTAUR_SCOM_SETUP_ERROR         = 0x007ccc0a,
-    CENTAUR_NOT_CONFIGURED           = 0x007ccc0b,
-    CENTAUR_MASK_ERROR               = 0x007ccc0c,
-    CENTAUR_READ_TPC_ID_FAILURE      = 0x007ccc0d,
-    CENTAUR_BARMSKN_PUTSCOM_FAILURE  = 0x007ccc0e,   
-    CENTAUR_BARN_PUTSCOM_FAILURE     = 0x007ccc0f,
-    CENTAUR_BARMSKN_GETSCOM_FAILURE  = 0x007ccc10,   
-    CENTAUR_BARN_GETSCOM_FAILURE     = 0x007ccc11,
-};
-
-
-/// Create (initialize) G_centaurConfiguration
-///
-/// G_centaurConfiguration is a global structure used by GPE procedures to
-/// access Centaur, and the mb_*() APIs to return CFAM-id type information
-/// about the Centaurs.
-///
-/// To complete Centaur configuration requires running the GPE program
-/// gpe_scom_centaur() on PORE-GPE1 to collect the TPC device Ids of the
-/// Centaur chips. This means that the "async" drivers must be set up prior to
-/// the call. We assume this API will be called before threads have started,
-/// thus it will poll the async request for completion. Assuming no other GPE
-/// programs are scheduled this should take a few microseconds at most.
-///
-/// \returns Either 0 for success or an element of the
-/// CentaurConfigurationCreateRc enumeration.
-int
-centaur_configuration_create(void);
-
-
-/// Create (initialize) G_centaurConfiguration (Internal API)
-///
-/// \param[in] i_bar The index of the PBA BAR reserved for access to
-/// Centaur. This will normally be passed as the constant PBA_BAR_CENTAUR but
-/// is allowed to be variable for special cases. 
-///
-/// \param[in] i_slave The index of the PBA slave reserved for access from the
-/// GPE complex. This will normally be passed as the constant
-/// PBA_SLAVE_PORE_GPE but is allowed to be variable for special cases.
-///
-/// \param[in] i_setup If non-0, then this procedure will set up the PBA BAR
-/// correctly for access to Centaur. If > 1, then the procedure will also
-/// designate an MCS to recieve the Centaur SYNC if the firmware failed to do
-/// so. 
-///
-/// This API must be run early in the initialization flow, likely before the
-/// real-time loop is activated. The API first scans the MBS configuration for
-/// correctness and (optionally) sets up the PBA BAR and mask for access to
-/// Centaur. The API then runs the gpe_scom_centaur() procedure to get the
-/// CFAM Id from each configured Centaur.
-///
-/// \note Normally we would implement test/bringup workarounds like the \a
-/// i_setup parameter separately, however the setup of Centaur is at a level
-/// of complexity where it makes sense to implement this override in a
-/// mainline procedure.
-int
-_centaur_configuration_create(int i_bar, int i_slave, int i_setup);
-
-
-/// Get a Centaur (MB) CFAM Chip Id
-/// 
-/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being
-/// queried.
-///
-/// \returns A 32-bit value to be compared against the enumeration of known
-/// CFAM ids.  See \ref pgp_cfam_chip_ids.  If the \a i_mb is invalid or the
-/// Centaur is not configured or the G_centaurConfiguration is not valid then
-/// (uint32_t)-1 is returned.
-uint32_t mb_id(int i_mb);
-
-
-/// Get a Centaur (MB) Chip Type
-/// 
-/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being
-/// queried.
-///
-/// \returns An 8-bit value to be compared against the enumeration of known
-/// CFAM chip types.  See \ref pgp_cfam_chip_types. If the \a i_mb is invalid
-/// or the Centaur is not configured or the G_centaurConfiguration is not
-/// valid then (uint8_t)-1 is returned.
-uint8_t mb_chip_type(int i_mb);
-
-
-/// Get a Centaur (MB) CFAM Chip EC Level
-/// 
-/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being
-/// queried.
-///
-/// \returns An 8-bit value; The high-order nibble is the major EC level and
-/// the low-order nibble is the minor EC level. For example a value of 0x21
-/// indicates DD 2.1. If the \a i_mb is invalid or the Centaur is not
-/// configured or the G_centaurConfiguration is not valid then (uint8_t)-1 is
-/// returned.
-uint8_t mb_ec_level(int i_mb);
-
-#endif // __ASSEMBLER
-
-#endif // __PGP_CENTAUR_H__
diff --git a/src/ssx/pgp/pgp_common.h b/src/ssx/pgp/pgp_common.h
deleted file mode 100755
index 305f7c2..0000000
--- a/src/ssx/pgp/pgp_common.h
+++ /dev/null
@@ -1,717 +0,0 @@
-#ifndef __PGP_COMMON_H__
-#define __PGP_COMMON_H__
-
-// $Id: pgp_common.h,v 1.4 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_common.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_common.h
-/// \brief Common header for SSX and PMX versions of PgP
-///
-/// This header is maintained as part of the SSX port for PgP, but needs to be
-/// physically present in the PMX area to allow dropping PMX code as a whole
-/// to other teams.
-
-// -*- WARNING: This file is maintained as part of SSX.  Do not edit in -*-
-// -*- the PMX area as your edits will be lost.                         -*-
-
-#ifndef __ASSEMBLER__
-#include <stdint.h>
-extern unsigned int g_ocb_timer_divider; //grm
-#endif
-
-////////////////////////////////////////////////////////////////////////////
-// Configuration
-////////////////////////////////////////////////////////////////////////////
-
-#define PGP_NCORES            16
-#define PGP_NCORE_PARTITIONS   4
-#define PGP_NMCS               8
-#define PGP_NCENTAUR           8
-#define PGP_NTHREADS           8
-#define PGP_NDTSCPM            4
-
-#ifndef PROCESSOR_EC_LEVEL
-#define MURANO_DD10 1
-#else
-#define MURANO_DD10 0
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////
-// Clocking
-////////////////////////////////////////////////////////////////////////////
-//
-// The SSX timebase is driven by the pervasive clock, which is nest / 4.  This
-// will typically be 600MHz, but may be 500MHz for power-constrained system
-// designs. 
-
-/// The pervasive hang timer divider used for the OCB timer
-///
-/// This is supposed to yield an approximately 1us timer, however for MURANO
-/// DD10 we need to use an approximate 64us timer
-
-#if MURANO_DD10
-#define OCB_TIMER_DIVIDER_DEFAULT (64 * 512)
-#else
-#define OCB_TIMER_DIVIDER_DEFAULT 512
-#endif
-
-/// This is set to the above default at compile time but may be updated
-/// at run time. grm
-#define OCB_TIMER_DIVIDER g_ocb_timer_divider
-
-/// The OCB timer frequency
-#define OCB_TIMER_FREQUENCY_HZ (SSX_TIMEBASE_FREQUENCY_HZ / OCB_TIMER_DIVIDER)
-
-/// The pervasive hang timer divider used for the PMC (same as OCB timer)
-#define PMC_TIMER_DIVIDER OCB_TIMER_DIVIDER
-
-/// The PMC hang pulse frequency
-#define PMC_HANG_PULSE_FREQUENCY_HZ \
-    (SSX_TIMEBASE_FREQUENCY_HZ / PMC_TIMER_DIVIDER)
-
-/// The pervasive hang timer divider for PCBS 'fast' timers
-///
-/// This timer yeilds an approximate 100ns pulse with a 2.4 GHz pervasive clock
-#define PCBS_FAST_TIMER_DIVIDER 64
-
-/// The pervasive hang timer divider for PCBS 'slow' timers
-///
-/// This timer yeilds an approximate 1us pulse with a 2.4 GHz pervasive clock
-#define PCBS_SLOW_TIMER_DIVIDER 512
-
-/// The PCBS slow divider frequency
-#define PCBS_SLOW_HANG_PULSE_FREQUENCY_HZ \
-    (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_SLOW_TIMER_DIVIDER)
-
-/// The PCBS occ heartbeat pulse is predivided in hardware by 64
-#define PCBS_HEARTBEAT_DIVIDER \
-    (PCBS_SLOW_TIMER_DIVIDER * 64)
-
-/// The PCBS heartbeat pulse frequency
-#define PCBS_HEARTBEAT_PULSE_FREQUENCY_HZ \
-    (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_HEARTBEAT_DIVIDER)
-
-
-
-////////////////////////////////////////////////////////////////////////////
-// OCI
-////////////////////////////////////////////////////////////////////////////
-
-// OCI Master Id assigments - required for PBA slave programming.  These Ids
-// also appear as bits 12:15 of the OCI register space addresses of the OCI
-// registers for each device that contains OCI-addressable registers (GPE,
-// PMC, PBA, SLW and OCB).
-
-#define OCI_MASTER_ID_PORE_GPE 0
-#define OCI_MASTER_ID_PMC      1
-#define OCI_MASTER_ID_PBA      2
-#define OCI_MASTER_ID_UNUSED   3
-#define OCI_MASTER_ID_PORE_SLW 4
-#define OCI_MASTER_ID_OCB      5
-#define OCI_MASTER_ID_OCC_ICU  6
-#define OCI_MASTER_ID_OCC_DCU  7
-
-
-////////////////////////////////////////////////////////////////////////////
-// IRQ
-////////////////////////////////////////////////////////////////////////////
-
-// The OCB interrupt controller consists of 2 x 32-bit controllers.  Unlike
-// PPC ASICs, the OCB controllers are _not_ cascaded.  The combined
-// controllers are presented to the application as if there were a single
-// 64-bit interrupt controller, while the code underlying the abstraction
-// manipulates the 2 x 32-bit controllers independently.
-//
-// Note that the bits named *RESERVED* are actually implemented in the
-// controller, but the interrupt input is tied low. That means they can also
-// be used as IPI targets. Logical bits 32..63 are not implemented.
-
-#define PGP_IRQ_DEBUGGER                        0 /* 0x00 */
-#define PGP_IRQ_TRACE_TRIGGER                   1 /* 0x01 */
-#define PGP_IRQ_OCC_ERROR                       2 /* 0x02 */
-#define PGP_IRQ_PBA_ERROR                       3 /* 0x03 */
-#define PGP_IRQ_SRT_ERROR                       4 /* 0x04 */
-#define PGP_IRQ_PORE_SW_ERROR                   5 /* 0x05 */
-#define PGP_IRQ_PORE_GPE0_FATAL_ERROR           6 /* 0x06 */
-#define PGP_IRQ_PORE_GPE1_FATAL_ERROR           7 /* 0x07 */
-#define PGP_IRQ_PORE_SBE_FATAL_ERROR            8 /* 0x08 */
-#define PGP_IRQ_PMC_ERROR                       9 /* 0x09 */
-#define PGP_IRQ_OCB_ERROR                      10 /* 0x0a */
-#define PGP_IRQ_SPIPSS_ERROR                   11 /* 0x0b */
-#define PGP_IRQ_CHECK_STOP                     12 /* 0x0c */
-#define PGP_IRQ_PMC_MALF_ALERT                 13 /* 0x0d */
-#define PGP_IRQ_ADU_MALF_ALERT                 14 /* 0x0e */
-#define PGP_IRQ_EXTERNAL_TRAP                  15 /* 0x0f */
-#define PGP_IRQ_OCC_TIMER0                     16 /* 0x10 */
-#define PGP_IRQ_OCC_TIMER1                     17 /* 0x11 */
-#define PGP_IRQ_PORE_GPE0_ERROR                18 /* 0x12 */
-#define PGP_IRQ_PORE_GPE1_ERROR                19 /* 0x13 */
-#define PGP_IRQ_PORE_SBE_ERROR                 20 /* 0x14 */
-#define PGP_IRQ_PMC_INTERCHIP_MSG_RECV         21 /* 0x15 */
-#define PGP_IRQ_RESERVED_22                    22 /* 0x16 */
-#define PGP_IRQ_PORE_GPE0_COMPLETE             23 /* 0x17 */
-#define PGP_IRQ_PORE_GPE1_COMPLETE             24 /* 0x18 */
-#define PGP_IRQ_ADCFSM_ONGOING                 25 /* 0x19 */
-#define PGP_IRQ_RESERVED_26                    26 /* 0x1a */
-#define PGP_IRQ_PBA_OCC_PUSH0                  27 /* 0x1b */
-#define PGP_IRQ_PBA_OCC_PUSH1                  28 /* 0x1c */
-#define PGP_IRQ_PBA_BCDE_ATTN                  29 /* 0x1d */
-#define PGP_IRQ_PBA_BCUE_ATTN                  30 /* 0x1e */
-#define PGP_IRQ_RESERVED_31                    31 /* 0x1f */
-
-#define PGP_IRQ_RESERVED_32                    32 /* 0x20 */
-#define PGP_IRQ_RESERVED_33                    33 /* 0x21 */
-#define PGP_IRQ_STRM0_PULL                     34 /* 0x22 */
-#define PGP_IRQ_STRM0_PUSH                     35 /* 0x23 */
-#define PGP_IRQ_STRM1_PULL                     36 /* 0x24 */
-#define PGP_IRQ_STRM1_PUSH                     37 /* 0x25 */
-#define PGP_IRQ_STRM2_PULL                     38 /* 0x26 */
-#define PGP_IRQ_STRM2_PUSH                     39 /* 0x27 */
-#define PGP_IRQ_STRM3_PULL                     40 /* 0x28 */
-#define PGP_IRQ_STRM3_PUSH                     41 /* 0x29 */
-#define PGP_IRQ_RESERVED_42                    42 /* 0x2a */
-#define PGP_IRQ_RESERVED_43                    43 /* 0x2b */
-#define PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING     44 /* 0x2c */
-#define PGP_IRQ_PMC_PROTOCOL_ONGOING           45 /* 0x2d */
-#define PGP_IRQ_PMC_SYNC                       46 /* 0x2e */
-#define PGP_IRQ_PMC_PSTATE_REQUEST             47 /* 0x2f */
-#define PGP_IRQ_RESERVED_48                    48 /* 0x30 */
-#define PGP_IRQ_RESERVED_49                    49 /* 0x31 */
-#define PGP_IRQ_PMC_IDLE_EXIT                  50 /* 0x32 */
-#define PGP_IRQ_PORE_SW_COMPLETE               51 /* 0x33 */
-#define PGP_IRQ_PMC_IDLE_ENTER                 52 /* 0x34 */
-#define PGP_IRQ_RESERVED_53                    53 /* 0x35 */
-#define PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING 54 /* 0x36 */
-#define PGP_IRQ_OCI2SPIVID_ONGOING             55 /* 0x37 */
-#define PGP_IRQ_PMC_OCB_O2P_ONGOING            56 /* 0x38 */
-#define PGP_IRQ_PSSBRIDGE_ONGOING              57 /* 0x39 */
-#define PGP_IRQ_PORE_SBE_COMPLETE              58 /* 0x3a */
-#define PGP_IRQ_IPI0                           59 /* 0x3b */
-#define PGP_IRQ_IPI1                           60 /* 0x3c */
-#define PGP_IRQ_IPI2                           61 /* 0x3d */
-#define PGP_IRQ_IPI3                           62 /* 0x3e */
-#define PGP_IRQ_RESERVED_63                    63 /* 0x3f */
-
-
-// Please keep the string definitions up-to-date as they are used for
-// reporting in the Simics simulation.
-
-#define PGP_IRQ_STRINGS(var)                      \
-    const char* var[64] = {                       \
-        "PGP_IRQ_DEBUGGER",                       \
-        "PGP_IRQ_TRACE_TRIGGER",                  \
-        "PGP_IRQ_OCC_ERROR",                      \
-        "PGP_IRQ_PBA_ERROR",                      \
-        "PGP_IRQ_SRT_ERROR",                      \
-        "PGP_IRQ_PORE_SW_ERROR",                  \
-        "PGP_IRQ_PORE_GPE0_FATAL_ERROR",          \
-        "PGP_IRQ_PORE_GPE1_FATAL_ERROR",          \
-        "PGP_IRQ_PORE_SBE_FATAL_ERROR",           \
-        "PGP_IRQ_PMC_ERROR",                      \
-        "PGP_IRQ_OCB_ERROR",                      \
-        "PGP_IRQ_SPIPSS_ERROR",                   \
-        "PGP_IRQ_CHECK_STOP",                     \
-        "PGP_IRQ_PMC_MALF_ALERT",                 \
-        "PGP_IRQ_ADU_MALF_ALERT",                 \
-        "PGP_IRQ_EXTERNAL_TRAP",                  \
-        "PGP_IRQ_OCC_TIMER0",                     \
-        "PGP_IRQ_OCC_TIMER1",                     \
-        "PGP_IRQ_PORE_GPE0_ERROR",                \
-        "PGP_IRQ_PORE_GPE1_ERROR",                \
-        "PGP_IRQ_PORE_SBE_ERROR",                 \
-        "PGP_IRQ_PMC_INTERCHIP_MSG_RECV",         \
-        "PGP_IRQ_RESERVED_22",                    \
-        "PGP_IRQ_PORE_GPE0_COMPLETE",             \
-        "PGP_IRQ_PORE_GPE1_COMPLETE",             \
-        "PGP_IRQ_ADCFSM_ONGOING",                 \
-        "PGP_IRQ_RESERVED_26",                    \
-        "PGP_IRQ_PBA_OCC_PUSH0",                  \
-        "PGP_IRQ_PBA_OCC_PUSH1",                  \
-        "PGP_IRQ_PBA_BCDE_ATTN",                  \
-        "PGP_IRQ_PBA_BCUE_ATTN",                  \
-        "PGP_IRQ_RESERVED_31",                    \
-        "PGP_IRQ_RESERVED_32",                    \
-        "PGP_IRQ_RESERVED_33",                    \
-        "PGP_IRQ_STRM0_PULL",                     \
-        "PGP_IRQ_STRM0_PUSH",                     \
-        "PGP_IRQ_STRM1_PULL",                     \
-        "PGP_IRQ_STRM1_PUSH",                     \
-        "PGP_IRQ_STRM2_PULL",                     \
-        "PGP_IRQ_STRM2_PUSH",                     \
-        "PGP_IRQ_STRM3_PULL",                     \
-        "PGP_IRQ_STRM3_PUSH",                     \
-        "PGP_IRQ_RESERVED_42",                    \
-        "PGP_IRQ_RESERVED_43",                    \
-        "PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING",     \
-        "PGP_IRQ_PMC_PROTOCOL_ONGOING",           \
-        "PGP_IRQ_PMC_SYNC",                       \
-        "PGP_IRQ_PMC_PSTATE_REQUEST",             \
-        "PGP_IRQ_RESERVED_48",                    \
-        "PGP_IRQ_RESERVED_49",                    \
-        "PGP_IRQ_PMC_IDLE_EXIT",                  \
-        "PGP_IRQ_PORE_SW_COMPLETE",               \
-        "PGP_IRQ_PMC_IDLE_ENTER",                 \
-        "PGP_IRQ_RESERVED_53",                    \
-        "PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING", \
-        "PGP_IRQ_OCI2SPIVID_ONGOING",             \
-        "PGP_IRQ_PMC_OCB_O2P_ONGOING",            \
-        "PGP_IRQ_PSSBRIDGE_ONGOING",              \
-        "PGP_IRQ_PORE_SBE_COMPLETE",              \
-        "PGP_IRQ_IPI0",                           \
-        "PGP_IRQ_IPI1",                           \
-        "PGP_IRQ_IPI2",                           \
-        "PGP_IRQ_IPI3 (ASYNC-IPI)",               \
-        "PGP_IRQ_RESERVED_63"                     \
-    };
-
-
-/// This constant is used to define the size of the table of interrupt handler
-/// structures as well as a limit for error checking.  The entire 64-bit
-/// vector is now in use.
-
-#define PPC405_IRQS 64
-
-
-// Note: All standard-product IPI uses are declared here to avoid conflicts
-// Validation- and lab-only IPI uses are documented in validation.h
-
-/// The deferred callback queue interrupt
-///
-/// This IPI is reserved for use of the async deferred callback mechanism.
-/// This IPI is used by both critical and noncritical async handlers to
-/// activate the deferred callback mechanism.
-#define PGP_IRQ_ASYNC_IPI PGP_IRQ_IPI3
-
-
-/// The PTS completion queue intererupt
-///
-/// This IPI is reserved for use of the PTS completion queues.  A single
-/// interrupt serves PTS for both GPE0 and GPE1.  Note that as defined here,
-/// PTS completion takes precedence over other ASYNC processing, however in
-/// reality they both run callbacks preemptible so they will tend to be more
-/// or less at the same priority.  If this is a problem then they could be
-/// combined onto a single interrupt and handled with the appropriate priority
-/// in the async_callback_handler_full().
-
-#define PGP_IRQ_PTS_IPI PGP_IRQ_IPI2
-
-
-#ifndef __ASSEMBLER__
-
-/// This expression recognizes only those IRQ numbers that have named
-/// (non-reserved) interrupts in the OCB interrupt controller.
-
-// There are so many invalid interrupts now that it's a slight improvement in
-// code size to let the compiler optimize the invalid IRQs to a bit mask for
-// the comparison.
-
-#define PGP_IRQ_VALID(irq) \
-    ({unsigned __irq = (unsigned)(irq); \
-        ((__irq < PPC405_IRQS) &&                               \
-         ((PGP_IRQ_MASK64(__irq) &                              \
-           (PGP_IRQ_MASK64(PGP_IRQ_RESERVED_22) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_26) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_31) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_32) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_33) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_42) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_43) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_48) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_49) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_53) |               \
-            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_63))) == 0));})
-
-/// This is a 32-bit mask, with big-endian bit (irq % 32) set.
-#define PGP_IRQ_MASK32(irq) (((uint32_t)0x80000000) >> ((irq) % 32))
-
-/// This is a 64-bit mask, with big-endian bit 'irq' set.
-#define PGP_IRQ_MASK64(irq) (0x8000000000000000ull >> (irq))
-
-#endif  /* __ASSEMBLER__ */
-
-
-////////////////////////////////////////////////////////////////////////////
-// OCB
-////////////////////////////////////////////////////////////////////////////
-
-/// The base address of the OCI control register space
-#define OCI_REGISTER_SPACE_BASE 0x40000000
-
-/// The base address of the entire PIB port mapped by the OCB.  The
-/// OCB-contained PIB registers are based at OCB_PIB_BASE.
-#define OCB_PIB_SLAVE_BASE 0x00060000
-
-/// The size of the OCI control register address space
-///
-/// There are at most 8 slaves, each of which maps 2**16 bytes of register
-/// address space.
-#define OCI_REGISTER_SPACE_SIZE POW2_32(19)
-
-/// This macro converts an OCI register space address into a PIB address as
-/// seen through the OCB direct bridge.
-#define OCI2PIB(addr) ((((addr) & 0x0007ffff) >> 3) + OCB_PIB_SLAVE_BASE)
-
-
-// OCB communication channel constants
-
-#define OCB_INDIRECT_CHANNELS 4
-
-#define OCB_RW_READ  0
-#define OCB_RW_WRITE 1
-
-#define OCB_STREAM_MODE_DISABLED 0
-#define OCB_STREAM_MODE_ENABLED  1
-
-#define OCB_STREAM_TYPE_LINEAR   0
-#define OCB_STREAM_TYPE_CIRCULAR 1
-
-#define OCB_INTR_ACTION_FULL      0
-#define OCB_INTR_ACTION_NOT_FULL  1
-#define OCB_INTR_ACTION_EMPTY     2
-#define OCB_INTR_ACTION_NOT_EMPTY 3
-
-#ifndef __ASSEMBLER__
-
-// These macros select OCB interrupt controller registers based on the IRQ
-// number.
-
-#define OCB_OIMR_AND(irq) (((irq) & 0x20) ? OCB_OIMR1_AND : OCB_OIMR0_AND)
-#define OCB_OIMR_OR(irq)  (((irq) & 0x20) ? OCB_OIMR1_OR  : OCB_OIMR0_OR)
-
-#define OCB_OISR(irq)     (((irq) & 0x20) ? OCB_OISR1     : OCB_OISR0)
-#define OCB_OISR_AND(irq) (((irq) & 0x20) ? OCB_OISR1_AND : OCB_OISR0_AND)
-#define OCB_OISR_OR(irq)  (((irq) & 0x20) ? OCB_OISR1_OR  : OCB_OISR0_OR)
-
-#define OCB_OIEPR(irq) (((irq) & 0x20) ? OCB_OIEPR1 : OCB_OIEPR0)
-#define OCB_OITR(irq)  (((irq) & 0x20) ? OCB_OITR1  : OCB_OITR0)
-#define OCB_OCIR(irq)  (((irq) & 0x20) ? OCB_OCIR1  : OCB_OCIR0)
-#define OCB_OUDER(irq) (((irq) & 0x20) ? OCB_OUDER1 : OCB_OUDER0)
-
-#endif  /* __ASSEMBLER__ */
-
-
-////////////////////////////////////////////////////////////////////////////
-// PMC
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-/// A Pstate type
-///
-/// Pstates are signed, but our register access macros operate on unsigned
-/// values.  To avoid bugs, Pstate register fields should always be extracted
-/// to a variable of type Pstate.  If the size of Pstate variables ever
-/// changes we will have to revisit this convention.
-typedef int8_t Pstate;
-
-/// A DPLL frequency code
-///
-/// DPLL frequency codes moved from 8 to 9 bits going from P7 to P8
-typedef uint16_t DpllCode;
-
-/// A VRM11 VID code
-typedef uint8_t Vid11;
-
-#endif  /* __ASSEMBLER__ */
-
-/// The minimum Pstate
-#define PSTATE_MIN -128
-
-/// The maximum Pstate
-#define PSTATE_MAX 127
-
-/// The minimum \e legal DPLL frequency code
-///
-/// This is ~1GHz with a 33.3MHz tick frequency.
-#define DPLL_MIN 0x01e
-
-/// The maximum DPLL frequency code
-#define DPLL_MAX 0x1ff
-
-/// The minimum \a legal (non-power-off) VRM11 VID code
-#define VID11_MIN 0x02
-
-/// The maximum \a legal (non-power-off) VRM11 VID code
-#define VID11_MAX 0xfd
-
-
-////////////////////////////////////////////////////////////////////////////
-// PCB
-////////////////////////////////////////////////////////////////////////////
-
-/// Convert a core chiplet 0 SCOM address to the equivalent address for any
-/// other core chiplet.
-///
-/// Note that it is unusual to address core chiplet SCOMs directly.  Normally
-/// this is done as part of a GPE program where the program iterates over core
-/// chiplets, using the chiplet-0 address + a programmable offset held in a
-/// chiplet address register.  Therefore the only address macro defined is the
-/// chiplet-0 address. This macro is used for the rare cases of explicit
-/// getscom()/ putscom() to a particular chiplet.
-
-#define CORE_CHIPLET_ADDRESS(addr, core) ((addr) + ((core) << 24))
-
-
-// PCB Error codes
-
-#define PCB_ERROR_NONE              0
-#define PCB_ERROR_RESOURCE_OCCUPIED 1
-#define PCB_ERROR_CHIPLET_OFFLINE   2
-#define PCB_ERROR_PARTIAL_GOOD      3
-#define PCB_ERROR_ADDRESS_ERROR     4
-#define PCB_ERROR_CLOCK_ERROR       5
-#define PCB_ERROR_PACKET_ERROR      6
-#define PCB_ERROR_TIMEOUT           7
-
-// PCB Multicast modes
-
-#define PCB_MULTICAST_OR      0
-#define PCB_MULTICAST_AND     1
-#define PCB_MULTICAST_SELECT  2
-#define PCB_MULTICAST_COMPARE 4
-#define PCB_MULTICAST_WRITE   5
-
-/// \defgroup pcb_multicast_groups PCB Multicast Groups
-///
-/// Technically the multicast groups are programmable; This is the multicast
-/// grouping established by proc_sbe_chiplet_init().
-///
-/// - Group 0 : All functional chiplets (PRV PB XBUS ABUS PCIE TPCEX)
-/// - Group 1 : All functional EX chiplets (no cores)
-/// - Group 2 : All functional EX chiplets (core only)
-/// - Group 3 : All functional chiplets except pervasive (PRV)
-///
-/// @{
-
-#define MC_GROUP_ALL         0
-#define MC_GROUP_EX          1
-#define MC_GROUP_EX_CORE     2
-#define MC_GROUP_ALL_BUT_PRV 3
-
-/// @}
-
-
-/// Convert any SCOM address to a multicast address
-#define MC_ADDRESS(address, group, mode) \
-    (((address) & 0x00ffffff) | ((0x40 | ((mode) << 3) | (group)) << 24))
-
-
-
-////////////////////////////////////////////////////////////////////////////
-// PBA
-////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////
-// Macros for fields of PBA_MODECTL
-////////////////////////////////////
-
-/// The 64KB OCI HTM marker space is enabled by default at 0x40070000
-///
-/// See the comments for pgp_trace.h
-
-#define PBA_OCI_MARKER_BASE 0x40070000
-
-
-// SSX Kernel reserved trace addresses, see pgp_trace.h.
-
-#define SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE           0xf000
-#define SSX_TRACE_CRITICAL_IRQ_EXIT_BASE            0xf100
-#define SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE        0xf200
-#define SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE         0xf300
-#define SSX_TRACE_THREAD_SWITCH_BASE                0xf400
-#define SSX_TRACE_THREAD_SLEEP_BASE                 0xf500
-#define SSX_TRACE_THREAD_WAKEUP_BASE                0xf600
-#define SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE        0xf700
-#define SSX_TRACE_THREAD_SEMAPHORE_POST_BASE        0xf800
-#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE     0xf900
-#define SSX_TRACE_THREAD_SUSPENDED_BASE             0xfa00
-#define SSX_TRACE_THREAD_DELETED_BASE               0xfb00
-#define SSX_TRACE_THREAD_COMPLETED_BASE             0xfc00
-#define SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE       0xfd00
-#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE 0xfe00
-#define SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE       0xff00
-
-
-// Please keep the string definitions up to date as they are used for
-// reporting in the Simics simulation.
-
-#define SSX_TRACE_STRINGS(var)                  \
-    const char* var[16] = {                     \
-        "Critical IRQ Entry             ",      \
-        "Critical IRQ Exit              ",      \
-        "Noncritical IRQ Entry          ",      \
-        "Noncritical IRQ Exit           ",      \
-        "Thread Switch                  ",      \
-        "Thread Blocked : Sleep         ",      \
-        "Thread Unblocked : Wakeup      ",      \
-        "Thread Blocked : Semaphore     ",      \
-        "Thread Unblocked : Semaphore   ",      \
-        "Thread Unblocked : Sem. Timeout",      \
-        "Thread Suspended               ",      \
-        "Thread Deleted                 ",      \
-        "Thread Completed               ",      \
-        "Thread Mapped Runnable         ",      \
-        "Thread Mapped Semaphore Pend.  ",      \
-        "Thread Mapped Sleeping         ",      \
-    };
-
-
-// PBA transaction sizes for the block copy engines
-
-#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0
-#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1
-#define PBA_BCE_OCI_TRANSACTION_8_BYTES  2
-
-
-// PBAX communication channel constants
-
-#define PBAX_CHANNELS 2
-
-#define PBAX_INTR_ACTION_FULL      0
-#define PBAX_INTR_ACTION_NOT_FULL  1
-#define PBAX_INTR_ACTION_EMPTY     2
-#define PBAX_INTR_ACTION_NOT_EMPTY 3
-
-
-// PBA Write Buffer fields
-
-#define PBA_WBUFVALN_STATUS_EMPTY     0x01
-#define PBA_WBUFVALN_STATUS_GATHERING 0x02
-#define PBA_WBUFVALN_STATUS_WAIT      0x04
-#define PBA_WBUFVALN_STATUS_WRITING   0x08
-#define PBA_WBUFVALN_STATUS_CRESPERR  0x10
-
-
-////////////////////////////////////////////////////////////////////////////
-// VRM
-////////////////////////////////////////////////////////////////////////////
-
-// These are the command types recognized by the VRMs
-
-#define VRM_WRITE_VOLTAGE  0x0
-#define VRM_READ_STATE     0xc
-#define VRM_READ_VOLTAGE   0x3
-
-// Voltage rail designations for the read voltage command
-#define VRM_RD_VDD_RAIL    0x0
-#define VRM_RD_VCS_RAIL    0x1
-
-
-////////////////////////////////////////////////////////////////////////////
-// OHA
-////////////////////////////////////////////////////////////////////////////
-
-// Power proxy trace record idle state encodings.  These encodings are unique
-// to the Power proxy trace record.
-
-#define PPT_IDLE_NON_IDLE     0x0
-#define PPT_IDLE_NAP          0x1
-#define PPT_IDLE_LIGHT_SLEEP  0x2
-#define PPT_IDLE_FAST_SLEEP   0x3
-#define PPT_IDLE_DEEP_SLEEP   0x4
-#define PPT_IDLE_LIGHT_WINKLE 0x5
-#define PPT_IDLE_FAST_WINKLE  0x6
-#define PPT_IDLE_DEEP_WINKLE  0x7
-
-
-////////////////////////////////////////////////////////////////////////////
-// PC
-////////////////////////////////////////////////////////////////////////////
-
-// SPRC numbers for PC counters.  The low-order 3 bits are always defined as
-// 0. The address can also be modified by OR-ing in 0x400 to indicate
-// auto-increment addressing.  Note that the frequency-sensitivity counters
-// are called "workrate" counters in the hardware documentation.
-//
-// Notes on the throttle counters:
-//
-// SPRN_IFU_THROTTLE_COUNTER
-//     Cycles the IFU throttle was actually blocking fetch
-//
-//     <= if_pc_didt_throttle_blocked
-//
-// SPRN_ISU_THROTTLE_COUNTER
-//     Cycles that ISU throttle was active and modeably IFU throttle request
-//     was not
-//
-//     <= sd_pc_uthrottle_active AND 
-//        (NOT scom_isuonly_count_mode OR NOT trigger_didt_throttle)
-//
-// SPRN_IFU_ACTIVE_COUNTER
-//     Cycles that IFU throttle active input is asserted
-//
-//     <= if_pc_didt_throttle_active
-
-
-/// \note The OCC SPRC/SPRD hardware has a bug that makes it such that the OCC
-/// SPRC increments whenever the OCC SPRD is accessed, regardless of the
-/// setting of the SPRN_PC_AUTOINCREMENT bit. This bug won't be fixed.
-
-#define SPRN_CORE_INSTRUCTION_DISPATCH         0x200
-#define SPRN_CORE_INSTRUCTION_COMPLETE         0x208
-#define SPRN_CORE_FREQUENCY_SENSITIVITY_BUSY   0x210
-#define SPRN_CORE_FREQUENCY_SENSITIVITY_FINISH 0x218
-#define SPRN_CORE_RUN_CYCLE                    0x220
-#define SPRN_CORE_RAW_CYCLE                    0x228
-#define SPRN_CORE_MEM_HIER_A                   0x230
-#define SPRN_CORE_MEM_HIER_B                   0x238
-#define SPRN_CORE_MEM_C_LPAR(p)                (0x240 + (8 * (p)))
-#define SPRN_WEIGHTED_INSTRUCTION_PROCESSING   0x260
-#define SPRN_WEIGHTED_GPR_REGFILE_ACCESS       0x268
-#define SPRN_WEIGHTED_VRF_REGFILE_ACCESS       0x270
-#define SPRN_WEIGHTED_FLOATING_POINT_ISSUE     0x278
-#define SPRN_WEIGHTED_CACHE_READ               0x280
-#define SPRN_WEIGHTED_CACHE_WRITE              0x288
-#define SPRN_WEIGHTED_ISSUE                    0x290
-#define SPRN_WEIGHTED_CACHE_ACCESS             0x298
-#define SPRN_WEIGHTED_VSU_ISSUE                0x2a0
-#define SPRN_WEIGHTED_FXU_ISSUE                0x2a8
-
-#define SPRN_THREAD_RUN_CYCLES(t)              (0x2b0 + (0x20 * (t)))
-#define SPRN_THREAD_INSTRUCTION_COMPLETE(t)    (0x2b8 + (0x20 * (t)))
-#define SPRN_THREAD_MEM_HIER_A(t)              (0x2c0 + (0x20 * (t)))
-#define SPRN_THREAD_MEM_HIER_B(t)              (0x2c8 + (0x20 * (t)))
-
-#define SPRN_IFU_THROTTLE_COUNTER              0x3b0
-#define SPRN_ISU_THROTTLE_COUNTER              0x3b8
-#define SPRN_IFU_ACTIVE_COUNTER                0x3c0
-
-#define SPRN_PC_AUTOINCREMENT                  0x400
-
-
-////////////////////////////////////////////////////////////////////////////
-// Centaur
-////////////////////////////////////////////////////////////////////////////
-
-// DIMM sensor status codes
-
-/// The next sampling period began before this sensor was read or the master
-/// enable is off, or the individual sensor is disabled. If the subsequent
-/// read completes on time, this will return to valid reading. Sensor data may
-/// be accurate, but stale.  If due to a stall, the StallError FIR will be
-/// set.
-#define DIMM_SENSOR_STATUS_STALLED 0
-
-/// The sensor data was not returned correctly either due to parity
-/// error or PIB bus error code. Will return to valid if the next PIB
-/// access to this sensor is valid, but a FIR will be set; Refer to FIR
-/// for exact error. Sensor data should not be considered valid while
-/// this code is present.
-#define DIMM_SENSOR_STATUS_ERROR 1
-
-/// Sensor data is valid, and has been valid since the last time this
-/// register was read.
-#define DIMM_SENSOR_STATUS_VALID_OLD 2
-
-/// Sensor data is valid and has not yet been read by a SCOM. The status code
-/// return to DIMM_SENSOR_STATUS_VALID_OLD after this register is read.
-#define DIMM_SENSOR_STATUS_VALID_NEW 3
-
-
-#endif  /* __PGP_COMMON_H__ */
diff --git a/src/ssx/pgp/pgp_core.h b/src/ssx/pgp/pgp_core.h
deleted file mode 100755
index 59edb26..0000000
--- a/src/ssx/pgp/pgp_core.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __PGP_CORE_H__
-#define __PGP_CORE_H__
-
-// $Id: pgp_core.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_core.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_core.h
-/// \brief PgP core units header.  Local and mechanically generated macros.
-
-#include "pc_register_addresses.h"
-#include "pc_firmware_registers.h"
-#include "sensors_register_addresses.h"
-#include "sensors_firmware_registers.h"
-
-#endif  /* __PGP_CORE_H__ */
diff --git a/src/ssx/pgp/pgp_ocb.h b/src/ssx/pgp/pgp_ocb.h
deleted file mode 100755
index fd36c9a..0000000
--- a/src/ssx/pgp/pgp_ocb.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef __PGP_OCB_H__
-#define __PGP_OCB_H__
-
-// $Id: pgp_ocb.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_ocb.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_ocb.h
-/// \brief OCB unit header.  Local and mechanically generated macros and APIs.
-
-#include "ssx.h"
-#include "ppc32.h"
-
-#include "pgp_common.h"
-#include "ocb_register_addresses.h"
-#include "ocb_firmware_registers.h"
-
-#include "ppc405_irq.h"
-
-#define OCB_TIMER0 0
-#define OCB_TIMER1 1
-
-#define OCB_TIMERS 2
-
-#define OCB_TIMER_ONE_SHOT    0
-#define OCB_TIMER_AUTO_RELOAD 1
-
-#define OCB_LW_LOG_SIZE_MIN 3
-#define OCB_LW_LOG_SIZE_MAX 15
-
-#define OCB_INVALID_ARGUMENT_TIMER         0x00622001
-#define OCB_INVALID_ARGUMENT_LW_INIT       0x00622002
-#define OCB_INVALID_ARGUMENT_LW_DISABLE    0x00622003
-#define OCB_INVALID_ARGUMENT_UNTRUST       0x00622004
-
-#ifndef __ASSEMBLER__
-
-int 
-ocb_timer_reset(int timer, 
-                int auto_reload,
-                int timeout_ns);
-
-#ifdef OCC
-int
-ocb_timer_setup(int timer, 
-                int auto_reload,
-                int timeout_ns,
-                SsxIrqHandler handler,
-                void *arg,
-                int priority) INIT_SECTION;
-#else
-int
-ocb_timer_setup(int timer,
-        int auto_reload,
-        int timeout_ns,
-        SsxIrqHandler handler,
-        void *arg,
-        int priority);
-#endif
-
-/// Clear OCB timer status based on the IRQ
-///
-/// This API can be called from OCB timer interrupt handlers, using the IRQ
-/// provided to the handler.  No error checks are provided.
-
-static inline void
-ocb_timer_status_clear(SsxIrqId irq)
-{
-    out32(OCB_OTRN(irq - PGP_IRQ_OCC_TIMER0), OCB_OTRN_TIMEOUT);
-}
-
-int
-ocb_linear_window_initialize(int channel, uint32_t base, int log_size);
-
-int
-ocb_linear_window_disable(int channel);
-
-int
-ocb_allow_untrusted_initialize(int channel, int allow_untrusted);
-    
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __PGP_OCB_H__ */
diff --git a/src/ssx/pgp/pgp_pore.h b/src/ssx/pgp/pgp_pore.h
deleted file mode 100755
index e40ccac..0000000
--- a/src/ssx/pgp/pgp_pore.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef __PGP_PORE_H__
-#define __PGP_PORE_H__
-
-// $Id: pgp_pore.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pore.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_pore.h
-/// \brief PORE unit header.  Local and mechanically generated macros.
-
-#include "pore_register_addresses.h"
-#include "pore_firmware_registers.h"
-
-/// The parameter for GPE-protocol triggering is the low-order word of the
-/// EXE_TRIGGER register
-#define PORE_EXE_PARAMETER_OFFSET (PORE_EXE_TRIGGER_OFFSET + 4)
-
-/// The PORE OCI address space descriptor 
-#define PORE_ADDRESS_SPACE_OCI 0x8000
-
-/// The PORE BRAI opcode
-#define PORE_BRAI 0xa2000000
-
-/// The PORE BRAD D0 opcode
-#define PORE_BRAD_D0 0x38500000
-
-
-#ifndef __ASSEMBLER__
-
-/// The putative type of PORE program entry points - to make GCC happy
-typedef void *(PoreEntryPoint)(void);
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __PGP_PORE_H__ */
diff --git a/src/ssx/pgp/pgp_sramctl.h b/src/ssx/pgp/pgp_sramctl.h
deleted file mode 100755
index fe2ed69..0000000
--- a/src/ssx/pgp/pgp_sramctl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __PGP_SRAMCTL_H__
-#define __PGP_SRAMCTL_H__
-
-// $Id: pgp_sramctl.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_sramctl.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_sramctl.h
-/// \brief SRAMCTL unit header.  Local and mechanically generated macros.
-
-#include "sramctl_register_addresses.h"
-#include "sramctl_firmware_registers.h"
-
-#endif  /* __PGP_SRAMCTL_H__ */
diff --git a/src/ssx/pgp/pgp_trace.h b/src/ssx/pgp/pgp_trace.h
deleted file mode 100755
index 3544ce0..0000000
--- a/src/ssx/pgp/pgp_trace.h
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef __PGP_TRACE_H__
-#define __PGP_TRACE_H__
-
-// $Id: pgp_trace.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_trace.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_trace.h
-/// \brief Implementation of SSX_TRACE macros for PgP
-///
-/// Kernel and application tracing uses the PBA "OCI Marker Space", a 64KB OCI
-/// register space implemented by PBA. When enabled in the PBA, any OCI write
-/// transactions of any size are ACK'ed by the PBA and the data is ignored.
-/// This creates an OCI transaction record that can be captured by the NHTM
-/// for later analysis.
-///
-/// SSX provides a generic SSX_TRACE() macro that accepts a single
-/// parameter. On PgP, valid parameters are integers in the range
-/// 0x0,...,0xffff.  The PgP SSX kernel reserves trace addresses
-/// 0xe000,...,0xffff for kernel event traces. Applications are free to use
-/// the other trace addresses in the range 0x0000,...,0xdfff as they see fit.
-///
-/// Application tracing is globally disabled by default, and is enabled by
-/// defining the switch SSX_TRACE_ENABLE=1.  Kernel event tracing is also
-/// globally disabled by default, and is enabled by defining the switch
-/// SSX_KERNEL_TRACE_ENABLE=1. Kernel event tracing adds overhead to every
-/// interrupt handler and kernel API so should probably remain disabled unless
-/// required.
-///
-/// The Simics PBA model supports trace reporting, either to stdout or to a
-/// file. To enable trace reporting set pba->trace_report = 1. To capture
-/// traces to a file other than stdout, set pba->trace_file = \<filename\>.  The
-/// Simics model understands SSX kernel trace events and produces a readable
-/// commentary of kernel traces events - user events will be reported simply
-/// as the integer tag.
-
-#include "pgp_common.h"
-
-/// Output an OCI Trace Marker
-///
-/// See the comments for the file pgp_trace.h
-
-#if SSX_TRACE_ENABLE
-#define SSX_TRACE(event) out8(PBA_OCI_MARKER_BASE + (event), 0)
-#endif
-
-#if SSX_KERNEL_TRACE_ENABLE
-
-// Note: The *BASE constants are defined in pgp_common.h
-
-#define SSX_KERNEL_TRACE(event) out8(PBA_OCI_MARKER_BASE + (event), 0)
-
-#define SSX_TRACE_THREAD_SLEEP(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SLEEP_BASE + priority)
-
-#define SSX_TRACE_THREAD_WAKEUP(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_WAKEUP_BASE + priority)
-
-#define SSX_TRACE_THREAD_SEMAPHORE_PEND(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE + priority)
-
-#define SSX_TRACE_THREAD_SEMAPHORE_POST(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_POST_BASE + priority)
-
-#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE + priority)
-
-#define SSX_TRACE_THREAD_SUSPENDED(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SUSPENDED_BASE + priority)
-
-#define SSX_TRACE_THREAD_DELETED(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_DELETED_BASE + priority)
-
-#define SSX_TRACE_THREAD_COMPLETED(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_COMPLETED_BASE + priority)
-
-#define SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE + priority)
-
-#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE + priority)
-
-#define SSX_TRACE_THREAD_MAPPED_SLEEPING(priority) \
-    SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE + priority)
-
-#endif  /* SSX_KERNEL_TRACE_ENABLE */
-
-
-#ifdef __ASSEMBLER__
-
-// NB: CPP macros are not expanded as arguments to .if in GAS macro
-// definitions.  That's why e.g. we have to use _liw instead of _liwa.
-
-#if SSX_KERNEL_TRACE_ENABLE
-
-        .macro  SSX_TRACE_CRITICAL_IRQ_ENTRY, irqreg, scratch
-        _liw    \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE)
-        stbx    \irqreg, \irqreg, \scratch
-        eieio
-        .endm
-
-        .macro  SSX_TRACE_CRITICAL_IRQ_EXIT, scratch0, scratch1
-        _liw    \scratch0, (PBA_OCI_MARKER_BASE + SSX_TRACE_CRITICAL_IRQ_EXIT_BASE)
-        mfusprg0 \scratch1
-        extrwi  \scratch1, \scratch1, 8, 16
-        stbx    \scratch1, \scratch0, \scratch1
-        eieio
-        .endm
-
-        .macro  SSX_TRACE_NONCRITICAL_IRQ_ENTRY, irqreg, scratch
-        _liw    \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE)
-        stbx    \irqreg, \irqreg, \scratch
-        eieio
-        .endm
-
-        .macro  SSX_TRACE_NONCRITICAL_IRQ_EXIT, scratch0, scratch1
-        _liw    \scratch0, (PBA_OCI_MARKER_BASE + SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE)
-        mfusprg0 \scratch1
-        extrwi  \scratch1, \scratch1, 8, 16
-        stbx    \scratch1, \scratch0, \scratch1
-        eieio
-        .endm
-
-        .macro  SSX_TRACE_THREAD_SWITCH, priority, scratch
-        _liw    \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_THREAD_SWITCH_BASE)
-        stbx    \priority, \priority, \scratch
-        eieio
-        .endm
-
-#else  /* SSX_KERNEL_TRACE_ENABLE */
-
-        .macro  SSX_TRACE_CRITICAL_IRQ_ENTRY, irq, scratch
-        .endm
-
-        .macro  SSX_TRACE_CRITICAL_IRQ_EXIT, scratch0, scratch1
-        .endm
-
-        .macro  SSX_TRACE_NONCRITICAL_IRQ_ENTRY, irq, scratch
-        .endm
-
-        .macro  SSX_TRACE_NONCRITICAL_IRQ_EXIT, scratch0, scratch1
-        .endm
-
-        .macro  SSX_TRACE_THREAD_SWITCH, priority, scratch
-        .endm
-
-#endif  /* SSX_KERNEL_TRACE_ENABLE */
-             
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __PGP_TRACE_H__ */
diff --git a/src/ssx/pgp/pgp_vrm.h b/src/ssx/pgp/pgp_vrm.h
deleted file mode 100755
index aaa6760..0000000
--- a/src/ssx/pgp/pgp_vrm.h
+++ /dev/null
@@ -1,223 +0,0 @@
-#ifndef __PGP_VRM_H__
-#define __PGP_VRM_H__
-
-// $Id: pgp_vrm.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_vrm.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pgp_vrm.h
-/// \brief Header for PgP VRM device drivers.  Some constants are also held in
-/// pgp_common.h.
-
-#include "pgp_common.h"
-
-
-#ifndef __ASSEMBLER__
-
-/// VRM Command Header
-///
-/// This structure defines the values written on the SPI interface for
-/// 'read' commands.
-
-//typedef union {
-//    uint64_t value;
-//    uint32_t word[2];
-//    struct {
-//      uint64_t address : 4;
-//      uint64_t command : 4;
-//    } fields;
-//} vrm_command_t;
-
-
-/// VRM Write Transaction Command 
-///
-/// The 8-bit \a phase_enable is an 8-bit VRM-11 VID code 
-///
-/// The 8-bit \a vcs_offset is an 8-bit signed offset
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t command      : 4;
-        uint64_t phase_enable : 4;
-        uint64_t vdd_vid      : 8;
-        uint64_t vcs_offset   : 8;
-        uint64_t master_crc   : 8;
-    } fields;
-} vrm_write_transaction_t;
-        
-
-/// VRM Write Transaction Response
-/// writes status is duplicated 3x for the minority detect feature.
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t write_status0 : 8;
-        uint64_t write_status1 : 8;
-        uint64_t write_status2 : 8;
-        uint64_t optional_crc  : 8;
-    } fields;
-} vrm_write_resp_t;
-
-
-
-/// VRM Read State Command
-///  reserved field should be sent as 0s
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t command    : 4;
-        uint64_t reserved   : 20;
-        uint64_t master_crc : 8;
-    } fields;
-} vrm_read_state_t;
-        
-
-/// VRM Read State Response
-/// Results are duplicated 3x for the minority detecte feature.
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t read_ready0    : 1;
-        uint64_t minus_nplus1_0 : 1;
-        uint64_t minus_n0       : 1;
-        uint64_t reserved1_0    : 1;
-        uint64_t vrm_fan0       : 1;
-        uint64_t vrm_overtemp0  : 1;
-        uint64_t reserved2_0    : 2;
-        uint64_t read_ready1    : 1;
-        uint64_t minus_nplus1_1 : 1;
-        uint64_t minus_n1       : 1;
-        uint64_t reserved1_1    : 1;
-        uint64_t vrm_fan1       : 1;
-        uint64_t vrm_overtemp1  : 1;
-        uint64_t reserved2_1    : 2;
-        uint64_t read_ready2    : 1;
-        uint64_t minus_nplus1_2 : 1;
-        uint64_t minus_n2       : 1;
-        uint64_t reserved1_2    : 1;
-        uint64_t vrm_fan2       : 1;
-        uint64_t vrm_overtemp2  : 1;
-        uint64_t reserved2_2    : 2;
-        uint64_t slave_crc      : 8;
-    } fields;
-} vrm_read_state_resp_t;
-
-/// VRM Read Voltage Command
-///  reserved field should be sent as 0s
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t command    : 4;
-        uint64_t rail       : 4;
-        uint64_t reserved   : 1;
-        uint64_t master_crc : 8;
-    } fields;
-} vrm_read_voltage_t;
-        
-
-/// VRM Read Voltage Response
-/// Results are duplicated 3x for the minority detect feature.
-
-typedef union {
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-        uint64_t vid0 : 8;
-        uint64_t vid1 : 8;
-        uint64_t vid2 : 8;
-        uint64_t slave_crc : 8;
-    } fields;
-} vrm_read_voltage_resp_t;
-
-
-/// VRM Read Current 1 Response
-///
-/// The 16-bit current readings come from 12-bit DACS; the DAC output is
-/// right-padded with 0b0000.  The current units are 0.025 Ampere.
-
-//typedef union {
-//    uint64_t value;
-//    uint32_t word[2];
-//    struct {
-//      uint64_t header : 8;
-//      uint64_t read_not_ready : 1;
-//      uint64_t minus_nplus1 : 1;
-//      uint64_t minus_n : 1;
-//      uint64_t reserved0 : 1;
-//      uint64_t vrm_fan : 1;
-//      uint64_t vrm_overtemp : 1;
-//      uint64_t reserved1 : 2;
-//      uint64_t vdd_current : 16;
-//      uint64_t vcs_current : 16;
-//      uint64_t vio_current : 16;
-//   } fields;
-//} vrm_read_current_1_t;
-
-
-/// VRM Read Current 2 Response
-///
-/// The 16-bit current readings come from 12-bit DACS; the DAC output is
-/// right-padded with 0b0000.  The current units are 0.025 Ampere.
-
-//typedef union {
-//    uint64_t value;
-//    uint32_t word[2];
-//    struct {
-//      uint64_t header : 8;
-//      uint64_t read_not_ready : 1;
-//      uint64_t minus_nplus1 : 1;
-//      uint64_t minus_n : 1;
-//      uint64_t reserved0 : 1;
-//      uint64_t vrm_fan : 1;
-//      uint64_t vrm_overtemp : 1;
-//      uint64_t reserved1 : 2;
-//      uint64_t spare1_current : 16;
-//      uint64_t spare2_current : 16;
-//      uint64_t spare3_current : 16;
-//  } fields;
-//} vrm_read_current_2_t;
-
-#endif  /* __ASSEMBLER__ */
-
-// These are the default values for the SPIVRM/O2S interface
-
-#define SPIVRM_BITS 71          /* Actual # of bits minus 1 */
-#define SPIVRM_CPOL 0           /* Clock polarity */
-#define SPIVRM_CPHA 0           /* Clock phase */
-#define SPIVRM_FREQUENCY_HZ 16000000 /* 16 MHz */
-#define SPIVRM_ENABLE_ECC 1
-#define SPIVRM_NPORTS 3         /* Maximum # of ports supported by HW */
-#define SPIVRM_NRAILS 2         /* Maximum # of rails supported by read voltage cmd*/
-#define SPIVRM_ENABLED_PORTS 0x4 /* 3 bit mask, left justified */
-#define SPIVRM_PHASES 15        /* System dependent */
-
-/// Convert an integer index into a VRM designator (mask)
-#define SPIVRM_PORT(i) (1 << (SPIVRM_NPORTS - (i) - 1))
-
-// SPIVRM specific setup defaults
-
-#define SPIVRM_READ_STATUS_DELAY 48 /* Cycles, system dependent */
-#define SPIVRM_ADDRESS 0        /* First 4 bits of SPIVRM packet */
-
-// Default values for the O2S bridge
-
-#define O2S_BRIDGE_ENABLE 1
-#define O2S_READ_DELAY 48       /* Cycles, system dependent */
-#define O2S_ADDRESS 0           /* First 4 bits of O2S packet */
-
-
-#endif  /* __PGP_VRM_H__ */
diff --git a/src/ssx/pgp/registers/centaur_firmware_registers.h b/src/ssx/pgp/registers/centaur_firmware_registers.h
deleted file mode 100755
index 39f168f..0000000
--- a/src/ssx/pgp/registers/centaur_firmware_registers.h
+++ /dev/null
@@ -1,1496 +0,0 @@
-#ifndef __CENTAUR_FIRMWARE_REGISTERS_H__
-#define __CENTAUR_FIRMWARE_REGISTERS_H__
-
-// $Id: centaur_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file centaur_firmware_registers.h
-/// \brief C register structs for the CENTAUR unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union centaur_device_id {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cfam_id : 32;
-    uint64_t module_id : 2;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t module_id : 2;
-    uint64_t cfam_id : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_device_id_t;
-
-
-
-typedef union centaur_mbs_fir_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_reg_t;
-
-
-
-typedef union centaur_mbs_fir_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_reg_and_t;
-
-
-
-typedef union centaur_mbs_fir_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_reg_or_t;
-
-
-
-typedef union centaur_mbs_fir_mask_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_mask_reg_t;
-
-
-
-typedef union centaur_mbs_fir_mask_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_mask_reg_and_t;
-
-
-
-typedef union centaur_mbs_fir_mask_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_mask_reg_or_t;
-
-
-
-typedef union centaur_mbs_fir_action0_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_fir_action0_reg_t;
-
-
-
-typedef union centaur_mbs_firact1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t host_protocol_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t external_timeout : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t lru_error : 1;
-    uint64_t edram_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t internal_scom_error_copy : 1;
-    uint64_t internal_scom_error : 1;
-    uint64_t spare_fir31 : 1;
-    uint64_t spare_fir30 : 1;
-    uint64_t dir_purge_ce : 1;
-    uint64_t srb_buffer_sue : 1;
-    uint64_t srb_buffer_ue : 1;
-    uint64_t srb_buffer_ce : 1;
-    uint64_t occ_inband_write_error : 1;
-    uint64_t occ_inband_read_error : 1;
-    uint64_t host_inband_write_error : 1;
-    uint64_t host_inband_read_error : 1;
-    uint64_t emergency_throttle_set : 1;
-    uint64_t edram_error : 1;
-    uint64_t lru_error : 1;
-    uint64_t dir_all_members_deleted : 1;
-    uint64_t dir_member_deleted : 1;
-    uint64_t dir_ue : 1;
-    uint64_t dir_ce : 1;
-    uint64_t cache_co_sue : 1;
-    uint64_t cache_co_ue : 1;
-    uint64_t cache_co_ce : 1;
-    uint64_t cache_srw_sue : 1;
-    uint64_t cache_srw_ue : 1;
-    uint64_t cache_srw_ce : 1;
-    uint64_t int_parity_error : 1;
-    uint64_t int_buffer_sue : 1;
-    uint64_t int_buffer_ue : 1;
-    uint64_t int_buffer_ce : 1;
-    uint64_t internal_timeout : 1;
-    uint64_t external_timeout : 1;
-    uint64_t invalid_address_error : 1;
-    uint64_t int_protocol_error : 1;
-    uint64_t host_protocol_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbs_firact1_t;
-
-
-
-typedef union centaur_mbscfgq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t eccbp_exit_sel : 1;
-    uint64_t dram_ecc_bypass_dis : 1;
-    uint64_t mbs_scom_wat_trigger : 1;
-    uint64_t mbs_prq_ref_avoidance_en : 1;
-    uint64_t reserved4_6 : 3;
-    uint64_t occ_deadman_timer_sel : 4;
-    uint64_t sync_fsync_mba_strobe_en : 1;
-    uint64_t hca_timebase_op_mode : 1;
-    uint64_t hca_local_timer_inc_select : 3;
-    uint64_t mbs_01_rdtag_delay : 4;
-    uint64_t mbs_01_rdtag_force_dead_cycle : 1;
-    uint64_t sync_lat_pol_01 : 1;
-    uint64_t sync_lat_adj_01 : 2;
-    uint64_t mbs_23_rdtag_delay : 4;
-    uint64_t mbs_23_rdtag_force_dead_cycle : 1;
-    uint64_t sync_lat_pol_23 : 1;
-    uint64_t sync_lat_adj_23 : 2;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t sync_lat_adj_23 : 2;
-    uint64_t sync_lat_pol_23 : 1;
-    uint64_t mbs_23_rdtag_force_dead_cycle : 1;
-    uint64_t mbs_23_rdtag_delay : 4;
-    uint64_t sync_lat_adj_01 : 2;
-    uint64_t sync_lat_pol_01 : 1;
-    uint64_t mbs_01_rdtag_force_dead_cycle : 1;
-    uint64_t mbs_01_rdtag_delay : 4;
-    uint64_t hca_local_timer_inc_select : 3;
-    uint64_t hca_timebase_op_mode : 1;
-    uint64_t sync_fsync_mba_strobe_en : 1;
-    uint64_t occ_deadman_timer_sel : 4;
-    uint64_t reserved4_6 : 3;
-    uint64_t mbs_prq_ref_avoidance_en : 1;
-    uint64_t mbs_scom_wat_trigger : 1;
-    uint64_t dram_ecc_bypass_dis : 1;
-    uint64_t eccbp_exit_sel : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbscfgq_t;
-
-
-
-typedef union centaur_mbsemerthroq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t emergency_throttle_ip : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t emergency_throttle_ip : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbsemerthroq_t;
-
-
-
-typedef union centaur_mbsocc01hq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_01_rd_hit : 32;
-    uint64_t occ_01_wr_hit : 32;
-#else
-    uint64_t occ_01_wr_hit : 32;
-    uint64_t occ_01_rd_hit : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbsocc01hq_t;
-
-
-
-typedef union centaur_mbsocc23hq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_23_rd_hit : 32;
-    uint64_t occ_23_wr_hit : 32;
-#else
-    uint64_t occ_23_wr_hit : 32;
-    uint64_t occ_23_rd_hit : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbsocc23hq_t;
-
-
-
-typedef union centaur_mbsoccitcq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_cent_idle_th_cnt : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t occ_cent_idle_th_cnt : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbsoccitcq_t;
-
-
-
-typedef union centaur_mbsoccscanq {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_01_spec_can : 32;
-    uint64_t occ_23_spec_can : 32;
-#else
-    uint64_t occ_23_spec_can : 32;
-    uint64_t occ_01_spec_can : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbsoccscanq_t;
-
-
-
-typedef union centaur_mbarpc0qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cfg_lp2_entry_req : 1;
-    uint64_t cfg_lp2_state : 1;
-    uint64_t cfg_min_max_domains_enable : 1;
-    uint64_t cfg_min_max_domains : 3;
-    uint64_t cfg_pup_avail : 5;
-    uint64_t cfg_pdn_pup : 5;
-    uint64_t cfg_pup_pdn : 5;
-    uint64_t reserved0 : 1;
-    uint64_t cfg_min_domain_reduction_enable : 1;
-    uint64_t cfg_min_domain_reduction_on_time : 10;
-    uint64_t cfg_pup_after_activate_wait_enable : 1;
-    uint64_t cfg_pup_after_activate_wait_time : 8;
-    uint64_t cfg_force_spare_pup : 1;
-    uint64_t _reserved0 : 21;
-#else
-    uint64_t _reserved0 : 21;
-    uint64_t cfg_force_spare_pup : 1;
-    uint64_t cfg_pup_after_activate_wait_time : 8;
-    uint64_t cfg_pup_after_activate_wait_enable : 1;
-    uint64_t cfg_min_domain_reduction_on_time : 10;
-    uint64_t cfg_min_domain_reduction_enable : 1;
-    uint64_t reserved0 : 1;
-    uint64_t cfg_pup_pdn : 5;
-    uint64_t cfg_pdn_pup : 5;
-    uint64_t cfg_pup_avail : 5;
-    uint64_t cfg_min_max_domains : 3;
-    uint64_t cfg_min_max_domains_enable : 1;
-    uint64_t cfg_lp2_state : 1;
-    uint64_t cfg_lp2_entry_req : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbarpc0qn_t;
-
-
-
-typedef union centaur_mba_farb3qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cfg_nm_n_per_mba : 15;
-    uint64_t cfg_nm_n_per_chip : 16;
-    uint64_t cfg_nm_m : 14;
-    uint64_t cfg_nm_ras_weight : 3;
-    uint64_t cfg_nm_cas_weight : 3;
-    uint64_t cfg_nm_per_slot_enabled : 1;
-    uint64_t cfg_nm_count_other_mba_dis : 1;
-    uint64_t _reserved0 : 11;
-#else
-    uint64_t _reserved0 : 11;
-    uint64_t cfg_nm_count_other_mba_dis : 1;
-    uint64_t cfg_nm_per_slot_enabled : 1;
-    uint64_t cfg_nm_cas_weight : 3;
-    uint64_t cfg_nm_ras_weight : 3;
-    uint64_t cfg_nm_m : 14;
-    uint64_t cfg_nm_n_per_chip : 16;
-    uint64_t cfg_nm_n_per_mba : 15;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mba_farb3qn_t;
-
-
-
-typedef union centaur_mbapcn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t mode_hp_sub_cnt : 1;
-    uint64_t mode_lp_sub_cnt : 1;
-    uint64_t mode_static_idle_dly : 5;
-    uint64_t mode_emer_min_max_domain : 3;
-    uint64_t mode_pup_all_wr_pending : 2;
-    uint64_t mode_lp_ref_sim_enq : 1;
-    uint64_t _reserved0 : 51;
-#else
-    uint64_t _reserved0 : 51;
-    uint64_t mode_lp_ref_sim_enq : 1;
-    uint64_t mode_pup_all_wr_pending : 2;
-    uint64_t mode_emer_min_max_domain : 3;
-    uint64_t mode_static_idle_dly : 5;
-    uint64_t mode_lp_sub_cnt : 1;
-    uint64_t mode_hp_sub_cnt : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbapcn_t;
-
-
-
-typedef union centaur_mbasrqn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t emergency_m : 14;
-    uint64_t emergency_n : 15;
-    uint64_t _reserved0 : 35;
-#else
-    uint64_t _reserved0 : 35;
-    uint64_t emergency_n : 15;
-    uint64_t emergency_m : 14;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_mbasrqn_t;
-
-
-
-typedef union centaur_pmu0qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t read_count : 32;
-    uint64_t write_count : 32;
-#else
-    uint64_t write_count : 32;
-    uint64_t read_count : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu0qn_t;
-
-
-
-typedef union centaur_pmu1qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t activate_count : 32;
-    uint64_t pu_counts : 32;
-#else
-    uint64_t pu_counts : 32;
-    uint64_t activate_count : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu1qn_t;
-
-
-
-typedef union centaur_pmu2qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t frame_count : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t frame_count : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu2qn_t;
-
-
-
-typedef union centaur_pmu3qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t low_idle_threshold : 16;
-    uint64_t med_idle_threshold : 16;
-    uint64_t high_idle_threshold : 32;
-#else
-    uint64_t high_idle_threshold : 32;
-    uint64_t med_idle_threshold : 16;
-    uint64_t low_idle_threshold : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu3qn_t;
-
-
-
-typedef union centaur_pmu4qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t base_idle_count : 32;
-    uint64_t low_idle_count : 32;
-#else
-    uint64_t low_idle_count : 32;
-    uint64_t base_idle_count : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu4qn_t;
-
-
-
-typedef union centaur_pmu5qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t med_idle_count : 32;
-    uint64_t high_idle_count : 32;
-#else
-    uint64_t high_idle_count : 32;
-    uint64_t med_idle_count : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu5qn_t;
-
-
-
-typedef union centaur_pmu6qn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t total_gap_counts : 18;
-    uint64_t specific_gap_counts : 18;
-    uint64_t gap_length_adder : 3;
-    uint64_t specific_gap_condition : 4;
-    uint64_t cmd_to_cmd_count : 18;
-    uint64_t command_pattern_to_count : 3;
-#else
-    uint64_t command_pattern_to_count : 3;
-    uint64_t cmd_to_cmd_count : 18;
-    uint64_t specific_gap_condition : 4;
-    uint64_t gap_length_adder : 3;
-    uint64_t specific_gap_counts : 18;
-    uint64_t total_gap_counts : 18;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_pmu6qn_t;
-
-
-
-typedef union centaur_sensor_cache_data0_3 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t crittrip0 : 1;
-    uint64_t abovetrip0 : 1;
-    uint64_t belowtrip0 : 1;
-    uint64_t signbit0 : 1;
-    uint64_t temperature0 : 8;
-    uint64_t temp_frac0 : 2;
-    uint64_t status0 : 2;
-    uint64_t crittrip1 : 1;
-    uint64_t abovetrip1 : 1;
-    uint64_t belowtrip1 : 1;
-    uint64_t signbit1 : 1;
-    uint64_t temperature1 : 8;
-    uint64_t temp_frac1 : 2;
-    uint64_t status1 : 2;
-    uint64_t crittrip2 : 1;
-    uint64_t abovetrip2 : 1;
-    uint64_t belowtrip2 : 1;
-    uint64_t signbit2 : 1;
-    uint64_t temperature2 : 8;
-    uint64_t temp_frac2 : 2;
-    uint64_t status2 : 2;
-    uint64_t crittrip3 : 1;
-    uint64_t abovetrip3 : 1;
-    uint64_t belowtrip3 : 1;
-    uint64_t signbit3 : 1;
-    uint64_t temperature3 : 8;
-    uint64_t temp_frac3 : 2;
-    uint64_t status3 : 2;
-#else
-    uint64_t status3 : 2;
-    uint64_t temp_frac3 : 2;
-    uint64_t temperature3 : 8;
-    uint64_t signbit3 : 1;
-    uint64_t belowtrip3 : 1;
-    uint64_t abovetrip3 : 1;
-    uint64_t crittrip3 : 1;
-    uint64_t status2 : 2;
-    uint64_t temp_frac2 : 2;
-    uint64_t temperature2 : 8;
-    uint64_t signbit2 : 1;
-    uint64_t belowtrip2 : 1;
-    uint64_t abovetrip2 : 1;
-    uint64_t crittrip2 : 1;
-    uint64_t status1 : 2;
-    uint64_t temp_frac1 : 2;
-    uint64_t temperature1 : 8;
-    uint64_t signbit1 : 1;
-    uint64_t belowtrip1 : 1;
-    uint64_t abovetrip1 : 1;
-    uint64_t crittrip1 : 1;
-    uint64_t status0 : 2;
-    uint64_t temp_frac0 : 2;
-    uint64_t temperature0 : 8;
-    uint64_t signbit0 : 1;
-    uint64_t belowtrip0 : 1;
-    uint64_t abovetrip0 : 1;
-    uint64_t crittrip0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_sensor_cache_data0_3_t;
-
-
-
-typedef union centaur_sensor_cache_data4_7 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t crittrip4 : 1;
-    uint64_t abovetrip4 : 1;
-    uint64_t belowtrip4 : 1;
-    uint64_t signbit4 : 1;
-    uint64_t temperature4 : 8;
-    uint64_t temp_frac4 : 2;
-    uint64_t status4 : 2;
-    uint64_t crittrip5 : 1;
-    uint64_t abovetrip5 : 1;
-    uint64_t belowtrip5 : 1;
-    uint64_t signbit5 : 1;
-    uint64_t temperature5 : 8;
-    uint64_t temp_frac5 : 2;
-    uint64_t status5 : 2;
-    uint64_t crittrip6 : 1;
-    uint64_t abovetrip6 : 1;
-    uint64_t belowtrip6 : 1;
-    uint64_t signbit6 : 1;
-    uint64_t temperature6 : 8;
-    uint64_t temp_frac6 : 2;
-    uint64_t status6 : 2;
-    uint64_t crittrip7 : 1;
-    uint64_t abovetrip7 : 1;
-    uint64_t belowtrip7 : 1;
-    uint64_t signbit7 : 1;
-    uint64_t temperature7 : 8;
-    uint64_t temp_frac7 : 2;
-    uint64_t status7 : 2;
-#else
-    uint64_t status7 : 2;
-    uint64_t temp_frac7 : 2;
-    uint64_t temperature7 : 8;
-    uint64_t signbit7 : 1;
-    uint64_t belowtrip7 : 1;
-    uint64_t abovetrip7 : 1;
-    uint64_t crittrip7 : 1;
-    uint64_t status6 : 2;
-    uint64_t temp_frac6 : 2;
-    uint64_t temperature6 : 8;
-    uint64_t signbit6 : 1;
-    uint64_t belowtrip6 : 1;
-    uint64_t abovetrip6 : 1;
-    uint64_t crittrip6 : 1;
-    uint64_t status5 : 2;
-    uint64_t temp_frac5 : 2;
-    uint64_t temperature5 : 8;
-    uint64_t signbit5 : 1;
-    uint64_t belowtrip5 : 1;
-    uint64_t abovetrip5 : 1;
-    uint64_t crittrip5 : 1;
-    uint64_t status4 : 2;
-    uint64_t temp_frac4 : 2;
-    uint64_t temperature4 : 8;
-    uint64_t signbit4 : 1;
-    uint64_t belowtrip4 : 1;
-    uint64_t abovetrip4 : 1;
-    uint64_t crittrip4 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_sensor_cache_data4_7_t;
-
-
-
-typedef union centaur_dts_thermal_sensor_results {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts0 : 12;
-    uint64_t thermal_trip0 : 2;
-    uint64_t spare0 : 1;
-    uint64_t valid0 : 1;
-    uint64_t dts1 : 12;
-    uint64_t thermal_trip1 : 2;
-    uint64_t spare1 : 1;
-    uint64_t valid1 : 1;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t valid1 : 1;
-    uint64_t spare1 : 1;
-    uint64_t thermal_trip1 : 2;
-    uint64_t dts1 : 12;
-    uint64_t valid0 : 1;
-    uint64_t spare0 : 1;
-    uint64_t thermal_trip0 : 2;
-    uint64_t dts0 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} centaur_dts_thermal_sensor_results_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __CENTAUR_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/centaur_register_addresses.h b/src/ssx/pgp/registers/centaur_register_addresses.h
deleted file mode 100755
index 7c9c095..0000000
--- a/src/ssx/pgp/registers/centaur_register_addresses.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __CENTAUR_REGISTER_ADDRESSES_H__
-#define __CENTAUR_REGISTER_ADDRESSES_H__
-
-// $Id: centaur_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file centaur_register_addresses.h
-/// \brief Symbolic addresses for the CENTAUR unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define CENTAUR_PIB_BASE 0
-#define CENTAUR_DEVICE_ID 0x000f000f
-#define CENTAUR_MBS_FIR_REG 0x02011400
-#define CENTAUR_MBS_FIR_REG_AND 0x02011401
-#define CENTAUR_MBS_FIR_REG_OR 0x02011402
-#define CENTAUR_MBS_FIR_MASK_REG 0x02011403
-#define CENTAUR_MBS_FIR_MASK_REG_AND 0x02011404
-#define CENTAUR_MBS_FIR_MASK_REG_OR 0x02011405
-#define CENTAUR_MBS_FIR_ACTION0_REG 0x02011406
-#define CENTAUR_MBS_FIRACT1 0x02011407
-#define CENTAUR_MBSCFGQ 0x02011411
-#define CENTAUR_MBSEMERTHROQ 0x0201142d
-#define CENTAUR_MBSOCC01HQ 0x02011429
-#define CENTAUR_MBSOCC23HQ 0x0201142a
-#define CENTAUR_MBSOCCITCQ 0x02011428
-#define CENTAUR_MBSOCCSCANQ 0x0201142b
-#define CENTAUR_MBARPC0QN(n) (CENTAUR_MBARPC0Q0 + ((CENTAUR_MBARPC0Q1 - CENTAUR_MBARPC0Q0) * (n)))
-#define CENTAUR_MBARPC0Q0 0x03010434
-#define CENTAUR_MBARPC0Q1 0x03010c34
-#define CENTAUR_MBA_FARB3QN(n) (CENTAUR_MBA_FARB3Q0 + ((CENTAUR_MBA_FARB3Q1 - CENTAUR_MBA_FARB3Q0) * (n)))
-#define CENTAUR_MBA_FARB3Q0 0x03010416
-#define CENTAUR_MBA_FARB3Q1 0x03010c16
-#define CENTAUR_PMU0QN(n) (CENTAUR_PMU0Q0 + ((CENTAUR_PMU0Q1 - CENTAUR_PMU0Q0) * (n)))
-#define CENTAUR_PMU0Q0 0x03010437
-#define CENTAUR_PMU0Q1 0x03010c37
-#define CENTAUR_PMU1QN(n) (CENTAUR_PMU1Q0 + ((CENTAUR_PMU1Q1 - CENTAUR_PMU1Q0) * (n)))
-#define CENTAUR_PMU1Q0 0x03010438
-#define CENTAUR_PMU1Q1 0x03010c38
-#define CENTAUR_PMU2QN(n) (CENTAUR_PMU2Q0 + ((CENTAUR_PMU2Q1 - CENTAUR_PMU2Q0) * (n)))
-#define CENTAUR_PMU2Q0 0x03010439
-#define CENTAUR_PMU2Q1 0x03010c39
-#define CENTAUR_PMU3QN(n) (CENTAUR_PMU3Q0 + ((CENTAUR_PMU3Q1 - CENTAUR_PMU3Q0) * (n)))
-#define CENTAUR_PMU3Q0 0x0301043a
-#define CENTAUR_PMU3Q1 0x03010c3a
-#define CENTAUR_PMU4QN(n) (CENTAUR_PMU4Q0 + ((CENTAUR_PMU4Q1 - CENTAUR_PMU4Q0) * (n)))
-#define CENTAUR_PMU4Q0 0x0301043b
-#define CENTAUR_PMU4Q1 0x03010c3b
-#define CENTAUR_PMU5QN(n) (CENTAUR_PMU5Q0 + ((CENTAUR_PMU5Q1 - CENTAUR_PMU5Q0) * (n)))
-#define CENTAUR_PMU5Q0 0x0301043c
-#define CENTAUR_PMU5Q1 0x03010c3c
-#define CENTAUR_PMU6QN(n) (CENTAUR_PMU6Q0 + ((CENTAUR_PMU6Q1 - CENTAUR_PMU6Q0) * (n)))
-#define CENTAUR_PMU6Q0 0x0301043d
-#define CENTAUR_PMU6Q1 0x03010c3d
-#define CENTAUR_SENSOR_CACHE_DATA0_3 0x020115ca
-#define CENTAUR_SENSOR_CACHE_DATA4_7 0x020115cb
-#define CENTAUR_DTS_THERMAL_SENSOR_RESULTS 0x02050000
-
-#endif // __CENTAUR_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/fasti2c_firmware_registers.h b/src/ssx/pgp/registers/fasti2c_firmware_registers.h
deleted file mode 100644
index 4390508..0000000
--- a/src/ssx/pgp/registers/fasti2c_firmware_registers.h
+++ /dev/null
@@ -1,232 +0,0 @@
-#ifndef __FASTI2C_FIRMWARE_REGISTERS_H__
-#define __FASTI2C_FIRMWARE_REGISTERS_H__
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-// $Id: fasti2c_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-
-/// \file fasti2c_firmware_registers.h
-/// \brief C register structs for the FASTI2C unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#include <stdint.h>
-
-
-
-typedef union fasti2c_control {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t with_start : 1;
-	uint64_t with_address : 1;
-	uint64_t read_continue : 1;
-	uint64_t with_stop : 1;
-	uint64_t data_length : 4;
-	uint64_t device_address : 7;
-	uint64_t read_not_write : 1;
-	uint64_t speed : 2;
-	uint64_t port_number : 5;
-	uint64_t address_range : 3;
-	uint64_t _reserved0 : 6;
-	uint64_t data0 : 8;
-	uint64_t data1 : 8;
-	uint64_t data2 : 8;
-	uint64_t data3 : 8;
-#else
-	uint64_t data3 : 8;
-	uint64_t data2 : 8;
-	uint64_t data1 : 8;
-	uint64_t data0 : 8;
-	uint64_t _reserved0 : 6;
-	uint64_t address_range : 3;
-	uint64_t port_number : 5;
-	uint64_t speed : 2;
-	uint64_t read_not_write : 1;
-	uint64_t device_address : 7;
-	uint64_t data_length : 4;
-	uint64_t with_stop : 1;
-	uint64_t read_continue : 1;
-	uint64_t with_address : 1;
-	uint64_t with_start : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_control_t;
-
-
-
-typedef union fasti2c_reset {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_reset_t;
-
-
-
-typedef union fasti2c_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t pib_address_invalid : 1;
-	uint64_t pib_write_invalid : 1;
-	uint64_t pib_read_invalid : 1;
-	uint64_t pib_address_parity_error : 1;
-	uint64_t pib_parity_error : 1;
-	uint64_t lb_parity_error : 1;
-	uint64_t read_data : 32;
-	uint64_t _reserved0 : 6;
-	uint64_t i2c_macro_busy : 1;
-	uint64_t i2c_invalid_command : 1;
-	uint64_t i2c_parity_error : 1;
-	uint64_t i2c_back_end_overrun_error : 1;
-	uint64_t i2c_back_end_access_error : 1;
-	uint64_t i2c_arbitration_lost : 1;
-	uint64_t i2c_nack_received : 1;
-	uint64_t i2c_data_request : 1;
-	uint64_t i2c_command_complete : 1;
-	uint64_t i2c_stop_error : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t i2c_fifo_entry_count : 8;
-#else
-	uint64_t i2c_fifo_entry_count : 8;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t i2c_stop_error : 1;
-	uint64_t i2c_command_complete : 1;
-	uint64_t i2c_data_request : 1;
-	uint64_t i2c_nack_received : 1;
-	uint64_t i2c_arbitration_lost : 1;
-	uint64_t i2c_back_end_access_error : 1;
-	uint64_t i2c_back_end_overrun_error : 1;
-	uint64_t i2c_parity_error : 1;
-	uint64_t i2c_invalid_command : 1;
-	uint64_t i2c_macro_busy : 1;
-	uint64_t _reserved0 : 6;
-	uint64_t read_data : 32;
-	uint64_t lb_parity_error : 1;
-	uint64_t pib_parity_error : 1;
-	uint64_t pib_address_parity_error : 1;
-	uint64_t pib_read_invalid : 1;
-	uint64_t pib_write_invalid : 1;
-	uint64_t pib_address_invalid : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_status_t;
-
-
-
-typedef union fasti2c_data {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_data_t;
-
-
-
-typedef union fasti2c_ecc_start {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_ecc_start_t;
-
-
-
-typedef union fasti2c_ecc_stop {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} fasti2c_ecc_stop_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __FASTI2C_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/fasti2c_register_addresses.h b/src/ssx/pgp/registers/fasti2c_register_addresses.h
deleted file mode 100644
index b034831..0000000
--- a/src/ssx/pgp/registers/fasti2c_register_addresses.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __FASTI2C_REGISTER_ADDRESSES_H__
-#define __FASTI2C_REGISTER_ADDRESSES_H__
-
-// $Id: fasti2c_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-
-/// \file fasti2c_register_addresses.h
-/// \brief Symbolic addresses for the FASTI2C unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define FASTI2C_LPCM_PIB_BASE 0x0000000b
-#define FASTI2C_CONTROL_OFFSET 0x00000000
-#define FASTI2C_LPCM_CONTROL 0x0000000b
-#define FASTI2C_RESET_OFFSET 0x00000001
-#define FASTI2C_LPCM_RESET 0x0000000c
-#define FASTI2C_STATUS_OFFSET 0x00000002
-#define FASTI2C_LPCM_STATUS 0x0000000d
-#define FASTI2C_DATA_OFFSET 0x00000003
-#define FASTI2C_LPCM_DATA 0x0000000e
-#define FASTI2C_ECC_START_OFFSET 0x00000004
-#define FASTI2C_LPCM_ECC_START 0x0000000f
-#define FASTI2C_ECC_STOP_OFFSET 0x00000005
-#define FASTI2C_LPCM_ECC_STOP 0x00000010
-
-#endif // __FASTI2C_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/i2cengine_firmware_registers.h b/src/ssx/pgp/registers/i2cengine_firmware_registers.h
deleted file mode 100644
index ed02574..0000000
--- a/src/ssx/pgp/registers/i2cengine_firmware_registers.h
+++ /dev/null
@@ -1,710 +0,0 @@
-#ifndef __I2CENGINE_FIRMWARE_REGISTERS_H__
-#define __I2CENGINE_FIRMWARE_REGISTERS_H__
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-// $Id: i2cengine_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-
-/// \file i2cengine_firmware_registers.h
-/// \brief C register structs for the I2CENGINE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#include <stdint.h>
-
-
-
-typedef union i2cengine_fast_control {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t with_start : 1;
-	uint64_t with_address : 1;
-	uint64_t read_continue : 1;
-	uint64_t with_stop : 1;
-	uint64_t data_length : 4;
-	uint64_t device_address : 7;
-	uint64_t read_not_write : 1;
-	uint64_t speed : 2;
-	uint64_t port_number : 5;
-	uint64_t address_range : 3;
-	uint64_t _reserved0 : 6;
-	uint64_t data0 : 8;
-	uint64_t data1 : 8;
-	uint64_t data2 : 8;
-	uint64_t data3 : 8;
-#else
-	uint64_t data3 : 8;
-	uint64_t data2 : 8;
-	uint64_t data1 : 8;
-	uint64_t data0 : 8;
-	uint64_t _reserved0 : 6;
-	uint64_t address_range : 3;
-	uint64_t port_number : 5;
-	uint64_t speed : 2;
-	uint64_t read_not_write : 1;
-	uint64_t device_address : 7;
-	uint64_t data_length : 4;
-	uint64_t with_stop : 1;
-	uint64_t read_continue : 1;
-	uint64_t with_address : 1;
-	uint64_t with_start : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fast_control_t;
-
-
-
-typedef union i2cengine_fast_reset {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fast_reset_t;
-
-
-
-typedef union i2cengine_fast_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t pib_address_invalid : 1;
-	uint64_t pib_write_invalid : 1;
-	uint64_t pib_read_invalid : 1;
-	uint64_t pib_address_parity_error : 1;
-	uint64_t pib_parity_error : 1;
-	uint64_t lb_parity_error : 1;
-	uint64_t read_data : 32;
-	uint64_t _reserved0 : 6;
-	uint64_t i2c_macro_busy : 1;
-	uint64_t i2c_invalid_command : 1;
-	uint64_t i2c_parity_error : 1;
-	uint64_t i2c_back_end_overrun_error : 1;
-	uint64_t i2c_back_end_access_error : 1;
-	uint64_t i2c_arbitration_lost : 1;
-	uint64_t i2c_nack_received : 1;
-	uint64_t i2c_data_request : 1;
-	uint64_t i2c_command_complete : 1;
-	uint64_t i2c_stop_error : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t i2c_fifo_entry_count : 8;
-#else
-	uint64_t i2c_fifo_entry_count : 8;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t i2c_stop_error : 1;
-	uint64_t i2c_command_complete : 1;
-	uint64_t i2c_data_request : 1;
-	uint64_t i2c_nack_received : 1;
-	uint64_t i2c_arbitration_lost : 1;
-	uint64_t i2c_back_end_access_error : 1;
-	uint64_t i2c_back_end_overrun_error : 1;
-	uint64_t i2c_parity_error : 1;
-	uint64_t i2c_invalid_command : 1;
-	uint64_t i2c_macro_busy : 1;
-	uint64_t _reserved0 : 6;
-	uint64_t read_data : 32;
-	uint64_t lb_parity_error : 1;
-	uint64_t pib_parity_error : 1;
-	uint64_t pib_address_parity_error : 1;
-	uint64_t pib_read_invalid : 1;
-	uint64_t pib_write_invalid : 1;
-	uint64_t pib_address_invalid : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fast_status_t;
-
-
-
-typedef union i2cengine_fast_data {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t value : 64;
-#else
-	uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fast_data_t;
-
-
-
-typedef union i2cengine_fifo_byte {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t data : 32;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t data : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fifo_byte_t;
-
-
-
-typedef union i2cengine_command {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t with_start : 1;
-	uint64_t with_address : 1;
-	uint64_t read_continue : 1;
-	uint64_t not_used : 1;
-	uint64_t reserved : 4;
-	uint64_t device_address : 7;
-	uint64_t read_not_write : 1;
-	uint64_t length_bytes : 16;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t length_bytes : 16;
-	uint64_t read_not_write : 1;
-	uint64_t device_address : 7;
-	uint64_t reserved : 4;
-	uint64_t not_used : 1;
-	uint64_t read_continue : 1;
-	uint64_t with_address : 1;
-	uint64_t with_start : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_command_t;
-
-
-
-typedef union i2cengine_mode {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t bit_rate_divisor : 15;
-	uint64_t _reserved0 : 1;
-	uint64_t port_number : 6;
-	uint64_t reserved : 6;
-	uint64_t enhanced_mode : 1;
-	uint64_t diagnostic_mode : 1;
-	uint64_t pacing_allow_mode : 1;
-	uint64_t wrap_mode : 1;
-	uint64_t _reserved1 : 32;
-#else
-	uint64_t _reserved1 : 32;
-	uint64_t wrap_mode : 1;
-	uint64_t pacing_allow_mode : 1;
-	uint64_t diagnostic_mode : 1;
-	uint64_t enhanced_mode : 1;
-	uint64_t reserved : 6;
-	uint64_t port_number : 6;
-	uint64_t _reserved0 : 1;
-	uint64_t bit_rate_divisor : 15;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_mode_t;
-
-
-
-typedef union i2cengine_watermark {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved : 15;
-	uint64_t _reserved0 : 1;
-	uint64_t high_water_mark : 4;
-	uint64_t reserved1 : 4;
-	uint64_t low_water_mark : 4;
-	uint64_t reserved2 : 4;
-	uint64_t _reserved1 : 32;
-#else
-	uint64_t _reserved1 : 32;
-	uint64_t reserved2 : 4;
-	uint64_t low_water_mark : 4;
-	uint64_t reserved1 : 4;
-	uint64_t high_water_mark : 4;
-	uint64_t _reserved0 : 1;
-	uint64_t reserved : 15;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_watermark_t;
-
-
-
-typedef union i2cengine_interrupt_mask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved : 16;
-	uint64_t invalid_command : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t data_request : 1;
-	uint64_t command_complete : 1;
-	uint64_t stop_error : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t reserved1 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t sda_eq_0 : 1;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t sda_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t reserved1 : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t stop_error : 1;
-	uint64_t command_complete : 1;
-	uint64_t data_request : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t invalid_command : 1;
-	uint64_t reserved : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_interrupt_mask_t;
-
-
-
-typedef union i2cengine_interrupt_condition {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved : 16;
-	uint64_t invalid_command : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t data_request : 1;
-	uint64_t command_complete : 1;
-	uint64_t stop_error : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t reserved1 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t sda_eq_0 : 1;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t sda_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t reserved1 : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t stop_error : 1;
-	uint64_t command_complete : 1;
-	uint64_t data_request : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t invalid_command : 1;
-	uint64_t reserved : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_interrupt_condition_t;
-
-
-
-typedef union i2cengine_interrupts {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved : 16;
-	uint64_t invalid_command : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t data_request : 1;
-	uint64_t command_complete : 1;
-	uint64_t stop_error : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t reserved1 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t sda_eq_0 : 1;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t sda_eq_0 : 1;
-	uint64_t sda_eq_1 : 1;
-	uint64_t scl_eq_0 : 1;
-	uint64_t scl_eq_1 : 1;
-	uint64_t reserved1 : 1;
-	uint64_t not_i2c_busy : 1;
-	uint64_t i2c_busy : 1;
-	uint64_t stop_error : 1;
-	uint64_t command_complete : 1;
-	uint64_t data_request : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t invalid_command : 1;
-	uint64_t reserved : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_interrupts_t;
-
-
-
-typedef union i2cengine_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t invalid_command : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t data_request : 1;
-	uint64_t command_complete : 1;
-	uint64_t stop_error : 1;
-	uint64_t upper_threshold : 6;
-	uint64_t _reserved0 : 1;
-	uint64_t any_i2c_interrupt : 1;
-	uint64_t reserved1 : 3;
-	uint64_t scl_input_lvl : 1;
-	uint64_t sda_input_lvl : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t fifo_entry_count : 8;
-	uint64_t _reserved1 : 32;
-#else
-	uint64_t _reserved1 : 32;
-	uint64_t fifo_entry_count : 8;
-	uint64_t i2c_interface_busy : 1;
-	uint64_t i2c_port_busy : 1;
-	uint64_t sda_input_lvl : 1;
-	uint64_t scl_input_lvl : 1;
-	uint64_t reserved1 : 3;
-	uint64_t any_i2c_interrupt : 1;
-	uint64_t _reserved0 : 1;
-	uint64_t upper_threshold : 6;
-	uint64_t stop_error : 1;
-	uint64_t command_complete : 1;
-	uint64_t data_request : 1;
-	uint64_t nack_received_error : 1;
-	uint64_t arbitration_lost_error : 1;
-	uint64_t back_end_access_error : 1;
-	uint64_t back_end_overrun_error : 1;
-	uint64_t lbus_parity_error : 1;
-	uint64_t invalid_command : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_status_t;
-
-
-
-typedef union i2cengine_extended_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t table_base_addr : 32;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t table_base_addr : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_extended_status_t;
-
-
-
-typedef union i2cengine_residual_front_end_back_end_length {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t residual_front_end_length : 16;
-	uint64_t residual_back_end_length : 16;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t residual_back_end_length : 16;
-	uint64_t residual_front_end_length : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_residual_front_end_back_end_length_t;
-
-
-
-typedef union i2cengine_immediate_reset_s_scl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t residual_front_end_length : 16;
-	uint64_t residual_back_end_length : 16;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t residual_back_end_length : 16;
-	uint64_t residual_front_end_length : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_immediate_reset_s_scl_t;
-
-
-
-typedef union i2cengine_immediate_set_s_sda {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t residual_front_end_length : 16;
-	uint64_t residual_back_end_length : 16;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t residual_back_end_length : 16;
-	uint64_t residual_front_end_length : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_immediate_set_s_sda_t;
-
-
-
-typedef union i2cengine_immediate_reset_s_sda {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t field : 1;
-	uint64_t _reserved0 : 63;
-#else
-	uint64_t _reserved0 : 63;
-	uint64_t field : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_immediate_reset_s_sda_t;
-
-
-
-typedef union i2cengine_fifo_word {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t data : 32;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t data : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} i2cengine_fifo_word_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __I2CENGINE_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/i2cengine_register_addresses.h b/src/ssx/pgp/registers/i2cengine_register_addresses.h
deleted file mode 100644
index bbe9104..0000000
--- a/src/ssx/pgp/registers/i2cengine_register_addresses.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __I2CENGINE_REGISTER_ADDRESSES_H__
-#define __I2CENGINE_REGISTER_ADDRESSES_H__
-
-// $Id: i2cengine_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-
-/// \file i2cengine_register_addresses.h
-/// \brief Symbolic addresses for the I2CENGINE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define I2CENGINE_PIB_BASE 0x00000000
-#define I2CENGINE_FAST_CONTROL 0x00000000
-#define I2CENGINE_FAST_RESET 0x00000001
-#define I2CENGINE_FAST_STATUS 0x00000002
-#define I2CENGINE_FAST_DATA 0x00000003
-#define I2CENGINE_FIFO_BYTE 0x00000004
-#define I2CENGINE_COMMAND 0x00000005
-#define I2CENGINE_MODE 0x00000006
-#define I2CENGINE_WATERMARK 0x00000007
-#define I2CENGINE_INTERRUPT_MASK 0x00000008
-#define I2CENGINE_INTERRUPT_CONDITION 0x00000009
-#define I2CENGINE_INTERRUPTS 0x0000000a
-#define I2CENGINE_STATUS 0x0000000b
-#define I2CENGINE_EXTENDED_STATUS 0x0000000c
-#define I2CENGINE_RESIDUAL_FRONT_END_BACK_END_LENGTH 0x0000000d
-#define I2CENGINE_IMMEDIATE_RESET_S_SCL 0x0000000f
-#define I2CENGINE_IMMEDIATE_SET_S_SDA 0x00000010
-#define I2CENGINE_IMMEDIATE_RESET_S_SDA 0x00000011
-#define I2CENGINE_FIFO_WORD 0x00000012
-
-#endif // __I2CENGINE_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/icp_firmware_registers.h b/src/ssx/pgp/registers/icp_firmware_registers.h
deleted file mode 100755
index 4e17a68..0000000
--- a/src/ssx/pgp/registers/icp_firmware_registers.h
+++ /dev/null
@@ -1,189 +0,0 @@
-#ifndef __ICP_FIRMWARE_REGISTERS_H__
-#define __ICP_FIRMWARE_REGISTERS_H__
-
-// $Id: icp_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file icp_firmware_registers.h
-/// \brief C register structs for the ICP unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union icp_bar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t icp_bar : 30;
-    uint64_t icp_bar_en : 1;
-    uint64_t _reserved0 : 33;
-#else
-    uint64_t _reserved0 : 33;
-    uint64_t icp_bar_en : 1;
-    uint64_t icp_bar : 30;
-#endif // _BIG_ENDIAN
-    } fields;
-} icp_bar_t;
-
-#endif // __ASSEMBLER__
-#define ICP_BAR_ICP_BAR_MASK SIXTYFOUR_BIT_CONSTANT(0xfffffffc00000000)
-#define ICP_BAR_ICP_BAR_EN SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union icp_mode0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t priority : 8;
-    uint64_t reserved0 : 1;
-    uint64_t scope_initial : 3;
-    uint64_t reserved1 : 1;
-    uint64_t no_hang2status : 1;
-    uint64_t oper_disable_hang : 1;
-    uint64_t oper_hang_div : 5;
-    uint64_t reserved2 : 2;
-    uint64_t data_disable_hang : 1;
-    uint64_t data_hang_div : 5;
-    uint64_t backoff_disable : 1;
-    uint64_t fwd_que_fwd_conv_disable : 1;
-    uint64_t disa_wait4cresp_mode4ris : 1;
-    uint64_t disa_auto_no_retry4ris : 1;
-    uint64_t disa_retry_mode4ris : 1;
-    uint64_t hang_on_addr_error : 1;
-    uint64_t eoi_correction : 2;
-    uint64_t max_load_count : 4;
-    uint64_t max_store_count : 4;
-    uint64_t reserved3 : 3;
-    uint64_t enable_inject : 1;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t enable_inject : 1;
-    uint64_t reserved3 : 3;
-    uint64_t max_store_count : 4;
-    uint64_t max_load_count : 4;
-    uint64_t eoi_correction : 2;
-    uint64_t hang_on_addr_error : 1;
-    uint64_t disa_retry_mode4ris : 1;
-    uint64_t disa_auto_no_retry4ris : 1;
-    uint64_t disa_wait4cresp_mode4ris : 1;
-    uint64_t fwd_que_fwd_conv_disable : 1;
-    uint64_t backoff_disable : 1;
-    uint64_t data_hang_div : 5;
-    uint64_t data_disable_hang : 1;
-    uint64_t reserved2 : 2;
-    uint64_t oper_hang_div : 5;
-    uint64_t oper_disable_hang : 1;
-    uint64_t no_hang2status : 1;
-    uint64_t reserved1 : 1;
-    uint64_t scope_initial : 3;
-    uint64_t reserved0 : 1;
-    uint64_t priority : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} icp_mode0_t;
-
-#endif // __ASSEMBLER__
-#define ICP_MODE0_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000)
-#define ICP_MODE0_SCOPE_INITIAL_MASK SIXTYFOUR_BIT_CONSTANT(0x0070000000000000)
-#define ICP_MODE0_NO_HANG2STATUS SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define ICP_MODE0_OPER_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define ICP_MODE0_OPER_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x0001f00000000000)
-#define ICP_MODE0_DATA_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define ICP_MODE0_DATA_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x000001f000000000)
-#define ICP_MODE0_BACKOFF_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define ICP_MODE0_FWD_QUE_FWD_CONV_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#define ICP_MODE0_DISA_WAIT4CRESP_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#define ICP_MODE0_DISA_AUTO_NO_RETRY4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
-#define ICP_MODE0_DISA_RETRY_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
-#define ICP_MODE0_HANG_ON_ADDR_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
-#define ICP_MODE0_EOI_CORRECTION_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000030000000)
-#define ICP_MODE0_MAX_LOAD_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x000000000f000000)
-#define ICP_MODE0_MAX_STORE_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000f00000)
-#define ICP_MODE0_ENABLE_INJECT SIXTYFOUR_BIT_CONSTANT(0x0000000000010000)
-#ifndef __ASSEMBLER__
-
-
-typedef union icp_iir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t inject_target_core : 16;
-    uint64_t inject_target_thread : 8;
-    uint64_t reserved0 : 8;
-    uint64_t inject_level : 4;
-    uint64_t reserved1 : 4;
-    uint64_t inject_priority : 8;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t inject_priority : 8;
-    uint64_t reserved1 : 4;
-    uint64_t inject_level : 4;
-    uint64_t reserved0 : 8;
-    uint64_t inject_target_thread : 8;
-    uint64_t inject_target_core : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} icp_iir_t;
-
-#endif // __ASSEMBLER__
-#define ICP_IIR_INJECT_TARGET_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0xffff000000000000)
-#define ICP_IIR_INJECT_TARGET_THREAD_MASK SIXTYFOUR_BIT_CONSTANT(0x0000ff0000000000)
-#define ICP_IIR_INJECT_LEVEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000f0000000)
-#define ICP_IIR_INJECT_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000ff0000)
-#ifndef __ASSEMBLER__
-
-#endif // __ASSEMBLER__
-#endif // __ICP_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/icp_register_addresses.h b/src/ssx/pgp/registers/icp_register_addresses.h
deleted file mode 100755
index 7cb8350..0000000
--- a/src/ssx/pgp/registers/icp_register_addresses.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __ICP_REGISTER_ADDRESSES_H__
-#define __ICP_REGISTER_ADDRESSES_H__
-
-// $Id: icp_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file icp_register_addresses.h
-/// \brief Symbolic addresses for the ICP unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define ICP_PIB_BASE 0x020109c0
-#define ICP_BAR 0x020109ca
-#define ICP_MODE0 0x020109cb
-#define ICP_IIR 0x020109cc
-
-#endif // __ICP_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/mcs_firmware_registers.h b/src/ssx/pgp/registers/mcs_firmware_registers.h
deleted file mode 100755
index 23e04b8..0000000
--- a/src/ssx/pgp/registers/mcs_firmware_registers.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/ssx/pgp/registers/mcs_firmware_registers.h $              */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __MCS_FIRMWARE_REGISTERS_H__
-#define __MCS_FIRMWARE_REGISTERS_H__
-
-// $Id: mcs_firmware_registers.h,v 1.4 2015/01/27 17:56:30 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file mcs_firmware_registers.h
-/// \brief C register structs for the MCS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union mcfgpr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t mcfgprq_valid : 1;
-    uint64_t reserved0 : 5;
-    uint64_t mcfgprq_base_address : 14;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t mcfgprq_base_address : 14;
-    uint64_t reserved0 : 5;
-    uint64_t mcfgprq_valid : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} mcfgpr_t;
-
-#endif // __ASSEMBLER__
-#define MCFGPR_MCFGPRQ_VALID SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define MCFGPR_MCFGPRQ_BASE_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x03fff00000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union mcsmode0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_cmd_byp_stutter : 1;
-    uint64_t reserved1 : 1;
-    uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1;
-    uint64_t enable_centaur_local_checkstop_command : 1;
-    uint64_t l3_prefetch_retry_threshold : 4;
-    uint64_t number_of_cl_entries_reserved_for_read : 4;
-    uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4;
-    uint64_t number_of_cl_entries_reserved_for_writes : 4;
-    uint64_t number_of_cl_entries_reserved_for_cp_writes : 4;
-    uint64_t number_of_cl_entries_reserved_for_cp_ig : 4;
-    uint64_t number_of_cl_entries_reserved_for_htm_ops : 4;
-    uint64_t number_of_cl_entries_reserved_for_ha_assist : 4;
-    uint64_t mcfgrp_19_is_ho_bit : 1;
-    uint64_t cl_channel_timeout_forces_channel_fail : 1;
-    uint64_t enable_fault_line_for_global_checkstop : 1;
-    uint64_t reserved39 : 5;
-    uint64_t address_collision_modes : 9;
-    uint64_t include_cp_ig_in_cp_write_fullness_group : 1;
-    uint64_t enable_dmawr_cmd_bit : 1;
-    uint64_t enable_read_lsfr_data : 1;
-    uint64_t force_channel_fail : 1;
-    uint64_t disable_read_crc_ecc_bypass_taken : 1;
-    uint64_t disable_cl_ao_queueus : 1;
-    uint64_t address_select_lfsr_value : 2;
-    uint64_t enable_centaur_sync : 1;
-    uint64_t write_data_buffer_ecc_check_disable : 1;
-    uint64_t write_data_buffer_ecc_correct_disable : 1;
-#else
-    uint64_t write_data_buffer_ecc_correct_disable : 1;
-    uint64_t write_data_buffer_ecc_check_disable : 1;
-    uint64_t enable_centaur_sync : 1;
-    uint64_t address_select_lfsr_value : 2;
-    uint64_t disable_cl_ao_queueus : 1;
-    uint64_t disable_read_crc_ecc_bypass_taken : 1;
-    uint64_t force_channel_fail : 1;
-    uint64_t enable_read_lsfr_data : 1;
-    uint64_t enable_dmawr_cmd_bit : 1;
-    uint64_t include_cp_ig_in_cp_write_fullness_group : 1;
-    uint64_t address_collision_modes : 9;
-    uint64_t reserved39 : 5;
-    uint64_t enable_fault_line_for_global_checkstop : 1;
-    uint64_t cl_channel_timeout_forces_channel_fail : 1;
-    uint64_t mcfgrp_19_is_ho_bit : 1;
-    uint64_t number_of_cl_entries_reserved_for_ha_assist : 4;
-    uint64_t number_of_cl_entries_reserved_for_htm_ops : 4;
-    uint64_t number_of_cl_entries_reserved_for_cp_ig : 4;
-    uint64_t number_of_cl_entries_reserved_for_cp_writes : 4;
-    uint64_t number_of_cl_entries_reserved_for_writes : 4;
-    uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4;
-    uint64_t number_of_cl_entries_reserved_for_read : 4;
-    uint64_t l3_prefetch_retry_threshold : 4;
-    uint64_t enable_centaur_local_checkstop_command : 1;
-    uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1;
-    uint64_t reserved1 : 1;
-    uint64_t enable_cmd_byp_stutter : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} mcsmode0_t;
-
-#endif // __ASSEMBLER__
-#define MCSMODE0_ENABLE_CMD_BYP_STUTTER SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define MCSMODE0_ENABLE_NS_RD_AO_SFU_FOR_DCBZ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define MCSMODE0_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define MCSMODE0_L3_PREFETCH_RETRY_THRESHOLD_MASK SIXTYFOUR_BIT_CONSTANT(0x0f00000000000000)
-#define MCSMODE0_MCFGRP_19_IS_HO_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
-#define MCSMODE0_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
-#define MCSMODE0_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
-#define MCSMODE0_ADDRESS_COLLISION_MODES_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000ff800)
-#define MCSMODE0_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000400)
-#define MCSMODE0_ENABLE_DMAWR_CMD_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000000000200)
-#define MCSMODE0_ENABLE_READ_LSFR_DATA SIXTYFOUR_BIT_CONSTANT(0x0000000000000100)
-#define MCSMODE0_FORCE_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000000000080)
-#define MCSMODE0_DISABLE_READ_CRC_ECC_BYPASS_TAKEN SIXTYFOUR_BIT_CONSTANT(0x0000000000000040)
-#define MCSMODE0_DISABLE_CL_AO_QUEUEUS SIXTYFOUR_BIT_CONSTANT(0x0000000000000020)
-#define MCSMODE0_ADDRESS_SELECT_LFSR_VALUE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000000018)
-#define MCSMODE0_ENABLE_CENTAUR_SYNC SIXTYFOUR_BIT_CONSTANT(0x0000000000000004)
-#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000002)
-#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000001)
-#ifndef __ASSEMBLER__
-
-typedef union mcifir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 30;
-    uint64_t channel_fail_signal_active : 1;
-    uint64_t _reserved1 : 33;
-#else
-    uint64_t _reserved1 : 33;
-    uint64_t channel_fail_signal_active : 1;
-    uint64_t _reserved0 : 30;
-#endif // _BIG_ENDIAN
-    } fields;
-} mcifir_t;
-
-#endif // __ASSEMBLER__
-#endif // __MCS_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/ocb_firmware_registers.h b/src/ssx/pgp/registers/ocb_firmware_registers.h
deleted file mode 100755
index 34037ff..0000000
--- a/src/ssx/pgp/registers/ocb_firmware_registers.h
+++ /dev/null
@@ -1,2698 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/ssx/pgp/registers/ocb_firmware_registers.h $              */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __OCB_FIRMWARE_REGISTERS_H__
-#define __OCB_FIRMWARE_REGISTERS_H__
-
-// $Id: ocb_firmware_registers.h,v 1.3 2015/02/18 20:35:27 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2014
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file ocb_firmware_registers.h
-/// \brief C register structs for the OCB unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union ocb_oitr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oitr0_t;
-
-
-
-typedef union ocb_oiepr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oiepr0_t;
-
-
-
-typedef union ocb_ocir0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocir0_t;
-
-
-
-typedef union ocb_onisr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_onisr0_t;
-
-
-
-typedef union ocb_ouder0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ouder0_t;
-
-
-
-typedef union ocb_ocisr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocisr0_t;
-
-
-
-typedef union ocb_odher0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t dbg_halt_en : 32;
-#else
-    uint32_t dbg_halt_en : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_odher0_t;
-
-
-
-typedef union ocb_oisr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr0_t;
-
-
-
-typedef union ocb_oisr0_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr0_and_t;
-
-
-
-typedef union ocb_oisr0_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr0_or_t;
-
-
-
-typedef union ocb_oimr0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr0_t;
-
-
-
-typedef union ocb_oimr0_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr0_and_t;
-
-
-
-typedef union ocb_oimr0_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t debugger : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t pba_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t spipss_error : 1;
-    uint32_t check_stop : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t external_trap : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t reserved_31 : 1;
-#else
-    uint32_t reserved_31 : 1;
-    uint32_t pba_bcue_attn : 1;
-    uint32_t pba_bcde_attn : 1;
-    uint32_t pba_occ_push1 : 1;
-    uint32_t pba_occ_push0 : 1;
-    uint32_t reserved_26 : 1;
-    uint32_t adcfsm_ongoing : 1;
-    uint32_t pore_gpe1_complete : 1;
-    uint32_t pore_gpe0_complete : 1;
-    uint32_t reserved_22 : 1;
-    uint32_t pmc_interchip_msg_recv : 1;
-    uint32_t pore_sbe_error : 1;
-    uint32_t pore_gpe1_error : 1;
-    uint32_t pore_gpe0_error : 1;
-    uint32_t occ_timer1 : 1;
-    uint32_t occ_timer0 : 1;
-    uint32_t external_trap : 1;
-    uint32_t adu_malf_alert : 1;
-    uint32_t pmc_malf_alert : 1;
-    uint32_t check_stop : 1;
-    uint32_t spipss_error : 1;
-    uint32_t ocb_error : 1;
-    uint32_t pmc_error : 1;
-    uint32_t pore_sbe_fatal_error : 1;
-    uint32_t pore_gpe1_fatal_error : 1;
-    uint32_t pore_gpe0_fatal_error : 1;
-    uint32_t pore_sw_error : 1;
-    uint32_t srt_error : 1;
-    uint32_t pba_error : 1;
-    uint32_t reserved_2 : 1;
-    uint32_t trace_trigger : 1;
-    uint32_t debugger : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr0_or_t;
-
-
-
-typedef union ocb_oitr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oitr1_t;
-
-
-
-typedef union ocb_oiepr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oiepr1_t;
-
-
-
-typedef union ocb_ocir1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocir1_t;
-
-
-
-typedef union ocb_onisr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_onisr1_t;
-
-
-
-typedef union ocb_ouder1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ouder1_t;
-
-
-
-typedef union ocb_ocisr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocisr1_t;
-
-
-
-typedef union ocb_odher1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t dbg_halt_en : 32;
-#else
-    uint32_t dbg_halt_en : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_odher1_t;
-
-
-
-typedef union ocb_oisr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr1_t;
-
-
-
-typedef union ocb_oisr1_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr1_and_t;
-
-
-
-typedef union ocb_oisr1_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oisr1_or_t;
-
-
-
-typedef union ocb_oimr1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr1_t;
-
-
-
-typedef union ocb_oimr1_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr1_and_t;
-
-
-
-typedef union ocb_oimr1_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved_32 : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t ipi0 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t reserved_63 : 1;
-#else
-    uint32_t reserved_63 : 1;
-    uint32_t ipi3 : 1;
-    uint32_t ipi2 : 1;
-    uint32_t ipi1 : 1;
-    uint32_t ipi0 : 1;
-    uint32_t pore_sbe_complete : 1;
-    uint32_t pssbridge_ongoing : 1;
-    uint32_t pmc_ocb_o2p_ongoing : 1;
-    uint32_t oci2spivid_ongoing : 1;
-    uint32_t pmc_interchip_msg_send_ongoing : 1;
-    uint32_t reserved_53 : 1;
-    uint32_t pmc_idle_enter : 1;
-    uint32_t pore_sw_complete : 1;
-    uint32_t pmc_idle_exit : 1;
-    uint32_t reserved_49 : 1;
-    uint32_t reserved_48 : 1;
-    uint32_t pmc_pstate_change : 1;
-    uint32_t pmc_sync : 1;
-    uint32_t pmc_protocol_ongoing : 1;
-    uint32_t pmc_voltage_change_ongoing : 1;
-    uint32_t reserved_43 : 1;
-    uint32_t reserved_42 : 1;
-    uint32_t occ_strm3_push : 1;
-    uint32_t occ_strm3_pull : 1;
-    uint32_t occ_strm2_push : 1;
-    uint32_t occ_strm2_pull : 1;
-    uint32_t occ_strm1_push : 1;
-    uint32_t occ_strm1_pull : 1;
-    uint32_t occ_strm0_push : 1;
-    uint32_t occ_strm0_pull : 1;
-    uint32_t reserved_33 : 1;
-    uint32_t reserved_32 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oimr1_or_t;
-
-
-
-typedef union ocb_occmisc {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t core_ext_intr : 1;
-    uint32_t reason_intr : 1;
-    uint32_t _reserved0 : 30;
-#else
-    uint32_t _reserved0 : 30;
-    uint32_t reason_intr : 1;
-    uint32_t core_ext_intr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occmisc_t;
-
-
-
-typedef union ocb_occmisc_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t core_ext_intr : 1;
-    uint32_t reason_intr : 1;
-    uint32_t _reserved0 : 30;
-#else
-    uint32_t _reserved0 : 30;
-    uint32_t reason_intr : 1;
-    uint32_t core_ext_intr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occmisc_and_t;
-
-
-
-typedef union ocb_occmisc_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t core_ext_intr : 1;
-    uint32_t reason_intr : 1;
-    uint32_t _reserved0 : 30;
-#else
-    uint32_t _reserved0 : 30;
-    uint32_t reason_intr : 1;
-    uint32_t core_ext_intr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occmisc_or_t;
-
-
-
-typedef union ocb_otrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t timeout : 1;
-    uint32_t control : 1;
-    uint32_t auto_reload : 1;
-    uint32_t reserved : 13;
-    uint32_t timer : 16;
-#else
-    uint32_t timer : 16;
-    uint32_t reserved : 13;
-    uint32_t auto_reload : 1;
-    uint32_t control : 1;
-    uint32_t timeout : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_otrn_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OTRN_TIMEOUT 0x80000000
-#define OCB_OTRN_CONTROL 0x40000000
-#define OCB_OTRN_AUTO_RELOAD 0x20000000
-#define OCB_OTRN_TIMER_MASK 0x0000ffff
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_ohtmcr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t htm_src_sel : 2;
-    uint32_t htm_stop : 1;
-    uint32_t htm_marker_slave_adrs : 3;
-    uint32_t event2halt_mode : 2;
-    uint32_t event2halt_en : 11;
-    uint32_t reserved : 1;
-    uint32_t event2halt_halt : 1;
-    uint32_t _reserved0 : 11;
-#else
-    uint32_t _reserved0 : 11;
-    uint32_t event2halt_halt : 1;
-    uint32_t reserved : 1;
-    uint32_t event2halt_en : 11;
-    uint32_t event2halt_mode : 2;
-    uint32_t htm_marker_slave_adrs : 3;
-    uint32_t htm_stop : 1;
-    uint32_t htm_src_sel : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ohtmcr_t;
-
-
-
-typedef union ocb_oehdr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t event2halt_delay : 20;
-    uint32_t _reserved0 : 12;
-#else
-    uint32_t _reserved0 : 12;
-    uint32_t event2halt_delay : 20;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oehdr_t;
-
-
-
-typedef union ocb_ocbslbrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pull_oci_region : 2;
-    uint32_t pull_start : 27;
-    uint32_t _reserved0 : 3;
-#else
-    uint32_t _reserved0 : 3;
-    uint32_t pull_start : 27;
-    uint32_t pull_oci_region : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbslbrn_t;
-
-
-
-typedef union ocb_ocbshbrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t push_oci_region : 2;
-    uint32_t push_start : 27;
-    uint32_t _reserved0 : 3;
-#else
-    uint32_t _reserved0 : 3;
-    uint32_t push_start : 27;
-    uint32_t push_oci_region : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbshbrn_t;
-
-
-
-typedef union ocb_ocbslcsn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pull_full : 1;
-    uint32_t pull_empty : 1;
-    uint32_t reserved0 : 2;
-    uint32_t pull_intr_action : 2;
-    uint32_t pull_length : 5;
-    uint32_t reserved1 : 2;
-    uint32_t pull_write_ptr : 5;
-    uint32_t reserved2 : 3;
-    uint32_t pull_read_ptr : 5;
-    uint32_t reserved3 : 5;
-    uint32_t pull_enable : 1;
-#else
-    uint32_t pull_enable : 1;
-    uint32_t reserved3 : 5;
-    uint32_t pull_read_ptr : 5;
-    uint32_t reserved2 : 3;
-    uint32_t pull_write_ptr : 5;
-    uint32_t reserved1 : 2;
-    uint32_t pull_length : 5;
-    uint32_t pull_intr_action : 2;
-    uint32_t reserved0 : 2;
-    uint32_t pull_empty : 1;
-    uint32_t pull_full : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbslcsn_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OCBSLCSN_PULL_FULL 0x80000000
-#define OCB_OCBSLCSN_PULL_EMPTY 0x40000000
-#define OCB_OCBSLCSN_PULL_INTR_ACTION_MASK 0x0c000000
-#define OCB_OCBSLCSN_PULL_LENGTH_MASK 0x03e00000
-#define OCB_OCBSLCSN_PULL_WRITE_PTR_MASK 0x0007c000
-#define OCB_OCBSLCSN_PULL_READ_PTR_MASK 0x000007c0
-#define OCB_OCBSLCSN_PULL_ENABLE 0x00000001
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_ocbshcsn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t push_full : 1;
-    uint32_t push_empty : 1;
-    uint32_t reserved0 : 2;
-    uint32_t push_intr_action : 2;
-    uint32_t push_length : 5;
-    uint32_t reserved1 : 2;
-    uint32_t push_write_ptr : 5;
-    uint32_t reserved2 : 3;
-    uint32_t push_read_ptr : 5;
-    uint32_t reserved3 : 5;
-    uint32_t push_enable : 1;
-#else
-    uint32_t push_enable : 1;
-    uint32_t reserved3 : 5;
-    uint32_t push_read_ptr : 5;
-    uint32_t reserved2 : 3;
-    uint32_t push_write_ptr : 5;
-    uint32_t reserved1 : 2;
-    uint32_t push_length : 5;
-    uint32_t push_intr_action : 2;
-    uint32_t reserved0 : 2;
-    uint32_t push_empty : 1;
-    uint32_t push_full : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbshcsn_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OCBSHCSN_PUSH_FULL 0x80000000
-#define OCB_OCBSHCSN_PUSH_EMPTY 0x40000000
-#define OCB_OCBSHCSN_PUSH_INTR_ACTION_MASK 0x0c000000
-#define OCB_OCBSHCSN_PUSH_LENGTH_MASK 0x03e00000
-#define OCB_OCBSHCSN_PUSH_WRITE_PTR_MASK 0x0007c000
-#define OCB_OCBSHCSN_PUSH_READ_PTR_MASK 0x000007c0
-#define OCB_OCBSHCSN_PUSH_ENABLE 0x00000001
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_ocbslin {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved : 32;
-#else
-    uint32_t reserved : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbslin_t;
-
-
-
-typedef union ocb_ocbshin {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved : 32;
-#else
-    uint32_t reserved : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbshin_t;
-
-
-
-typedef union ocb_ocbsesn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t push_read_underflow : 1;
-    uint32_t pull_write_overflow : 1;
-    uint32_t _reserved0 : 30;
-#else
-    uint32_t _reserved0 : 30;
-    uint32_t pull_write_overflow : 1;
-    uint32_t push_read_underflow : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbsesn_t;
-
-
-
-typedef union ocb_ocbicrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t allow_unsecure_pib_masters : 1;
-    uint32_t _reserved0 : 31;
-#else
-    uint32_t _reserved0 : 31;
-    uint32_t allow_unsecure_pib_masters : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbicrn_t;
-
-
-
-typedef union ocb_ocblwcrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t linear_window_enable : 1;
-    uint32_t spare_0 : 3;
-    uint32_t linear_window_bar : 16;
-    uint32_t linear_window_mask : 12;
-#else
-    uint32_t linear_window_mask : 12;
-    uint32_t linear_window_bar : 16;
-    uint32_t spare_0 : 3;
-    uint32_t linear_window_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocblwcrn_t;
-
-
-
-typedef union ocb_ocblwsrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t linear_window_scresp : 3;
-    uint32_t spare_0 : 5;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    uint32_t spare_0 : 5;
-    uint32_t linear_window_scresp : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocblwsrn_t;
-
-
-
-typedef union ocb_ocblwsbrn {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t linear_window_region : 2;
-    uint32_t linear_window_base : 8;
-    uint32_t _reserved0 : 22;
-#else
-    uint32_t _reserved0 : 22;
-    uint32_t linear_window_base : 8;
-    uint32_t linear_window_region : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocblwsbrn_t;
-
-
-
-typedef union ocb_ocichsw {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t m0_priority : 2;
-    uint32_t m1_priority : 2;
-    uint32_t m2_priority : 2;
-    uint32_t m3_priority : 2;
-    uint32_t m4_priority : 2;
-    uint32_t m5_priority : 2;
-    uint32_t m6_priority : 2;
-    uint32_t m7_priority : 2;
-    uint32_t dcu_priority_sel : 1;
-    uint32_t icu_priority_sel : 1;
-    uint32_t plbarb_lockerr : 1;
-    uint32_t _reserved0 : 13;
-#else
-    uint32_t _reserved0 : 13;
-    uint32_t plbarb_lockerr : 1;
-    uint32_t icu_priority_sel : 1;
-    uint32_t dcu_priority_sel : 1;
-    uint32_t m7_priority : 2;
-    uint32_t m6_priority : 2;
-    uint32_t m5_priority : 2;
-    uint32_t m4_priority : 2;
-    uint32_t m3_priority : 2;
-    uint32_t m2_priority : 2;
-    uint32_t m1_priority : 2;
-    uint32_t m0_priority : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocichsw_t;
-
-
-
-typedef union ocb_ocr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t trace_disable : 1;
-    uint64_t trace_event : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t critical_interrupt : 1;
-    uint64_t spare : 7;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t spare : 7;
-    uint64_t critical_interrupt : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t trace_event : 1;
-    uint64_t trace_disable : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t core_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocr_t;
-
-
-
-typedef union ocb_ocr_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t trace_disable : 1;
-    uint64_t trace_event : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t critical_interrupt : 1;
-    uint64_t spare : 7;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t spare : 7;
-    uint64_t critical_interrupt : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t trace_event : 1;
-    uint64_t trace_disable : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t core_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocr_and_t;
-
-
-
-typedef union ocb_ocr_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t trace_disable : 1;
-    uint64_t trace_event : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t critical_interrupt : 1;
-    uint64_t spare : 7;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t spare : 7;
-    uint64_t critical_interrupt : 1;
-    uint64_t ext_interrupt : 1;
-    uint64_t dbg_unconditional_event : 1;
-    uint64_t trace_event : 1;
-    uint64_t trace_disable : 1;
-    uint64_t oci_arb_reset : 1;
-    uint64_t system_reset : 1;
-    uint64_t chip_reset : 1;
-    uint64_t core_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocr_or_t;
-
-
-
-typedef union ocb_ocdbg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 12;
-    uint64_t _reserved0 : 52;
-#else
-    uint64_t _reserved0 : 52;
-    uint64_t value : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocdbg_t;
-
-
-
-typedef union ocb_ocbarn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_region : 2;
-    uint64_t ocb_address : 27;
-    uint64_t reserved : 3;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t reserved : 3;
-    uint64_t ocb_address : 27;
-    uint64_t oci_region : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbarn_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OCBARN_OCI_REGION_MASK SIXTYFOUR_BIT_CONSTANT(0xc000000000000000)
-#define OCB_OCBARN_OCB_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x3ffffff800000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_ocbcsrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pull_read_underflow : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t ocb_stream_type : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t _reserved0 : 49;
-#else
-    uint64_t _reserved0 : 49;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_stream_type : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbcsrn_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OCBCSRN_PULL_READ_UNDERFLOW SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define OCB_OCBCSRN_PULL_READ_UNDERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define OCB_OCBCSRN_OCB_STREAM_MODE SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define OCB_OCBCSRN_OCB_STREAM_TYPE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define OCB_OCBCSRN_OCB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define OCB_OCBCSRN_OCB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define OCB_OCBCSRN_OCB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define OCB_OCBCSRN_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define OCB_OCBCSRN_OCB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define OCB_OCBCSRN_OCB_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_ocbcsrn_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pull_read_underflow : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t ocb_stream_type : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t _reserved0 : 49;
-#else
-    uint64_t _reserved0 : 49;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_stream_type : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbcsrn_and_t;
-
-
-
-typedef union ocb_ocbcsrn_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pull_read_underflow : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t ocb_stream_type : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t _reserved0 : 49;
-#else
-    uint64_t _reserved0 : 49;
-    uint64_t ocb_fsm_err : 1;
-    uint64_t reserved2 : 1;
-    uint64_t ocb_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_oci_slave_error : 1;
-    uint64_t ocb_oci_read_data_parity : 1;
-    uint64_t ocb_oci_timeout : 1;
-    uint64_t reserved1 : 2;
-    uint64_t ocb_stream_type : 1;
-    uint64_t ocb_stream_mode : 1;
-    uint64_t push_write_overflow_en : 1;
-    uint64_t pull_read_underflow_en : 1;
-    uint64_t push_write_overflow : 1;
-    uint64_t pull_read_underflow : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbcsrn_or_t;
-
-
-
-typedef union ocb_ocbesrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ocb_error_addr : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t ocb_error_addr : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbesrn_t;
-
-
-
-typedef union ocb_ocbdrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ocb_data : 64;
-#else
-    uint64_t ocb_data : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_ocbdrn_t;
-
-
-
-typedef union ocb_osbcr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_block_unsecure_masters : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t occ_block_unsecure_masters : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_osbcr_t;
-
-
-
-typedef union ocb_otdcr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t trace_bus_en : 1;
-    uint64_t ocb_trace_mux_sel : 1;
-    uint64_t occ_trace_mux_sel : 2;
-    uint64_t oci_trace_mux_sel : 4;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t oci_trace_mux_sel : 4;
-    uint64_t occ_trace_mux_sel : 2;
-    uint64_t ocb_trace_mux_sel : 1;
-    uint64_t trace_bus_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_otdcr_t;
-
-
-
-typedef union ocb_oppcinj {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_err_inj_dcu : 1;
-    uint64_t oci_err_inj_icu : 1;
-    uint64_t oci_err_inj_ce_ue : 1;
-    uint64_t oci_err_inj_singl_cont : 1;
-    uint64_t _reserved0 : 60;
-#else
-    uint64_t _reserved0 : 60;
-    uint64_t oci_err_inj_singl_cont : 1;
-    uint64_t oci_err_inj_ce_ue : 1;
-    uint64_t oci_err_inj_icu : 1;
-    uint64_t oci_err_inj_dcu : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_oppcinj_t;
-
-
-
-typedef union ocb_occlfir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_fw0 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pmc_error : 1;
-    uint64_t srt_ue : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t external_trap : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t spare_fir : 12;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-#else
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 12;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t external_trap : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_ue : 1;
-    uint64_t pmc_error : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfir_t;
-
-#endif // __ASSEMBLER__
-#define OCB_OCCLFIR_OCC_FW0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define OCB_OCCLFIR_OCC_FW1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define OCB_OCCLFIR_OCC_FW2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define OCB_OCCLFIR_OCC_FW3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define OCB_OCCLFIR_PMC_PORE_SW_MALF SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define OCB_OCCLFIR_PMC_OCC_HB_MALF SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define OCB_OCCLFIR_PORE_GPE0_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define OCB_OCCLFIR_PORE_GPE1_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define OCB_OCCLFIR_OCB_ERROR SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define OCB_OCCLFIR_PMC_ERROR SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define OCB_OCCLFIR_SRT_UE SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define OCB_OCCLFIR_SRT_CE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define OCB_OCCLFIR_SRT_READ_ERROR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define OCB_OCCLFIR_SRT_WRITE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define OCB_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define OCB_OCCLFIR_SRT_OCI_BE_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define OCB_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define OCB_OCCLFIR_PORE_SW_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define OCB_OCCLFIR_PORE_GPE0_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define OCB_OCCLFIR_PORE_GPE1_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define OCB_OCCLFIR_EXTERNAL_TRAP SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define OCB_OCCLFIR_PPC405_CORE_RESET SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define OCB_OCCLFIR_PPC405_CHIP_RESET SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define OCB_OCCLFIR_PPC405_SYSTEM_RESET SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define OCB_OCCLFIR_PPC405_DBGMSRWE SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define OCB_OCCLFIR_PPC405_DBGSTOPACK SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define OCB_OCCLFIR_OCB_DB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define OCB_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define OCB_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define OCB_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#define OCB_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#define OCB_OCCLFIR_OCB_IDC0_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
-#define OCB_OCCLFIR_OCB_IDC1_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
-#define OCB_OCCLFIR_OCB_IDC2_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
-#define OCB_OCCLFIR_OCB_IDC3_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
-#define OCB_OCCLFIR_SRT_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
-#define OCB_OCCLFIR_JTAGACC_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
-#define OCB_OCCLFIR_OCB_DW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
-#define OCB_OCCLFIR_C405_ECC_UE SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
-#define OCB_OCCLFIR_C405_ECC_CE SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
-#define OCB_OCCLFIR_C405_OCI_MACHINECHECK SIXTYFOUR_BIT_CONSTANT(0x0000000000800000)
-#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0000000000400000)
-#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000000000200000)
-#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000100000)
-#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
-#define OCB_OCCLFIR_SLW_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000)
-#define OCB_OCCLFIR_GPE_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000020000)
-#define OCB_OCCLFIR_OCB_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000010000)
-#define OCB_OCCLFIR_C405ICU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000008000)
-#define OCB_OCCLFIR_C405DCU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000004000)
-#define OCB_OCCLFIR_SPARE_FIR_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000003ffc)
-#define OCB_OCCLFIR_FIR_PARITY_ERR_DUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000002)
-#define OCB_OCCLFIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000000001)
-#ifndef __ASSEMBLER__
-
-
-typedef union ocb_occlfir_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_fw0 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pmc_error : 1;
-    uint64_t srt_ue : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t external_trap : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t spare_fir : 12;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-#else
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 12;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t external_trap : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_ue : 1;
-    uint64_t pmc_error : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfir_and_t;
-
-
-
-typedef union ocb_occlfir_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_fw0 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pmc_error : 1;
-    uint64_t srt_ue : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t external_trap : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t spare_fir : 12;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-#else
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 12;
-    uint64_t c405dcu_m_timeout : 1;
-    uint64_t c405icu_m_timeout : 1;
-    uint64_t ocb_ocislv_err : 1;
-    uint64_t gpe_ocislv_err : 1;
-    uint64_t slw_ocislv_err : 1;
-    uint64_t sram_spare_direct_error3 : 1;
-    uint64_t sram_spare_direct_error2 : 1;
-    uint64_t sram_spare_direct_error1 : 1;
-    uint64_t sram_spare_direct_error0 : 1;
-    uint64_t c405_oci_machinecheck : 1;
-    uint64_t c405_ecc_ce : 1;
-    uint64_t c405_ecc_ue : 1;
-    uint64_t ocb_dw_err : 1;
-    uint64_t jtagacc_err : 1;
-    uint64_t srt_fsm_err : 1;
-    uint64_t ocb_idc3_error : 1;
-    uint64_t ocb_idc2_error : 1;
-    uint64_t ocb_idc1_error : 1;
-    uint64_t ocb_idc0_error : 1;
-    uint64_t ocb_db_pib_data_parity_err : 1;
-    uint64_t ocb_pib_addr_parity_err : 1;
-    uint64_t ocb_db_oci_slave_error : 1;
-    uint64_t ocb_db_oci_read_data_parity : 1;
-    uint64_t ocb_db_oci_timeout : 1;
-    uint64_t ppc405_dbgstopack : 1;
-    uint64_t ppc405_dbgmsrwe : 1;
-    uint64_t ppc405_system_reset : 1;
-    uint64_t ppc405_chip_reset : 1;
-    uint64_t ppc405_core_reset : 1;
-    uint64_t external_trap : 1;
-    uint64_t pore_gpe1_error_err : 1;
-    uint64_t pore_gpe0_error_err : 1;
-    uint64_t pore_sw_error_err : 1;
-    uint64_t srt_oci_addr_parity_err : 1;
-    uint64_t srt_oci_be_parity_err : 1;
-    uint64_t srt_oci_write_data_parity : 1;
-    uint64_t srt_write_error : 1;
-    uint64_t srt_read_error : 1;
-    uint64_t srt_ce : 1;
-    uint64_t srt_ue : 1;
-    uint64_t pmc_error : 1;
-    uint64_t ocb_error : 1;
-    uint64_t pore_gpe1_fatal_err : 1;
-    uint64_t pore_gpe0_fatal_err : 1;
-    uint64_t pmc_occ_hb_malf : 1;
-    uint64_t pmc_pore_sw_malf : 1;
-    uint64_t occ_fw3 : 1;
-    uint64_t occ_fw2 : 1;
-    uint64_t occ_fw1 : 1;
-    uint64_t occ_fw0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfir_or_t;
-
-
-
-typedef union ocb_occlfirmask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfirmask_t;
-
-
-
-typedef union ocb_occlfirmask_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfirmask_and_t;
-
-
-
-typedef union ocb_occlfirmask_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfirmask_or_t;
-
-
-
-typedef union ocb_occlfiract0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfiract0_t;
-
-
-
-typedef union ocb_occlfiract1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occlfiract1_t;
-
-
-
-typedef union ocb_occerrrpt {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t sram_cerrrpt : 10;
-    uint64_t jtagacc_cerrrpt : 6;
-    uint64_t c405_dcu_ecc_ue_cerrrpt : 1;
-    uint64_t c405_dcu_ecc_ce_cerrrpt : 1;
-    uint64_t c405_icu_ecc_ue_cerrrpt : 1;
-    uint64_t c405_icu_ecc_ce_cerrrpt : 1;
-    uint64_t slw_ocislv_err : 7;
-    uint64_t gpe_ocislv_err : 7;
-    uint64_t ocb_ocislv_err : 6;
-    uint64_t _reserved0 : 24;
-#else
-    uint64_t _reserved0 : 24;
-    uint64_t ocb_ocislv_err : 6;
-    uint64_t gpe_ocislv_err : 7;
-    uint64_t slw_ocislv_err : 7;
-    uint64_t c405_icu_ecc_ce_cerrrpt : 1;
-    uint64_t c405_icu_ecc_ue_cerrrpt : 1;
-    uint64_t c405_dcu_ecc_ce_cerrrpt : 1;
-    uint64_t c405_dcu_ecc_ue_cerrrpt : 1;
-    uint64_t jtagacc_cerrrpt : 6;
-    uint64_t sram_cerrrpt : 10;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_occerrrpt_t;
-
-
-
-typedef union ocb_scan_dummy_1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 48;
-    uint64_t value : 16;
-#else
-    uint64_t value : 16;
-    uint64_t _reserved0 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_scan_dummy_1_t;
-
-
-
-typedef union ocb_scan_dummy_2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 63;
-    uint64_t value : 1;
-#else
-    uint64_t value : 1;
-    uint64_t _reserved0 : 63;
-#endif // _BIG_ENDIAN
-    } fields;
-} ocb_scan_dummy_2_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __OCB_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/ocb_register_addresses.h b/src/ssx/pgp/registers/ocb_register_addresses.h
deleted file mode 100755
index 3290e59..0000000
--- a/src/ssx/pgp/registers/ocb_register_addresses.h
+++ /dev/null
@@ -1,148 +0,0 @@
-#ifndef __OCB_REGISTER_ADDRESSES_H__
-#define __OCB_REGISTER_ADDRESSES_H__
-
-// $Id: ocb_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file ocb_register_addresses.h
-/// \brief Symbolic addresses for the OCB unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define OCB_OCI_BASE 0x40050000
-#define OCB_OITR0 0x40050040
-#define OCB_OIEPR0 0x40050048
-#define OCB_OCIR0 0x40050050
-#define OCB_ONISR0 0x40050058
-#define OCB_OUDER0 0x40050060
-#define OCB_OCISR0 0x40050068
-#define OCB_ODHER0 0x40050070
-#define OCB_OISR0 0x40050000
-#define OCB_OISR0_AND 0x40050008
-#define OCB_OISR0_OR 0x40050010
-#define OCB_OIMR0 0x40050020
-#define OCB_OIMR0_AND 0x40050028
-#define OCB_OIMR0_OR 0x40050030
-#define OCB_OITR1 0x400500c0
-#define OCB_OIEPR1 0x400500c8
-#define OCB_OCIR1 0x400500d0
-#define OCB_ONISR1 0x400500d8
-#define OCB_OUDER1 0x400500e0
-#define OCB_OCISR1 0x400500e8
-#define OCB_ODHER1 0x400500f0
-#define OCB_OISR1 0x40050080
-#define OCB_OISR1_AND 0x40050088
-#define OCB_OISR1_OR 0x40050090
-#define OCB_OIMR1 0x400500a0
-#define OCB_OIMR1_AND 0x400500a8
-#define OCB_OIMR1_OR 0x400500b0
-#define OCB_OCCMISC 0x40050100
-#define OCB_OCCMISC_AND 0x40050108
-#define OCB_OCCMISC_OR 0x40050110
-#define OCB_OTRN(n) (OCB_OTR0 + ((OCB_OTR1 - OCB_OTR0) * (n)))
-#define OCB_OTR0 0x40050800
-#define OCB_OTR1 0x40050808
-#define OCB_OHTMCR 0x40050118
-#define OCB_OEHDR 0x40050120
-#define OCB_OCBSLBRN(n) (OCB_OCBSLBR0 + ((OCB_OCBSLBR1 - OCB_OCBSLBR0) * (n)))
-#define OCB_OCBSLBR0 0x40051000
-#define OCB_OCBSLBR1 0x40051080
-#define OCB_OCBSLBR2 0x40051100
-#define OCB_OCBSHBRN(n) (OCB_OCBSHBR0 + ((OCB_OCBSHBR1 - OCB_OCBSHBR0) * (n)))
-#define OCB_OCBSHBR0 0x40051018
-#define OCB_OCBSHBR1 0x40051098
-#define OCB_OCBSHBR2 0x40051118
-#define OCB_OCBSLCSN(n) (OCB_OCBSLCS0 + ((OCB_OCBSLCS1 - OCB_OCBSLCS0) * (n)))
-#define OCB_OCBSLCS0 0x40051008
-#define OCB_OCBSLCS1 0x40051088
-#define OCB_OCBSLCS2 0x40051108
-#define OCB_OCBSHCSN(n) (OCB_OCBSHCS0 + ((OCB_OCBSHCS1 - OCB_OCBSHCS0) * (n)))
-#define OCB_OCBSHCS0 0x40051020
-#define OCB_OCBSHCS1 0x400510a0
-#define OCB_OCBSHCS2 0x40051120
-#define OCB_OCBSLIN(n) (OCB_OCBSLI0 + ((OCB_OCBSLI1 - OCB_OCBSLI0) * (n)))
-#define OCB_OCBSLI0 0x40051010
-#define OCB_OCBSLI1 0x40051090
-#define OCB_OCBSLI2 0x40051110
-#define OCB_OCBSHIN(n) (OCB_OCBSHI0 + ((OCB_OCBSHI1 - OCB_OCBSHI0) * (n)))
-#define OCB_OCBSHI0 0x40051028
-#define OCB_OCBSHI1 0x400510a8
-#define OCB_OCBSHI2 0x40051128
-#define OCB_OCBSESN(n) (OCB_OCBSES0 + ((OCB_OCBSES1 - OCB_OCBSES0) * (n)))
-#define OCB_OCBSES0 0x40051030
-#define OCB_OCBSES1 0x400510b0
-#define OCB_OCBSES2 0x40051130
-#define OCB_OCBICRN(n) (OCB_OCBICR0 + ((OCB_OCBICR1 - OCB_OCBICR0) * (n)))
-#define OCB_OCBICR0 0x40051038
-#define OCB_OCBICR1 0x400510b8
-#define OCB_OCBICR2 0x40051138
-#define OCB_OCBLWCRN(n) (OCB_OCBLWCR0 + ((OCB_OCBLWCR1 - OCB_OCBLWCR0) * (n)))
-#define OCB_OCBLWCR0 0x40051040
-#define OCB_OCBLWCR1 0x400510c0
-#define OCB_OCBLWCR2 0x40051140
-#define OCB_OCBLWSRN(n) (OCB_OCBLWSR0 + ((OCB_OCBLWSR1 - OCB_OCBLWSR0) * (n)))
-#define OCB_OCBLWSR0 0x40051050
-#define OCB_OCBLWSR1 0x400510d0
-#define OCB_OCBLWSR2 0x40051150
-#define OCB_OCBLWSBRN(n) (OCB_OCBLWSBR0 + ((OCB_OCBLWSBR1 - OCB_OCBLWSBR0) * (n)))
-#define OCB_OCBLWSBR0 0x40051060
-#define OCB_OCBLWSBR1 0x400510e0
-#define OCB_OCBLWSBR2 0x40051160
-#define OCB_OCICHSW 0x40050128
-#define OCB_PIB_BASE 0x0006a000
-#define OCB_OCR 0x0006b000
-#define OCB_OCR_AND 0x0006b001
-#define OCB_OCR_OR 0x0006b002
-#define OCB_OCDBG 0x0006b003
-#define OCB_OCBARN(n) (OCB_OCBAR0 + ((OCB_OCBAR1 - OCB_OCBAR0) * (n)))
-#define OCB_OCBAR0 0x0006b010
-#define OCB_OCBAR1 0x0006b030
-#define OCB_OCBAR2 0x0006b050
-#define OCB_OCBAR3 0x0006b070
-#define OCB_OCBCSRN(n) (OCB_OCBCSR0 + ((OCB_OCBCSR1 - OCB_OCBCSR0) * (n)))
-#define OCB_OCBCSR0 0x0006b011
-#define OCB_OCBCSR1 0x0006b031
-#define OCB_OCBCSR2 0x0006b051
-#define OCB_OCBCSR3 0x0006b071
-#define OCB_OCBCSRN_AND(n) (OCB_OCBCSR0_AND + ((OCB_OCBCSR1_AND - OCB_OCBCSR0_AND) * (n)))
-#define OCB_OCBCSR0_AND 0x0006b012
-#define OCB_OCBCSR1_AND 0x0006b032
-#define OCB_OCBCSR2_AND 0x0006b052
-#define OCB_OCBCSR3_AND 0x0006b072
-#define OCB_OCBCSRN_OR(n) (OCB_OCBCSR0_OR + ((OCB_OCBCSR1_OR - OCB_OCBCSR0_OR) * (n)))
-#define OCB_OCBCSR0_OR 0x0006b013
-#define OCB_OCBCSR1_OR 0x0006b033
-#define OCB_OCBCSR2_OR 0x0006b053
-#define OCB_OCBCSR3_OR 0x0006b073
-#define OCB_OCBESRN(n) (OCB_OCBESR0 + ((OCB_OCBESR1 - OCB_OCBESR0) * (n)))
-#define OCB_OCBESR0 0x0006b014
-#define OCB_OCBESR1 0x0006b034
-#define OCB_OCBESR2 0x0006b054
-#define OCB_OCBESR3 0x0006b074
-#define OCB_OCBDRN(n) (OCB_OCBDR0 + ((OCB_OCBDR1 - OCB_OCBDR0) * (n)))
-#define OCB_OCBDR0 0x0006b015
-#define OCB_OCBDR1 0x0006b035
-#define OCB_OCBDR2 0x0006b055
-#define OCB_OCBDR3 0x0006b075
-#define OCB_OSBCR 0x0006b100
-#define OCB_OTDCR 0x0006b110
-#define OCB_OPPCINJ 0x0006b111
-#define OCB_FIRPIB_BASE 0x01010800
-#define OCB_OCCLFIR 0x01010800
-#define OCB_OCCLFIR_AND 0x01010801
-#define OCB_OCCLFIR_OR 0x01010802
-#define OCB_OCCLFIRMASK 0x01010803
-#define OCB_OCCLFIRMASK_AND 0x01010804
-#define OCB_OCCLFIRMASK_OR 0x01010805
-#define OCB_OCCLFIRACT0 0x01010806
-#define OCB_OCCLFIRACT1 0x01010807
-#define OCB_OCCERRRPT 0x0101080a
-
-#endif // __OCB_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/oha_firmware_registers.h b/src/ssx/pgp/registers/oha_firmware_registers.h
deleted file mode 100755
index cba1500..0000000
--- a/src/ssx/pgp/registers/oha_firmware_registers.h
+++ /dev/null
@@ -1,1248 +0,0 @@
-#ifndef __OHA_FIRMWARE_REGISTERS_H__
-#define __OHA_FIRMWARE_REGISTERS_H__
-
-// $Id: oha_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file oha_firmware_registers.h
-/// \brief C register structs for the OHA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union oha_activity_sample_mode_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_activity_sampling : 1;
-    uint64_t enable_ppt_trace : 1;
-    uint64_t l2_act_count_is_free_running : 1;
-    uint64_t l3_act_count_is_free_running : 1;
-    uint64_t activity_sample_l2l3_enable : 1;
-    uint64_t core_activity_sample_enable : 1;
-    uint64_t disable_activity_proxy_reset : 1;
-    uint64_t power_proxy_activity_range_select_vcs : 5;
-    uint64_t power_proxy_activity_range_select_vdd : 5;
-    uint64_t memory_activity_range_select : 4;
-    uint64_t avg_freq_counter_scaler : 3;
-    uint64_t ppt_trace_timer_match_val : 11;
-    uint64_t disable_ppt_int_timer_reset : 1;
-    uint64_t ppt_int_timer_select : 2;
-    uint64_t disable_ppt_cycle_counter_reset : 1;
-    uint64_t ppt_cycle_counter_scaler : 3;
-    uint64_t ppt_squash_timer_match_val : 6;
-    uint64_t ppt_timer_timeout_enable : 1;
-    uint64_t ppt_lpar_change_enable : 1;
-    uint64_t ppt_global_actual_change_enable : 1;
-    uint64_t ppt_local_voltage_change_enable : 1;
-    uint64_t ppt_ivrm_bypass_change_enable : 1;
-    uint64_t ppt_idle_entry_enable : 1;
-    uint64_t ppt_idle_exit_enable : 1;
-    uint64_t ppt_timer_timeout_priority : 1;
-    uint64_t ppt_lpar_change_priority : 1;
-    uint64_t ppt_global_actual_change_priority : 1;
-    uint64_t ppt_local_voltage_change_priority : 1;
-    uint64_t ppt_ivrm_bypass_change_priority : 1;
-    uint64_t ppt_idle_entry_priority : 1;
-    uint64_t ppt_idle_exit_priority : 1;
-    uint64_t ppt_legacy_mode : 1;
-    uint64_t _reserved0 : 1;
-#else
-    uint64_t _reserved0 : 1;
-    uint64_t ppt_legacy_mode : 1;
-    uint64_t ppt_idle_exit_priority : 1;
-    uint64_t ppt_idle_entry_priority : 1;
-    uint64_t ppt_ivrm_bypass_change_priority : 1;
-    uint64_t ppt_local_voltage_change_priority : 1;
-    uint64_t ppt_global_actual_change_priority : 1;
-    uint64_t ppt_lpar_change_priority : 1;
-    uint64_t ppt_timer_timeout_priority : 1;
-    uint64_t ppt_idle_exit_enable : 1;
-    uint64_t ppt_idle_entry_enable : 1;
-    uint64_t ppt_ivrm_bypass_change_enable : 1;
-    uint64_t ppt_local_voltage_change_enable : 1;
-    uint64_t ppt_global_actual_change_enable : 1;
-    uint64_t ppt_lpar_change_enable : 1;
-    uint64_t ppt_timer_timeout_enable : 1;
-    uint64_t ppt_squash_timer_match_val : 6;
-    uint64_t ppt_cycle_counter_scaler : 3;
-    uint64_t disable_ppt_cycle_counter_reset : 1;
-    uint64_t ppt_int_timer_select : 2;
-    uint64_t disable_ppt_int_timer_reset : 1;
-    uint64_t ppt_trace_timer_match_val : 11;
-    uint64_t avg_freq_counter_scaler : 3;
-    uint64_t memory_activity_range_select : 4;
-    uint64_t power_proxy_activity_range_select_vdd : 5;
-    uint64_t power_proxy_activity_range_select_vcs : 5;
-    uint64_t disable_activity_proxy_reset : 1;
-    uint64_t core_activity_sample_enable : 1;
-    uint64_t activity_sample_l2l3_enable : 1;
-    uint64_t l3_act_count_is_free_running : 1;
-    uint64_t l2_act_count_is_free_running : 1;
-    uint64_t enable_ppt_trace : 1;
-    uint64_t enable_activity_sampling : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_activity_sample_mode_reg_t;
-
-
-
-typedef union oha_vcs_activity_cnt_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t l2_activity_count_24bit_vcs : 24;
-    uint64_t l3_activity_count_24bit_vcs : 24;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t l3_activity_count_24bit_vcs : 24;
-    uint64_t l2_activity_count_24bit_vcs : 24;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_vcs_activity_cnt_reg_t;
-
-
-
-typedef union oha_vdd_activity_cnt_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t l2_activity_count_24bit_vdd : 24;
-    uint64_t l3_activity_count_24bit_vdd : 24;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t l3_activity_count_24bit_vdd : 24;
-    uint64_t l2_activity_count_24bit_vdd : 24;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_vdd_activity_cnt_reg_t;
-
-
-
-typedef union oha_low_activity_detect_mode_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t low_activity_detect_sample_enable : 1;
-    uint64_t low_activity_detect_timer_select_for_entry : 8;
-    uint64_t low_activity_detect_timer_select_for_exit : 8;
-    uint64_t low_activity_detect_threshold_range : 4;
-    uint64_t low_activity_detect_threshold_entry : 16;
-    uint64_t low_activity_detect_threshold_exit : 16;
-    uint64_t _reserved0 : 11;
-#else
-    uint64_t _reserved0 : 11;
-    uint64_t low_activity_detect_threshold_exit : 16;
-    uint64_t low_activity_detect_threshold_entry : 16;
-    uint64_t low_activity_detect_threshold_range : 4;
-    uint64_t low_activity_detect_timer_select_for_exit : 8;
-    uint64_t low_activity_detect_timer_select_for_entry : 8;
-    uint64_t low_activity_detect_sample_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_low_activity_detect_mode_reg_t;
-
-
-
-typedef union oha_activity_and_frequ_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t low_activity_detect_engaged : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t low_activity_detect_engaged : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_activity_and_frequ_reg_t;
-
-
-
-typedef union oha_counter_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t base_counter : 16;
-    uint64_t idle_detec_timer : 16;
-    uint64_t tod_count_msbs : 16;
-    uint64_t ppt_cycle_count_ovfl : 1;
-    uint64_t ppt_parity_error : 1;
-    uint64_t _reserved0 : 14;
-#else
-    uint64_t _reserved0 : 14;
-    uint64_t ppt_parity_error : 1;
-    uint64_t ppt_cycle_count_ovfl : 1;
-    uint64_t tod_count_msbs : 16;
-    uint64_t idle_detec_timer : 16;
-    uint64_t base_counter : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_counter_reg_t;
-
-
-
-typedef union oha_proxy_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t average_frequency : 32;
-    uint64_t special_memory_activity_cnt : 24;
-    uint64_t _reserved0 : 8;
-#else
-    uint64_t _reserved0 : 8;
-    uint64_t special_memory_activity_cnt : 24;
-    uint64_t average_frequency : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_proxy_reg_t;
-
-
-
-typedef union oha_proxy_legacy_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t aproxy_vdd : 16;
-    uint64_t aproxy_vcs : 16;
-    uint64_t memory_activity_cnt : 16;
-    uint64_t scaled_average_frequency : 16;
-#else
-    uint64_t scaled_average_frequency : 16;
-    uint64_t memory_activity_cnt : 16;
-    uint64_t aproxy_vcs : 16;
-    uint64_t aproxy_vdd : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_proxy_legacy_reg_t;
-
-
-
-typedef union oha_skitter_ctrl_mode_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t start_skitter_mux_sel : 3;
-    uint64_t stop_skitter_mux_sel : 3;
-    uint64_t skitter_timer_start_mux_sel : 3;
-    uint64_t disable_skitter_qualification_mode : 1;
-    uint64_t skitter_timer_enable_freerun_mode : 1;
-    uint64_t skitter_timer_range_select : 4;
-    uint64_t _reserved0 : 49;
-#else
-    uint64_t _reserved0 : 49;
-    uint64_t skitter_timer_range_select : 4;
-    uint64_t skitter_timer_enable_freerun_mode : 1;
-    uint64_t disable_skitter_qualification_mode : 1;
-    uint64_t skitter_timer_start_mux_sel : 3;
-    uint64_t stop_skitter_mux_sel : 3;
-    uint64_t start_skitter_mux_sel : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_skitter_ctrl_mode_reg_t;
-
-
-
-typedef union oha_cpm_ctrl_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cpm_bit_sel : 2;
-    uint64_t cpm_bit_sel_trig_0 : 3;
-    uint64_t cpm_bit_sel_trig_1 : 3;
-    uint64_t scom_marker : 8;
-    uint64_t cpm_mark_select : 2;
-    uint64_t cpm_htm_mode : 1;
-    uint64_t cpm_scom_mask : 8;
-    uint64_t cpm_scom_mode : 2;
-    uint64_t cpm_data_mode : 1;
-    uint64_t _reserved0 : 34;
-#else
-    uint64_t _reserved0 : 34;
-    uint64_t cpm_data_mode : 1;
-    uint64_t cpm_scom_mode : 2;
-    uint64_t cpm_scom_mask : 8;
-    uint64_t cpm_htm_mode : 1;
-    uint64_t cpm_mark_select : 2;
-    uint64_t scom_marker : 8;
-    uint64_t cpm_bit_sel_trig_1 : 3;
-    uint64_t cpm_bit_sel_trig_0 : 3;
-    uint64_t cpm_bit_sel : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_cpm_ctrl_reg_t;
-
-
-
-typedef union oha_cpm_hist_reset_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t hist_reset : 1;
-    uint64_t pconly_special_wakeup : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t pconly_special_wakeup : 1;
-    uint64_t hist_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_cpm_hist_reset_reg_t;
-
-#endif // __ASSEMBLER__
-#define OHA_CPM_HIST_RESET_REG_HIST_RESET SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define OHA_CPM_HIST_RESET_REG_PCONLY_SPECIAL_WAKEUP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union oha_ro_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t low_activity_detect_bit : 1;
-    uint64_t special_wakeup_completed : 1;
-    uint64_t architected_idle_state_from_core : 3;
-    uint64_t core_access_impossible : 1;
-    uint64_t eco_access_impossible : 1;
-    uint64_t spare_6bit : 6;
-    uint64_t current_aiss_fsm_state_vector : 7;
-    uint64_t eff_idle_state : 3;
-    uint64_t spare_1bit : 1;
-    uint64_t pc_tc_deep_idle_thread_state : 8;
-    uint64_t lpar_id : 12;
-    uint64_t ppt_fsm_l : 4;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t ppt_fsm_l : 4;
-    uint64_t lpar_id : 12;
-    uint64_t pc_tc_deep_idle_thread_state : 8;
-    uint64_t spare_1bit : 1;
-    uint64_t eff_idle_state : 3;
-    uint64_t current_aiss_fsm_state_vector : 7;
-    uint64_t spare_6bit : 6;
-    uint64_t eco_access_impossible : 1;
-    uint64_t core_access_impossible : 1;
-    uint64_t architected_idle_state_from_core : 3;
-    uint64_t special_wakeup_completed : 1;
-    uint64_t low_activity_detect_bit : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_ro_status_reg_t;
-
-#endif // __ASSEMBLER__
-#define OHA_RO_STATUS_REG_LOW_ACTIVITY_DETECT_BIT SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define OHA_RO_STATUS_REG_SPECIAL_WAKEUP_COMPLETED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define OHA_RO_STATUS_REG_ARCHITECTED_IDLE_STATE_FROM_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0x3800000000000000)
-#define OHA_RO_STATUS_REG_CORE_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define OHA_RO_STATUS_REG_ECO_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define OHA_RO_STATUS_REG_SPARE_6BIT_MASK SIXTYFOUR_BIT_CONSTANT(0x01f8000000000000)
-#define OHA_RO_STATUS_REG_CURRENT_AISS_FSM_STATE_VECTOR_MASK SIXTYFOUR_BIT_CONSTANT(0x0007f00000000000)
-#define OHA_RO_STATUS_REG_EFF_IDLE_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x00000e0000000000)
-#define OHA_RO_STATUS_REG_SPARE_1BIT SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define OHA_RO_STATUS_REG_PC_TC_DEEP_IDLE_THREAD_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x000000ff00000000)
-#define OHA_RO_STATUS_REG_LPAR_ID_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000fff00000)
-#define OHA_RO_STATUS_REG_PPT_FSM_L_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000f0000)
-#ifndef __ASSEMBLER__
-
-
-typedef union oha_mode_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_ignore_recov_errors : 1;
-    uint64_t enable_arch_idle_mode_sequencer : 1;
-    uint64_t treat_sleep_as_nap : 1;
-    uint64_t treat_winkle_as_sleep : 1;
-    uint64_t enable_pstate_tracing : 1;
-    uint64_t enable_suppress_purges_and_pcb_fence : 1;
-    uint64_t idle_state_override_en : 1;
-    uint64_t idle_state_override_value : 3;
-    uint64_t disable_aiss_core_handshake : 1;
-    uint64_t aiss_hang_detect_timer_sel : 4;
-    uint64_t enable_l2_purge_abort : 1;
-    uint64_t enable_l3_purge_abort : 1;
-    uint64_t tod_pulse_count_match_val : 14;
-    uint64_t trace_debug_mode_select : 2;
-    uint64_t lpft_mode : 1;
-    uint64_t _reserved0 : 30;
-#else
-    uint64_t _reserved0 : 30;
-    uint64_t lpft_mode : 1;
-    uint64_t trace_debug_mode_select : 2;
-    uint64_t tod_pulse_count_match_val : 14;
-    uint64_t enable_l3_purge_abort : 1;
-    uint64_t enable_l2_purge_abort : 1;
-    uint64_t aiss_hang_detect_timer_sel : 4;
-    uint64_t disable_aiss_core_handshake : 1;
-    uint64_t idle_state_override_value : 3;
-    uint64_t idle_state_override_en : 1;
-    uint64_t enable_suppress_purges_and_pcb_fence : 1;
-    uint64_t enable_pstate_tracing : 1;
-    uint64_t treat_winkle_as_sleep : 1;
-    uint64_t treat_sleep_as_nap : 1;
-    uint64_t enable_arch_idle_mode_sequencer : 1;
-    uint64_t enable_ignore_recov_errors : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_mode_reg_t;
-
-
-
-typedef union oha_error_and_error_mask_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oha_error_mask : 8;
-    uint64_t oha_chiplet_errors : 8;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t oha_chiplet_errors : 8;
-    uint64_t oha_error_mask : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_error_and_error_mask_reg_t;
-
-
-
-typedef union oha_arch_idle_state_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t aiss_thold_sequence_select : 1;
-    uint64_t disable_waiting_on_l3 : 1;
-    uint64_t idle_seq_timer_select : 2;
-    uint64_t allow_aiss_interrupts : 1;
-    uint64_t enable_reset_of_counters_while_sleepwinkle : 1;
-    uint64_t select_p7p_seq_wait_time : 1;
-    uint64_t disable_auto_sleep_entry : 1;
-    uint64_t disable_auto_winkle_entry : 1;
-    uint64_t reset_idle_state_sequencer : 1;
-    uint64_t _reserved0 : 54;
-#else
-    uint64_t _reserved0 : 54;
-    uint64_t reset_idle_state_sequencer : 1;
-    uint64_t disable_auto_winkle_entry : 1;
-    uint64_t disable_auto_sleep_entry : 1;
-    uint64_t select_p7p_seq_wait_time : 1;
-    uint64_t enable_reset_of_counters_while_sleepwinkle : 1;
-    uint64_t allow_aiss_interrupts : 1;
-    uint64_t idle_seq_timer_select : 2;
-    uint64_t disable_waiting_on_l3 : 1;
-    uint64_t aiss_thold_sequence_select : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_arch_idle_state_reg_t;
-
-
-
-typedef union oha_pmu_config_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmu_pstate_threshold_a : 8;
-    uint64_t pmu_pstate_threshold_b : 8;
-    uint64_t pmu_configuration : 3;
-    uint64_t _reserved0 : 45;
-#else
-    uint64_t _reserved0 : 45;
-    uint64_t pmu_configuration : 3;
-    uint64_t pmu_pstate_threshold_b : 8;
-    uint64_t pmu_pstate_threshold_a : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_pmu_config_reg_t;
-
-
-
-typedef union oha_aiss_io_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare_2bits_b : 2;
-    uint64_t tc_tp_chiplet_pm_state : 4;
-    uint64_t tc_pb_sleep : 1;
-    uint64_t tc_tc_pm_thold_ctrl : 3;
-    uint64_t tc_l3_fence_lco : 1;
-    uint64_t tc_ncu_fence : 1;
-    uint64_t chksw_hw237039dis : 1;
-    uint64_t tc_l3_init_dram : 1;
-    uint64_t tc_pb_purge : 1;
-    uint64_t tc_pc_pm_wake_up : 1;
-    uint64_t spare_entry_for_config_bit : 1;
-    uint64_t reset_of_counters_while_sleepwinkle : 1;
-    uint64_t tc_chtm_purge : 1;
-    uint64_t tc_tp_terminate_pcb : 1;
-    uint64_t tc_oha_therm_purge_lvl : 1;
-    uint64_t pscom_core_fence_lvl : 1;
-    uint64_t pb_eco_fence_lvl : 1;
-    uint64_t core2cache_fence_req : 1;
-    uint64_t cache2core_fence_req : 1;
-    uint64_t pervasive_eco_fence_req : 1;
-    uint64_t tc_oha_pmx_fence_req_lvl_l : 1;
-    uint64_t updateohafreq : 1;
-    uint64_t req_idle_state_change : 1;
-    uint64_t tc_l2_purge : 1;
-    uint64_t tc_l3_purge : 1;
-    uint64_t tc_ncu_purge : 1;
-    uint64_t tc_l2_purge_abort : 1;
-    uint64_t tc_l3_purge_abort : 1;
-    uint64_t pc_tc_pm_state : 3;
-    uint64_t l2_purge_is_done : 1;
-    uint64_t l3_ncu_chtm_purge_done : 3;
-    uint64_t tc_tc_xstop_err : 1;
-    uint64_t tc_tc_recov_err : 1;
-    uint64_t pb_tc_purge_active_lvl : 1;
-    uint64_t l3_tc_dram_ready_lvl : 1;
-    uint64_t core_fsm_non_idle : 1;
-    uint64_t tc_pscom_core_fence_done : 1;
-    uint64_t tc_pmx_oha_fence_done : 1;
-    uint64_t l2_purge_abort_sticky : 1;
-    uint64_t l3_purge_abort_sticky : 1;
-    uint64_t _reserved0 : 14;
-#else
-    uint64_t _reserved0 : 14;
-    uint64_t l3_purge_abort_sticky : 1;
-    uint64_t l2_purge_abort_sticky : 1;
-    uint64_t tc_pmx_oha_fence_done : 1;
-    uint64_t tc_pscom_core_fence_done : 1;
-    uint64_t core_fsm_non_idle : 1;
-    uint64_t l3_tc_dram_ready_lvl : 1;
-    uint64_t pb_tc_purge_active_lvl : 1;
-    uint64_t tc_tc_recov_err : 1;
-    uint64_t tc_tc_xstop_err : 1;
-    uint64_t l3_ncu_chtm_purge_done : 3;
-    uint64_t l2_purge_is_done : 1;
-    uint64_t pc_tc_pm_state : 3;
-    uint64_t tc_l3_purge_abort : 1;
-    uint64_t tc_l2_purge_abort : 1;
-    uint64_t tc_ncu_purge : 1;
-    uint64_t tc_l3_purge : 1;
-    uint64_t tc_l2_purge : 1;
-    uint64_t req_idle_state_change : 1;
-    uint64_t updateohafreq : 1;
-    uint64_t tc_oha_pmx_fence_req_lvl_l : 1;
-    uint64_t pervasive_eco_fence_req : 1;
-    uint64_t cache2core_fence_req : 1;
-    uint64_t core2cache_fence_req : 1;
-    uint64_t pb_eco_fence_lvl : 1;
-    uint64_t pscom_core_fence_lvl : 1;
-    uint64_t tc_oha_therm_purge_lvl : 1;
-    uint64_t tc_tp_terminate_pcb : 1;
-    uint64_t tc_chtm_purge : 1;
-    uint64_t reset_of_counters_while_sleepwinkle : 1;
-    uint64_t spare_entry_for_config_bit : 1;
-    uint64_t tc_pc_pm_wake_up : 1;
-    uint64_t tc_pb_purge : 1;
-    uint64_t tc_l3_init_dram : 1;
-    uint64_t chksw_hw237039dis : 1;
-    uint64_t tc_ncu_fence : 1;
-    uint64_t tc_l3_fence_lco : 1;
-    uint64_t tc_tc_pm_thold_ctrl : 3;
-    uint64_t tc_pb_sleep : 1;
-    uint64_t tc_tp_chiplet_pm_state : 4;
-    uint64_t spare_2bits_b : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_aiss_io_reg_t;
-
-
-
-typedef union oha_ppt_bar_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ppt_bar : 46;
-    uint64_t ppt_size_mask : 7;
-    uint64_t ppt_address_scope : 3;
-    uint64_t _reserved0 : 8;
-#else
-    uint64_t _reserved0 : 8;
-    uint64_t ppt_address_scope : 3;
-    uint64_t ppt_size_mask : 7;
-    uint64_t ppt_bar : 46;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_ppt_bar_reg_t;
-
-
-
-typedef union oha_l2_vcs_directory_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vcs_directory_read_weight_t;
-
-
-
-typedef union oha_l2_vcs_directory_write_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vcs_directory_write_weight_t;
-
-
-
-typedef union oha_l2_vcs_cache_full_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vcs_cache_full_read_weight_t;
-
-
-
-typedef union oha_l2_vcs_cache_targeted_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vcs_cache_targeted_read_weight_t;
-
-
-
-typedef union oha_l2_vcs_cache_write_cnt_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vcs_cache_write_cnt_weight_t;
-
-
-
-typedef union oha_l3_vcs_directory_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vcs_directory_read_weight_t;
-
-
-
-typedef union oha_l3_vcs_directory_write_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vcs_directory_write_weight_t;
-
-
-
-typedef union oha_l3_vcs_cache_access_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vcs_cache_access_weight_t;
-
-
-
-typedef union oha_l2_vdd_directory_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vdd_directory_read_weight_t;
-
-
-
-typedef union oha_l2_vdd_directory_write_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vdd_directory_write_weight_t;
-
-
-
-typedef union oha_l2_vdd_cache_full_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vdd_cache_full_read_weight_t;
-
-
-
-typedef union oha_l2_vdd_cache_targeted_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vdd_cache_targeted_read_weight_t;
-
-
-
-typedef union oha_l2_vdd_cache_write_cnt_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l2_vdd_cache_write_cnt_weight_t;
-
-
-
-typedef union oha_l3_vdd_directory_read_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vdd_directory_read_weight_t;
-
-
-
-typedef union oha_l3_vdd_directory_write_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vdd_directory_write_weight_t;
-
-
-
-typedef union oha_l3_vdd_cache_access_weight {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 6;
-    uint64_t _reserved0 : 58;
-#else
-    uint64_t _reserved0 : 58;
-    uint64_t value : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_l3_vdd_cache_access_weight_t;
-
-
-
-typedef union oha_chksw_hw132623dis {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t value : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_chksw_hw132623dis_t;
-
-
-
-typedef union oha_activity_scale_factor_array {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 56;
-    uint64_t _reserved0 : 8;
-#else
-    uint64_t _reserved0 : 8;
-    uint64_t value : 56;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_activity_scale_factor_array_t;
-
-
-
-typedef union oha_activity_scale_shift_factor_array {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 42;
-    uint64_t _reserved0 : 22;
-#else
-    uint64_t _reserved0 : 22;
-    uint64_t value : 42;
-#endif // _BIG_ENDIAN
-    } fields;
-} oha_activity_scale_shift_factor_array_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __OHA_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/oha_register_addresses.h b/src/ssx/pgp/registers/oha_register_addresses.h
deleted file mode 100755
index 1f07b37..0000000
--- a/src/ssx/pgp/registers/oha_register_addresses.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef __OHA_REGISTER_ADDRESSES_H__
-#define __OHA_REGISTER_ADDRESSES_H__
-
-// $Id: oha_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file oha_register_addresses.h
-/// \brief Symbolic addresses for the OHA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define OHA_PCB_BASE 0x10020000
-#define OHA_ACTIVITY_SAMPLE_MODE_REG 0x10020000
-#define OHA_VCS_ACTIVITY_CNT_REG 0x10020001
-#define OHA_VDD_ACTIVITY_CNT_REG 0x10020002
-#define OHA_LOW_ACTIVITY_DETECT_MODE_REG 0x10020003
-#define OHA_ACTIVITY_AND_FREQU_REG 0x10020004
-#define OHA_COUNTER_REG 0x10020005
-#define OHA_PROXY_REG 0x10020006
-#define OHA_PROXY_LEGACY_REG 0x10020007
-#define OHA_SKITTER_CTRL_MODE_REG 0x10020008
-#define OHA_CPM_CTRL_REG 0x1002000a
-#define OHA_CPM_HIST_RESET_REG 0x10020013
-#define OHA_RO_STATUS_REG 0x1002000b
-#define OHA_MODE_REG 0x1002000d
-#define OHA_ERROR_AND_ERROR_MASK_REG 0x1002000e
-#define OHA_ARCH_IDLE_STATE_REG 0x10020011
-#define OHA_PMU_CONFIG_REG 0x10020012
-#define OHA_AISS_IO_REG 0x10020014
-#define OHA_PPT_BAR_REG 0x10020015
-
-#endif // __OHA_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pba_firmware_registers.h b/src/ssx/pgp/registers/pba_firmware_registers.h
deleted file mode 100755
index 502ef51..0000000
--- a/src/ssx/pgp/registers/pba_firmware_registers.h
+++ /dev/null
@@ -1,2184 +0,0 @@
-#ifndef __PBA_FIRMWARE_REGISTERS_H__
-#define __PBA_FIRMWARE_REGISTERS_H__
-
-// $Id: pba_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pba_firmware_registers.h
-/// \brief C register structs for the PBA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pba_barn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cmd_scope : 3;
-    uint64_t reserved0 : 1;
-    uint64_t reserved1 : 10;
-    uint64_t addr : 30;
-    uint64_t _reserved0 : 20;
-#else
-    uint64_t _reserved0 : 20;
-    uint64_t addr : 30;
-    uint64_t reserved1 : 10;
-    uint64_t reserved0 : 1;
-    uint64_t cmd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barn_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
-#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_barmskn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 23;
-    uint64_t mask : 21;
-    uint64_t _reserved0 : 20;
-#else
-    uint64_t _reserved0 : 20;
-    uint64_t mask : 21;
-    uint64_t reserved0 : 23;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barmskn_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_fir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_t;
-
-#endif // __ASSEMBLER__
-#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
-#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
-#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
-#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
-#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
-#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
-#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
-#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
-#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
-#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000)
-#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
-#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_fir_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_and_t;
-
-
-
-typedef union pba_fir_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_or_t;
-
-
-
-typedef union pba_firmask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_t;
-
-
-
-typedef union pba_firmask_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_and_t;
-
-
-
-typedef union pba_firmask_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_or_t;
-
-
-
-typedef union pba_firact0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firact0_t;
-
-
-
-typedef union pba_firact1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firact1_t;
-
-
-
-typedef union pba_occact {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_occact_t;
-
-
-
-typedef union pba_cfg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pbreq_slvfw_max_priority : 2;
-    uint64_t pbreq_bce_max_priority : 2;
-    uint64_t pbreq_data_hang_div : 5;
-    uint64_t pbreq_oper_hang_div : 5;
-    uint64_t pbreq_drop_priority_mask : 6;
-    uint64_t reserved20 : 4;
-    uint64_t chsw_hang_on_adrerror : 1;
-    uint64_t chsw_dis_ociabuspar_check : 1;
-    uint64_t chsw_dis_ocibepar_check : 1;
-    uint64_t chsw_hang_on_derror : 1;
-    uint64_t chsw_hang_on_rereq_timeout : 1;
-    uint64_t chsw_dis_write_match_rearb : 1;
-    uint64_t chsw_dis_ocidatapar_gen : 1;
-    uint64_t chsw_dis_ocidatapar_check : 1;
-    uint64_t chsw_dis_oper_hang : 1;
-    uint64_t chsw_dis_data_hang : 1;
-    uint64_t chsw_dis_ecc_check : 1;
-    uint64_t chsw_dis_retry_backoff : 1;
-    uint64_t chsw_hang_on_invalid_cresp : 1;
-    uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
-    uint64_t chsw_dis_group_scope : 1;
-    uint64_t chsw_dis_rtag_parity_chk : 1;
-    uint64_t chsw_dis_pb_parity_chk : 1;
-    uint64_t _reserved0 : 23;
-#else
-    uint64_t _reserved0 : 23;
-    uint64_t chsw_dis_pb_parity_chk : 1;
-    uint64_t chsw_dis_rtag_parity_chk : 1;
-    uint64_t chsw_dis_group_scope : 1;
-    uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
-    uint64_t chsw_hang_on_invalid_cresp : 1;
-    uint64_t chsw_dis_retry_backoff : 1;
-    uint64_t chsw_dis_ecc_check : 1;
-    uint64_t chsw_dis_data_hang : 1;
-    uint64_t chsw_dis_oper_hang : 1;
-    uint64_t chsw_dis_ocidatapar_check : 1;
-    uint64_t chsw_dis_ocidatapar_gen : 1;
-    uint64_t chsw_dis_write_match_rearb : 1;
-    uint64_t chsw_hang_on_rereq_timeout : 1;
-    uint64_t chsw_hang_on_derror : 1;
-    uint64_t chsw_dis_ocibepar_check : 1;
-    uint64_t chsw_dis_ociabuspar_check : 1;
-    uint64_t chsw_hang_on_adrerror : 1;
-    uint64_t reserved20 : 4;
-    uint64_t pbreq_drop_priority_mask : 6;
-    uint64_t pbreq_oper_hang_div : 5;
-    uint64_t pbreq_data_hang_div : 5;
-    uint64_t pbreq_bce_max_priority : 2;
-    uint64_t pbreq_slvfw_max_priority : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_cfg_t;
-
-
-
-typedef union pba_errpt0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cerr_pb_rddatato_fw : 6;
-    uint64_t cerr_pb_rdadrerr_fw : 6;
-    uint64_t cerr_pb_wradrerr_fw : 4;
-    uint64_t cerr_pb_ackdead_fw_rd : 6;
-    uint64_t cerr_pb_ackdead_fw_wr : 2;
-    uint64_t cerr_pb_unexpcresp : 11;
-    uint64_t cerr_pb_unexpdata : 6;
-    uint64_t _reserved0 : 23;
-#else
-    uint64_t _reserved0 : 23;
-    uint64_t cerr_pb_unexpdata : 6;
-    uint64_t cerr_pb_unexpcresp : 11;
-    uint64_t cerr_pb_ackdead_fw_wr : 2;
-    uint64_t cerr_pb_ackdead_fw_rd : 6;
-    uint64_t cerr_pb_wradrerr_fw : 4;
-    uint64_t cerr_pb_rdadrerr_fw : 6;
-    uint64_t cerr_pb_rddatato_fw : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt0_t;
-
-
-
-typedef union pba_errpt1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cerr_pb_badcresp : 12;
-    uint64_t cerr_pb_crespto : 12;
-    uint64_t cerr_oci_rereqto : 6;
-    uint64_t cerr_bcde_setup_err : 2;
-    uint64_t cerr_bcue_setup_err : 2;
-    uint64_t cerr_bcue_oci_dataerr : 2;
-    uint64_t _reserved0 : 28;
-#else
-    uint64_t _reserved0 : 28;
-    uint64_t cerr_bcue_oci_dataerr : 2;
-    uint64_t cerr_bcue_setup_err : 2;
-    uint64_t cerr_bcde_setup_err : 2;
-    uint64_t cerr_oci_rereqto : 6;
-    uint64_t cerr_pb_crespto : 12;
-    uint64_t cerr_pb_badcresp : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt1_t;
-
-
-
-typedef union pba_errpt2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cerr_slv_internal_err : 8;
-    uint64_t cerr_bcde_internal_err : 4;
-    uint64_t cerr_bcue_internal_err : 4;
-    uint64_t cerr_bar_parity_err : 1;
-    uint64_t cerr_scomtb_err : 1;
-    uint64_t reserved18 : 2;
-    uint64_t cerr_pbdout_parity_err : 1;
-    uint64_t cerr_pb_parity_err : 3;
-    uint64_t cerr_axflow_err : 5;
-    uint64_t cerr_axpush_wrerr : 2;
-    uint64_t _reserved0 : 33;
-#else
-    uint64_t _reserved0 : 33;
-    uint64_t cerr_axpush_wrerr : 2;
-    uint64_t cerr_axflow_err : 5;
-    uint64_t cerr_pb_parity_err : 3;
-    uint64_t cerr_pbdout_parity_err : 1;
-    uint64_t reserved18 : 2;
-    uint64_t cerr_scomtb_err : 1;
-    uint64_t cerr_bar_parity_err : 1;
-    uint64_t cerr_bcue_internal_err : 4;
-    uint64_t cerr_bcde_internal_err : 4;
-    uint64_t cerr_slv_internal_err : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt2_t;
-
-
-
-typedef union pba_rbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t rd_slvnum : 2;
-    uint64_t cur_rd_addr : 23;
-    uint64_t spare1 : 3;
-    uint64_t prefetch : 1;
-    uint64_t spare2 : 2;
-    uint64_t abort : 1;
-    uint64_t spare3 : 1;
-    uint64_t buffer_status : 7;
-    uint64_t spare4 : 1;
-    uint64_t masterid : 3;
-    uint64_t _reserved0 : 20;
-#else
-    uint64_t _reserved0 : 20;
-    uint64_t masterid : 3;
-    uint64_t spare4 : 1;
-    uint64_t buffer_status : 7;
-    uint64_t spare3 : 1;
-    uint64_t abort : 1;
-    uint64_t spare2 : 2;
-    uint64_t prefetch : 1;
-    uint64_t spare1 : 3;
-    uint64_t cur_rd_addr : 23;
-    uint64_t rd_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_rbufvaln_t;
-
-
-
-typedef union pba_wbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t wr_slvnum : 2;
-    uint64_t start_wr_addr : 30;
-    uint64_t spare1 : 3;
-    uint64_t wr_buffer_status : 5;
-    uint64_t spare2 : 1;
-    uint64_t wr_byte_count : 7;
-    uint64_t spare3 : 16;
-#else
-    uint64_t spare3 : 16;
-    uint64_t wr_byte_count : 7;
-    uint64_t spare2 : 1;
-    uint64_t wr_buffer_status : 5;
-    uint64_t spare1 : 3;
-    uint64_t start_wr_addr : 30;
-    uint64_t wr_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_wbufvaln_t;
-
-
-
-typedef union pba_mode {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 4;
-    uint64_t dis_rearb : 1;
-    uint64_t dis_mstid_match_pref_inv : 1;
-    uint64_t dis_slave_rdpipe : 1;
-    uint64_t dis_slave_wrpipe : 1;
-    uint64_t en_marker_ack : 1;
-    uint64_t dis_slvmatch_order : 1;
-    uint64_t en_second_wrbuf : 1;
-    uint64_t dis_rerequest_to : 1;
-    uint64_t inject_type : 2;
-    uint64_t inject_mode : 2;
-    uint64_t pba_region : 2;
-    uint64_t oci_marker_space : 3;
-    uint64_t bcde_ocitrans : 2;
-    uint64_t bcue_ocitrans : 2;
-    uint64_t dis_master_rd_pipe : 1;
-    uint64_t dis_master_wr_pipe : 1;
-    uint64_t en_slave_fairness : 1;
-    uint64_t en_event_count : 1;
-    uint64_t pb_noci_event_sel : 1;
-    uint64_t slv_event_mux : 2;
-    uint64_t enable_debug_bus : 1;
-    uint64_t debug_pb_not_oci : 1;
-    uint64_t debug_oci_mode : 5;
-    uint64_t reserved2 : 1;
-    uint64_t ocislv_fairness_mask : 5;
-    uint64_t ocislv_rereq_hang_div : 5;
-    uint64_t dis_chgrate_count : 1;
-    uint64_t pbreq_event_mux : 2;
-    uint64_t _reserved0 : 11;
-#else
-    uint64_t _reserved0 : 11;
-    uint64_t pbreq_event_mux : 2;
-    uint64_t dis_chgrate_count : 1;
-    uint64_t ocislv_rereq_hang_div : 5;
-    uint64_t ocislv_fairness_mask : 5;
-    uint64_t reserved2 : 1;
-    uint64_t debug_oci_mode : 5;
-    uint64_t debug_pb_not_oci : 1;
-    uint64_t enable_debug_bus : 1;
-    uint64_t slv_event_mux : 2;
-    uint64_t pb_noci_event_sel : 1;
-    uint64_t en_event_count : 1;
-    uint64_t en_slave_fairness : 1;
-    uint64_t dis_master_wr_pipe : 1;
-    uint64_t dis_master_rd_pipe : 1;
-    uint64_t bcue_ocitrans : 2;
-    uint64_t bcde_ocitrans : 2;
-    uint64_t oci_marker_space : 3;
-    uint64_t pba_region : 2;
-    uint64_t inject_mode : 2;
-    uint64_t inject_type : 2;
-    uint64_t dis_rerequest_to : 1;
-    uint64_t en_second_wrbuf : 1;
-    uint64_t dis_slvmatch_order : 1;
-    uint64_t en_marker_ack : 1;
-    uint64_t dis_slave_wrpipe : 1;
-    uint64_t dis_slave_rdpipe : 1;
-    uint64_t dis_mstid_match_pref_inv : 1;
-    uint64_t dis_rearb : 1;
-    uint64_t reserved0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_mode_t;
-
-
-
-typedef union pba_slvrst {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t set : 3;
-    uint64_t notimp1 : 1;
-    uint64_t in_prog : 4;
-    uint64_t busy_status : 4;
-    uint64_t _reserved0 : 52;
-#else
-    uint64_t _reserved0 : 52;
-    uint64_t busy_status : 4;
-    uint64_t in_prog : 4;
-    uint64_t notimp1 : 1;
-    uint64_t set : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvrst_t;
-
-
-
-typedef union pba_slvctln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable : 1;
-    uint64_t mid_match_value : 3;
-    uint64_t _reserved0 : 1;
-    uint64_t mid_care_mask : 3;
-    uint64_t write_ttype : 3;
-    uint64_t _reserved1 : 4;
-    uint64_t read_ttype : 1;
-    uint64_t read_prefetch_ctl : 2;
-    uint64_t buf_invalidate_ctl : 1;
-    uint64_t buf_alloc_w : 1;
-    uint64_t buf_alloc_a : 1;
-    uint64_t buf_alloc_b : 1;
-    uint64_t buf_alloc_c : 1;
-    uint64_t _reserved2 : 1;
-    uint64_t dis_write_gather : 1;
-    uint64_t wr_gather_timeout : 3;
-    uint64_t write_tsize : 7;
-    uint64_t extaddr : 14;
-    uint64_t _reserved3 : 15;
-#else
-    uint64_t _reserved3 : 15;
-    uint64_t extaddr : 14;
-    uint64_t write_tsize : 7;
-    uint64_t wr_gather_timeout : 3;
-    uint64_t dis_write_gather : 1;
-    uint64_t _reserved2 : 1;
-    uint64_t buf_alloc_c : 1;
-    uint64_t buf_alloc_b : 1;
-    uint64_t buf_alloc_a : 1;
-    uint64_t buf_alloc_w : 1;
-    uint64_t buf_invalidate_ctl : 1;
-    uint64_t read_prefetch_ctl : 2;
-    uint64_t read_ttype : 1;
-    uint64_t _reserved1 : 4;
-    uint64_t write_ttype : 3;
-    uint64_t mid_care_mask : 3;
-    uint64_t _reserved0 : 1;
-    uint64_t mid_match_value : 3;
-    uint64_t enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvctln_t;
-
-
-
-typedef union pba_bcde_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t stop : 1;
-    uint64_t start : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t start : 1;
-    uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcde_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t copy_length : 6;
-    uint64_t _reserved1 : 56;
-#else
-    uint64_t _reserved1 : 56;
-    uint64_t copy_length : 6;
-    uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_set_t;
-
-
-
-typedef union pba_bcde_stat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t running : 1;
-    uint64_t waiting : 1;
-    uint64_t wrcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t rdcmp : 6;
-    uint64_t debug : 9;
-    uint64_t stopped : 1;
-    uint64_t error : 1;
-    uint64_t done : 1;
-    uint64_t _reserved1 : 32;
-#else
-    uint64_t _reserved1 : 32;
-    uint64_t done : 1;
-    uint64_t error : 1;
-    uint64_t stopped : 1;
-    uint64_t debug : 9;
-    uint64_t rdcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t wrcmp : 6;
-    uint64_t waiting : 1;
-    uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_stat_t;
-
-
-
-typedef union pba_bcde_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved1 : 2;
-    uint64_t extaddr : 14;
-    uint64_t _reserved2 : 23;
-#else
-    uint64_t _reserved2 : 23;
-    uint64_t extaddr : 14;
-    uint64_t _reserved1 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_pbadr_t;
-
-
-
-typedef union pba_bcde_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t addr : 25;
-    uint64_t _reserved0 : 39;
-#else
-    uint64_t _reserved0 : 39;
-    uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ocibar_t;
-
-
-
-typedef union pba_bcue_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t stop : 1;
-    uint64_t start : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t start : 1;
-    uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcue_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t copy_length : 6;
-    uint64_t _reserved1 : 56;
-#else
-    uint64_t _reserved1 : 56;
-    uint64_t copy_length : 6;
-    uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_set_t;
-
-
-
-typedef union pba_bcue_stat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t running : 1;
-    uint64_t waiting : 1;
-    uint64_t wrcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t rdcmp : 6;
-    uint64_t debug : 9;
-    uint64_t stopped : 1;
-    uint64_t error : 1;
-    uint64_t done : 1;
-    uint64_t _reserved1 : 32;
-#else
-    uint64_t _reserved1 : 32;
-    uint64_t done : 1;
-    uint64_t error : 1;
-    uint64_t stopped : 1;
-    uint64_t debug : 9;
-    uint64_t rdcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t wrcmp : 6;
-    uint64_t waiting : 1;
-    uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_stat_t;
-
-
-
-typedef union pba_bcue_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved1 : 2;
-    uint64_t extaddr : 14;
-    uint64_t _reserved2 : 23;
-#else
-    uint64_t _reserved2 : 23;
-    uint64_t extaddr : 14;
-    uint64_t _reserved1 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_pbadr_t;
-
-
-
-typedef union pba_bcue_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t addr : 25;
-    uint64_t _reserved0 : 39;
-#else
-    uint64_t _reserved0 : 39;
-    uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ocibar_t;
-
-
-
-typedef union pba_pbocrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 16;
-    uint64_t event : 16;
-    uint64_t _reserved1 : 12;
-    uint64_t accum : 20;
-#else
-    uint64_t accum : 20;
-    uint64_t _reserved1 : 12;
-    uint64_t event : 16;
-    uint64_t _reserved0 : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_pbocrn_t;
-
-
-
-typedef union pba_xsndtx {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t snd_scope : 3;
-    uint64_t snd_qid : 1;
-    uint64_t snd_type : 1;
-    uint64_t snd_reservation : 1;
-    uint64_t spare6 : 2;
-    uint64_t snd_nodeid : 3;
-    uint64_t snd_chipid : 3;
-    uint64_t spare14 : 2;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t spare14 : 2;
-    uint64_t snd_chipid : 3;
-    uint64_t snd_nodeid : 3;
-    uint64_t spare6 : 2;
-    uint64_t snd_reservation : 1;
-    uint64_t snd_type : 1;
-    uint64_t snd_qid : 1;
-    uint64_t snd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndtx_t;
-
-
-
-typedef union pba_xcfg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pbax_en : 1;
-    uint64_t reservation_en : 1;
-    uint64_t snd_reset : 1;
-    uint64_t rcv_reset : 1;
-    uint64_t rcv_nodeid : 3;
-    uint64_t rcv_chipid : 3;
-    uint64_t spare10 : 2;
-    uint64_t rcv_brdcst_group : 8;
-    uint64_t rcv_datato_div : 5;
-    uint64_t spare25 : 2;
-    uint64_t snd_retry_count_overcom : 1;
-    uint64_t snd_retry_thresh : 8;
-    uint64_t snd_rsvto_div : 5;
-    uint64_t _reserved0 : 23;
-#else
-    uint64_t _reserved0 : 23;
-    uint64_t snd_rsvto_div : 5;
-    uint64_t snd_retry_thresh : 8;
-    uint64_t snd_retry_count_overcom : 1;
-    uint64_t spare25 : 2;
-    uint64_t rcv_datato_div : 5;
-    uint64_t rcv_brdcst_group : 8;
-    uint64_t spare10 : 2;
-    uint64_t rcv_chipid : 3;
-    uint64_t rcv_nodeid : 3;
-    uint64_t rcv_reset : 1;
-    uint64_t snd_reset : 1;
-    uint64_t reservation_en : 1;
-    uint64_t pbax_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xcfg_t;
-
-
-
-typedef union pba_xsndstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t snd_in_progress : 1;
-    uint64_t snd_error : 1;
-    uint64_t snd_status : 6;
-    uint64_t snd_retry_count : 8;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t snd_retry_count : 8;
-    uint64_t snd_status : 6;
-    uint64_t snd_error : 1;
-    uint64_t snd_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndstat_t;
-
-
-
-typedef union pba_xsnddat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pbax_datahi : 32;
-    uint64_t pbax_datalo : 32;
-#else
-    uint64_t pbax_datalo : 32;
-    uint64_t pbax_datahi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsnddat_t;
-
-
-
-typedef union pba_xrcvstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t rcv_in_progress : 1;
-    uint64_t rcv_error : 1;
-    uint64_t rcv_write_in_progress : 1;
-    uint64_t rcv_reservation_set : 1;
-    uint64_t rcv_capture : 14;
-    uint64_t _reserved0 : 46;
-#else
-    uint64_t _reserved0 : 46;
-    uint64_t rcv_capture : 14;
-    uint64_t rcv_reservation_set : 1;
-    uint64_t rcv_write_in_progress : 1;
-    uint64_t rcv_error : 1;
-    uint64_t rcv_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xrcvstat_t;
-
-
-
-typedef union pba_xshbrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t push_start : 29;
-    uint64_t _reserved0 : 35;
-#else
-    uint64_t _reserved0 : 35;
-    uint64_t push_start : 29;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshbrn_t;
-
-
-
-typedef union pba_xshcsn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t push_full : 1;
-    uint64_t push_empty : 1;
-    uint64_t spare1 : 2;
-    uint64_t push_intr_action : 2;
-    uint64_t push_length : 5;
-    uint64_t notimp1 : 2;
-    uint64_t push_write_ptr : 5;
-    uint64_t notimp2 : 3;
-    uint64_t push_read_ptr : 5;
-    uint64_t notimp3 : 5;
-    uint64_t push_enable : 1;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t push_enable : 1;
-    uint64_t notimp3 : 5;
-    uint64_t push_read_ptr : 5;
-    uint64_t notimp2 : 3;
-    uint64_t push_write_ptr : 5;
-    uint64_t notimp1 : 2;
-    uint64_t push_length : 5;
-    uint64_t push_intr_action : 2;
-    uint64_t spare1 : 2;
-    uint64_t push_empty : 1;
-    uint64_t push_full : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshcsn_t;
-
-
-
-typedef union pba_xshincn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved : 64;
-#else
-    uint64_t reserved : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshincn_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PBA_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pba_register_addresses.h b/src/ssx/pgp/registers/pba_register_addresses.h
deleted file mode 100755
index 1703629..0000000
--- a/src/ssx/pgp/registers/pba_register_addresses.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef __PBA_REGISTER_ADDRESSES_H__
-#define __PBA_REGISTER_ADDRESSES_H__
-
-// $Id: pba_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pba_register_addresses.h
-/// \brief Symbolic addresses for the PBA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define TRUSTEDPIB_BASE 0x02013f00
-#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
-#define PBA_BAR0 0x02013f00
-#define PBA_BAR1 0x02013f01
-#define PBA_BAR2 0x02013f02
-#define PBA_BAR3 0x02013f03
-#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
-#define PBA_BARMSK0 0x02013f04
-#define PBA_BARMSK1 0x02013f05
-#define PBA_BARMSK2 0x02013f06
-#define PBA_BARMSK3 0x02013f07
-#define PIB_BASE 0x02010840
-#define PBA_FIR 0x02010840
-#define PBA_FIR_AND 0x02010841
-#define PBA_FIR_OR 0x02010842
-#define PBA_FIRMASK 0x02010843
-#define PBA_FIRMASK_AND 0x02010844
-#define PBA_FIRMASK_OR 0x02010845
-#define PBA_FIRACT0 0x02010846
-#define PBA_FIRACT1 0x02010847
-#define PBA_OCCACT 0x0201084a
-#define PBA_CFG 0x0201084b
-#define PBA_ERRPT0 0x0201084c
-#define PBA_ERRPT1 0x0201084d
-#define PBA_ERRPT2 0x0201084e
-#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
-#define PBA_RBUFVAL0 0x02010850
-#define PBA_RBUFVAL1 0x02010851
-#define PBA_RBUFVAL2 0x02010852
-#define PBA_RBUFVAL3 0x02010853
-#define PBA_RBUFVAL4 0x02010854
-#define PBA_RBUFVAL5 0x02010855
-#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
-#define PBA_WBUFVAL0 0x02010858
-#define PBA_WBUFVAL1 0x02010859
-#define OCI_BASE 0x40020000
-#define PBA_MODE 0x40020000
-#define PBA_SLVRST 0x40020008
-#define PBA_SLVCTLN(n) (PBA_SLVCTL0 + ((PBA_SLVCTL1 - PBA_SLVCTL0) * (n)))
-#define PBA_SLVCTL0 0x40020020
-#define PBA_SLVCTL1 0x40020028
-#define PBA_SLVCTL2 0x40020030
-#define PBA_SLVCTL3 0x40020038
-#define PBA_BCDE_CTL 0x40020080
-#define PBA_BCDE_SET 0x40020088
-#define PBA_BCDE_STAT 0x40020090
-#define PBA_BCDE_PBADR 0x40020098
-#define PBA_BCDE_OCIBAR 0x400200a0
-#define PBA_BCUE_CTL 0x400200a8
-#define PBA_BCUE_SET 0x400200b0
-#define PBA_BCUE_STAT 0x400200b8
-#define PBA_BCUE_PBADR 0x400200c0
-#define PBA_BCUE_OCIBAR 0x400200c8
-#define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n)))
-#define PBA_PBOCR0 0x400200d0
-#define PBA_PBOCR1 0x400200d8
-#define PBA_PBOCR2 0x400200e0
-#define PBA_PBOCR3 0x400200e8
-#define PBA_PBOCR4 0x400200f0
-#define PBA_PBOCR5 0x400200f8
-#define PBA_XSNDTX 0x40020100
-#define PBA_XCFG 0x40020108
-#define PBA_XSNDSTAT 0x40020110
-#define PBA_XSNDDAT 0x40020118
-#define PBA_XRCVSTAT 0x40020120
-#define PBA_XSHBRN(n) (PBA_XSHBR0 + ((PBA_XSHBR1 - PBA_XSHBR0) * (n)))
-#define PBA_XSHBR0 0x40020130
-#define PBA_XSHBR1 0x40020150
-#define PBA_XSHCSN(n) (PBA_XSHCS0 + ((PBA_XSHCS1 - PBA_XSHCS0) * (n)))
-#define PBA_XSHCS0 0x40020138
-#define PBA_XSHCS1 0x40020158
-#define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n)))
-#define PBA_XSHINC0 0x40020140
-#define PBA_XSHINC1 0x40020160
-
-#endif // __PBA_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pc_firmware_registers.h b/src/ssx/pgp/registers/pc_firmware_registers.h
deleted file mode 100755
index 2c86308..0000000
--- a/src/ssx/pgp/registers/pc_firmware_registers.h
+++ /dev/null
@@ -1,442 +0,0 @@
-#ifndef __PC_FIRMWARE_REGISTERS_H__
-#define __PC_FIRMWARE_REGISTERS_H__
-
-// $Id: pc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pc_firmware_registers.h
-/// \brief C register structs for the PC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pc_pfth_modereg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pfth_cntr_dis : 1;
-    uint64_t pfth_charac_mode : 1;
-    uint64_t pfth_cntr_run_latch_gate_dis : 1;
-    uint64_t sprd_pfth_tx_run_latches : 8;
-    uint64_t tx_threads_stopped : 8;
-    uint64_t _reserved0 : 45;
-#else
-    uint64_t _reserved0 : 45;
-    uint64_t tx_threads_stopped : 8;
-    uint64_t sprd_pfth_tx_run_latches : 8;
-    uint64_t pfth_cntr_run_latch_gate_dis : 1;
-    uint64_t pfth_charac_mode : 1;
-    uint64_t pfth_cntr_dis : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_pfth_modereg_t;
-
-
-
-typedef union pc_occ_sprc {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 53;
-    uint64_t autoinc : 1;
-    uint64_t sprn : 7;
-    uint64_t reserved1 : 3;
-#else
-    uint64_t reserved1 : 3;
-    uint64_t sprn : 7;
-    uint64_t autoinc : 1;
-    uint64_t reserved0 : 53;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_occ_sprc_t;
-
-
-
-typedef union pc_occ_sprd {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_occ_sprd_t;
-
-
-
-typedef union pc_pfth_oha_instr_cnt_sel {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 62;
-    uint64_t value : 2;
-#else
-    uint64_t value : 2;
-    uint64_t _reserved0 : 62;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_pfth_oha_instr_cnt_sel_t;
-
-
-
-typedef union pc_pfth_throt_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t didt_trigger_enable : 1;
-    uint64_t isu_trigger_enable : 1;
-    uint64_t didt_throttle : 2;
-    uint64_t uthrottle : 2;
-    uint64_t force_suppress_speedup : 1;
-    uint64_t suppress_speedup_on_throttle : 1;
-    uint64_t core_slowdown : 1;
-    uint64_t suppress_on_slowdown : 1;
-    uint64_t isu_only_count_mode : 1;
-    uint64_t spare : 5;
-    uint64_t reserved : 48;
-#else
-    uint64_t reserved : 48;
-    uint64_t spare : 5;
-    uint64_t isu_only_count_mode : 1;
-    uint64_t suppress_on_slowdown : 1;
-    uint64_t core_slowdown : 1;
-    uint64_t suppress_speedup_on_throttle : 1;
-    uint64_t force_suppress_speedup : 1;
-    uint64_t uthrottle : 2;
-    uint64_t didt_throttle : 2;
-    uint64_t isu_trigger_enable : 1;
-    uint64_t didt_trigger_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_pfth_throt_reg_t;
-
-
-
-typedef union pc_direct_controln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 42;
-    uint64_t dc_prestart_sleep : 1;
-    uint64_t dc_prestart_winkle : 1;
-    uint64_t dc_clear_maint : 1;
-    uint64_t dc_ntc_flush : 1;
-    uint64_t reserved46 : 1;
-    uint64_t dc_prestart_nap : 1;
-    uint64_t dc_cancel_lost : 1;
-    uint64_t dc_reset_maint : 1;
-    uint64_t reserved50 : 1;
-    uint64_t dc_set_maint : 1;
-    uint64_t dc_goto_quiesce_state : 1;
-    uint64_t reserved53 : 1;
-    uint64_t dc_inj_test_hang : 2;
-    uint64_t dc_core_running : 1;
-    uint64_t dc_hang_inject : 1;
-    uint64_t dc_smt_start_suppress : 1;
-    uint64_t reserved59 : 1;
-    uint64_t dc_sreset_request : 1;
-    uint64_t dc_core_step : 1;
-    uint64_t dc_core_start : 1;
-    uint64_t dc_core_stop : 1;
-#else
-    uint64_t dc_core_stop : 1;
-    uint64_t dc_core_start : 1;
-    uint64_t dc_core_step : 1;
-    uint64_t dc_sreset_request : 1;
-    uint64_t reserved59 : 1;
-    uint64_t dc_smt_start_suppress : 1;
-    uint64_t dc_hang_inject : 1;
-    uint64_t dc_core_running : 1;
-    uint64_t dc_inj_test_hang : 2;
-    uint64_t reserved53 : 1;
-    uint64_t dc_goto_quiesce_state : 1;
-    uint64_t dc_set_maint : 1;
-    uint64_t reserved50 : 1;
-    uint64_t dc_reset_maint : 1;
-    uint64_t dc_cancel_lost : 1;
-    uint64_t dc_prestart_nap : 1;
-    uint64_t reserved46 : 1;
-    uint64_t dc_ntc_flush : 1;
-    uint64_t dc_clear_maint : 1;
-    uint64_t dc_prestart_winkle : 1;
-    uint64_t dc_prestart_sleep : 1;
-    uint64_t reserved0 : 42;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_direct_controln_t;
-
-
-
-typedef union pc_ras_moderegn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 43;
-    uint64_t mr_thread_in_debug_mode : 1;
-    uint64_t mr_pmon_inhibit : 1;
-    uint64_t mr_fence_interrupts : 1;
-    uint64_t mr_stop_fetch : 1;
-    uint64_t mr_stop_prefetch : 1;
-    uint64_t mr_stop_dispatch : 1;
-    uint64_t mr_single_decode : 1;
-    uint64_t mr_do_single_mode : 1;
-    uint64_t mr_one_ppc_mode : 1;
-    uint64_t mr_hang_test_ctrl : 2;
-    uint64_t mr_attempt_gps_hr : 3;
-    uint64_t mr_hang_dis : 1;
-    uint64_t mr_on_corehng : 1;
-    uint64_t mr_on_ambihng : 1;
-    uint64_t mr_on_nesthng : 1;
-    uint64_t mr_recov_enable : 1;
-    uint64_t mr_block_hmi_on_maint : 1;
-    uint64_t mr_fence_intr_on_checkstop : 1;
-#else
-    uint64_t mr_fence_intr_on_checkstop : 1;
-    uint64_t mr_block_hmi_on_maint : 1;
-    uint64_t mr_recov_enable : 1;
-    uint64_t mr_on_nesthng : 1;
-    uint64_t mr_on_ambihng : 1;
-    uint64_t mr_on_corehng : 1;
-    uint64_t mr_hang_dis : 1;
-    uint64_t mr_attempt_gps_hr : 3;
-    uint64_t mr_hang_test_ctrl : 2;
-    uint64_t mr_one_ppc_mode : 1;
-    uint64_t mr_do_single_mode : 1;
-    uint64_t mr_single_decode : 1;
-    uint64_t mr_stop_dispatch : 1;
-    uint64_t mr_stop_prefetch : 1;
-    uint64_t mr_stop_fetch : 1;
-    uint64_t mr_fence_interrupts : 1;
-    uint64_t mr_pmon_inhibit : 1;
-    uint64_t mr_thread_in_debug_mode : 1;
-    uint64_t reserved0 : 43;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_ras_moderegn_t;
-
-
-
-typedef union pc_ras_statusn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t quiesce_status : 20;
-    uint64_t reserved20 : 1;
-    uint64_t reserved21 : 1;
-    uint64_t reserved22 : 1;
-    uint64_t other_thread_active : 1;
-    uint64_t hang_fsm : 3;
-    uint64_t reserved27 : 1;
-    uint64_t hang_hist0 : 1;
-    uint64_t hang_hist1 : 1;
-    uint64_t hang_hist2 : 1;
-    uint64_t hang_hist3 : 1;
-    uint64_t reserved32 : 1;
-    uint64_t hr_comp_cnt : 8;
-    uint64_t smt_dead_stop : 1;
-    uint64_t stop_fetch : 1;
-    uint64_t stop_dispatch : 1;
-    uint64_t stop_completion : 1;
-    uint64_t hold_decode : 1;
-    uint64_t reserved46 : 1;
-    uint64_t reserved47 : 1;
-    uint64_t thread_enabled : 1;
-    uint64_t pow_status_thread_state : 4;
-    uint64_t reserved53 : 1;
-    uint64_t maint_single_mode : 1;
-    uint64_t reserved55 : 1;
-    uint64_t reserved56 : 1;
-    uint64_t reserved57 : 7;
-#else
-    uint64_t reserved57 : 7;
-    uint64_t reserved56 : 1;
-    uint64_t reserved55 : 1;
-    uint64_t maint_single_mode : 1;
-    uint64_t reserved53 : 1;
-    uint64_t pow_status_thread_state : 4;
-    uint64_t thread_enabled : 1;
-    uint64_t reserved47 : 1;
-    uint64_t reserved46 : 1;
-    uint64_t hold_decode : 1;
-    uint64_t stop_completion : 1;
-    uint64_t stop_dispatch : 1;
-    uint64_t stop_fetch : 1;
-    uint64_t smt_dead_stop : 1;
-    uint64_t hr_comp_cnt : 8;
-    uint64_t reserved32 : 1;
-    uint64_t hang_hist3 : 1;
-    uint64_t hang_hist2 : 1;
-    uint64_t hang_hist1 : 1;
-    uint64_t hang_hist0 : 1;
-    uint64_t reserved27 : 1;
-    uint64_t hang_fsm : 3;
-    uint64_t other_thread_active : 1;
-    uint64_t reserved22 : 1;
-    uint64_t reserved21 : 1;
-    uint64_t reserved20 : 1;
-    uint64_t quiesce_status : 20;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_ras_statusn_t;
-
-
-
-typedef union pc_pow_statusn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t thread_state : 4;
-    uint64_t thread_pow_state : 2;
-    uint64_t smt_mode : 3;
-    uint64_t hmi_intr : 1;
-    uint64_t maybe_ext_intr : 1;
-    uint64_t decr_intr : 1;
-    uint64_t maybe_debug_intr : 1;
-    uint64_t hdec_intr : 1;
-    uint64_t maybe_pmu_intr : 1;
-    uint64_t sp_attn_intr : 1;
-    uint64_t sreset_type : 3;
-    uint64_t reserved19 : 1;
-    uint64_t sreset_pending : 1;
-    uint64_t debug_fetch_stop : 1;
-    uint64_t async_pending : 1;
-    uint64_t core_pow_state : 3;
-    uint64_t reserved26 : 3;
-    uint64_t _reserved0 : 35;
-#else
-    uint64_t _reserved0 : 35;
-    uint64_t reserved26 : 3;
-    uint64_t core_pow_state : 3;
-    uint64_t async_pending : 1;
-    uint64_t debug_fetch_stop : 1;
-    uint64_t sreset_pending : 1;
-    uint64_t reserved19 : 1;
-    uint64_t sreset_type : 3;
-    uint64_t sp_attn_intr : 1;
-    uint64_t maybe_pmu_intr : 1;
-    uint64_t hdec_intr : 1;
-    uint64_t maybe_debug_intr : 1;
-    uint64_t decr_intr : 1;
-    uint64_t maybe_ext_intr : 1;
-    uint64_t hmi_intr : 1;
-    uint64_t smt_mode : 3;
-    uint64_t thread_pow_state : 2;
-    uint64_t thread_state : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pc_pow_statusn_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PC_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pc_register_addresses.h b/src/ssx/pgp/registers/pc_register_addresses.h
deleted file mode 100755
index 8b9baf2..0000000
--- a/src/ssx/pgp/registers/pc_register_addresses.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __PC_REGISTER_ADDRESSES_H__
-#define __PC_REGISTER_ADDRESSES_H__
-
-// $Id: pc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pc_register_addresses.h
-/// \brief Symbolic addresses for the PC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PC_PCB_BASE 0x10010000
-#define PC_PFTH_MODEREG 0x100132a7
-#define PC_OCC_SPRC 0x100132ab
-#define PC_OCC_SPRD 0x100132ac
-#define PC_PFTH_THROT_REG 0x100132ad
-#define PC_DIRECT_CONTROLN(n) (PC_DIRECT_CONTROL0 + ((PC_DIRECT_CONTROL1 - PC_DIRECT_CONTROL0) * (n)))
-#define PC_DIRECT_CONTROL0 0x10013000
-#define PC_DIRECT_CONTROL1 0x10013010
-#define PC_DIRECT_CONTROL2 0x10013020
-#define PC_DIRECT_CONTROL3 0x10013030
-#define PC_DIRECT_CONTROL4 0x10013040
-#define PC_DIRECT_CONTROL5 0x10013050
-#define PC_DIRECT_CONTROL6 0x10013060
-#define PC_DIRECT_CONTROL7 0x10013070
-#define PC_RAS_MODEREGN(n) (PC_RAS_MODEREG0 + ((PC_RAS_MODEREG1 - PC_RAS_MODEREG0) * (n)))
-#define PC_RAS_MODEREG0 0x10013001
-#define PC_RAS_MODEREG1 0x10013011
-#define PC_RAS_MODEREG2 0x10013021
-#define PC_RAS_MODEREG3 0x10013031
-#define PC_RAS_MODEREG4 0x10013041
-#define PC_RAS_MODEREG5 0x10013051
-#define PC_RAS_MODEREG6 0x10013061
-#define PC_RAS_MODEREG7 0x10013071
-#define PC_RAS_STATUSN(n) (PC_RAS_STATUS0 + ((PC_RAS_STATUS1 - PC_RAS_STATUS0) * (n)))
-#define PC_RAS_STATUS0 0x10013002
-#define PC_RAS_STATUS1 0x10013012
-#define PC_RAS_STATUS2 0x10013022
-#define PC_RAS_STATUS3 0x10013032
-#define PC_RAS_STATUS4 0x10013042
-#define PC_RAS_STATUS5 0x10013052
-#define PC_RAS_STATUS6 0x10013062
-#define PC_RAS_STATUS7 0x10013072
-#define PC_POW_STATUSN(n) (PC_POW_STATUS0 + ((PC_POW_STATUS1 - PC_POW_STATUS0) * (n)))
-#define PC_POW_STATUS0 0x10013004
-#define PC_POW_STATUS1 0x10013014
-#define PC_POW_STATUS2 0x10013024
-#define PC_POW_STATUS3 0x10013034
-#define PC_POW_STATUS4 0x10013044
-#define PC_POW_STATUS5 0x10013054
-#define PC_POW_STATUS6 0x10013064
-#define PC_POW_STATUS7 0x10013074
-
-#endif // __PC_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pcbs_firmware_registers.h b/src/ssx/pgp/registers/pcbs_firmware_registers.h
deleted file mode 100755
index 1d268a2..0000000
--- a/src/ssx/pgp/registers/pcbs_firmware_registers.h
+++ /dev/null
@@ -1,2477 +0,0 @@
-#ifndef __PCBS_FIRMWARE_REGISTERS_H__
-#define __PCBS_FIRMWARE_REGISTERS_H__
-
-// $Id: pcbs_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pcbs_firmware_registers.h
-/// \brief C register structs for the PCBS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pcbs_pmgp0_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pm_disable : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t perv_thold : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t dpll_lock : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t _reserved0 : 10;
-#else
-    uint64_t _reserved0 : 10;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t dpll_lock : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t perv_thold : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t pm_disable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp0_reg_t;
-
-
-
-typedef union pcbs_pmgp0_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pm_disable : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t perv_thold : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t dpll_lock : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t _reserved0 : 10;
-#else
-    uint64_t _reserved0 : 10;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t dpll_lock : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t perv_thold : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t pm_disable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp0_reg_and_t;
-
-
-
-typedef union pcbs_pmgp0_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pm_disable : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t perv_thold : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t dpll_lock : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t _reserved0 : 10;
-#else
-    uint64_t _reserved0 : 10;
-    uint64_t block_reg_wkup_sources : 1;
-    uint64_t regular_wkup_available : 1;
-    uint64_t special_wkup_all_sources_ored : 1;
-    uint64_t dpll_lock : 1;
-    uint64_t wakeup_int_type : 2;
-    uint64_t pmgp0_spare3 : 1;
-    uint64_t chksw_hw259509_enable : 1;
-    uint64_t chksw_hw257534_disable : 1;
-    uint64_t chksw_hw245103_disable : 1;
-    uint64_t chksw_hw273115_disable : 1;
-    uint64_t chksw_hw241939_disable : 1;
-    uint64_t tp_cplt_ivrm_refbypass_dc : 1;
-    uint64_t l3_enable_switch : 1;
-    uint64_t pm_slv_winkle_fence : 1;
-    uint64_t tp_tc_dpll_testmode_dc : 1;
-    uint64_t block_all_wakeup_sources : 1;
-    uint64_t thold_timer_sel : 2;
-    uint64_t tp_clkglm_const_dc : 1;
-    uint64_t tp_clkglm_core_sel_dc : 2;
-    uint64_t special_wkup_done : 1;
-    uint64_t tp_clkglm_eco_sel_dc : 1;
-    uint64_t tp_clkglm_sel_dc : 3;
-    uint64_t tp_clk_async_reset_dc : 3;
-    uint64_t chksw_hw257424_disable : 1;
-    uint64_t tp_tc_pervasive_eco_fence : 1;
-    uint64_t tp_tc_core2cache_fence : 1;
-    uint64_t tp_tc_cache2core_fence : 1;
-    uint64_t dpll_testout_ctl : 8;
-    uint64_t pmgp0_spare_bit11 : 1;
-    uint64_t dpll_reset : 1;
-    uint64_t pmgp0_spare2 : 1;
-    uint64_t dpll_lock_sense : 1;
-    uint64_t pm_dpll_timer_ena : 1;
-    uint64_t cpm_cal_set_val : 1;
-    uint64_t cpm_cal_set_override_en : 1;
-    uint64_t perv_thold : 1;
-    uint64_t dpll_thold : 1;
-    uint64_t tp_tc_restart_core_domain : 1;
-    uint64_t pmgp0_spare_bit1 : 1;
-    uint64_t pm_disable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp0_reg_or_t;
-
-
-
-typedef union pcbs_pmgp1_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t sleep_power_down_en : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t _reserved0 : 43;
-#else
-    uint64_t _reserved0 : 43;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_down_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp1_reg_t;
-
-
-
-typedef union pcbs_pmgp1_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t sleep_power_down_en : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t _reserved0 : 43;
-#else
-    uint64_t _reserved0 : 43;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_down_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp1_reg_and_t;
-
-
-
-typedef union pcbs_pmgp1_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t sleep_power_down_en : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t _reserved0 : 43;
-#else
-    uint64_t _reserved0 : 43;
-    uint64_t disable_force_deep_to_fast_winkle : 1;
-    uint64_t disable_force_deep_to_fast_sleep : 1;
-    uint64_t serialize_pfet_powerup : 1;
-    uint64_t serialize_pfet_powerdown : 1;
-    uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1;
-    uint64_t pmicr_latency_en : 1;
-    uint64_t ivrm_safe_mode_force_active : 1;
-    uint64_t ivrm_safe_mode_en : 1;
-    uint64_t force_safe_mode : 1;
-    uint64_t pm_spr_override_en : 1;
-    uint64_t dpll_freq_override_enable : 1;
-    uint64_t endp_reset_pm_only : 1;
-    uint64_t oha_spc_wkup_override : 1;
-    uint64_t oha_pm_wkup_override : 1;
-    uint64_t oha_wkup_override_en : 1;
-    uint64_t winkle_power_off_sel : 1;
-    uint64_t winkle_power_up_en : 1;
-    uint64_t winkle_power_down_en : 1;
-    uint64_t sleep_power_off_sel : 1;
-    uint64_t sleep_power_up_en : 1;
-    uint64_t sleep_power_down_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmgp1_reg_or_t;
-
-
-
-typedef union pcbs_pfvddcntlstat_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_vdd_pfet_force_state : 2;
-    uint64_t eco_vdd_pfet_force_state : 2;
-    uint64_t core_vdd_pfet_val_override : 1;
-    uint64_t core_vdd_pfet_sel_override : 1;
-    uint64_t eco_vdd_pfet_val_override : 1;
-    uint64_t eco_vdd_pfet_sel_override : 1;
-    uint64_t core_vdd_pfet_enable_regulation_finger : 1;
-    uint64_t eco_vdd_pfet_enable_regulation_finger : 1;
-    uint64_t core_vdd_pfet_enable_value : 12;
-    uint64_t core_vdd_pfet_sel_value : 4;
-    uint64_t eco_vdd_pfet_enable_value : 12;
-    uint64_t eco_vdd_pfet_sel_value : 4;
-    uint64_t core_vdd_pg_state : 4;
-    uint64_t core_vdd_pg_sel : 4;
-    uint64_t eco_vdd_pg_state : 4;
-    uint64_t eco_vdd_pg_sel : 4;
-    uint64_t _reserved0 : 6;
-#else
-    uint64_t _reserved0 : 6;
-    uint64_t eco_vdd_pg_sel : 4;
-    uint64_t eco_vdd_pg_state : 4;
-    uint64_t core_vdd_pg_sel : 4;
-    uint64_t core_vdd_pg_state : 4;
-    uint64_t eco_vdd_pfet_sel_value : 4;
-    uint64_t eco_vdd_pfet_enable_value : 12;
-    uint64_t core_vdd_pfet_sel_value : 4;
-    uint64_t core_vdd_pfet_enable_value : 12;
-    uint64_t eco_vdd_pfet_enable_regulation_finger : 1;
-    uint64_t core_vdd_pfet_enable_regulation_finger : 1;
-    uint64_t eco_vdd_pfet_sel_override : 1;
-    uint64_t eco_vdd_pfet_val_override : 1;
-    uint64_t core_vdd_pfet_sel_override : 1;
-    uint64_t core_vdd_pfet_val_override : 1;
-    uint64_t eco_vdd_pfet_force_state : 2;
-    uint64_t core_vdd_pfet_force_state : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pfvddcntlstat_reg_t;
-
-
-
-typedef union pcbs_pfvcscntlstat_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_vcs_pfet_force_state : 2;
-    uint64_t eco_vcs_pfet_force_state : 2;
-    uint64_t core_vcs_pfet_val_override : 1;
-    uint64_t core_vcs_pfet_sel_override : 1;
-    uint64_t eco_vcs_pfet_val_override : 1;
-    uint64_t eco_vcs_pfet_sel_override : 1;
-    uint64_t core_vcs_pfet_enable_regulation_finger : 1;
-    uint64_t eco_vcs_pfet_enable_regulation_finger : 1;
-    uint64_t core_vcs_pfet_enable_value : 12;
-    uint64_t core_vcs_pfet_sel_value : 4;
-    uint64_t eco_vcs_pfet_enable_value : 12;
-    uint64_t eco_vcs_pfet_sel_value : 4;
-    uint64_t core_vcs_pg_state : 4;
-    uint64_t core_vcs_pg_sel : 4;
-    uint64_t eco_vcs_pg_state : 4;
-    uint64_t eco_vcs_pg_sel : 4;
-    uint64_t _reserved0 : 6;
-#else
-    uint64_t _reserved0 : 6;
-    uint64_t eco_vcs_pg_sel : 4;
-    uint64_t eco_vcs_pg_state : 4;
-    uint64_t core_vcs_pg_sel : 4;
-    uint64_t core_vcs_pg_state : 4;
-    uint64_t eco_vcs_pfet_sel_value : 4;
-    uint64_t eco_vcs_pfet_enable_value : 12;
-    uint64_t core_vcs_pfet_sel_value : 4;
-    uint64_t core_vcs_pfet_enable_value : 12;
-    uint64_t eco_vcs_pfet_enable_regulation_finger : 1;
-    uint64_t core_vcs_pfet_enable_regulation_finger : 1;
-    uint64_t eco_vcs_pfet_sel_override : 1;
-    uint64_t eco_vcs_pfet_val_override : 1;
-    uint64_t core_vcs_pfet_sel_override : 1;
-    uint64_t core_vcs_pfet_val_override : 1;
-    uint64_t eco_vcs_pfet_force_state : 2;
-    uint64_t core_vcs_pfet_force_state : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pfvcscntlstat_reg_t;
-
-
-
-typedef union pcbs_pfsense_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t tp_core_vdd_pfet_enable_sense : 12;
-    uint64_t tp_eco_vdd_pfet_enable_sense : 12;
-    uint64_t tp_core_vcs_pfet_enable_sense : 12;
-    uint64_t tp_eco_vcs_pfet_enable_sense : 12;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t tp_eco_vcs_pfet_enable_sense : 12;
-    uint64_t tp_core_vcs_pfet_enable_sense : 12;
-    uint64_t tp_eco_vdd_pfet_enable_sense : 12;
-    uint64_t tp_core_vdd_pfet_enable_sense : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pfsense_reg_t;
-
-
-
-typedef union pcbs_pmerrsum_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pm_error : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t pm_error : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmerrsum_reg_t;
-
-
-
-typedef union pcbs_pmerr_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_err : 1;
-    uint64_t pcbs_sleep_exit_invoke_pore_err : 1;
-    uint64_t pcbs_winkle_entry_notify_pmc_err : 1;
-    uint64_t pcbs_winkle_entry_send_int_assist_err : 1;
-    uint64_t pcbs_winkle_exit_notify_pmc_err : 1;
-    uint64_t pcbs_wait_dpll_lock_err : 1;
-    uint64_t pcbs_spare8_err : 1;
-    uint64_t pcbs_winkle_exit_send_int_assist_err : 1;
-    uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1;
-    uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1;
-    uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1;
-    uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1;
-    uint64_t pcbs_eco_rs_bypass_confusion_err : 1;
-    uint64_t pcbs_core_rs_bypass_confusion_err : 1;
-    uint64_t pcbs_read_lpst_in_pstate_mode_err : 1;
-    uint64_t pcbs_lpst_read_corr_err : 1;
-    uint64_t pcbs_lpst_read_uncorr_err : 1;
-    uint64_t pcbs_pfet_strength_overflow_err : 1;
-    uint64_t pcbs_vds_lookup_err : 1;
-    uint64_t pcbs_idle_interrupt_timeout_err : 1;
-    uint64_t pcbs_pstate_interrupt_timeout_err : 1;
-    uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1;
-    uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1;
-    uint64_t pcbs_global_actual_pstate_protocol_err : 1;
-    uint64_t pcbs_pmax_protocol_err : 1;
-    uint64_t pcbs_ivrm_gross_or_fine_err : 1;
-    uint64_t pcbs_ivrm_range_err : 1;
-    uint64_t pcbs_dpll_cpm_fmin_err : 1;
-    uint64_t pcbs_dpll_dco_full_err : 1;
-    uint64_t pcbs_dpll_dco_empty_err : 1;
-    uint64_t pcbs_dpll_int_err : 1;
-    uint64_t pcbs_fmin_and_not_cpmbit_err : 1;
-    uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1;
-    uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1;
-    uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1;
-    uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1;
-    uint64_t pcbs_occ_heartbeat_loss_err : 1;
-    uint64_t pcbs_spare39_err : 1;
-    uint64_t pcbs_spare40_err : 1;
-    uint64_t pcbs_spare41_err : 1;
-    uint64_t pcbs_spare42_err : 1;
-    uint64_t _reserved0 : 21;
-#else
-    uint64_t _reserved0 : 21;
-    uint64_t pcbs_spare42_err : 1;
-    uint64_t pcbs_spare41_err : 1;
-    uint64_t pcbs_spare40_err : 1;
-    uint64_t pcbs_spare39_err : 1;
-    uint64_t pcbs_occ_heartbeat_loss_err : 1;
-    uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1;
-    uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1;
-    uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1;
-    uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1;
-    uint64_t pcbs_fmin_and_not_cpmbit_err : 1;
-    uint64_t pcbs_dpll_int_err : 1;
-    uint64_t pcbs_dpll_dco_empty_err : 1;
-    uint64_t pcbs_dpll_dco_full_err : 1;
-    uint64_t pcbs_dpll_cpm_fmin_err : 1;
-    uint64_t pcbs_ivrm_range_err : 1;
-    uint64_t pcbs_ivrm_gross_or_fine_err : 1;
-    uint64_t pcbs_pmax_protocol_err : 1;
-    uint64_t pcbs_global_actual_pstate_protocol_err : 1;
-    uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1;
-    uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1;
-    uint64_t pcbs_pstate_interrupt_timeout_err : 1;
-    uint64_t pcbs_idle_interrupt_timeout_err : 1;
-    uint64_t pcbs_vds_lookup_err : 1;
-    uint64_t pcbs_pfet_strength_overflow_err : 1;
-    uint64_t pcbs_lpst_read_uncorr_err : 1;
-    uint64_t pcbs_lpst_read_corr_err : 1;
-    uint64_t pcbs_read_lpst_in_pstate_mode_err : 1;
-    uint64_t pcbs_core_rs_bypass_confusion_err : 1;
-    uint64_t pcbs_eco_rs_bypass_confusion_err : 1;
-    uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1;
-    uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1;
-    uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1;
-    uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1;
-    uint64_t pcbs_winkle_exit_send_int_assist_err : 1;
-    uint64_t pcbs_spare8_err : 1;
-    uint64_t pcbs_wait_dpll_lock_err : 1;
-    uint64_t pcbs_winkle_exit_notify_pmc_err : 1;
-    uint64_t pcbs_winkle_entry_send_int_assist_err : 1;
-    uint64_t pcbs_winkle_entry_notify_pmc_err : 1;
-    uint64_t pcbs_sleep_exit_invoke_pore_err : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_err : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmerr_reg_t;
-
-
-
-typedef union pcbs_pmerrmask_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1;
-    uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1;
-    uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1;
-    uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1;
-    uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1;
-    uint64_t pcbs_wait_dpll_lock_err_mask : 1;
-    uint64_t pcbs_spare8_err_mask : 1;
-    uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1;
-    uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1;
-    uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1;
-    uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1;
-    uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1;
-    uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1;
-    uint64_t pcbs_lpst_read_corr_err_mask : 1;
-    uint64_t pcbs_lpst_read_uncorr_err_mask : 1;
-    uint64_t pcbs_pfet_strength_overflow_err_mask : 1;
-    uint64_t pcbs_vds_lookup_err_mask : 1;
-    uint64_t pcbs_idle_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1;
-    uint64_t pcbs_pmax_protocol_err_mask : 1;
-    uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1;
-    uint64_t pcbs_ivrm_range_err_mask : 1;
-    uint64_t pcbs_dpll_cpm_fmin_err_mask : 1;
-    uint64_t pcbs_dpll_dco_full_err_mask : 1;
-    uint64_t pcbs_dpll_dco_empty_err_mask : 1;
-    uint64_t pcbs_dpll_int_err_mask : 1;
-    uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1;
-    uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1;
-    uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1;
-    uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_occ_heartbeat_loss_err_mask : 1;
-    uint64_t pcbs_spare39_err_mask : 1;
-    uint64_t pcbs_spare40_err_mask : 1;
-    uint64_t pcbs_spare41_err_mask : 1;
-    uint64_t pcbs_spare42_err_mask : 1;
-    uint64_t _reserved0 : 21;
-#else
-    uint64_t _reserved0 : 21;
-    uint64_t pcbs_spare42_err_mask : 1;
-    uint64_t pcbs_spare41_err_mask : 1;
-    uint64_t pcbs_spare40_err_mask : 1;
-    uint64_t pcbs_spare39_err_mask : 1;
-    uint64_t pcbs_occ_heartbeat_loss_err_mask : 1;
-    uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1;
-    uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1;
-    uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1;
-    uint64_t pcbs_dpll_int_err_mask : 1;
-    uint64_t pcbs_dpll_dco_empty_err_mask : 1;
-    uint64_t pcbs_dpll_dco_full_err_mask : 1;
-    uint64_t pcbs_dpll_cpm_fmin_err_mask : 1;
-    uint64_t pcbs_ivrm_range_err_mask : 1;
-    uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1;
-    uint64_t pcbs_pmax_protocol_err_mask : 1;
-    uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1;
-    uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_idle_interrupt_timeout_err_mask : 1;
-    uint64_t pcbs_vds_lookup_err_mask : 1;
-    uint64_t pcbs_pfet_strength_overflow_err_mask : 1;
-    uint64_t pcbs_lpst_read_uncorr_err_mask : 1;
-    uint64_t pcbs_lpst_read_corr_err_mask : 1;
-    uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1;
-    uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1;
-    uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1;
-    uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1;
-    uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1;
-    uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1;
-    uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1;
-    uint64_t pcbs_spare8_err_mask : 1;
-    uint64_t pcbs_wait_dpll_lock_err_mask : 1;
-    uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1;
-    uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1;
-    uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1;
-    uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1;
-    uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmerrmask_reg_t;
-
-
-
-typedef union pcbs_pmspcwkupfsp_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t fsp_special_wakeup : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t fsp_special_wakeup : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmspcwkupfsp_reg_t;
-
-
-
-typedef union pcbs_pmspcwkupocc_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_special_wakeup : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t occ_special_wakeup : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmspcwkupocc_reg_t;
-
-
-
-typedef union pcbs_pmspcwkupphyp_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t phyp_special_wakeup : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t phyp_special_wakeup : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmspcwkupphyp_reg_t;
-
-
-
-typedef union pcbs_pmstatehistphyp_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t phyp_pm_state : 3;
-    uint64_t phyp_past_core_instruct_stop : 1;
-    uint64_t phyp_past_core_clk_stop : 1;
-    uint64_t phyp_past_core_pwr_off : 1;
-    uint64_t phyp_past_eco_clk_stop : 1;
-    uint64_t phyp_past_eco_pwr_off : 1;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t phyp_past_eco_pwr_off : 1;
-    uint64_t phyp_past_eco_clk_stop : 1;
-    uint64_t phyp_past_core_pwr_off : 1;
-    uint64_t phyp_past_core_clk_stop : 1;
-    uint64_t phyp_past_core_instruct_stop : 1;
-    uint64_t phyp_pm_state : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmstatehistphyp_reg_t;
-
-
-
-typedef union pcbs_pmstatehistfsp_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t fsp_pm_state : 3;
-    uint64_t fsp_past_core_instruct_stop : 1;
-    uint64_t fsp_past_core_clk_stop : 1;
-    uint64_t fsp_past_core_pwr_off : 1;
-    uint64_t fsp_past_eco_clk_stop : 1;
-    uint64_t fsp_past_eco_pwr_off : 1;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t fsp_past_eco_pwr_off : 1;
-    uint64_t fsp_past_eco_clk_stop : 1;
-    uint64_t fsp_past_core_pwr_off : 1;
-    uint64_t fsp_past_core_clk_stop : 1;
-    uint64_t fsp_past_core_instruct_stop : 1;
-    uint64_t fsp_pm_state : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmstatehistfsp_reg_t;
-
-
-
-typedef union pcbs_pmstatehistocc_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_pm_state : 3;
-    uint64_t occ_past_core_instruct_stop : 1;
-    uint64_t occ_past_core_clk_stop : 1;
-    uint64_t occ_past_core_pwr_off : 1;
-    uint64_t occ_past_eco_clk_stop : 1;
-    uint64_t occ_past_eco_pwr_off : 1;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t occ_past_eco_pwr_off : 1;
-    uint64_t occ_past_eco_clk_stop : 1;
-    uint64_t occ_past_core_pwr_off : 1;
-    uint64_t occ_past_core_clk_stop : 1;
-    uint64_t occ_past_core_instruct_stop : 1;
-    uint64_t occ_pm_state : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmstatehistocc_reg_t;
-
-
-
-typedef union pcbs_pmstatehistperf_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t perf_pm_state : 3;
-    uint64_t perf_past_core_instruct_stop : 1;
-    uint64_t perf_past_core_clk_stop : 1;
-    uint64_t perf_past_core_pwr_off : 1;
-    uint64_t perf_past_eco_clk_stop : 1;
-    uint64_t perf_past_eco_pwr_off : 1;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t perf_past_eco_pwr_off : 1;
-    uint64_t perf_past_eco_clk_stop : 1;
-    uint64_t perf_past_core_pwr_off : 1;
-    uint64_t perf_past_core_clk_stop : 1;
-    uint64_t perf_past_core_instruct_stop : 1;
-    uint64_t perf_pm_state : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmstatehistperf_reg_t;
-
-
-
-typedef union pcbs_idlefsmgotocmd_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t idle_fsm_goto_cmd : 2;
-    uint64_t babystp_trigger_sleep_entry : 1;
-    uint64_t babystp_trigger_winkle_entry : 1;
-    uint64_t babystp_trigger_wakeup : 1;
-    uint64_t _reserved0 : 59;
-#else
-    uint64_t _reserved0 : 59;
-    uint64_t babystp_trigger_wakeup : 1;
-    uint64_t babystp_trigger_winkle_entry : 1;
-    uint64_t babystp_trigger_sleep_entry : 1;
-    uint64_t idle_fsm_goto_cmd : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_idlefsmgotocmd_reg_t;
-
-
-
-typedef union pcbs_corepfpudly_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_powup_dly0 : 4;
-    uint64_t core_powup_dly1 : 4;
-    uint64_t core_power_up_delay_sel : 12;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t core_power_up_delay_sel : 12;
-    uint64_t core_powup_dly1 : 4;
-    uint64_t core_powup_dly0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_corepfpudly_reg_t;
-
-
-
-typedef union pcbs_corepfpddly_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_powdn_dly0 : 4;
-    uint64_t core_powdn_dly1 : 4;
-    uint64_t core_power_dn_delay_sel : 12;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t core_power_dn_delay_sel : 12;
-    uint64_t core_powdn_dly1 : 4;
-    uint64_t core_powdn_dly0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_corepfpddly_reg_t;
-
-
-
-typedef union pcbs_corepfvret_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t core_vret_sel : 4;
-    uint64_t core_voff_sel : 4;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t core_voff_sel : 4;
-    uint64_t core_vret_sel : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_corepfvret_reg_t;
-
-
-
-typedef union pcbs_ecopfpudly_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t eco_powup_dly0 : 4;
-    uint64_t eco_powup_dly1 : 4;
-    uint64_t eco_power_up_delay_sel : 12;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t eco_power_up_delay_sel : 12;
-    uint64_t eco_powup_dly1 : 4;
-    uint64_t eco_powup_dly0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ecopfpudly_reg_t;
-
-
-
-typedef union pcbs_ecopfpddly_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t eco_powdn_dly0 : 4;
-    uint64_t eco_powdn_dly1 : 4;
-    uint64_t eco_power_dn_delay_sel : 12;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t eco_power_dn_delay_sel : 12;
-    uint64_t eco_powdn_dly1 : 4;
-    uint64_t eco_powdn_dly0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ecopfpddly_reg_t;
-
-
-
-typedef union pcbs_ecopfvret_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t eco_vret_sel : 4;
-    uint64_t eco_voff_sel : 4;
-    uint64_t _reserved0 : 56;
-#else
-    uint64_t _reserved0 : 56;
-    uint64_t eco_voff_sel : 4;
-    uint64_t eco_vret_sel : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ecopfvret_reg_t;
-
-
-
-typedef union pcbs_freq_ctrl_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dpll_fmin : 9;
-    uint64_t dpll_fmax : 9;
-    uint64_t dpll_fmax_bias : 4;
-    uint64_t frequ_at_pstate0 : 9;
-    uint64_t _reserved0 : 33;
-#else
-    uint64_t _reserved0 : 33;
-    uint64_t frequ_at_pstate0 : 9;
-    uint64_t dpll_fmax_bias : 4;
-    uint64_t dpll_fmax : 9;
-    uint64_t dpll_fmin : 9;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_freq_ctrl_reg_t;
-
-
-
-typedef union pcbs_dpll_cpm_parm_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t lf_slewratexpi : 8;
-    uint64_t lf_use_cpmxpi : 1;
-    uint64_t ff_use_cpmxpi : 1;
-    uint64_t cpm_filter_enable : 1;
-    uint64_t ff_bypassxpi : 1;
-    uint64_t dco_override : 1;
-    uint64_t dco_incr : 1;
-    uint64_t dco_decr : 1;
-    uint64_t dpll_lock_timer_replacement_value : 9;
-    uint64_t pre_vret_pstate : 8;
-    uint64_t override_pcbs_dpll_synchronizer : 1;
-    uint64_t dpll_char_delta1 : 4;
-    uint64_t dpll_char_delta2 : 4;
-    uint64_t _reserved0 : 23;
-#else
-    uint64_t _reserved0 : 23;
-    uint64_t dpll_char_delta2 : 4;
-    uint64_t dpll_char_delta1 : 4;
-    uint64_t override_pcbs_dpll_synchronizer : 1;
-    uint64_t pre_vret_pstate : 8;
-    uint64_t dpll_lock_timer_replacement_value : 9;
-    uint64_t dco_decr : 1;
-    uint64_t dco_incr : 1;
-    uint64_t dco_override : 1;
-    uint64_t ff_bypassxpi : 1;
-    uint64_t cpm_filter_enable : 1;
-    uint64_t ff_use_cpmxpi : 1;
-    uint64_t lf_use_cpmxpi : 1;
-    uint64_t lf_slewratexpi : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_dpll_cpm_parm_reg_t;
-
-
-
-typedef union pcbs_power_management_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t global_pstate_actual : 8;
-    int64_t local_pstate_actual : 8;
-    int64_t pv_min : 8;
-    int64_t pvf_max : 8;
-    uint64_t spr_em_disabled : 1;
-    uint64_t psafe_mode_active : 1;
-    uint64_t ivrm_safe_mode_active : 1;
-    uint64_t ivrm_enable : 1;
-    uint64_t all_fsms_in_safe_state : 1;
-    uint64_t pmsr_spares : 4;
-    uint64_t _reserved0 : 23;
-#else
-    uint64_t _reserved0 : 23;
-    uint64_t pmsr_spares : 4;
-    uint64_t all_fsms_in_safe_state : 1;
-    uint64_t ivrm_enable : 1;
-    uint64_t ivrm_safe_mode_active : 1;
-    uint64_t psafe_mode_active : 1;
-    uint64_t spr_em_disabled : 1;
-    int64_t pvf_max : 8;
-    int64_t pv_min : 8;
-    int64_t local_pstate_actual : 8;
-    int64_t global_pstate_actual : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_power_management_status_reg_t;
-
-
-
-typedef union pcbs_ivrm_control_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivrm_fsm_enable : 1;
-    uint64_t use_ivrm_for_vret : 1;
-    uint64_t binsearch_cal_ena : 1;
-    uint64_t pvref_en : 1;
-    uint64_t ivrm_core_vdd_bypass_b : 1;
-    uint64_t ivrm_core_vdd_poweron : 1;
-    uint64_t ivrm_core_vcs_bypass_b : 1;
-    uint64_t ivrm_core_vcs_poweron : 1;
-    uint64_t ivrm_eco_vdd_bypass_b : 1;
-    uint64_t ivrm_eco_vdd_poweron : 1;
-    uint64_t ivrm_eco_vcs_bypass_b : 1;
-    uint64_t ivrm_eco_vcs_poweron : 1;
-    uint64_t ivrm_vret_vdd : 7;
-    uint64_t ivrm_vret_vcs : 7;
-    uint64_t ivrm_vret_core_vdd_pfet_strength : 5;
-    uint64_t ivrm_vret_core_vcs_pfet_strength : 5;
-    uint64_t ivrm_vret_eco_vdd_pfet_strength : 5;
-    uint64_t ivrm_vret_eco_vcs_pfet_strength : 5;
-    uint64_t pvref_fail : 1;
-    uint64_t ivrm_pref_error_gross : 1;
-    uint64_t ivrm_pref_error_fine : 1;
-    uint64_t ivrm_core_vdd_range_hi : 1;
-    uint64_t ivrm_core_vdd_range_lo : 1;
-    uint64_t ivrm_eco_vdd_range_hi : 1;
-    uint64_t ivrm_eco_vdd_range_lo : 1;
-    uint64_t ivrm_core_vcs_range_hi : 1;
-    uint64_t ivrm_core_vcs_range_lo : 1;
-    uint64_t ivrm_eco_vcs_range_hi : 1;
-    uint64_t ivrm_eco_vcs_range_lo : 1;
-    uint64_t binsearch_cal_done : 1;
-    uint64_t ivrm_core_vdd_pfet_low_vout : 1;
-    uint64_t ivrm_core_vcs_pfet_low_vout : 1;
-    uint64_t ivrm_eco_vdd_pfet_low_vout : 1;
-    uint64_t ivrm_eco_vcs_pfet_low_vout : 1;
-    uint64_t ivrm_power_down_disable : 1;
-    uint64_t _reserved0 : 1;
-#else
-    uint64_t _reserved0 : 1;
-    uint64_t ivrm_power_down_disable : 1;
-    uint64_t ivrm_eco_vcs_pfet_low_vout : 1;
-    uint64_t ivrm_eco_vdd_pfet_low_vout : 1;
-    uint64_t ivrm_core_vcs_pfet_low_vout : 1;
-    uint64_t ivrm_core_vdd_pfet_low_vout : 1;
-    uint64_t binsearch_cal_done : 1;
-    uint64_t ivrm_eco_vcs_range_lo : 1;
-    uint64_t ivrm_eco_vcs_range_hi : 1;
-    uint64_t ivrm_core_vcs_range_lo : 1;
-    uint64_t ivrm_core_vcs_range_hi : 1;
-    uint64_t ivrm_eco_vdd_range_lo : 1;
-    uint64_t ivrm_eco_vdd_range_hi : 1;
-    uint64_t ivrm_core_vdd_range_lo : 1;
-    uint64_t ivrm_core_vdd_range_hi : 1;
-    uint64_t ivrm_pref_error_fine : 1;
-    uint64_t ivrm_pref_error_gross : 1;
-    uint64_t pvref_fail : 1;
-    uint64_t ivrm_vret_eco_vcs_pfet_strength : 5;
-    uint64_t ivrm_vret_eco_vdd_pfet_strength : 5;
-    uint64_t ivrm_vret_core_vcs_pfet_strength : 5;
-    uint64_t ivrm_vret_core_vdd_pfet_strength : 5;
-    uint64_t ivrm_vret_vcs : 7;
-    uint64_t ivrm_vret_vdd : 7;
-    uint64_t ivrm_eco_vcs_poweron : 1;
-    uint64_t ivrm_eco_vcs_bypass_b : 1;
-    uint64_t ivrm_eco_vdd_poweron : 1;
-    uint64_t ivrm_eco_vdd_bypass_b : 1;
-    uint64_t ivrm_core_vcs_poweron : 1;
-    uint64_t ivrm_core_vcs_bypass_b : 1;
-    uint64_t ivrm_core_vdd_poweron : 1;
-    uint64_t ivrm_core_vdd_bypass_b : 1;
-    uint64_t pvref_en : 1;
-    uint64_t binsearch_cal_ena : 1;
-    uint64_t use_ivrm_for_vret : 1;
-    uint64_t ivrm_fsm_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ivrm_control_status_reg_t;
-
-
-
-typedef union pcbs_ivrm_value_setting_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivrm_core_vdd_ivid : 8;
-    uint64_t ivrm_core_vcs_ivid : 8;
-    uint64_t ivrm_eco_vdd_ivid : 8;
-    uint64_t ivrm_eco_vcs_ivid : 8;
-    uint64_t ivrm_core_vdd_pfet_strength : 5;
-    uint64_t ivrm_core_vcs_pfet_strength : 5;
-    uint64_t ivrm_eco_vdd_pfet_strength : 5;
-    uint64_t ivrm_eco_vcs_pfet_strength : 5;
-    uint64_t ivrm_vdd_core_pfetstr_valid : 1;
-    uint64_t ivrm_vcs_core_pfetstr_valid : 1;
-    uint64_t ivrm_vdd_eco_pfetstr_valid : 1;
-    uint64_t ivrm_vcs_eco_pfetstr_valid : 1;
-    uint64_t core_vdd_vpump_en : 1;
-    uint64_t core_vcs_vpump_en : 1;
-    uint64_t eco_vdd_vpump_en : 1;
-    uint64_t eco_vcs_vpump_en : 1;
-    uint64_t _reserved0 : 4;
-#else
-    uint64_t _reserved0 : 4;
-    uint64_t eco_vcs_vpump_en : 1;
-    uint64_t eco_vdd_vpump_en : 1;
-    uint64_t core_vcs_vpump_en : 1;
-    uint64_t core_vdd_vpump_en : 1;
-    uint64_t ivrm_vcs_eco_pfetstr_valid : 1;
-    uint64_t ivrm_vdd_eco_pfetstr_valid : 1;
-    uint64_t ivrm_vcs_core_pfetstr_valid : 1;
-    uint64_t ivrm_vdd_core_pfetstr_valid : 1;
-    uint64_t ivrm_eco_vcs_pfet_strength : 5;
-    uint64_t ivrm_eco_vdd_pfet_strength : 5;
-    uint64_t ivrm_core_vcs_pfet_strength : 5;
-    uint64_t ivrm_core_vdd_pfet_strength : 5;
-    uint64_t ivrm_eco_vcs_ivid : 8;
-    uint64_t ivrm_eco_vdd_ivid : 8;
-    uint64_t ivrm_core_vcs_ivid : 8;
-    uint64_t ivrm_core_vdd_ivid : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ivrm_value_setting_reg_t;
-
-
-
-typedef union pcbs_pcbspm_mode_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_pstate_mode : 1;
-    uint64_t global_pstate_change_for_idle_state_enabled : 1;
-    uint64_t enable_global_pstate_req : 1;
-    uint64_t enable_winkle_with_cpm_mode : 1;
-    uint64_t enable_clipping_of_global_pstate_req : 1;
-    uint64_t chksw_hw214553 : 1;
-    uint64_t enable_pmc_pmax_sync_notification : 1;
-    uint64_t dpll_lock_replacement_timer_mode_en : 1;
-    uint64_t dpll_freqout_mode_en : 1;
-    uint64_t dpll_flock_mode_en : 1;
-    uint64_t enable_sense_delay_characterization : 1;
-    uint64_t sense_delay_timer_val : 7;
-    uint64_t cpm_fmin_clip_error_sel : 2;
-    uint64_t dbg_trace_sel : 4;
-    uint64_t trace_data_sel : 2;
-    uint64_t tp_cplt_ivrm_vpp_tune : 4;
-    uint64_t _reserved0 : 34;
-#else
-    uint64_t _reserved0 : 34;
-    uint64_t tp_cplt_ivrm_vpp_tune : 4;
-    uint64_t trace_data_sel : 2;
-    uint64_t dbg_trace_sel : 4;
-    uint64_t cpm_fmin_clip_error_sel : 2;
-    uint64_t sense_delay_timer_val : 7;
-    uint64_t enable_sense_delay_characterization : 1;
-    uint64_t dpll_flock_mode_en : 1;
-    uint64_t dpll_freqout_mode_en : 1;
-    uint64_t dpll_lock_replacement_timer_mode_en : 1;
-    uint64_t enable_pmc_pmax_sync_notification : 1;
-    uint64_t chksw_hw214553 : 1;
-    uint64_t enable_clipping_of_global_pstate_req : 1;
-    uint64_t enable_winkle_with_cpm_mode : 1;
-    uint64_t enable_global_pstate_req : 1;
-    uint64_t global_pstate_change_for_idle_state_enabled : 1;
-    uint64_t enable_pstate_mode : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pcbspm_mode_reg_t;
-
-#endif // __ASSEMBLER__
-#define PCBS_PCBSPM_MODE_REG_ENABLE_PSTATE_MODE SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PCBS_PCBSPM_MODE_REG_GLOBAL_PSTATE_CHANGE_FOR_IDLE_STATE_ENABLED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PCBS_PCBSPM_MODE_REG_ENABLE_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PCBS_PCBSPM_MODE_REG_ENABLE_WINKLE_WITH_CPM_MODE SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PCBS_PCBSPM_MODE_REG_ENABLE_CLIPPING_OF_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PCBS_PCBSPM_MODE_REG_CHKSW_HW214553 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PCBS_PCBSPM_MODE_REG_ENABLE_PMC_PMAX_SYNC_NOTIFICATION SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PCBS_PCBSPM_MODE_REG_DPLL_LOCK_REPLACEMENT_TIMER_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PCBS_PCBSPM_MODE_REG_DPLL_FREQOUT_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PCBS_PCBSPM_MODE_REG_DPLL_FLOCK_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PCBS_PCBSPM_MODE_REG_ENABLE_SENSE_DELAY_CHARACTERIZATION SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PCBS_PCBSPM_MODE_REG_SENSE_DELAY_TIMER_VAL_MASK SIXTYFOUR_BIT_CONSTANT(0x001fc00000000000)
-#define PCBS_PCBSPM_MODE_REG_CPM_FMIN_CLIP_ERROR_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x0000300000000000)
-#define PCBS_PCBSPM_MODE_REG_DBG_TRACE_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000f0000000000)
-#define PCBS_PCBSPM_MODE_REG_TRACE_DATA_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x000000c000000000)
-#define PCBS_PCBSPM_MODE_REG_TP_CPLT_IVRM_VPP_TUNE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000003c00000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pcbs_ivrm_pfetstr_sense_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivrm_core_vdd_pfetstr_sns : 5;
-    uint64_t ivrm_core_vcs_pfetstr_sns : 5;
-    uint64_t ivrm_eco_vdd_pfetstr_sns : 5;
-    uint64_t ivrm_eco_vcs_pfetstr_sns : 5;
-    uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1;
-    uint64_t core_vdd_bypass_b_sense : 1;
-    uint64_t core_vcs_bypass_b_sense : 1;
-    uint64_t eco_vdd_bypass_b_sense : 1;
-    uint64_t eco_vcs_bypass_b_sense : 1;
-    uint64_t core_vdd_poweron_sense : 1;
-    uint64_t core_vcs_poweron_sense : 1;
-    uint64_t eco_vdd_poweron_sense : 1;
-    uint64_t eco_vcs_poweron_sense : 1;
-    uint64_t core_vdd_vpump_en_sense : 1;
-    uint64_t core_vcs_vpump_en_sense : 1;
-    uint64_t eco_vdd_vpump_en_sense : 1;
-    uint64_t eco_vcs_vpump_en_sense : 1;
-    uint64_t core_vdd_pfet_low_vout_sns : 1;
-    uint64_t core_vcs_pfet_low_vout_sns : 1;
-    uint64_t eco_vdd_pfet_low_vout_sns : 1;
-    uint64_t eco_vcs_pfet_low_vout_sns : 1;
-    uint64_t _reserved0 : 24;
-#else
-    uint64_t _reserved0 : 24;
-    uint64_t eco_vcs_pfet_low_vout_sns : 1;
-    uint64_t eco_vdd_pfet_low_vout_sns : 1;
-    uint64_t core_vcs_pfet_low_vout_sns : 1;
-    uint64_t core_vdd_pfet_low_vout_sns : 1;
-    uint64_t eco_vcs_vpump_en_sense : 1;
-    uint64_t eco_vdd_vpump_en_sense : 1;
-    uint64_t core_vcs_vpump_en_sense : 1;
-    uint64_t core_vdd_vpump_en_sense : 1;
-    uint64_t eco_vcs_poweron_sense : 1;
-    uint64_t eco_vdd_poweron_sense : 1;
-    uint64_t core_vcs_poweron_sense : 1;
-    uint64_t core_vdd_poweron_sense : 1;
-    uint64_t eco_vcs_bypass_b_sense : 1;
-    uint64_t eco_vdd_bypass_b_sense : 1;
-    uint64_t core_vcs_bypass_b_sense : 1;
-    uint64_t core_vdd_bypass_b_sense : 1;
-    uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1;
-    uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1;
-    uint64_t ivrm_eco_vcs_pfetstr_sns : 5;
-    uint64_t ivrm_eco_vdd_pfetstr_sns : 5;
-    uint64_t ivrm_core_vcs_pfetstr_sns : 5;
-    uint64_t ivrm_core_vdd_pfetstr_sns : 5;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ivrm_pfetstr_sense_reg_t;
-
-
-
-typedef union pcbs_power_management_idle_control_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t nap_pstate_req : 8;
-    uint64_t nap_pstate_en : 1;
-    uint64_t nap_global_en : 1;
-    uint64_t nap_latency : 2;
-    uint64_t reserved_ppmicr_0 : 4;
-    int64_t sleep_pstate_req : 8;
-    uint64_t sleep_pstate_en : 1;
-    uint64_t sleep_global_en : 1;
-    uint64_t sleep_latency : 2;
-    uint64_t reserved_ppmicr_1 : 4;
-    int64_t winkle_pstate_req : 8;
-    uint64_t winkle_pstate_en : 1;
-    uint64_t winkle_global_en : 1;
-    uint64_t winkle_latency : 2;
-    uint64_t reserved_ppmicr_2 : 4;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t reserved_ppmicr_2 : 4;
-    uint64_t winkle_latency : 2;
-    uint64_t winkle_global_en : 1;
-    uint64_t winkle_pstate_en : 1;
-    int64_t winkle_pstate_req : 8;
-    uint64_t reserved_ppmicr_1 : 4;
-    uint64_t sleep_latency : 2;
-    uint64_t sleep_global_en : 1;
-    uint64_t sleep_pstate_en : 1;
-    int64_t sleep_pstate_req : 8;
-    uint64_t reserved_ppmicr_0 : 4;
-    uint64_t nap_latency : 2;
-    uint64_t nap_global_en : 1;
-    uint64_t nap_pstate_en : 1;
-    int64_t nap_pstate_req : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_power_management_idle_control_reg_t;
-
-
-
-typedef union pcbs_power_management_control_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t global_pstate_req : 8;
-    int64_t local_pstate_req : 8;
-    uint64_t auto_override0_pstate_limit_en : 1;
-    uint64_t auto_override1_pstate_limit_en : 1;
-    uint64_t reserved_ppmcr : 6;
-    int64_t auto_override_pstate0 : 8;
-    int64_t auto_override_pstate1 : 8;
-    uint64_t _reserved0 : 24;
-#else
-    uint64_t _reserved0 : 24;
-    int64_t auto_override_pstate1 : 8;
-    int64_t auto_override_pstate0 : 8;
-    uint64_t reserved_ppmcr : 6;
-    uint64_t auto_override1_pstate_limit_en : 1;
-    uint64_t auto_override0_pstate_limit_en : 1;
-    int64_t local_pstate_req : 8;
-    int64_t global_pstate_req : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_power_management_control_reg_t;
-
-
-
-typedef union pcbs_pmc_vf_ctrl_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t pglobal_actual : 8;
-    uint64_t maxregvcs : 8;
-    uint64_t maxregvdd : 8;
-    uint64_t evidvcs_eff : 8;
-    uint64_t evidvdd_eff : 8;
-    uint64_t _reserved0 : 24;
-#else
-    uint64_t _reserved0 : 24;
-    uint64_t evidvdd_eff : 8;
-    uint64_t evidvcs_eff : 8;
-    uint64_t maxregvdd : 8;
-    uint64_t maxregvcs : 8;
-    int64_t pglobal_actual : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pmc_vf_ctrl_reg_t;
-
-
-
-typedef union pcbs_undervolting_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t puv_min : 8;
-    int64_t puv_max : 8;
-    uint64_t kuv : 6;
-    uint64_t _reserved0 : 42;
-#else
-    uint64_t _reserved0 : 42;
-    uint64_t kuv : 6;
-    int64_t puv_max : 8;
-    int64_t puv_min : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_undervolting_reg_t;
-
-
-
-typedef union pcbs_pstate_index_bound_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t lpsi_min : 8;
-    uint64_t lpsi_entries_minus_1 : 7;
-    uint64_t _reserved0 : 49;
-#else
-    uint64_t _reserved0 : 49;
-    uint64_t lpsi_entries_minus_1 : 7;
-    uint64_t lpsi_min : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pstate_index_bound_reg_t;
-
-
-
-typedef union pcbs_power_management_bounds_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t pmin_clip : 8;
-    int64_t pmax_clip : 8;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    int64_t pmax_clip : 8;
-    int64_t pmin_clip : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_power_management_bounds_reg_t;
-
-
-
-typedef union pcbs_pstate_table_ctrl_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pstate_table_address : 7;
-    uint64_t _reserved0 : 57;
-#else
-    uint64_t _reserved0 : 57;
-    uint64_t pstate_table_address : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pstate_table_ctrl_reg_t;
-
-
-
-typedef union pcbs_pstate_table_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pstate_data : 64;
-#else
-    uint64_t pstate_data : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pstate_table_reg_t;
-
-
-
-typedef union pcbs_pstate_step_target_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t local_pstate_eff_req : 8;
-    int64_t local_pstate_target : 8;
-    int64_t local_core_pstate_step_target : 8;
-    int64_t local_eco_pstate_step_target : 8;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    int64_t local_eco_pstate_step_target : 8;
-    int64_t local_core_pstate_step_target : 8;
-    int64_t local_pstate_target : 8;
-    int64_t local_pstate_eff_req : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_pstate_step_target_reg_t;
-
-
-
-typedef union pcbs_dpll_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dpll_ff_freqout : 15;
-    uint64_t dpll_frequ_change : 1;
-    uint64_t dpll_status_spare_bit1 : 1;
-    uint64_t pmax_sync_pending : 1;
-    uint64_t ga_ack_pending : 1;
-    int64_t capped_global_pstate_req : 8;
-    uint64_t dpll_fmax_and_cpmbit2 : 1;
-    uint64_t dpll_fmax_and_cpmbit3 : 1;
-    uint64_t dpll_fmax_and_cpmbit4 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit2 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit1 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit0 : 1;
-    uint64_t dpll_faster_than_fmax_plus_delta1 : 1;
-    uint64_t dpll_slower_than_fmin_minus_delta2 : 1;
-    uint64_t dpll_max_freqout_after_last_read : 14;
-    uint64_t dpll_min_freqout_after_last_read : 14;
-    uint64_t _reserved0 : 1;
-#else
-    uint64_t _reserved0 : 1;
-    uint64_t dpll_min_freqout_after_last_read : 14;
-    uint64_t dpll_max_freqout_after_last_read : 14;
-    uint64_t dpll_slower_than_fmin_minus_delta2 : 1;
-    uint64_t dpll_faster_than_fmax_plus_delta1 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit0 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit1 : 1;
-    uint64_t dpll_fmin_and_not_cpmbit2 : 1;
-    uint64_t dpll_fmax_and_cpmbit4 : 1;
-    uint64_t dpll_fmax_and_cpmbit3 : 1;
-    uint64_t dpll_fmax_and_cpmbit2 : 1;
-    int64_t capped_global_pstate_req : 8;
-    uint64_t ga_ack_pending : 1;
-    uint64_t pmax_sync_pending : 1;
-    uint64_t dpll_status_spare_bit1 : 1;
-    uint64_t dpll_frequ_change : 1;
-    uint64_t dpll_ff_freqout : 15;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_dpll_status_reg_t;
-
-
-
-typedef union pcbs_ivrm_vid_control_reg0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivrm_req_pstate_stepdelay_rising : 8;
-    uint64_t ivrm_req_pstate_stepdelay_lowering : 8;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t ivrm_req_pstate_stepdelay_lowering : 8;
-    uint64_t ivrm_req_pstate_stepdelay_rising : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ivrm_vid_control_reg0_t;
-
-
-
-typedef union pcbs_ivrm_vid_control_reg1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ivrm_stabilize_delay_run : 8;
-    uint64_t ivrm_stabilize_delay_idle : 8;
-    uint64_t ivrm_pfstr_prop_delay : 8;
-    uint64_t ivrm_pfstrvalid_prop_delay : 8;
-    uint64_t ivrm_vpump_poweron_time : 8;
-    uint64_t ivrm_bypass_delay : 8;
-    uint64_t pfet_vpump_enable_delay : 8;
-    uint64_t ivrm_vid_vout_threshold : 7;
-    uint64_t _reserved0 : 1;
-#else
-    uint64_t _reserved0 : 1;
-    uint64_t ivrm_vid_vout_threshold : 7;
-    uint64_t pfet_vpump_enable_delay : 8;
-    uint64_t ivrm_bypass_delay : 8;
-    uint64_t ivrm_vpump_poweron_time : 8;
-    uint64_t ivrm_pfstrvalid_prop_delay : 8;
-    uint64_t ivrm_pfstr_prop_delay : 8;
-    uint64_t ivrm_stabilize_delay_idle : 8;
-    uint64_t ivrm_stabilize_delay_run : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_ivrm_vid_control_reg1_t;
-
-
-
-typedef union pcbs_occ_heartbeat_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t occ_heartbeat_time : 8;
-    uint64_t occ_heartbeat_enable : 1;
-    uint64_t occ_heartbeat_reg_addr_offset : 8;
-    int64_t psafe : 8;
-    uint64_t _reserved0 : 39;
-#else
-    uint64_t _reserved0 : 39;
-    int64_t psafe : 8;
-    uint64_t occ_heartbeat_reg_addr_offset : 8;
-    uint64_t occ_heartbeat_enable : 1;
-    uint64_t occ_heartbeat_time : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_occ_heartbeat_reg_t;
-
-
-
-typedef union pcbs_resonant_clock_control_reg0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t resclk_dis : 1;
-    uint64_t resclk_control_mode : 1;
-    uint64_t resclk_sync_pw : 3;
-    uint64_t res_sync_delay_cnt : 7;
-    uint64_t res_csb_str_instr_lo : 15;
-    uint64_t res_csb_str_instr_hi : 15;
-    uint64_t _reserved0 : 22;
-#else
-    uint64_t _reserved0 : 22;
-    uint64_t res_csb_str_instr_hi : 15;
-    uint64_t res_csb_str_instr_lo : 15;
-    uint64_t res_sync_delay_cnt : 7;
-    uint64_t resclk_sync_pw : 3;
-    uint64_t resclk_control_mode : 1;
-    uint64_t resclk_dis : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_resonant_clock_control_reg0_t;
-
-
-
-typedef union pcbs_resonant_clock_control_reg1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    int64_t full_csb_ps : 8;
-    int64_t res_low_lower_ps : 8;
-    int64_t res_low_upper_ps : 8;
-    int64_t res_high_lower_ps : 8;
-    int64_t res_high_upper_ps : 8;
-    uint64_t nonres_csb_value_ti : 4;
-    uint64_t full_csb_value_ti : 4;
-    uint64_t resclk_value : 9;
-    uint64_t resclk_core_sync_value : 1;
-    uint64_t csb_eco_sync_value : 1;
-    uint64_t _reserved0 : 5;
-#else
-    uint64_t _reserved0 : 5;
-    uint64_t csb_eco_sync_value : 1;
-    uint64_t resclk_core_sync_value : 1;
-    uint64_t resclk_value : 9;
-    uint64_t full_csb_value_ti : 4;
-    uint64_t nonres_csb_value_ti : 4;
-    int64_t res_high_upper_ps : 8;
-    int64_t res_high_lower_ps : 8;
-    int64_t res_low_upper_ps : 8;
-    int64_t res_low_lower_ps : 8;
-    int64_t full_csb_ps : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_resonant_clock_control_reg1_t;
-
-
-
-typedef union pcbs_resonant_clock_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t resclk_state : 1;
-    uint64_t res_hi_induct_en : 1;
-    uint64_t resclk_inprogress : 1;
-    uint64_t resclk_full_csb : 1;
-    uint64_t _reserved0 : 60;
-#else
-    uint64_t _reserved0 : 60;
-    uint64_t resclk_full_csb : 1;
-    uint64_t resclk_inprogress : 1;
-    uint64_t res_hi_induct_en : 1;
-    uint64_t resclk_state : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_resonant_clock_status_reg_t;
-
-
-
-typedef union pcbs_local_pstate_frequency_target_control_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t delay_time : 3;
-    uint64_t record_transitions : 1;
-    uint64_t multiplier : 15;
-    uint64_t enable_lpft_function : 1;
-    uint64_t _reserved0 : 44;
-#else
-    uint64_t _reserved0 : 44;
-    uint64_t enable_lpft_function : 1;
-    uint64_t multiplier : 15;
-    uint64_t record_transitions : 1;
-    uint64_t delay_time : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_local_pstate_frequency_target_control_reg_t;
-
-
-
-typedef union pcbs_local_pstate_frequency_target_status_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t valid : 1;
-    uint64_t cpm_dpll : 1;
-    uint64_t ivrm : 1;
-    uint64_t transition : 1;
-    uint64_t stable : 1;
-    uint64_t delta : 24;
-    uint64_t cumulative : 24;
-    uint64_t pstate : 8;
-    uint64_t _reserved0 : 3;
-#else
-    uint64_t _reserved0 : 3;
-    uint64_t pstate : 8;
-    uint64_t cumulative : 24;
-    uint64_t delta : 24;
-    uint64_t stable : 1;
-    uint64_t transition : 1;
-    uint64_t ivrm : 1;
-    uint64_t cpm_dpll : 1;
-    uint64_t valid : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_local_pstate_frequency_target_status_reg_t;
-
-
-
-typedef union pcbs_fsm_monitor1_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t babystep_main_fsm : 7;
-    uint64_t babystep_slave_fsm : 5;
-    uint64_t core_railstepper_main_fsm : 5;
-    uint64_t eco_railstepper_main_fsm : 5;
-    uint64_t core_railstepper_sub_fsm : 4;
-    uint64_t eco_railstepper_sub_fsm : 4;
-    uint64_t core_railstepper_byp_fsm : 5;
-    uint64_t eco_railstepper_byp_fsm : 5;
-    uint64_t ivrm_core_vdd_sequencer_fsm : 6;
-    uint64_t ivrm_core_vcs_sequencer_fsm : 6;
-    uint64_t ivrm_eco_vdd_sequencer_fsm : 6;
-    uint64_t ivrm_eco_vcs_sequencer_fsm : 6;
-#else
-    uint64_t ivrm_eco_vcs_sequencer_fsm : 6;
-    uint64_t ivrm_eco_vdd_sequencer_fsm : 6;
-    uint64_t ivrm_core_vcs_sequencer_fsm : 6;
-    uint64_t ivrm_core_vdd_sequencer_fsm : 6;
-    uint64_t eco_railstepper_byp_fsm : 5;
-    uint64_t core_railstepper_byp_fsm : 5;
-    uint64_t eco_railstepper_sub_fsm : 4;
-    uint64_t core_railstepper_sub_fsm : 4;
-    uint64_t eco_railstepper_main_fsm : 5;
-    uint64_t core_railstepper_main_fsm : 5;
-    uint64_t babystep_slave_fsm : 5;
-    uint64_t babystep_main_fsm : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_fsm_monitor1_reg_t;
-
-
-
-typedef union pcbs_fsm_monitor2_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t resclk_band_fsm : 7;
-    uint64_t resclk_lowres_fsm : 4;
-    uint64_t resclk_highres_fsm : 4;
-    uint64_t resclk_fullcsb_fsm : 4;
-    uint64_t resclk_update_fsm : 4;
-    uint64_t idle_transition_fsm : 7;
-    uint64_t peco_step_target_uv : 8;
-    uint64_t pcore_step_target_uv : 8;
-    uint64_t _reserved0 : 18;
-#else
-    uint64_t _reserved0 : 18;
-    uint64_t pcore_step_target_uv : 8;
-    uint64_t peco_step_target_uv : 8;
-    uint64_t idle_transition_fsm : 7;
-    uint64_t resclk_update_fsm : 4;
-    uint64_t resclk_fullcsb_fsm : 4;
-    uint64_t resclk_highres_fsm : 4;
-    uint64_t resclk_lowres_fsm : 4;
-    uint64_t resclk_band_fsm : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_fsm_monitor2_reg_t;
-
-
-
-typedef union pcbs_chksw_unassisted_interrupts {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 1;
-    uint64_t _reserved0 : 63;
-#else
-    uint64_t _reserved0 : 63;
-    uint64_t value : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pcbs_chksw_unassisted_interrupts_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PCBS_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pcbs_register_addresses.h b/src/ssx/pgp/registers/pcbs_register_addresses.h
deleted file mode 100755
index 8c465d1..0000000
--- a/src/ssx/pgp/registers/pcbs_register_addresses.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef __PCBS_REGISTER_ADDRESSES_H__
-#define __PCBS_REGISTER_ADDRESSES_H__
-
-// $Id: pcbs_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pcbs_register_addresses.h
-/// \brief Symbolic addresses for the PCBS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PCBS_PIB_BASE 0x100f0100
-#define PCBS_PMGP0_REG 0x100f0100
-#define PCBS_PMGP0_REG_AND 0x100f0101
-#define PCBS_PMGP0_REG_OR 0x100f0102
-#define PCBS_PMGP1_REG 0x100f0103
-#define PCBS_PMGP1_REG_AND 0x100f0104
-#define PCBS_PMGP1_REG_OR 0x100f0105
-#define PCBS_PFVDDCNTLSTAT_REG 0x100f0106
-#define PCBS_PFVCSCNTLSTAT_REG 0x100f010e
-#define PCBS_PFSENSE_REG 0x100f0107
-#define PCBS_PMERRSUM_REG 0x100f0108
-#define PCBS_PMERR_REG 0x100f0109
-#define PCBS_PMERRMASK_REG 0x100f010a
-#define PCBS_PMSPCWKUPFSP_REG 0x100f010b
-#define PCBS_PMSPCWKUPOCC_REG 0x100f010c
-#define PCBS_PMSPCWKUPPHYP_REG 0x100f010d
-#define PCBS_PMSTATEHISTPHYP_REG 0x100f0110
-#define PCBS_PMSTATEHISTFSP_REG 0x100f0111
-#define PCBS_PMSTATEHISTOCC_REG 0x100f0112
-#define PCBS_PMSTATEHISTPERF_REG 0x100f0113
-#define PCBS_IDLEFSMGOTOCMD_REG 0x100f0114
-#define PCBS_COREPFPUDLY_REG 0x100f012c
-#define PCBS_COREPFPDDLY_REG 0x100f012d
-#define PCBS_COREPFVRET_REG 0x100f0130
-#define PCBS_ECOPFPUDLY_REG 0x100f014c
-#define PCBS_ECOPFPDDLY_REG 0x100f014d
-#define PCBS_ECOPFVRET_REG 0x100f0150
-#define PCBS_FREQ_CTRL_REG 0x100f0151
-#define PCBS_DPLL_CPM_PARM_REG 0x100f0152
-#define PCBS_POWER_MANAGEMENT_STATUS_REG 0x100f0153
-#define PCBS_IVRM_CONTROL_STATUS_REG 0x100f0154
-#define PCBS_IVRM_VALUE_SETTING_REG 0x100f0155
-#define PCBS_PCBSPM_MODE_REG 0x100f0156
-#define PCBS_IVRM_PFETSTR_SENSE_REG 0x100f0157
-#define PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG 0x100f0158
-#define PCBS_POWER_MANAGEMENT_CONTROL_REG 0x100f0159
-#define PCBS_PMC_VF_CTRL_REG 0x100f015a
-#define PCBS_UNDERVOLTING_REG 0x100f015b
-#define PCBS_PSTATE_INDEX_BOUND_REG 0x100f015c
-#define PCBS_POWER_MANAGEMENT_BOUNDS_REG 0x100f015d
-#define PCBS_PSTATE_TABLE_CTRL_REG 0x100f015e
-#define PCBS_PSTATE_TABLE_REG 0x100f015f
-#define PCBS_PSTATE_STEP_TARGET_REG 0x100f0160
-#define PCBS_DPLL_STATUS_REG 0x100f0161
-#define PCBS_IVRM_VID_CONTROL_REG0 0x100f0162
-#define PCBS_IVRM_VID_CONTROL_REG1 0x100f0163
-#define PCBS_OCC_HEARTBEAT_REG 0x100f0164
-#define PCBS_RESONANT_CLOCK_CONTROL_REG0 0x100f0165
-#define PCBS_RESONANT_CLOCK_CONTROL_REG1 0x100f0166
-#define PCBS_RESONANT_CLOCK_STATUS_REG 0x100f0167
-#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_CONTROL_REG 0x100f0168
-#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_STATUS_REG 0x100f0169
-#define PCBS_FSM_MONITOR1_REG 0x100f0170
-#define PCBS_FSM_MONITOR2_REG 0x100f0171
-
-#endif // __PCBS_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pibmem_firmware_registers.h b/src/ssx/pgp/registers/pibmem_firmware_registers.h
deleted file mode 100644
index 3b36fc1..0000000
--- a/src/ssx/pgp/registers/pibmem_firmware_registers.h
+++ /dev/null
@@ -1,264 +0,0 @@
-#ifndef __PIBMEM_FIRMWARE_REGISTERS_H__
-#define __PIBMEM_FIRMWARE_REGISTERS_H__
-
-// $Id: pibmem_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pibmem_firmware_registers.h
-/// \brief C register structs for the PIBMEM unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pibmem_data0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_data0_t;
-
-
-
-typedef union pibmem_control {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t auto_pre_increment : 1;
-    uint64_t auto_post_decrement : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t auto_post_decrement : 1;
-    uint64_t auto_pre_increment : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_control_t;
-
-
-
-typedef union pibmem_address {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 48;
-    uint64_t address : 16;
-#else
-    uint64_t address : 16;
-    uint64_t reserved0 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_address_t;
-
-
-
-typedef union pibmem_data {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_data_t;
-
-
-
-typedef union pibmem_data_inc {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_data_inc_t;
-
-
-
-typedef union pibmem_data_dec {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_data_dec_t;
-
-
-
-typedef union pibmem_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t addr_invalid : 1;
-    uint64_t write_invalid : 1;
-    uint64_t read_invalid : 1;
-    uint64_t ecc_uncorrected_error : 1;
-    uint64_t ecc_corrected_error : 1;
-    uint64_t bad_array_address : 1;
-    uint64_t reserved6 : 5;
-    uint64_t fsm_present_state : 7;
-    uint64_t _reserved0 : 46;
-#else
-    uint64_t _reserved0 : 46;
-    uint64_t fsm_present_state : 7;
-    uint64_t reserved6 : 5;
-    uint64_t bad_array_address : 1;
-    uint64_t ecc_corrected_error : 1;
-    uint64_t ecc_uncorrected_error : 1;
-    uint64_t read_invalid : 1;
-    uint64_t write_invalid : 1;
-    uint64_t addr_invalid : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_status_t;
-
-
-
-typedef union pibmem_reset {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reset_code : 2;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t reset_code : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_reset_t;
-
-
-
-typedef union pibmem_repair {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 64;
-#else
-    uint64_t value : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pibmem_repair_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PIBMEM_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pibmem_register_addresses.h b/src/ssx/pgp/registers/pibmem_register_addresses.h
deleted file mode 100644
index 0cffaa2..0000000
--- a/src/ssx/pgp/registers/pibmem_register_addresses.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __PIBMEM_REGISTER_ADDRESSES_H__
-#define __PIBMEM_REGISTER_ADDRESSES_H__
-
-// $Id: pibmem_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pibmem_register_addresses.h
-/// \brief Symbolic addresses for the PIBMEM unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PIBMEM_PIB_BASE 0x00080000
-#define PIBMEM_DATA0 0x00080000
-#define PIBMEM_CONTROL 0x00088000
-#define PIBMEM_ADDRESS 0x00088001
-#define PIBMEM_DATA 0x00088002
-#define PIBMEM_DATA_INC 0x00088003
-#define PIBMEM_DATA_DEC 0x00088004
-#define PIBMEM_STATUS 0x00088005
-#define PIBMEM_RESET 0x00088006
-#define PIBMEM_REPAIR 0x00088007
-
-#endif // __PIBMEM_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h b/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h
deleted file mode 100755
index 583e95d..0000000
--- a/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h
+++ /dev/null
@@ -1,215 +0,0 @@
-#ifndef __PLB_ARBITER_FIRMWARE_REGISTERS_H__
-#define __PLB_ARBITER_FIRMWARE_REGISTERS_H__
-
-// $Id: plb_arbiter_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file plb_arbiter_firmware_registers.h
-/// \brief C register structs for the PLB_ARBITER unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union plb_prev {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_prev_t;
-
-
-
-typedef union plb_pacr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t ppm : 1;
-    uint32_t ppo : 3;
-    uint32_t hbu : 1;
-    uint32_t rdp : 2;
-    uint32_t wrp : 1;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    uint32_t wrp : 1;
-    uint32_t rdp : 2;
-    uint32_t hbu : 1;
-    uint32_t ppo : 3;
-    uint32_t ppm : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_pacr_t;
-
-
-
-typedef union plb_pesr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pte0 : 1;
-    uint32_t rw0 : 1;
-    uint32_t flk0 : 1;
-    uint32_t alk0 : 1;
-    uint32_t pte1 : 1;
-    uint32_t rw1 : 1;
-    uint32_t flk1 : 1;
-    uint32_t alk1 : 1;
-    uint32_t pte2 : 1;
-    uint32_t rw2 : 1;
-    uint32_t flk2 : 1;
-    uint32_t alk2 : 1;
-    uint32_t pte3 : 1;
-    uint32_t rw3 : 1;
-    uint32_t flk3 : 1;
-    uint32_t alk3 : 1;
-    uint32_t pte4 : 1;
-    uint32_t rw4 : 1;
-    uint32_t flk4 : 1;
-    uint32_t alk4 : 1;
-    uint32_t pte5 : 1;
-    uint32_t rw5 : 1;
-    uint32_t flk5 : 1;
-    uint32_t alk5 : 1;
-    uint32_t pte6 : 1;
-    uint32_t rw6 : 1;
-    uint32_t flk6 : 1;
-    uint32_t alk6 : 1;
-    uint32_t pte7 : 1;
-    uint32_t rw7 : 1;
-    uint32_t flk7 : 1;
-    uint32_t alk7 : 1;
-#else
-    uint32_t alk7 : 1;
-    uint32_t flk7 : 1;
-    uint32_t rw7 : 1;
-    uint32_t pte7 : 1;
-    uint32_t alk6 : 1;
-    uint32_t flk6 : 1;
-    uint32_t rw6 : 1;
-    uint32_t pte6 : 1;
-    uint32_t alk5 : 1;
-    uint32_t flk5 : 1;
-    uint32_t rw5 : 1;
-    uint32_t pte5 : 1;
-    uint32_t alk4 : 1;
-    uint32_t flk4 : 1;
-    uint32_t rw4 : 1;
-    uint32_t pte4 : 1;
-    uint32_t alk3 : 1;
-    uint32_t flk3 : 1;
-    uint32_t rw3 : 1;
-    uint32_t pte3 : 1;
-    uint32_t alk2 : 1;
-    uint32_t flk2 : 1;
-    uint32_t rw2 : 1;
-    uint32_t pte2 : 1;
-    uint32_t alk1 : 1;
-    uint32_t flk1 : 1;
-    uint32_t rw1 : 1;
-    uint32_t pte1 : 1;
-    uint32_t alk0 : 1;
-    uint32_t flk0 : 1;
-    uint32_t rw0 : 1;
-    uint32_t pte0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_pesr_t;
-
-
-
-typedef union plb_pearl {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_pearl_t;
-
-
-
-typedef union plb_pearh {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_pearh_t;
-
-
-
-typedef union plb_sto_pesr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t icu_te : 1;
-    uint32_t icu_rw : 1;
-    uint32_t reserved2 : 2;
-    uint32_t dcu_te : 1;
-    uint32_t dcu_rw : 1;
-    uint32_t reserved6 : 2;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    uint32_t reserved6 : 2;
-    uint32_t dcu_rw : 1;
-    uint32_t dcu_te : 1;
-    uint32_t reserved2 : 2;
-    uint32_t icu_rw : 1;
-    uint32_t icu_te : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_sto_pesr_t;
-
-
-
-typedef union plb_sto_pear {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t value : 32;
-#else
-    uint32_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} plb_sto_pear_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PLB_ARBITER_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/plb_arbiter_register_addresses.h b/src/ssx/pgp/registers/plb_arbiter_register_addresses.h
deleted file mode 100755
index 2bc2f41..0000000
--- a/src/ssx/pgp/registers/plb_arbiter_register_addresses.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __PLB_ARBITER_REGISTER_ADDRESSES_H__
-#define __PLB_ARBITER_REGISTER_ADDRESSES_H__
-
-// $Id: plb_arbiter_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file plb_arbiter_register_addresses.h
-/// \brief Symbolic addresses for the PLB_ARBITER unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PLB_DCR_BASE 0x90
-#define PLB_PREV 0x00000092
-#define PLB_PACR 0x00000093
-#define PLB_PESR 0x00000094
-#define PLB_PEARL 0x00000096
-#define PLB_PEARH 0x00000097
-#define PLB_STO_PESR 0x00000099
-#define PLB_STO_PEAR 0x00000098
-
-#endif // __PLB_ARBITER_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pmc_firmware_registers.h b/src/ssx/pgp/registers/pmc_firmware_registers.h
deleted file mode 100755
index 76642a4..0000000
--- a/src/ssx/pgp/registers/pmc_firmware_registers.h
+++ /dev/null
@@ -1,3140 +0,0 @@
-#ifndef __PMC_FIRMWARE_REGISTERS_H__
-#define __PMC_FIRMWARE_REGISTERS_H__
-
-// $Id: pmc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pmc_firmware_registers.h
-/// \brief C register structs for the PMC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pmc_mode_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t enable_hw_pstate_mode : 1;
-    uint32_t enable_fw_auction_pstate_mode : 1;
-    uint32_t enable_fw_pstate_mode : 1;
-    uint32_t enable_pstate_voltage_changes : 1;
-    uint32_t enable_global_actual_pstate_forwarding : 1;
-    uint32_t halt_pstate_master_fsm : 1;
-    uint32_t enable_interchip_interface : 1;
-    uint32_t interchip_mode : 1;
-    uint32_t enable_interchip_pstate_in_haps : 1;
-    uint32_t enable_pstate_stepping : 1;
-    uint32_t honor_oha_idle_state_requests : 1;
-    uint32_t vid_endianess : 1;
-    uint32_t reset_all_pmc_registers : 1;
-    uint32_t safe_mode_without_spivid : 1;
-    uint32_t halt_idle_state_master_fsm : 1;
-    uint32_t interchip_halt_if : 1;
-    uint32_t unfreeze_pstate_processing : 1;
-    uint32_t spivid_reset_if : 1;
-    uint32_t unfreeze_istate_processing : 1;
-    uint32_t _reserved0 : 13;
-#else
-    uint32_t _reserved0 : 13;
-    uint32_t unfreeze_istate_processing : 1;
-    uint32_t spivid_reset_if : 1;
-    uint32_t unfreeze_pstate_processing : 1;
-    uint32_t interchip_halt_if : 1;
-    uint32_t halt_idle_state_master_fsm : 1;
-    uint32_t safe_mode_without_spivid : 1;
-    uint32_t reset_all_pmc_registers : 1;
-    uint32_t vid_endianess : 1;
-    uint32_t honor_oha_idle_state_requests : 1;
-    uint32_t enable_pstate_stepping : 1;
-    uint32_t enable_interchip_pstate_in_haps : 1;
-    uint32_t interchip_mode : 1;
-    uint32_t enable_interchip_interface : 1;
-    uint32_t halt_pstate_master_fsm : 1;
-    uint32_t enable_global_actual_pstate_forwarding : 1;
-    uint32_t enable_pstate_voltage_changes : 1;
-    uint32_t enable_fw_pstate_mode : 1;
-    uint32_t enable_fw_auction_pstate_mode : 1;
-    uint32_t enable_hw_pstate_mode : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_mode_reg_t;
-
-
-
-typedef union pmc_hardware_auction_pstate_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t haps : 8;
-    uint32_t kuv_actual : 8;
-    uint32_t kuv_received : 8;
-    uint32_t _reserved0 : 8;
-#else
-    uint32_t _reserved0 : 8;
-    uint32_t kuv_received : 8;
-    uint32_t kuv_actual : 8;
-    int32_t haps : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_hardware_auction_pstate_reg_t;
-
-
-
-typedef union pmc_pstate_monitor_and_ctrl_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t gpst_val : 8;
-    int32_t gpsst : 8;
-    int32_t gpsa : 8;
-    int32_t gapr : 8;
-#else
-    int32_t gapr : 8;
-    int32_t gpsa : 8;
-    int32_t gpsst : 8;
-    int32_t gpst_val : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pstate_monitor_and_ctrl_reg_t;
-
-
-
-typedef union pmc_rail_bounds_register {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pmin_rail : 8;
-    int32_t pmax_rail : 8;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    int32_t pmax_rail : 8;
-    int32_t pmin_rail : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_rail_bounds_register_t;
-
-
-
-typedef union pmc_global_pstate_bounds_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t gpsi_min : 8;
-    uint32_t gpst_number_of_entries_minus_one : 7;
-    uint32_t _reserved0 : 17;
-#else
-    uint32_t _reserved0 : 17;
-    uint32_t gpst_number_of_entries_minus_one : 7;
-    uint32_t gpsi_min : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_global_pstate_bounds_reg_t;
-
-
-
-typedef union pmc_parameter_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pstate_stepsize : 7;
-    uint32_t vrm_stepdelay_range : 4;
-    uint32_t vrm_stepdelay_value : 4;
-    uint32_t hangpulse_predivider : 6;
-    uint32_t gpsa_timeout_value : 8;
-    uint32_t gpsa_timeout_value_sel : 1;
-    uint32_t _reserved0 : 2;
-#else
-    uint32_t _reserved0 : 2;
-    uint32_t gpsa_timeout_value_sel : 1;
-    uint32_t gpsa_timeout_value : 8;
-    uint32_t hangpulse_predivider : 6;
-    uint32_t vrm_stepdelay_value : 4;
-    uint32_t vrm_stepdelay_range : 4;
-    uint32_t pstate_stepsize : 7;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_parameter_reg0_t;
-
-
-
-typedef union pmc_parameter_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t ba_sram_pstate_table : 22;
-    int32_t pvsafe : 8;
-    uint32_t _reserved0 : 2;
-#else
-    uint32_t _reserved0 : 2;
-    int32_t pvsafe : 8;
-    uint32_t ba_sram_pstate_table : 22;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_parameter_reg1_t;
-
-
-
-typedef union pmc_eff_global_actual_voltage_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t maxreg_vdd : 8;
-    uint32_t maxreg_vcs : 8;
-    uint32_t eff_evid_vdd : 8;
-    uint32_t eff_evid_vcs : 8;
-#else
-    uint32_t eff_evid_vcs : 8;
-    uint32_t eff_evid_vdd : 8;
-    uint32_t maxreg_vcs : 8;
-    uint32_t maxreg_vdd : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_eff_global_actual_voltage_reg_t;
-
-
-
-typedef union pmc_global_actual_voltage_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t evid_vdd : 8;
-    uint32_t evid_vcs : 8;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t evid_vcs : 8;
-    uint32_t evid_vdd : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_global_actual_voltage_reg_t;
-
-
-
-typedef union pmc_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pstate_processing_is_suspended : 1;
-    uint32_t gpsa_bdcst_error : 1;
-    uint32_t gpsa_bdcst_resp_info : 3;
-    uint32_t gpsa_vchg_error : 1;
-    uint32_t gpsa_timeout_error : 1;
-    uint32_t gpsa_chg_ongoing : 1;
-    uint32_t volt_chg_ongoing : 1;
-    uint32_t brd_cst_ongoing : 1;
-    uint32_t gps_table_error : 1;
-    uint32_t pstate_interchip_error : 1;
-    uint32_t istate_processing_is_suspended : 1;
-    uint32_t safe_mode_engaged : 1;
-    uint32_t _reserved0 : 18;
-#else
-    uint32_t _reserved0 : 18;
-    uint32_t safe_mode_engaged : 1;
-    uint32_t istate_processing_is_suspended : 1;
-    uint32_t pstate_interchip_error : 1;
-    uint32_t gps_table_error : 1;
-    uint32_t brd_cst_ongoing : 1;
-    uint32_t volt_chg_ongoing : 1;
-    uint32_t gpsa_chg_ongoing : 1;
-    uint32_t gpsa_timeout_error : 1;
-    uint32_t gpsa_vchg_error : 1;
-    uint32_t gpsa_bdcst_resp_info : 3;
-    uint32_t gpsa_bdcst_error : 1;
-    uint32_t pstate_processing_is_suspended : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_status_reg_t;
-
-
-
-typedef union pmc_phase_enable_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t phase_enable : 4;
-    uint32_t _reserved0 : 28;
-#else
-    uint32_t _reserved0 : 28;
-    uint32_t phase_enable : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_phase_enable_reg_t;
-
-
-
-typedef union pmc_undervolting_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t puv_min : 8;
-    int32_t puv_max : 8;
-    uint32_t kuv_request : 8;
-    uint32_t _reserved0 : 8;
-#else
-    uint32_t _reserved0 : 8;
-    uint32_t kuv_request : 8;
-    int32_t puv_max : 8;
-    int32_t puv_min : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_undervolting_reg_t;
-
-
-
-typedef union pmc_core_deconfiguration_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t core_chiplet_deconf_vector : 16;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t core_chiplet_deconf_vector : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_deconfiguration_reg_t;
-
-
-
-typedef union pmc_intchp_ctrl_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_ga_fsm_enable : 1;
-    uint32_t interchip_recv_done_valid_without_if_en : 1;
-    uint32_t pmcic1_reserved_2 : 1;
-    uint32_t interchip_cpha : 1;
-    uint32_t interchip_clock_divider : 10;
-    uint32_t pmcicr1_reserved_14_17 : 4;
-    uint32_t pmcicr1_reserved_18_20 : 3;
-    uint32_t _reserved0 : 11;
-#else
-    uint32_t _reserved0 : 11;
-    uint32_t pmcicr1_reserved_18_20 : 3;
-    uint32_t pmcicr1_reserved_14_17 : 4;
-    uint32_t interchip_clock_divider : 10;
-    uint32_t interchip_cpha : 1;
-    uint32_t pmcic1_reserved_2 : 1;
-    uint32_t interchip_recv_done_valid_without_if_en : 1;
-    uint32_t interchip_ga_fsm_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_ctrl_reg1_t;
-
-
-
-typedef union pmc_intchp_ctrl_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_ping_send : 1;
-    uint32_t interchip_ping_detect_clear : 1;
-    uint32_t interchip_ping_mode : 1;
-    uint32_t pmcic2_reserved3 : 1;
-    uint32_t pmcic2_reserved4 : 1;
-    uint32_t pmcic2_reserved5_7 : 3;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    uint32_t pmcic2_reserved5_7 : 3;
-    uint32_t pmcic2_reserved4 : 1;
-    uint32_t pmcic2_reserved3 : 1;
-    uint32_t interchip_ping_mode : 1;
-    uint32_t interchip_ping_detect_clear : 1;
-    uint32_t interchip_ping_send : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_ctrl_reg2_t;
-
-
-
-typedef union pmc_intchp_ctrl_reg4 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_ecc_gen_en : 1;
-    uint32_t interchip_ecc_check_en : 1;
-    uint32_t interchip_msg_rcv_overflow_check_en : 1;
-    uint32_t interchip_ecc_ue_block_en : 1;
-    uint32_t chksw_hw221732 : 1;
-    uint32_t slave_occ_timeout_forces_safe_mode_disable : 1;
-    uint32_t pmcic4_reserved6_7 : 2;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    uint32_t pmcic4_reserved6_7 : 2;
-    uint32_t slave_occ_timeout_forces_safe_mode_disable : 1;
-    uint32_t chksw_hw221732 : 1;
-    uint32_t interchip_ecc_ue_block_en : 1;
-    uint32_t interchip_msg_rcv_overflow_check_en : 1;
-    uint32_t interchip_ecc_check_en : 1;
-    uint32_t interchip_ecc_gen_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_ctrl_reg4_t;
-
-
-
-typedef union pmc_intchp_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_ga_ongoing : 1;
-    uint32_t interchip_ecc_ue : 1;
-    uint32_t interchip_ecc_ce : 1;
-    uint32_t interchip_ping_detected : 1;
-    uint32_t interchip_ping_ack_detected : 1;
-    uint32_t interchip_msg_send_ongoing : 1;
-    uint32_t interchip_msg_recv_detected : 1;
-    uint32_t interchip_fsm_err : 1;
-    uint32_t interchip_ping_detect_count : 8;
-    uint32_t interchip_slave_error_code : 4;
-    uint32_t interchip_msg_snd_overflow_detected : 1;
-    uint32_t interchip_msg_rcv_overflow_detected : 1;
-    uint32_t interchip_ecc_ue_err : 1;
-    uint32_t _reserved0 : 9;
-#else
-    uint32_t _reserved0 : 9;
-    uint32_t interchip_ecc_ue_err : 1;
-    uint32_t interchip_msg_rcv_overflow_detected : 1;
-    uint32_t interchip_msg_snd_overflow_detected : 1;
-    uint32_t interchip_slave_error_code : 4;
-    uint32_t interchip_ping_detect_count : 8;
-    uint32_t interchip_fsm_err : 1;
-    uint32_t interchip_msg_recv_detected : 1;
-    uint32_t interchip_msg_send_ongoing : 1;
-    uint32_t interchip_ping_ack_detected : 1;
-    uint32_t interchip_ping_detected : 1;
-    uint32_t interchip_ecc_ce : 1;
-    uint32_t interchip_ecc_ue : 1;
-    uint32_t interchip_ga_ongoing : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_status_reg_t;
-
-
-
-typedef union pmc_intchp_command_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_reset_if : 1;
-    uint32_t interchip_halt_msg_fsm : 1;
-    uint32_t interchip_clear_sticky_bits : 1;
-    uint32_t _reserved0 : 29;
-#else
-    uint32_t _reserved0 : 29;
-    uint32_t interchip_clear_sticky_bits : 1;
-    uint32_t interchip_halt_msg_fsm : 1;
-    uint32_t interchip_reset_if : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_command_reg_t;
-
-
-
-typedef union pmc_intchp_msg_wdata {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_msg_wdata : 32;
-#else
-    uint32_t interchip_msg_wdata : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_msg_wdata_t;
-
-
-
-typedef union pmc_intchp_msg_rdata {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t interchip_msg_rdata : 32;
-#else
-    uint32_t interchip_msg_rdata : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_msg_rdata_t;
-
-
-
-typedef union pmc_intchp_pstate_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pstate_interchip : 8;
-    uint32_t _reserved0 : 24;
-#else
-    uint32_t _reserved0 : 24;
-    int32_t pstate_interchip : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_pstate_reg_t;
-
-
-
-typedef union pmc_intchp_globack_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t gaack_interchip : 1;
-    int32_t gaack_interchip_pstate : 8;
-    uint32_t _reserved0 : 23;
-#else
-    uint32_t _reserved0 : 23;
-    int32_t gaack_interchip_pstate : 8;
-    uint32_t gaack_interchip : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_intchp_globack_reg_t;
-
-
-
-typedef union pmc_fsmstate_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t mis_fsm_state : 3;
-    uint32_t mps_fsm_state : 5;
-    uint32_t svs_fsm_state : 4;
-    uint32_t o2s_fsm_state : 4;
-    uint32_t m2p_fsm_state : 4;
-    uint32_t o2p_fsm_state : 4;
-    uint32_t icp_msg_fsm_state : 5;
-    uint32_t _reserved0 : 3;
-#else
-    uint32_t _reserved0 : 3;
-    uint32_t icp_msg_fsm_state : 5;
-    uint32_t o2p_fsm_state : 4;
-    uint32_t m2p_fsm_state : 4;
-    uint32_t o2s_fsm_state : 4;
-    uint32_t svs_fsm_state : 4;
-    uint32_t mps_fsm_state : 5;
-    uint32_t mis_fsm_state : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_fsmstate_status_reg_t;
-
-
-
-typedef union pmc_trace_mode_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmc_trace_mode : 4;
-    uint32_t trace_sel_data : 2;
-    uint32_t _reserved0 : 26;
-#else
-    uint32_t _reserved0 : 26;
-    uint32_t trace_sel_data : 2;
-    uint32_t pmc_trace_mode : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_trace_mode_reg_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg0a {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_frame_size : 6;
-    uint32_t spivid_out_count1 : 6;
-    uint32_t spivid_in_delay1 : 6;
-    uint32_t spivid_in_count1 : 6;
-    uint32_t _reserved0 : 8;
-#else
-    uint32_t _reserved0 : 8;
-    uint32_t spivid_in_count1 : 6;
-    uint32_t spivid_in_delay1 : 6;
-    uint32_t spivid_out_count1 : 6;
-    uint32_t spivid_frame_size : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg0a_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg0b {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_out_count2 : 6;
-    uint32_t spivid_in_delay2 : 6;
-    uint32_t spivid_in_count2 : 6;
-    uint32_t _reserved0 : 14;
-#else
-    uint32_t _reserved0 : 14;
-    uint32_t spivid_in_count2 : 6;
-    uint32_t spivid_in_delay2 : 6;
-    uint32_t spivid_out_count2 : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg0b_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_fsm_enable : 1;
-    uint32_t pmcscr1_reserved_1 : 1;
-    uint32_t spivid_cpol : 1;
-    uint32_t spivid_cpha : 1;
-    uint32_t spivid_clock_divider : 10;
-    uint32_t pmcscr1_reserved_2 : 4;
-    uint32_t spivid_port_enable : 3;
-    uint32_t _reserved0 : 11;
-#else
-    uint32_t _reserved0 : 11;
-    uint32_t spivid_port_enable : 3;
-    uint32_t pmcscr1_reserved_2 : 4;
-    uint32_t spivid_clock_divider : 10;
-    uint32_t spivid_cpha : 1;
-    uint32_t spivid_cpol : 1;
-    uint32_t pmcscr1_reserved_1 : 1;
-    uint32_t spivid_fsm_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg1_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_inter_frame_delay_write_status : 17;
-    uint32_t _reserved0 : 15;
-#else
-    uint32_t _reserved0 : 15;
-    uint32_t spivid_inter_frame_delay_write_status : 17;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg2_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_inter_retry_delay : 17;
-    uint32_t pmc_100ns_pls_range : 6;
-    uint32_t _reserved0 : 9;
-#else
-    uint32_t _reserved0 : 9;
-    uint32_t pmc_100ns_pls_range : 6;
-    uint32_t spivid_inter_retry_delay : 17;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg3_t;
-
-
-
-typedef union pmc_spiv_ctrl_reg4 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_crc_gen_en : 1;
-    uint32_t spivid_crc_check_en : 1;
-    uint32_t spivid_majority_vote_en : 1;
-    uint32_t spivid_max_retries : 5;
-    uint32_t spivid_crc_polynomial_enables : 8;
-    uint32_t spivid_crc_const_gen_enable : 1;
-    uint32_t spivid_crc_const_check_enable : 1;
-    uint32_t spivid_frame_sync_wrong_enable : 1;
-    uint32_t _reserved0 : 13;
-#else
-    uint32_t _reserved0 : 13;
-    uint32_t spivid_frame_sync_wrong_enable : 1;
-    uint32_t spivid_crc_const_check_enable : 1;
-    uint32_t spivid_crc_const_gen_enable : 1;
-    uint32_t spivid_crc_polynomial_enables : 8;
-    uint32_t spivid_max_retries : 5;
-    uint32_t spivid_majority_vote_en : 1;
-    uint32_t spivid_crc_check_en : 1;
-    uint32_t spivid_crc_gen_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_ctrl_reg4_t;
-
-
-
-typedef union pmc_spiv_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_ongoing : 1;
-    uint32_t spivid_crc_error0 : 1;
-    uint32_t spivid_crc_error1 : 1;
-    uint32_t spivid_crc_error2 : 1;
-    uint32_t spivid_retry_timeout : 1;
-    uint32_t pmcssr_reserved_1 : 2;
-    uint32_t spivid_fsm_err : 1;
-    uint32_t spivid_majority_detected_a_minority0 : 1;
-    uint32_t spivid_majority_detected_a_minority1 : 1;
-    uint32_t spivid_majority_detected_a_minority2 : 1;
-    uint32_t spivid_majority_nr_of_minorities0 : 4;
-    uint32_t spivid_majority_nr_of_minorities1 : 4;
-    uint32_t spivid_majority_nr_of_minorities2 : 4;
-    uint32_t _reserved0 : 9;
-#else
-    uint32_t _reserved0 : 9;
-    uint32_t spivid_majority_nr_of_minorities2 : 4;
-    uint32_t spivid_majority_nr_of_minorities1 : 4;
-    uint32_t spivid_majority_nr_of_minorities0 : 4;
-    uint32_t spivid_majority_detected_a_minority2 : 1;
-    uint32_t spivid_majority_detected_a_minority1 : 1;
-    uint32_t spivid_majority_detected_a_minority0 : 1;
-    uint32_t spivid_fsm_err : 1;
-    uint32_t pmcssr_reserved_1 : 2;
-    uint32_t spivid_retry_timeout : 1;
-    uint32_t spivid_crc_error2 : 1;
-    uint32_t spivid_crc_error1 : 1;
-    uint32_t spivid_crc_error0 : 1;
-    uint32_t spivid_ongoing : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_status_reg_t;
-
-
-
-typedef union pmc_spiv_command_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t spivid_halt_fsm : 1;
-    uint32_t _reserved0 : 31;
-#else
-    uint32_t _reserved0 : 31;
-    uint32_t spivid_halt_fsm : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_spiv_command_reg_t;
-
-
-
-typedef union pmc_o2s_ctrl_reg0a {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_frame_size : 6;
-    uint32_t o2s_out_count1 : 6;
-    uint32_t o2s_in_delay1 : 6;
-    uint32_t o2s_in_count1 : 6;
-    uint32_t _reserved0 : 8;
-#else
-    uint32_t _reserved0 : 8;
-    uint32_t o2s_in_count1 : 6;
-    uint32_t o2s_in_delay1 : 6;
-    uint32_t o2s_out_count1 : 6;
-    uint32_t o2s_frame_size : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_ctrl_reg0a_t;
-
-
-
-typedef union pmc_o2s_ctrl_reg0b {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_out_count2 : 6;
-    uint32_t o2s_in_delay2 : 6;
-    uint32_t o2s_in_count2 : 6;
-    uint32_t _reserved0 : 14;
-#else
-    uint32_t _reserved0 : 14;
-    uint32_t o2s_in_count2 : 6;
-    uint32_t o2s_in_delay2 : 6;
-    uint32_t o2s_out_count2 : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_ctrl_reg0b_t;
-
-
-
-typedef union pmc_o2s_ctrl_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_bridge_enable : 1;
-    uint32_t pmcocr1_reserved_1 : 1;
-    uint32_t o2s_cpol : 1;
-    uint32_t o2s_cpha : 1;
-    uint32_t o2s_clock_divider : 10;
-    uint32_t pmcocr1_reserved_2 : 3;
-    uint32_t o2s_nr_of_frames : 1;
-    uint32_t o2s_port_enable : 3;
-    uint32_t _reserved0 : 11;
-#else
-    uint32_t _reserved0 : 11;
-    uint32_t o2s_port_enable : 3;
-    uint32_t o2s_nr_of_frames : 1;
-    uint32_t pmcocr1_reserved_2 : 3;
-    uint32_t o2s_clock_divider : 10;
-    uint32_t o2s_cpha : 1;
-    uint32_t o2s_cpol : 1;
-    uint32_t pmcocr1_reserved_1 : 1;
-    uint32_t o2s_bridge_enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_ctrl_reg1_t;
-
-
-
-typedef union pmc_o2s_ctrl_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_inter_frame_delay : 17;
-    uint32_t _reserved0 : 15;
-#else
-    uint32_t _reserved0 : 15;
-    uint32_t o2s_inter_frame_delay : 17;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_ctrl_reg2_t;
-
-
-
-typedef union pmc_o2s_ctrl_reg4 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_crc_gen_en : 1;
-    uint32_t o2s_crc_check_en : 1;
-    uint32_t o2s_majority_vote_en : 1;
-    uint32_t o2s_max_retries : 5;
-    uint32_t pmcocr4_reserved8_15 : 8;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t pmcocr4_reserved8_15 : 8;
-    uint32_t o2s_max_retries : 5;
-    uint32_t o2s_majority_vote_en : 1;
-    uint32_t o2s_crc_check_en : 1;
-    uint32_t o2s_crc_gen_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_ctrl_reg4_t;
-
-
-
-typedef union pmc_o2s_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_ongoing : 1;
-    uint32_t o2s_crc_error0 : 1;
-    uint32_t o2s_crc_error1 : 1;
-    uint32_t o2s_crc_error2 : 1;
-    uint32_t o2s_retry_timeout : 1;
-    uint32_t o2s_write_while_bridge_busy_err : 1;
-    uint32_t pmcosr_reserved_6 : 1;
-    uint32_t o2s_fsm_err : 1;
-    uint32_t o2s_majority_detected_a_minority0 : 1;
-    uint32_t o2s_majority_detected_a_minority1 : 1;
-    uint32_t o2s_majority_detected_a_minority2 : 1;
-    uint32_t o2s_majority_nr_of_minorities0 : 4;
-    uint32_t o2s_majority_nr_of_minorities1 : 4;
-    uint32_t o2s_majority_nr_of_minorities2 : 4;
-    uint32_t _reserved0 : 9;
-#else
-    uint32_t _reserved0 : 9;
-    uint32_t o2s_majority_nr_of_minorities2 : 4;
-    uint32_t o2s_majority_nr_of_minorities1 : 4;
-    uint32_t o2s_majority_nr_of_minorities0 : 4;
-    uint32_t o2s_majority_detected_a_minority2 : 1;
-    uint32_t o2s_majority_detected_a_minority1 : 1;
-    uint32_t o2s_majority_detected_a_minority0 : 1;
-    uint32_t o2s_fsm_err : 1;
-    uint32_t pmcosr_reserved_6 : 1;
-    uint32_t o2s_write_while_bridge_busy_err : 1;
-    uint32_t o2s_retry_timeout : 1;
-    uint32_t o2s_crc_error2 : 1;
-    uint32_t o2s_crc_error1 : 1;
-    uint32_t o2s_crc_error0 : 1;
-    uint32_t o2s_ongoing : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_status_reg_t;
-
-
-
-typedef union pmc_o2s_command_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_halt_retries : 1;
-    uint32_t o2s_clear_sticky_bits : 1;
-    uint32_t _reserved0 : 30;
-#else
-    uint32_t _reserved0 : 30;
-    uint32_t o2s_clear_sticky_bits : 1;
-    uint32_t o2s_halt_retries : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_command_reg_t;
-
-
-
-typedef union pmc_o2s_wdata_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_wdata : 32;
-#else
-    uint32_t o2s_wdata : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_wdata_reg_t;
-
-
-
-typedef union pmc_o2s_rdata_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2s_rdata : 32;
-#else
-    uint32_t o2s_rdata : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2s_rdata_reg_t;
-
-
-
-typedef union pmc_o2p_addr_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_write_plus_read : 1;
-    uint32_t o2p_mc : 1;
-    uint32_t o2p_slave_addr : 6;
-    uint32_t o2p_read_not_write : 1;
-    uint32_t reserved_bit_pmco2par2 : 3;
-    uint32_t o2p_pcb_port : 4;
-    uint32_t o2p_pcb_reg_addr : 16;
-#else
-    uint32_t o2p_pcb_reg_addr : 16;
-    uint32_t o2p_pcb_port : 4;
-    uint32_t reserved_bit_pmco2par2 : 3;
-    uint32_t o2p_read_not_write : 1;
-    uint32_t o2p_slave_addr : 6;
-    uint32_t o2p_mc : 1;
-    uint32_t o2p_write_plus_read : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_addr_reg_t;
-
-
-
-typedef union pmc_o2p_ctrl_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_ongoing : 1;
-    uint32_t o2p_scresp : 3;
-    uint32_t o2p_write_while_bridge_busy_err : 1;
-    uint32_t o2p_fsm_err : 1;
-    uint32_t o2p_abort : 1;
-    uint32_t o2p_parity_error : 1;
-    uint32_t o2p_clear_sticky_bits : 1;
-    uint32_t _reserved0 : 23;
-#else
-    uint32_t _reserved0 : 23;
-    uint32_t o2p_clear_sticky_bits : 1;
-    uint32_t o2p_parity_error : 1;
-    uint32_t o2p_abort : 1;
-    uint32_t o2p_fsm_err : 1;
-    uint32_t o2p_write_while_bridge_busy_err : 1;
-    uint32_t o2p_scresp : 3;
-    uint32_t o2p_ongoing : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_ctrl_status_reg_t;
-
-
-
-typedef union pmc_o2p_send_data_hi_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_send_data_hi : 32;
-#else
-    uint32_t o2p_send_data_hi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_send_data_hi_reg_t;
-
-
-
-typedef union pmc_o2p_send_data_lo_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_send_data_lo : 32;
-#else
-    uint32_t o2p_send_data_lo : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_send_data_lo_reg_t;
-
-
-
-typedef union pmc_o2p_recv_data_hi_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_receive_data_hi : 32;
-#else
-    uint32_t o2p_receive_data_hi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_recv_data_hi_reg_t;
-
-
-
-typedef union pmc_o2p_recv_data_lo_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t o2p_receive_data_lo : 32;
-#else
-    uint32_t o2p_receive_data_lo : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_o2p_recv_data_lo_reg_t;
-
-
-
-typedef union pmc_occ_heartbeat_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmc_occ_heartbeat_time : 16;
-    uint32_t pmc_occ_heartbeat_en : 1;
-    uint32_t _reserved0 : 15;
-#else
-    uint32_t _reserved0 : 15;
-    uint32_t pmc_occ_heartbeat_en : 1;
-    uint32_t pmc_occ_heartbeat_time : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_occ_heartbeat_reg_t;
-
-
-
-typedef union pmc_error_int_mask_hi_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmc_error_int_mask_hi : 32;
-#else
-    uint32_t pmc_error_int_mask_hi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_error_int_mask_hi_reg_t;
-
-
-
-typedef union pmc_error_int_mask_lo_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmc_error_int_mask_lo : 32;
-#else
-    uint32_t pmc_error_int_mask_lo : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_error_int_mask_lo_reg_t;
-
-
-
-typedef union pmc_idle_suspend_mask_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmc_idle_suspend_mask : 16;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t pmc_idle_suspend_mask : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_idle_suspend_mask_reg_t;
-
-
-
-typedef union pmc_pend_idle_req_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t idle_pending_0 : 1;
-    uint32_t idle_op_0 : 2;
-    uint32_t idle_type_0 : 1;
-    uint32_t idle_scope_0 : 1;
-    uint32_t assist_mode_0 : 1;
-    uint32_t reserved_pirr_0 : 2;
-    uint32_t idle_pending_1 : 1;
-    uint32_t idle_op_1 : 2;
-    uint32_t idle_type_1 : 1;
-    uint32_t idle_scope_1 : 1;
-    uint32_t assist_mode_1 : 1;
-    uint32_t reserved_pirr_1 : 2;
-    uint32_t idle_pending_2 : 1;
-    uint32_t idle_op_2 : 2;
-    uint32_t idle_type_2 : 1;
-    uint32_t idle_scope_2 : 1;
-    uint32_t assist_mode_2 : 1;
-    uint32_t reserved_pirr_2 : 2;
-    uint32_t idle_pending_3 : 1;
-    uint32_t idle_op_3 : 2;
-    uint32_t idle_type_3 : 1;
-    uint32_t idle_scope_3 : 1;
-    uint32_t assist_mode_3 : 1;
-    uint32_t reserved_pirr_3 : 2;
-#else
-    uint32_t reserved_pirr_3 : 2;
-    uint32_t assist_mode_3 : 1;
-    uint32_t idle_scope_3 : 1;
-    uint32_t idle_type_3 : 1;
-    uint32_t idle_op_3 : 2;
-    uint32_t idle_pending_3 : 1;
-    uint32_t reserved_pirr_2 : 2;
-    uint32_t assist_mode_2 : 1;
-    uint32_t idle_scope_2 : 1;
-    uint32_t idle_type_2 : 1;
-    uint32_t idle_op_2 : 2;
-    uint32_t idle_pending_2 : 1;
-    uint32_t reserved_pirr_1 : 2;
-    uint32_t assist_mode_1 : 1;
-    uint32_t idle_scope_1 : 1;
-    uint32_t idle_type_1 : 1;
-    uint32_t idle_op_1 : 2;
-    uint32_t idle_pending_1 : 1;
-    uint32_t reserved_pirr_0 : 2;
-    uint32_t assist_mode_0 : 1;
-    uint32_t idle_scope_0 : 1;
-    uint32_t idle_type_0 : 1;
-    uint32_t idle_op_0 : 2;
-    uint32_t idle_pending_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pend_idle_req_reg0_t;
-
-
-
-typedef union pmc_pend_idle_req_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t idle_pending_4 : 1;
-    uint32_t idle_op_4 : 2;
-    uint32_t idle_type_4 : 1;
-    uint32_t idle_scope_4 : 1;
-    uint32_t assist_mode_4 : 1;
-    uint32_t reserved_pirr_4 : 2;
-    uint32_t idle_pending_5 : 1;
-    uint32_t idle_op_5 : 2;
-    uint32_t idle_type_5 : 1;
-    uint32_t idle_scope_5 : 1;
-    uint32_t assist_mode_5 : 1;
-    uint32_t reserved_pirr_5 : 2;
-    uint32_t idle_pending_6 : 1;
-    uint32_t idle_op_6 : 2;
-    uint32_t idle_type_6 : 1;
-    uint32_t idle_scope_6 : 1;
-    uint32_t assist_mode_6 : 1;
-    uint32_t reserved_pirr_6 : 2;
-    uint32_t idle_pending_7 : 1;
-    uint32_t idle_op_7 : 2;
-    uint32_t idle_type_7 : 1;
-    uint32_t idle_scope_7 : 1;
-    uint32_t assist_mode_7 : 1;
-    uint32_t reserved_pirr_7 : 2;
-#else
-    uint32_t reserved_pirr_7 : 2;
-    uint32_t assist_mode_7 : 1;
-    uint32_t idle_scope_7 : 1;
-    uint32_t idle_type_7 : 1;
-    uint32_t idle_op_7 : 2;
-    uint32_t idle_pending_7 : 1;
-    uint32_t reserved_pirr_6 : 2;
-    uint32_t assist_mode_6 : 1;
-    uint32_t idle_scope_6 : 1;
-    uint32_t idle_type_6 : 1;
-    uint32_t idle_op_6 : 2;
-    uint32_t idle_pending_6 : 1;
-    uint32_t reserved_pirr_5 : 2;
-    uint32_t assist_mode_5 : 1;
-    uint32_t idle_scope_5 : 1;
-    uint32_t idle_type_5 : 1;
-    uint32_t idle_op_5 : 2;
-    uint32_t idle_pending_5 : 1;
-    uint32_t reserved_pirr_4 : 2;
-    uint32_t assist_mode_4 : 1;
-    uint32_t idle_scope_4 : 1;
-    uint32_t idle_type_4 : 1;
-    uint32_t idle_op_4 : 2;
-    uint32_t idle_pending_4 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pend_idle_req_reg1_t;
-
-
-
-typedef union pmc_pend_idle_req_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t idle_pending_8 : 1;
-    uint32_t idle_op_8 : 2;
-    uint32_t idle_type_8 : 1;
-    uint32_t idle_scope_8 : 1;
-    uint32_t assist_mode_8 : 1;
-    uint32_t reserved_pirr_8 : 2;
-    uint32_t idle_pending_9 : 1;
-    uint32_t idle_op_9 : 2;
-    uint32_t idle_type_9 : 1;
-    uint32_t idle_scope_9 : 1;
-    uint32_t assist_mode_9 : 1;
-    uint32_t reserved_pirr_9 : 2;
-    uint32_t idle_pending_10 : 1;
-    uint32_t idle_op_10 : 2;
-    uint32_t idle_type_10 : 1;
-    uint32_t idle_scope_10 : 1;
-    uint32_t assist_mode_10 : 1;
-    uint32_t reserved_pirr_10 : 2;
-    uint32_t idle_pending_11 : 1;
-    uint32_t idle_op_11 : 2;
-    uint32_t idle_type_11 : 1;
-    uint32_t idle_scope_11 : 1;
-    uint32_t assist_mode_11 : 1;
-    uint32_t reserved_pirr_11 : 2;
-#else
-    uint32_t reserved_pirr_11 : 2;
-    uint32_t assist_mode_11 : 1;
-    uint32_t idle_scope_11 : 1;
-    uint32_t idle_type_11 : 1;
-    uint32_t idle_op_11 : 2;
-    uint32_t idle_pending_11 : 1;
-    uint32_t reserved_pirr_10 : 2;
-    uint32_t assist_mode_10 : 1;
-    uint32_t idle_scope_10 : 1;
-    uint32_t idle_type_10 : 1;
-    uint32_t idle_op_10 : 2;
-    uint32_t idle_pending_10 : 1;
-    uint32_t reserved_pirr_9 : 2;
-    uint32_t assist_mode_9 : 1;
-    uint32_t idle_scope_9 : 1;
-    uint32_t idle_type_9 : 1;
-    uint32_t idle_op_9 : 2;
-    uint32_t idle_pending_9 : 1;
-    uint32_t reserved_pirr_8 : 2;
-    uint32_t assist_mode_8 : 1;
-    uint32_t idle_scope_8 : 1;
-    uint32_t idle_type_8 : 1;
-    uint32_t idle_op_8 : 2;
-    uint32_t idle_pending_8 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pend_idle_req_reg2_t;
-
-
-
-typedef union pmc_pend_idle_req_reg3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t idle_pending_12 : 1;
-    uint32_t idle_op_12 : 2;
-    uint32_t idle_type_12 : 1;
-    uint32_t idle_scope_12 : 1;
-    uint32_t assist_mode_12 : 1;
-    uint32_t reserved_pirr_12 : 2;
-    uint32_t idle_pending_13 : 1;
-    uint32_t idle_op_13 : 2;
-    uint32_t idle_type_13 : 1;
-    uint32_t idle_scope_13 : 1;
-    uint32_t assist_mode_13 : 1;
-    uint32_t reserved_pirr_13 : 2;
-    uint32_t idle_pending_14 : 1;
-    uint32_t idle_op_14 : 2;
-    uint32_t idle_type_14 : 1;
-    uint32_t idle_scope_14 : 1;
-    uint32_t assist_mode_14 : 1;
-    uint32_t reserved_pirr_14 : 2;
-    uint32_t idle_pending_15 : 1;
-    uint32_t idle_op_15 : 2;
-    uint32_t idle_type_15 : 1;
-    uint32_t idle_scope_15 : 1;
-    uint32_t assist_mode_15 : 1;
-    uint32_t reserved_pirr_15 : 2;
-#else
-    uint32_t reserved_pirr_15 : 2;
-    uint32_t assist_mode_15 : 1;
-    uint32_t idle_scope_15 : 1;
-    uint32_t idle_type_15 : 1;
-    uint32_t idle_op_15 : 2;
-    uint32_t idle_pending_15 : 1;
-    uint32_t reserved_pirr_14 : 2;
-    uint32_t assist_mode_14 : 1;
-    uint32_t idle_scope_14 : 1;
-    uint32_t idle_type_14 : 1;
-    uint32_t idle_op_14 : 2;
-    uint32_t idle_pending_14 : 1;
-    uint32_t reserved_pirr_13 : 2;
-    uint32_t assist_mode_13 : 1;
-    uint32_t idle_scope_13 : 1;
-    uint32_t idle_type_13 : 1;
-    uint32_t idle_op_13 : 2;
-    uint32_t idle_pending_13 : 1;
-    uint32_t reserved_pirr_12 : 2;
-    uint32_t assist_mode_12 : 1;
-    uint32_t idle_scope_12 : 1;
-    uint32_t idle_type_12 : 1;
-    uint32_t idle_op_12 : 2;
-    uint32_t idle_pending_12 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pend_idle_req_reg3_t;
-
-
-
-typedef union pmc_sleep_int_req_vec_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t fastsleepentry_int_req_vec : 32;
-#else
-    uint32_t fastsleepentry_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_sleep_int_req_vec_reg0_t;
-
-
-
-typedef union pmc_sleep_int_req_vec_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deepsleepentry_int_req_vec : 32;
-#else
-    uint32_t deepsleepentry_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_sleep_int_req_vec_reg1_t;
-
-
-
-typedef union pmc_sleep_int_req_vec_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t fastsleepexit_int_req_vec : 32;
-#else
-    uint32_t fastsleepexit_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_sleep_int_req_vec_reg2_t;
-
-
-
-typedef union pmc_sleep_int_req_vec_reg3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deepsleepexit_int_req_vec : 32;
-#else
-    uint32_t deepsleepexit_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_sleep_int_req_vec_reg3_t;
-
-
-
-typedef union pmc_winkle_int_req_vec_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t fastwinkleentry_int_req_vec : 32;
-#else
-    uint32_t fastwinkleentry_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_winkle_int_req_vec_reg0_t;
-
-
-
-typedef union pmc_winkle_int_req_vec_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deepwinkleentry_int_req_vec : 32;
-#else
-    uint32_t deepwinkleentry_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_winkle_int_req_vec_reg1_t;
-
-
-
-typedef union pmc_winkle_int_req_vec_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t fastwinkleexit_int_req_vec : 32;
-#else
-    uint32_t fastwinkleexit_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_winkle_int_req_vec_reg2_t;
-
-
-
-typedef union pmc_winkle_int_req_vec_reg3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deepwinkleexit_int_req_vec : 32;
-#else
-    uint32_t deepwinkleexit_int_req_vec : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_winkle_int_req_vec_reg3_t;
-
-
-
-typedef union pmc_nap_int_req_vec_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t napentry_int_req_vec : 16;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t napentry_int_req_vec : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_nap_int_req_vec_reg0_t;
-
-
-
-typedef union pmc_nap_int_req_vec_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t napexit_int_req_vec : 25;
-    uint32_t _reserved0 : 7;
-#else
-    uint32_t _reserved0 : 7;
-    uint32_t napexit_int_req_vec : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_nap_int_req_vec_reg1_t;
-
-
-
-typedef union pmc_pore_req_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porrr_reserved0 : 8;
-    uint32_t porrr_start_vector : 4;
-    uint32_t porrr_reserved1 : 8;
-    uint32_t porrr_pore_busy : 1;
-    uint32_t porrr_pore_suspended : 1;
-    uint32_t porrr_porrtc_busy : 1;
-    uint32_t _reserved0 : 9;
-#else
-    uint32_t _reserved0 : 9;
-    uint32_t porrr_porrtc_busy : 1;
-    uint32_t porrr_pore_suspended : 1;
-    uint32_t porrr_pore_busy : 1;
-    uint32_t porrr_reserved1 : 8;
-    uint32_t porrr_start_vector : 4;
-    uint32_t porrr_reserved0 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_req_reg0_t;
-
-
-
-typedef union pmc_pore_req_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porrr_chiplet_enable_0 : 1;
-    uint32_t porrr_chiplet_enable_1 : 1;
-    uint32_t porrr_chiplet_enable_2 : 1;
-    uint32_t porrr_chiplet_enable_3 : 1;
-    uint32_t porrr_chiplet_enable_4 : 1;
-    uint32_t porrr_chiplet_enable_5 : 1;
-    uint32_t porrr_chiplet_enable_6 : 1;
-    uint32_t porrr_chiplet_enable_7 : 1;
-    uint32_t porrr_chiplet_enable_8 : 1;
-    uint32_t porrr_chiplet_enable_9 : 1;
-    uint32_t porrr_chiplet_enable_10 : 1;
-    uint32_t porrr_chiplet_enable_11 : 1;
-    uint32_t porrr_chiplet_enable_12 : 1;
-    uint32_t porrr_chiplet_enable_13 : 1;
-    uint32_t porrr_chiplet_enable_14 : 1;
-    uint32_t porrr_chiplet_enable_15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t porrr_chiplet_enable_15 : 1;
-    uint32_t porrr_chiplet_enable_14 : 1;
-    uint32_t porrr_chiplet_enable_13 : 1;
-    uint32_t porrr_chiplet_enable_12 : 1;
-    uint32_t porrr_chiplet_enable_11 : 1;
-    uint32_t porrr_chiplet_enable_10 : 1;
-    uint32_t porrr_chiplet_enable_9 : 1;
-    uint32_t porrr_chiplet_enable_8 : 1;
-    uint32_t porrr_chiplet_enable_7 : 1;
-    uint32_t porrr_chiplet_enable_6 : 1;
-    uint32_t porrr_chiplet_enable_5 : 1;
-    uint32_t porrr_chiplet_enable_4 : 1;
-    uint32_t porrr_chiplet_enable_3 : 1;
-    uint32_t porrr_chiplet_enable_2 : 1;
-    uint32_t porrr_chiplet_enable_1 : 1;
-    uint32_t porrr_chiplet_enable_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_req_reg1_t;
-
-
-
-typedef union pmc_pore_req_stat_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porrs_reserved0 : 8;
-    uint32_t porrs_start_vector : 4;
-    uint32_t pore_rc : 8;
-    uint32_t porrs_reserved1 : 1;
-    uint32_t porrs_recovery_write : 1;
-    uint32_t _reserved0 : 10;
-#else
-    uint32_t _reserved0 : 10;
-    uint32_t porrs_recovery_write : 1;
-    uint32_t porrs_reserved1 : 1;
-    uint32_t pore_rc : 8;
-    uint32_t porrs_start_vector : 4;
-    uint32_t porrs_reserved0 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_req_stat_reg_t;
-
-
-
-typedef union pmc_pore_req_tout_th_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porrtt_timeout_threshold : 8;
-    uint32_t porrtc_no_predivide : 1;
-    uint32_t _reserved0 : 23;
-#else
-    uint32_t _reserved0 : 23;
-    uint32_t porrtc_no_predivide : 1;
-    uint32_t porrtt_timeout_threshold : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_req_tout_th_reg_t;
-
-
-
-typedef union pmc_deep_exit_mask_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t chiplet_deep_exit_mask0 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_deep_exit_mask_reg_t;
-
-
-
-typedef union pmc_deep_exit_mask_reg_and {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t chiplet_deep_exit_mask0 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_deep_exit_mask_reg_and_t;
-
-
-
-typedef union pmc_deep_exit_mask_reg_or {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t chiplet_deep_exit_mask0 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t chiplet_deep_exit_mask15 : 1;
-    uint32_t chiplet_deep_exit_mask14 : 1;
-    uint32_t chiplet_deep_exit_mask13 : 1;
-    uint32_t chiplet_deep_exit_mask12 : 1;
-    uint32_t chiplet_deep_exit_mask11 : 1;
-    uint32_t chiplet_deep_exit_mask10 : 1;
-    uint32_t chiplet_deep_exit_mask9 : 1;
-    uint32_t chiplet_deep_exit_mask8 : 1;
-    uint32_t chiplet_deep_exit_mask7 : 1;
-    uint32_t chiplet_deep_exit_mask6 : 1;
-    uint32_t chiplet_deep_exit_mask5 : 1;
-    uint32_t chiplet_deep_exit_mask4 : 1;
-    uint32_t chiplet_deep_exit_mask3 : 1;
-    uint32_t chiplet_deep_exit_mask2 : 1;
-    uint32_t chiplet_deep_exit_mask1 : 1;
-    uint32_t chiplet_deep_exit_mask0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_deep_exit_mask_reg_or_t;
-
-
-
-typedef union pmc_core_pstate_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pstate_core0 : 8;
-    int32_t pstate_core1 : 8;
-    int32_t pstate_core2 : 8;
-    int32_t pstate_core3 : 8;
-#else
-    int32_t pstate_core3 : 8;
-    int32_t pstate_core2 : 8;
-    int32_t pstate_core1 : 8;
-    int32_t pstate_core0 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_pstate_reg0_t;
-
-
-
-typedef union pmc_core_pstate_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pstate_core4 : 8;
-    int32_t pstate_core5 : 8;
-    int32_t pstate_core6 : 8;
-    int32_t pstate_core7 : 8;
-#else
-    int32_t pstate_core7 : 8;
-    int32_t pstate_core6 : 8;
-    int32_t pstate_core5 : 8;
-    int32_t pstate_core4 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_pstate_reg1_t;
-
-
-
-typedef union pmc_core_pstate_reg2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pstate_core8 : 8;
-    int32_t pstate_core9 : 8;
-    int32_t pstate_core10 : 8;
-    int32_t pstate_core11 : 8;
-#else
-    int32_t pstate_core11 : 8;
-    int32_t pstate_core10 : 8;
-    int32_t pstate_core9 : 8;
-    int32_t pstate_core8 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_pstate_reg2_t;
-
-
-
-typedef union pmc_core_pstate_reg3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    int32_t pstate_core12 : 8;
-    int32_t pstate_core13 : 8;
-    int32_t pstate_core14 : 8;
-    int32_t pstate_core15 : 8;
-#else
-    int32_t pstate_core15 : 8;
-    int32_t pstate_core14 : 8;
-    int32_t pstate_core13 : 8;
-    int32_t pstate_core12 : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_pstate_reg3_t;
-
-
-
-typedef union pmc_core_power_donation_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t power_donation_core0 : 1;
-    uint32_t power_donation_core1 : 1;
-    uint32_t power_donation_core2 : 1;
-    uint32_t power_donation_core3 : 1;
-    uint32_t power_donation_core4 : 1;
-    uint32_t power_donation_core5 : 1;
-    uint32_t power_donation_core6 : 1;
-    uint32_t power_donation_core7 : 1;
-    uint32_t power_donation_core8 : 1;
-    uint32_t power_donation_core9 : 1;
-    uint32_t power_donation_core10 : 1;
-    uint32_t power_donation_core11 : 1;
-    uint32_t power_donation_core12 : 1;
-    uint32_t power_donation_core13 : 1;
-    uint32_t power_donation_core14 : 1;
-    uint32_t power_donation_core15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t power_donation_core15 : 1;
-    uint32_t power_donation_core14 : 1;
-    uint32_t power_donation_core13 : 1;
-    uint32_t power_donation_core12 : 1;
-    uint32_t power_donation_core11 : 1;
-    uint32_t power_donation_core10 : 1;
-    uint32_t power_donation_core9 : 1;
-    uint32_t power_donation_core8 : 1;
-    uint32_t power_donation_core7 : 1;
-    uint32_t power_donation_core6 : 1;
-    uint32_t power_donation_core5 : 1;
-    uint32_t power_donation_core4 : 1;
-    uint32_t power_donation_core3 : 1;
-    uint32_t power_donation_core2 : 1;
-    uint32_t power_donation_core1 : 1;
-    uint32_t power_donation_core0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_core_power_donation_reg_t;
-
-
-
-typedef union pmc_pmax_sync_collection_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmax_sync0 : 1;
-    uint32_t pmax_sync1 : 1;
-    uint32_t pmax_sync2 : 1;
-    uint32_t pmax_sync3 : 1;
-    uint32_t pmax_sync4 : 1;
-    uint32_t pmax_sync5 : 1;
-    uint32_t pmax_sync6 : 1;
-    uint32_t pmax_sync7 : 1;
-    uint32_t pmax_sync8 : 1;
-    uint32_t pmax_sync9 : 1;
-    uint32_t pmax_sync10 : 1;
-    uint32_t pmax_sync11 : 1;
-    uint32_t pmax_sync12 : 1;
-    uint32_t pmax_sync13 : 1;
-    uint32_t pmax_sync14 : 1;
-    uint32_t pmax_sync15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t pmax_sync15 : 1;
-    uint32_t pmax_sync14 : 1;
-    uint32_t pmax_sync13 : 1;
-    uint32_t pmax_sync12 : 1;
-    uint32_t pmax_sync11 : 1;
-    uint32_t pmax_sync10 : 1;
-    uint32_t pmax_sync9 : 1;
-    uint32_t pmax_sync8 : 1;
-    uint32_t pmax_sync7 : 1;
-    uint32_t pmax_sync6 : 1;
-    uint32_t pmax_sync5 : 1;
-    uint32_t pmax_sync4 : 1;
-    uint32_t pmax_sync3 : 1;
-    uint32_t pmax_sync2 : 1;
-    uint32_t pmax_sync1 : 1;
-    uint32_t pmax_sync0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pmax_sync_collection_reg_t;
-
-
-
-typedef union pmc_pmax_sync_collection_mask_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t pmax_sync_mask0 : 1;
-    uint32_t pmax_sync_mask1 : 1;
-    uint32_t pmax_sync_mask2 : 1;
-    uint32_t pmax_sync_mask3 : 1;
-    uint32_t pmax_sync_mask4 : 1;
-    uint32_t pmax_sync_mask5 : 1;
-    uint32_t pmax_sync_mask6 : 1;
-    uint32_t pmax_sync_mask7 : 1;
-    uint32_t pmax_sync_mask8 : 1;
-    uint32_t pmax_sync_mask9 : 1;
-    uint32_t pmax_sync_mask10 : 1;
-    uint32_t pmax_sync_mask11 : 1;
-    uint32_t pmax_sync_mask12 : 1;
-    uint32_t pmax_sync_mask13 : 1;
-    uint32_t pmax_sync_mask14 : 1;
-    uint32_t pmax_sync_mask15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t pmax_sync_mask15 : 1;
-    uint32_t pmax_sync_mask14 : 1;
-    uint32_t pmax_sync_mask13 : 1;
-    uint32_t pmax_sync_mask12 : 1;
-    uint32_t pmax_sync_mask11 : 1;
-    uint32_t pmax_sync_mask10 : 1;
-    uint32_t pmax_sync_mask9 : 1;
-    uint32_t pmax_sync_mask8 : 1;
-    uint32_t pmax_sync_mask7 : 1;
-    uint32_t pmax_sync_mask6 : 1;
-    uint32_t pmax_sync_mask5 : 1;
-    uint32_t pmax_sync_mask4 : 1;
-    uint32_t pmax_sync_mask3 : 1;
-    uint32_t pmax_sync_mask2 : 1;
-    uint32_t pmax_sync_mask1 : 1;
-    uint32_t pmax_sync_mask0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pmax_sync_collection_mask_reg_t;
-
-
-
-typedef union pmc_gpsa_ack_collection_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t gpsa_ack0 : 1;
-    uint32_t gpsa_ack1 : 1;
-    uint32_t gpsa_ack2 : 1;
-    uint32_t gpsa_ack3 : 1;
-    uint32_t gpsa_ack4 : 1;
-    uint32_t gpsa_ack5 : 1;
-    uint32_t gpsa_ack6 : 1;
-    uint32_t gpsa_ack7 : 1;
-    uint32_t gpsa_ack8 : 1;
-    uint32_t gpsa_ack9 : 1;
-    uint32_t gpsa_ack10 : 1;
-    uint32_t gpsa_ack11 : 1;
-    uint32_t gpsa_ack12 : 1;
-    uint32_t gpsa_ack13 : 1;
-    uint32_t gpsa_ack14 : 1;
-    uint32_t gpsa_ack15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t gpsa_ack15 : 1;
-    uint32_t gpsa_ack14 : 1;
-    uint32_t gpsa_ack13 : 1;
-    uint32_t gpsa_ack12 : 1;
-    uint32_t gpsa_ack11 : 1;
-    uint32_t gpsa_ack10 : 1;
-    uint32_t gpsa_ack9 : 1;
-    uint32_t gpsa_ack8 : 1;
-    uint32_t gpsa_ack7 : 1;
-    uint32_t gpsa_ack6 : 1;
-    uint32_t gpsa_ack5 : 1;
-    uint32_t gpsa_ack4 : 1;
-    uint32_t gpsa_ack3 : 1;
-    uint32_t gpsa_ack2 : 1;
-    uint32_t gpsa_ack1 : 1;
-    uint32_t gpsa_ack0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_gpsa_ack_collection_reg_t;
-
-
-
-typedef union pmc_gpsa_ack_collection_mask_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t gpsa_ack_mask0 : 1;
-    uint32_t gpsa_ack_mask1 : 1;
-    uint32_t gpsa_ack_mask2 : 1;
-    uint32_t gpsa_ack_mask3 : 1;
-    uint32_t gpsa_ack_mask4 : 1;
-    uint32_t gpsa_ack_mask5 : 1;
-    uint32_t gpsa_ack_mask6 : 1;
-    uint32_t gpsa_ack_mask7 : 1;
-    uint32_t gpsa_ack_mask8 : 1;
-    uint32_t gpsa_ack_mask9 : 1;
-    uint32_t gpsa_ack_mask10 : 1;
-    uint32_t gpsa_ack_mask11 : 1;
-    uint32_t gpsa_ack_mask12 : 1;
-    uint32_t gpsa_ack_mask13 : 1;
-    uint32_t gpsa_ack_mask14 : 1;
-    uint32_t gpsa_ack_mask15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t gpsa_ack_mask15 : 1;
-    uint32_t gpsa_ack_mask14 : 1;
-    uint32_t gpsa_ack_mask13 : 1;
-    uint32_t gpsa_ack_mask12 : 1;
-    uint32_t gpsa_ack_mask11 : 1;
-    uint32_t gpsa_ack_mask10 : 1;
-    uint32_t gpsa_ack_mask9 : 1;
-    uint32_t gpsa_ack_mask8 : 1;
-    uint32_t gpsa_ack_mask7 : 1;
-    uint32_t gpsa_ack_mask6 : 1;
-    uint32_t gpsa_ack_mask5 : 1;
-    uint32_t gpsa_ack_mask4 : 1;
-    uint32_t gpsa_ack_mask3 : 1;
-    uint32_t gpsa_ack_mask2 : 1;
-    uint32_t gpsa_ack_mask1 : 1;
-    uint32_t gpsa_ack_mask0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_gpsa_ack_collection_mask_reg_t;
-
-
-
-typedef union pmc_pore_scratch_reg0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porscr_scratch0 : 32;
-#else
-    uint32_t porscr_scratch0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_scratch_reg0_t;
-
-
-
-typedef union pmc_pore_scratch_reg1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t porscr_scratch1 : 32;
-#else
-    uint32_t porscr_scratch1 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pore_scratch_reg1_t;
-
-
-
-typedef union pmc_deep_idle_exit_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deep_exit_pending_and_masked_0 : 1;
-    uint32_t deep_exit_pending_and_masked_1 : 1;
-    uint32_t deep_exit_pending_and_masked_2 : 1;
-    uint32_t deep_exit_pending_and_masked_3 : 1;
-    uint32_t deep_exit_pending_and_masked_4 : 1;
-    uint32_t deep_exit_pending_and_masked_5 : 1;
-    uint32_t deep_exit_pending_and_masked_6 : 1;
-    uint32_t deep_exit_pending_and_masked_7 : 1;
-    uint32_t deep_exit_pending_and_masked_8 : 1;
-    uint32_t deep_exit_pending_and_masked_9 : 1;
-    uint32_t deep_exit_pending_and_masked_10 : 1;
-    uint32_t deep_exit_pending_and_masked_11 : 1;
-    uint32_t deep_exit_pending_and_masked_12 : 1;
-    uint32_t deep_exit_pending_and_masked_13 : 1;
-    uint32_t deep_exit_pending_and_masked_14 : 1;
-    uint32_t deep_exit_pending_and_masked_15 : 1;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t deep_exit_pending_and_masked_15 : 1;
-    uint32_t deep_exit_pending_and_masked_14 : 1;
-    uint32_t deep_exit_pending_and_masked_13 : 1;
-    uint32_t deep_exit_pending_and_masked_12 : 1;
-    uint32_t deep_exit_pending_and_masked_11 : 1;
-    uint32_t deep_exit_pending_and_masked_10 : 1;
-    uint32_t deep_exit_pending_and_masked_9 : 1;
-    uint32_t deep_exit_pending_and_masked_8 : 1;
-    uint32_t deep_exit_pending_and_masked_7 : 1;
-    uint32_t deep_exit_pending_and_masked_6 : 1;
-    uint32_t deep_exit_pending_and_masked_5 : 1;
-    uint32_t deep_exit_pending_and_masked_4 : 1;
-    uint32_t deep_exit_pending_and_masked_3 : 1;
-    uint32_t deep_exit_pending_and_masked_2 : 1;
-    uint32_t deep_exit_pending_and_masked_1 : 1;
-    uint32_t deep_exit_pending_and_masked_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_deep_idle_exit_reg_t;
-
-
-
-typedef union pmc_deep_status_reg {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t deep_idle_state_core0 : 1;
-    uint32_t deep_idle_state_core1 : 1;
-    uint32_t deep_idle_state_core2 : 1;
-    uint32_t deep_idle_state_core3 : 1;
-    uint32_t deep_idle_state_core4 : 1;
-    uint32_t deep_idle_state_core5 : 1;
-    uint32_t deep_idle_state_core6 : 1;
-    uint32_t deep_idle_state_core7 : 1;
-    uint32_t deep_idle_state_core8 : 1;
-    uint32_t deep_idle_state_core9 : 1;
-    uint32_t deep_idle_state_core10 : 1;
-    uint32_t deep_idle_state_core11 : 1;
-    uint32_t deep_idle_state_core12 : 1;
-    uint32_t deep_idle_state_core13 : 1;
-    uint32_t deep_idle_state_core14 : 1;
-    uint32_t deep_idle_state_core15 : 1;
-    uint32_t winkle_state_core0 : 1;
-    uint32_t winkle_state_core1 : 1;
-    uint32_t winkle_state_core2 : 1;
-    uint32_t winkle_state_core3 : 1;
-    uint32_t winkle_state_core4 : 1;
-    uint32_t winkle_state_core5 : 1;
-    uint32_t winkle_state_core6 : 1;
-    uint32_t winkle_state_core7 : 1;
-    uint32_t winkle_state_core8 : 1;
-    uint32_t winkle_state_core9 : 1;
-    uint32_t winkle_state_core10 : 1;
-    uint32_t winkle_state_core11 : 1;
-    uint32_t winkle_state_core12 : 1;
-    uint32_t winkle_state_core13 : 1;
-    uint32_t winkle_state_core14 : 1;
-    uint32_t winkle_state_core15 : 1;
-#else
-    uint32_t winkle_state_core15 : 1;
-    uint32_t winkle_state_core14 : 1;
-    uint32_t winkle_state_core13 : 1;
-    uint32_t winkle_state_core12 : 1;
-    uint32_t winkle_state_core11 : 1;
-    uint32_t winkle_state_core10 : 1;
-    uint32_t winkle_state_core9 : 1;
-    uint32_t winkle_state_core8 : 1;
-    uint32_t winkle_state_core7 : 1;
-    uint32_t winkle_state_core6 : 1;
-    uint32_t winkle_state_core5 : 1;
-    uint32_t winkle_state_core4 : 1;
-    uint32_t winkle_state_core3 : 1;
-    uint32_t winkle_state_core2 : 1;
-    uint32_t winkle_state_core1 : 1;
-    uint32_t winkle_state_core0 : 1;
-    uint32_t deep_idle_state_core15 : 1;
-    uint32_t deep_idle_state_core14 : 1;
-    uint32_t deep_idle_state_core13 : 1;
-    uint32_t deep_idle_state_core12 : 1;
-    uint32_t deep_idle_state_core11 : 1;
-    uint32_t deep_idle_state_core10 : 1;
-    uint32_t deep_idle_state_core9 : 1;
-    uint32_t deep_idle_state_core8 : 1;
-    uint32_t deep_idle_state_core7 : 1;
-    uint32_t deep_idle_state_core6 : 1;
-    uint32_t deep_idle_state_core5 : 1;
-    uint32_t deep_idle_state_core4 : 1;
-    uint32_t deep_idle_state_core3 : 1;
-    uint32_t deep_idle_state_core2 : 1;
-    uint32_t deep_idle_state_core1 : 1;
-    uint32_t deep_idle_state_core0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_deep_status_reg_t;
-
-
-
-typedef union pmc_ba_pore_exe_trigger_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_ba_pore_exe_trigger_reg_t;
-
-
-
-typedef union pmc_pcbs_gaps_brdcast_addr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t value : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t value : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_pcbs_gaps_brdcast_addr_t;
-
-
-
-typedef union pmc_lfir_err_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t spare_fir : 10;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 10;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_reg_t;
-
-
-
-typedef union pmc_lfir_err_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t spare_fir : 10;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 10;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_reg_and_t;
-
-
-
-typedef union pmc_lfir_err_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t spare_fir : 10;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err_dup : 1;
-    uint64_t spare_fir : 10;
-    uint64_t lfir_if_comp_parity_error : 1;
-    uint64_t lfir_oci_slave_err : 1;
-    uint64_t lfir_o2p_fsm_err : 1;
-    uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_majority_detected_a_minority : 1;
-    uint64_t lfir_o2s_fsm_err : 1;
-    uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
-    uint64_t lfir_o2s_retry_timeout : 1;
-    uint64_t lfir_o2s_crc_error2 : 1;
-    uint64_t lfir_o2s_crc_error1 : 1;
-    uint64_t lfir_o2s_crc_error0 : 1;
-    uint64_t lfir_spivid_majority_detected_a_minority : 1;
-    uint64_t lfir_spivid_fsm_err : 1;
-    uint64_t lfir_spivid_retry_timeout : 1;
-    uint64_t lfir_spivid_crc_error2 : 1;
-    uint64_t lfir_spivid_crc_error1 : 1;
-    uint64_t lfir_spivid_crc_error0 : 1;
-    uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
-    uint64_t lfir_int_comp_parity_err : 1;
-    uint64_t lfir_idle_internal_err : 1;
-    uint64_t lfir_idle_oci_master_write_timeout_err : 1;
-    uint64_t lfir_idle_poresw_timeout_err : 1;
-    uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
-    uint64_t lfir_idle_poresw_status_value_err : 1;
-    uint64_t lfir_idle_poresw_status_rc_err : 1;
-    uint64_t lfir_idle_poresw_fatal_err : 1;
-    uint64_t lfir_ms_comp_parity_err : 1;
-    uint64_t lfir_pstate_ms_fsm_err : 1;
-    uint64_t lfir_pstate_interchip_errorframe_err : 1;
-    uint64_t lfir_pstate_interchip_ue_err : 1;
-    uint64_t lfir_pstate_oci_master_to_err : 1;
-    uint64_t lfir_pstate_pib_master_offline_err : 1;
-    uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
-    uint64_t lfir_pstate_gack_to_err : 1;
-    uint64_t lfir_pstate_gpst_checkbyte_err : 1;
-    uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
-    uint64_t lfir_pstate_oci_master_rderr : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_reg_or_t;
-
-
-
-typedef union pmc_lfir_err_mask_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_mask_0 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_mask_reg_t;
-
-
-
-typedef union pmc_lfir_err_mask_reg_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_mask_0 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_mask_reg_and_t;
-
-
-
-typedef union pmc_lfir_err_mask_reg_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_mask_0 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_mask1_48 : 1;
-    uint64_t pmc_lfir_mask1_47 : 1;
-    uint64_t pmc_lfir_mask1_37_46 : 10;
-    uint64_t pmc_lfir_mask_36 : 1;
-    uint64_t pmc_lfir_mask_35 : 1;
-    uint64_t pmc_lfir_mask_34 : 1;
-    uint64_t pmc_lfir_mask_33 : 1;
-    uint64_t pmc_lfir_mask_32 : 1;
-    uint64_t pmc_lfir_mask_31 : 1;
-    uint64_t pmc_lfir_mask_30 : 1;
-    uint64_t pmc_lfir_mask_29 : 1;
-    uint64_t pmc_lfir_mask_28 : 1;
-    uint64_t pmc_lfir_mask_27 : 1;
-    uint64_t pmc_lfir_mask_26 : 1;
-    uint64_t pmc_lfir_mask_25 : 1;
-    uint64_t pmc_lfir_mask_24 : 1;
-    uint64_t pmc_lfir_mask_23 : 1;
-    uint64_t pmc_lfir_mask_22 : 1;
-    uint64_t pmc_lfir_mask_21 : 1;
-    uint64_t pmc_lfir_mask_20 : 1;
-    uint64_t pmc_lfir_mask_19 : 1;
-    uint64_t pmc_lfir_mask_18 : 1;
-    uint64_t pmc_lfir_mask_17 : 1;
-    uint64_t pmc_lfir_mask_16 : 1;
-    uint64_t pmc_lfir_mask_15 : 1;
-    uint64_t pmc_lfir_mask_14 : 1;
-    uint64_t pmc_lfir_mask_13 : 1;
-    uint64_t pmc_lfir_mask_12 : 1;
-    uint64_t pmc_lfir_mask_11 : 1;
-    uint64_t pmc_lfir_mask_10 : 1;
-    uint64_t pmc_lfir_mask_9 : 1;
-    uint64_t pmc_lfir_mask_8 : 1;
-    uint64_t pmc_lfir_mask_7 : 1;
-    uint64_t pmc_lfir_mask_6 : 1;
-    uint64_t pmc_lfir_mask_5 : 1;
-    uint64_t pmc_lfir_mask_4 : 1;
-    uint64_t pmc_lfir_mask_3 : 1;
-    uint64_t pmc_lfir_mask_2 : 1;
-    uint64_t pmc_lfir_mask_1 : 1;
-    uint64_t pmc_lfir_mask_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_err_mask_reg_or_t;
-
-
-
-typedef union pmc_lfir_action0_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_action0_0 : 1;
-    uint64_t pmc_lfir_action0_1 : 1;
-    uint64_t pmc_lfir_action0_2 : 1;
-    uint64_t pmc_lfir_action0_3 : 1;
-    uint64_t pmc_lfir_action0_4 : 1;
-    uint64_t pmc_lfir_action0_5 : 1;
-    uint64_t pmc_lfir_action0_6 : 1;
-    uint64_t pmc_lfir_action0_7 : 1;
-    uint64_t pmc_lfir_action0_8 : 1;
-    uint64_t pmc_lfir_action0_9 : 1;
-    uint64_t pmc_lfir_action0_10 : 1;
-    uint64_t pmc_lfir_action0_11 : 1;
-    uint64_t pmc_lfir_action0_12 : 1;
-    uint64_t pmc_lfir_action0_13 : 1;
-    uint64_t pmc_lfir_action0_14 : 1;
-    uint64_t pmc_lfir_action0_15 : 1;
-    uint64_t pmc_lfir_action0_16 : 1;
-    uint64_t pmc_lfir_action0_17 : 1;
-    uint64_t pmc_lfir_action0_18 : 1;
-    uint64_t pmc_lfir_action0_19 : 1;
-    uint64_t pmc_lfir_action0_20 : 1;
-    uint64_t pmc_lfir_action0_21 : 1;
-    uint64_t pmc_lfir_action0_22 : 1;
-    uint64_t pmc_lfir_action0_23 : 1;
-    uint64_t pmc_lfir_action0_24 : 1;
-    uint64_t pmc_lfir_action0_25 : 1;
-    uint64_t pmc_lfir_action0_26 : 1;
-    uint64_t pmc_lfir_action0_27 : 1;
-    uint64_t pmc_lfir_action0_28 : 1;
-    uint64_t pmc_lfir_action0_29 : 1;
-    uint64_t pmc_lfir_action0_30 : 1;
-    uint64_t pmc_lfir_action0_31 : 1;
-    uint64_t pmc_lfir_action0_32 : 1;
-    uint64_t pmc_lfir_action0_33 : 1;
-    uint64_t pmc_lfir_action0_34 : 1;
-    uint64_t pmc_lfir_action0_35 : 1;
-    uint64_t pmc_lfir_action0_36 : 1;
-    uint64_t pmc_lfir_action0_37_46 : 10;
-    uint64_t pmc_lfir_action0_47 : 1;
-    uint64_t pmc_lfir_action0_48 : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_action0_48 : 1;
-    uint64_t pmc_lfir_action0_47 : 1;
-    uint64_t pmc_lfir_action0_37_46 : 10;
-    uint64_t pmc_lfir_action0_36 : 1;
-    uint64_t pmc_lfir_action0_35 : 1;
-    uint64_t pmc_lfir_action0_34 : 1;
-    uint64_t pmc_lfir_action0_33 : 1;
-    uint64_t pmc_lfir_action0_32 : 1;
-    uint64_t pmc_lfir_action0_31 : 1;
-    uint64_t pmc_lfir_action0_30 : 1;
-    uint64_t pmc_lfir_action0_29 : 1;
-    uint64_t pmc_lfir_action0_28 : 1;
-    uint64_t pmc_lfir_action0_27 : 1;
-    uint64_t pmc_lfir_action0_26 : 1;
-    uint64_t pmc_lfir_action0_25 : 1;
-    uint64_t pmc_lfir_action0_24 : 1;
-    uint64_t pmc_lfir_action0_23 : 1;
-    uint64_t pmc_lfir_action0_22 : 1;
-    uint64_t pmc_lfir_action0_21 : 1;
-    uint64_t pmc_lfir_action0_20 : 1;
-    uint64_t pmc_lfir_action0_19 : 1;
-    uint64_t pmc_lfir_action0_18 : 1;
-    uint64_t pmc_lfir_action0_17 : 1;
-    uint64_t pmc_lfir_action0_16 : 1;
-    uint64_t pmc_lfir_action0_15 : 1;
-    uint64_t pmc_lfir_action0_14 : 1;
-    uint64_t pmc_lfir_action0_13 : 1;
-    uint64_t pmc_lfir_action0_12 : 1;
-    uint64_t pmc_lfir_action0_11 : 1;
-    uint64_t pmc_lfir_action0_10 : 1;
-    uint64_t pmc_lfir_action0_9 : 1;
-    uint64_t pmc_lfir_action0_8 : 1;
-    uint64_t pmc_lfir_action0_7 : 1;
-    uint64_t pmc_lfir_action0_6 : 1;
-    uint64_t pmc_lfir_action0_5 : 1;
-    uint64_t pmc_lfir_action0_4 : 1;
-    uint64_t pmc_lfir_action0_3 : 1;
-    uint64_t pmc_lfir_action0_2 : 1;
-    uint64_t pmc_lfir_action0_1 : 1;
-    uint64_t pmc_lfir_action0_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_action0_reg_t;
-
-
-
-typedef union pmc_lfir_action1_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_action1_0 : 1;
-    uint64_t pmc_lfir_action1_1 : 1;
-    uint64_t pmc_lfir_action1_2 : 1;
-    uint64_t pmc_lfir_action1_3 : 1;
-    uint64_t pmc_lfir_action1_4 : 1;
-    uint64_t pmc_lfir_action1_5 : 1;
-    uint64_t pmc_lfir_action1_6 : 1;
-    uint64_t pmc_lfir_action1_7 : 1;
-    uint64_t pmc_lfir_action1_8 : 1;
-    uint64_t pmc_lfir_action1_9 : 1;
-    uint64_t pmc_lfir_action1_10 : 1;
-    uint64_t pmc_lfir_action1_11 : 1;
-    uint64_t pmc_lfir_action1_12 : 1;
-    uint64_t pmc_lfir_action1_13 : 1;
-    uint64_t pmc_lfir_action1_14 : 1;
-    uint64_t pmc_lfir_action1_15 : 1;
-    uint64_t pmc_lfir_action1_16 : 1;
-    uint64_t pmc_lfir_action1_17 : 1;
-    uint64_t pmc_lfir_action1_18 : 1;
-    uint64_t pmc_lfir_action1_19 : 1;
-    uint64_t pmc_lfir_action1_20 : 1;
-    uint64_t pmc_lfir_action1_21 : 1;
-    uint64_t pmc_lfir_action1_22 : 1;
-    uint64_t pmc_lfir_action1_23 : 1;
-    uint64_t pmc_lfir_action1_24 : 1;
-    uint64_t pmc_lfir_action1_25 : 1;
-    uint64_t pmc_lfir_action1_26 : 1;
-    uint64_t pmc_lfir_action1_27 : 1;
-    uint64_t pmc_lfir_action1_28 : 1;
-    uint64_t pmc_lfir_action1_29 : 1;
-    uint64_t pmc_lfir_action1_30 : 1;
-    uint64_t pmc_lfir_action1_31 : 1;
-    uint64_t pmc_lfir_action1_32 : 1;
-    uint64_t pmc_lfir_action1_33 : 1;
-    uint64_t pmc_lfir_action1_34 : 1;
-    uint64_t pmc_lfir_action1_35 : 1;
-    uint64_t pmc_lfir_action1_36 : 1;
-    uint64_t pmc_lfir_action1_37_46 : 10;
-    uint64_t pmc_lfir_action1_47 : 1;
-    uint64_t pmc_lfir_action1_48 : 1;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_action1_48 : 1;
-    uint64_t pmc_lfir_action1_47 : 1;
-    uint64_t pmc_lfir_action1_37_46 : 10;
-    uint64_t pmc_lfir_action1_36 : 1;
-    uint64_t pmc_lfir_action1_35 : 1;
-    uint64_t pmc_lfir_action1_34 : 1;
-    uint64_t pmc_lfir_action1_33 : 1;
-    uint64_t pmc_lfir_action1_32 : 1;
-    uint64_t pmc_lfir_action1_31 : 1;
-    uint64_t pmc_lfir_action1_30 : 1;
-    uint64_t pmc_lfir_action1_29 : 1;
-    uint64_t pmc_lfir_action1_28 : 1;
-    uint64_t pmc_lfir_action1_27 : 1;
-    uint64_t pmc_lfir_action1_26 : 1;
-    uint64_t pmc_lfir_action1_25 : 1;
-    uint64_t pmc_lfir_action1_24 : 1;
-    uint64_t pmc_lfir_action1_23 : 1;
-    uint64_t pmc_lfir_action1_22 : 1;
-    uint64_t pmc_lfir_action1_21 : 1;
-    uint64_t pmc_lfir_action1_20 : 1;
-    uint64_t pmc_lfir_action1_19 : 1;
-    uint64_t pmc_lfir_action1_18 : 1;
-    uint64_t pmc_lfir_action1_17 : 1;
-    uint64_t pmc_lfir_action1_16 : 1;
-    uint64_t pmc_lfir_action1_15 : 1;
-    uint64_t pmc_lfir_action1_14 : 1;
-    uint64_t pmc_lfir_action1_13 : 1;
-    uint64_t pmc_lfir_action1_12 : 1;
-    uint64_t pmc_lfir_action1_11 : 1;
-    uint64_t pmc_lfir_action1_10 : 1;
-    uint64_t pmc_lfir_action1_9 : 1;
-    uint64_t pmc_lfir_action1_8 : 1;
-    uint64_t pmc_lfir_action1_7 : 1;
-    uint64_t pmc_lfir_action1_6 : 1;
-    uint64_t pmc_lfir_action1_5 : 1;
-    uint64_t pmc_lfir_action1_4 : 1;
-    uint64_t pmc_lfir_action1_3 : 1;
-    uint64_t pmc_lfir_action1_2 : 1;
-    uint64_t pmc_lfir_action1_1 : 1;
-    uint64_t pmc_lfir_action1_0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_action1_reg_t;
-
-
-
-typedef union pmc_lfir_wof_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pmc_lfir_wof : 49;
-    uint64_t _reserved0 : 15;
-#else
-    uint64_t _reserved0 : 15;
-    uint64_t pmc_lfir_wof : 49;
-#endif // _BIG_ENDIAN
-    } fields;
-} pmc_lfir_wof_reg_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PMC_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pmc_register_addresses.h b/src/ssx/pgp/registers/pmc_register_addresses.h
deleted file mode 100755
index 96f8dac..0000000
--- a/src/ssx/pgp/registers/pmc_register_addresses.h
+++ /dev/null
@@ -1,116 +0,0 @@
-#ifndef __PMC_REGISTER_ADDRESSES_H__
-#define __PMC_REGISTER_ADDRESSES_H__
-
-// $Id: pmc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pmc_register_addresses.h
-/// \brief Symbolic addresses for the PMC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PMC_OCI_BASE 0x40010000
-#define PMC_MODE_REG 0x40010000
-#define PMC_HARDWARE_AUCTION_PSTATE_REG 0x40010008
-#define PMC_PSTATE_MONITOR_AND_CTRL_REG 0x40010010
-#define PMC_RAIL_BOUNDS_REGISTER 0x40010018
-#define PMC_GLOBAL_PSTATE_BOUNDS_REG 0x40010020
-#define PMC_PARAMETER_REG0 0x40010028
-#define PMC_PARAMETER_REG1 0x40010030
-#define PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010038
-#define PMC_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010040
-#define PMC_STATUS_REG 0x40010048
-#define PMC_PHASE_ENABLE_REG 0x40010050
-#define PMC_UNDERVOLTING_REG 0x40010060
-#define PMC_CORE_DECONFIGURATION_REG 0x40010068
-#define PMC_INTCHP_CTRL_REG1 0x40010080
-#define PMC_INTCHP_CTRL_REG2 0x40010088
-#define PMC_INTCHP_CTRL_REG4 0x40010090
-#define PMC_INTCHP_STATUS_REG 0x40010098
-#define PMC_INTCHP_COMMAND_REG 0x400100a0
-#define PMC_INTCHP_MSG_WDATA 0x400100a8
-#define PMC_INTCHP_MSG_RDATA 0x400100b0
-#define PMC_INTCHP_PSTATE_REG 0x400100b8
-#define PMC_INTCHP_GLOBACK_REG 0x400100c0
-#define PMC_FSMSTATE_STATUS_REG 0x40010100
-#define PMC_TRACE_MODE_REG 0x40010180
-#define PMC_SPIV_CTRL_REG0A 0x40010200
-#define PMC_SPIV_CTRL_REG0B 0x40010208
-#define PMC_SPIV_CTRL_REG1 0x40010210
-#define PMC_SPIV_CTRL_REG2 0x40010218
-#define PMC_SPIV_CTRL_REG3 0x40010220
-#define PMC_SPIV_CTRL_REG4 0x40010228
-#define PMC_SPIV_STATUS_REG 0x40010230
-#define PMC_SPIV_COMMAND_REG 0x40010238
-#define PMC_O2S_CTRL_REG0A 0x40010280
-#define PMC_O2S_CTRL_REG0B 0x40010288
-#define PMC_O2S_CTRL_REG1 0x40010290
-#define PMC_O2S_CTRL_REG2 0x40010298
-#define PMC_O2S_CTRL_REG4 0x400102a8
-#define PMC_O2S_STATUS_REG 0x400102b0
-#define PMC_O2S_COMMAND_REG 0x400102b8
-#define PMC_O2S_WDATA_REG 0x400102c0
-#define PMC_O2S_RDATA_REG 0x400102c8
-#define PMC_O2P_ADDR_REG 0x40010300
-#define PMC_O2P_CTRL_STATUS_REG 0x40010308
-#define PMC_O2P_SEND_DATA_HI_REG 0x40010310
-#define PMC_O2P_SEND_DATA_LO_REG 0x40010318
-#define PMC_O2P_RECV_DATA_HI_REG 0x40010320
-#define PMC_O2P_RECV_DATA_LO_REG 0x40010328
-#define PMC_OCC_HEARTBEAT_REG 0x40010330
-#define PMC_ERROR_INT_MASK_HI_REG 0x40010338
-#define PMC_ERROR_INT_MASK_LO_REG 0x40010340
-#define PMC_IDLE_SUSPEND_MASK_REG 0x40010348
-#define PMC_PEND_IDLE_REQ_REG0 0x40010400
-#define PMC_PEND_IDLE_REQ_REG1 0x40010408
-#define PMC_PEND_IDLE_REQ_REG2 0x40010410
-#define PMC_PEND_IDLE_REQ_REG3 0x40010418
-#define PMC_SLEEP_INT_REQ_VEC_REG0 0x40010420
-#define PMC_SLEEP_INT_REQ_VEC_REG1 0x40010428
-#define PMC_SLEEP_INT_REQ_VEC_REG2 0x40010430
-#define PMC_SLEEP_INT_REQ_VEC_REG3 0x40010438
-#define PMC_WINKLE_INT_REQ_VEC_REG0 0x40010440
-#define PMC_WINKLE_INT_REQ_VEC_REG1 0x40010448
-#define PMC_WINKLE_INT_REQ_VEC_REG2 0x40010450
-#define PMC_WINKLE_INT_REQ_VEC_REG3 0x40010458
-#define PMC_NAP_INT_REQ_VEC_REG0 0x40010460
-#define PMC_NAP_INT_REQ_VEC_REG1 0x40010468
-#define PMC_PORE_REQ_REG0 0x40010470
-#define PMC_PORE_REQ_REG1 0x40010478
-#define PMC_PORE_REQ_STAT_REG 0x40010480
-#define PMC_PORE_REQ_TOUT_TH_REG 0x40010488
-#define PMC_DEEP_EXIT_MASK_REG 0x40010490
-#define PMC_DEEP_EXIT_MASK_REG_AND 0x40010500
-#define PMC_DEEP_EXIT_MASK_REG_OR 0x40010508
-#define PMC_CORE_PSTATE_REG0 0x400104a0
-#define PMC_CORE_PSTATE_REG1 0x400104a8
-#define PMC_CORE_PSTATE_REG2 0x400104b0
-#define PMC_CORE_PSTATE_REG3 0x400104b8
-#define PMC_CORE_POWER_DONATION_REG 0x400104c0
-#define PMC_PMAX_SYNC_COLLECTION_REG 0x400104c8
-#define PMC_PMAX_SYNC_COLLECTION_MASK_REG 0x400104d0
-#define PMC_GPSA_ACK_COLLECTION_REG 0x400104d8
-#define PMC_GPSA_ACK_COLLECTION_MASK_REG 0x400104e0
-#define PMC_PORE_SCRATCH_REG0 0x400104e8
-#define PMC_PORE_SCRATCH_REG1 0x400104f0
-#define PMC_DEEP_IDLE_EXIT_REG 0x400104f8
-#define PMC_DEEP_STATUS_REG 0x40010510
-#define PMC_PIB_BASE 0x01010840
-#define PMC_LFIR_ERR_REG 0x01010840
-#define PMC_LFIR_ERR_REG_AND 0x01010841
-#define PMC_LFIR_ERR_REG_OR 0x01010842
-#define PMC_LFIR_ERR_MASK_REG 0x01010843
-#define PMC_LFIR_ERR_MASK_REG_AND 0x01010844
-#define PMC_LFIR_ERR_MASK_REG_OR 0x01010845
-#define PMC_LFIR_ACTION0_REG 0x01010846
-#define PMC_LFIR_ACTION1_REG 0x01010847
-#define PMC_LFIR_WOF_REG 0x01010848
-
-#endif // __PMC_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/pore_firmware_registers.h b/src/ssx/pgp/registers/pore_firmware_registers.h
deleted file mode 100755
index 76127d9..0000000
--- a/src/ssx/pgp/registers/pore_firmware_registers.h
+++ /dev/null
@@ -1,906 +0,0 @@
-#ifndef __PORE_FIRMWARE_REGISTERS_H__
-#define __PORE_FIRMWARE_REGISTERS_H__
-
-// $Id: pore_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pore_firmware_registers.h
-/// \brief C register structs for the PORE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pore_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cur_state : 8;
-    uint64_t freeze_action : 1;
-    uint64_t interrupt_pending : 1;
-    uint64_t spare : 2;
-    uint64_t stack_pointer : 4;
-    uint64_t pc : 48;
-#else
-    uint64_t pc : 48;
-    uint64_t stack_pointer : 4;
-    uint64_t spare : 2;
-    uint64_t interrupt_pending : 1;
-    uint64_t freeze_action : 1;
-    uint64_t cur_state : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_status_t;
-
-#endif // __ASSEMBLER__
-#define PORE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000)
-#define PORE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000)
-#define PORE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000)
-#define PORE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_control {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t start_stop : 1;
-    uint64_t continue_step : 1;
-    uint64_t skip : 1;
-    uint64_t set_pc : 1;
-    uint64_t set_tp_scan_clk : 3;
-    uint64_t lock_exe_trig : 1;
-    uint64_t freeze_mask : 1;
-    uint64_t check_parity : 1;
-    uint64_t prv_parity : 1;
-    uint64_t trap_enable : 1;
-    uint64_t narrow_mode_trace : 1;
-    uint64_t interruptible : 1;
-    uint64_t pore_done_override : 1;
-    uint64_t interruptible_en : 1;
-    uint64_t pc_brk_pt : 48;
-#else
-    uint64_t pc_brk_pt : 48;
-    uint64_t interruptible_en : 1;
-    uint64_t pore_done_override : 1;
-    uint64_t interruptible : 1;
-    uint64_t narrow_mode_trace : 1;
-    uint64_t trap_enable : 1;
-    uint64_t prv_parity : 1;
-    uint64_t check_parity : 1;
-    uint64_t freeze_mask : 1;
-    uint64_t lock_exe_trig : 1;
-    uint64_t set_tp_scan_clk : 3;
-    uint64_t set_pc : 1;
-    uint64_t skip : 1;
-    uint64_t continue_step : 1;
-    uint64_t start_stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_control_t;
-
-#endif // __ASSEMBLER__
-#define PORE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PORE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PORE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PORE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PORE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000)
-#define PORE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PORE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PORE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PORE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PORE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PORE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PORE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PORE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_reset {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t fn_reset : 1;
-    uint64_t oci_reset : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t oci_reset : 1;
-    uint64_t fn_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_reset_t;
-
-
-
-typedef union pore_error_mask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_err_handler0 : 1;
-    uint64_t enable_err_handler1 : 1;
-    uint64_t enable_err_handler2 : 1;
-    uint64_t enable_err_handler3 : 1;
-    uint64_t enable_err_handler4 : 1;
-    uint64_t enable_err_output0 : 1;
-    uint64_t enable_err_output1 : 1;
-    uint64_t enable_err_output2 : 1;
-    uint64_t enable_err_output3 : 1;
-    uint64_t enable_err_output4 : 1;
-    uint64_t enable_fatal_err_output0 : 1;
-    uint64_t enable_fatal_err_output1 : 1;
-    uint64_t enable_fatal_err_output2 : 1;
-    uint64_t enable_fatal_err_output3 : 1;
-    uint64_t enable_fatal_err_output4 : 1;
-    uint64_t stop_exe_on_error0 : 1;
-    uint64_t stop_exe_on_error1 : 1;
-    uint64_t stop_exe_on_error2 : 1;
-    uint64_t stop_exe_on_error3 : 1;
-    uint64_t stop_exe_on_error4 : 1;
-    uint64_t gate_chiplet_offline_err : 1;
-    uint64_t i2c_bad_status_0 : 1;
-    uint64_t i2c_bad_status_1 : 1;
-    uint64_t i2c_bad_status_2 : 1;
-    uint64_t i2c_bad_status_3 : 1;
-    uint64_t group_parity_error_0 : 1;
-    uint64_t group_parity_error_1 : 1;
-    uint64_t group_parity_error_2 : 1;
-    uint64_t group_parity_error_3 : 1;
-    uint64_t group_parity_error_4 : 1;
-    uint64_t _reserved0 : 34;
-#else
-    uint64_t _reserved0 : 34;
-    uint64_t group_parity_error_4 : 1;
-    uint64_t group_parity_error_3 : 1;
-    uint64_t group_parity_error_2 : 1;
-    uint64_t group_parity_error_1 : 1;
-    uint64_t group_parity_error_0 : 1;
-    uint64_t i2c_bad_status_3 : 1;
-    uint64_t i2c_bad_status_2 : 1;
-    uint64_t i2c_bad_status_1 : 1;
-    uint64_t i2c_bad_status_0 : 1;
-    uint64_t gate_chiplet_offline_err : 1;
-    uint64_t stop_exe_on_error4 : 1;
-    uint64_t stop_exe_on_error3 : 1;
-    uint64_t stop_exe_on_error2 : 1;
-    uint64_t stop_exe_on_error1 : 1;
-    uint64_t stop_exe_on_error0 : 1;
-    uint64_t enable_fatal_err_output4 : 1;
-    uint64_t enable_fatal_err_output3 : 1;
-    uint64_t enable_fatal_err_output2 : 1;
-    uint64_t enable_fatal_err_output1 : 1;
-    uint64_t enable_fatal_err_output0 : 1;
-    uint64_t enable_err_output4 : 1;
-    uint64_t enable_err_output3 : 1;
-    uint64_t enable_err_output2 : 1;
-    uint64_t enable_err_output1 : 1;
-    uint64_t enable_err_output0 : 1;
-    uint64_t enable_err_handler4 : 1;
-    uint64_t enable_err_handler3 : 1;
-    uint64_t enable_err_handler2 : 1;
-    uint64_t enable_err_handler1 : 1;
-    uint64_t enable_err_handler0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_error_mask_t;
-
-#endif // __ASSEMBLER__
-#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define PORE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define PORE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define PORE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define PORE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define PORE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_prv_base_address0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 25;
-    uint64_t mc : 1;
-    uint64_t chiplet_id : 6;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t chiplet_id : 6;
-    uint64_t mc : 1;
-    uint64_t spare : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_prv_base_address0_t;
-
-
-
-typedef union pore_prv_base_address1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 25;
-    uint64_t mc : 1;
-    uint64_t chiplet_id : 6;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t chiplet_id : 6;
-    uint64_t mc : 1;
-    uint64_t spare : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_prv_base_address1_t;
-
-
-
-typedef union pore_oci_base_address0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 18;
-    uint64_t oci_mem_route : 14;
-    uint64_t oci_base_address : 32;
-#else
-    uint64_t oci_base_address : 32;
-    uint64_t oci_mem_route : 14;
-    uint64_t spare : 18;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_oci_base_address0_t;
-
-
-
-typedef union pore_oci_base_address1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 18;
-    uint64_t oci_mem_route : 14;
-    uint64_t oci_base_address : 32;
-#else
-    uint64_t oci_base_address : 32;
-    uint64_t oci_mem_route : 14;
-    uint64_t spare : 18;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_oci_base_address1_t;
-
-
-
-typedef union pore_table_base_addr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved : 16;
-    uint64_t memory_space : 16;
-    uint64_t table_base_address : 32;
-#else
-    uint64_t table_base_address : 32;
-    uint64_t memory_space : 16;
-    uint64_t reserved : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_table_base_addr_t;
-
-
-
-typedef union pore_exe_trigger {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved : 8;
-    uint64_t start_vector : 4;
-    uint64_t zeroes : 8;
-    uint64_t unused : 12;
-    uint64_t mc_chiplet_select_mask : 32;
-#else
-    uint64_t mc_chiplet_select_mask : 32;
-    uint64_t unused : 12;
-    uint64_t zeroes : 8;
-    uint64_t start_vector : 4;
-    uint64_t reserved : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_exe_trigger_t;
-
-
-
-typedef union pore_scratch0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t zeroes : 8;
-    uint64_t scratch0 : 24;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t scratch0 : 24;
-    uint64_t zeroes : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_scratch0_t;
-
-
-
-typedef union pore_scratch1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t scratch1 : 64;
-#else
-    uint64_t scratch1 : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_scratch1_t;
-
-
-
-typedef union pore_scratch2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t scratch2 : 64;
-#else
-    uint64_t scratch2 : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_scratch2_t;
-
-
-
-typedef union pore_ibuf_01 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ibuf0 : 32;
-    uint64_t ibuf1 : 32;
-#else
-    uint64_t ibuf1 : 32;
-    uint64_t ibuf0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_ibuf_01_t;
-
-
-
-typedef union pore_ibuf_2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ibuf2 : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t ibuf2 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_ibuf_2_t;
-
-
-
-typedef union pore_dbg0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t last_completed_address : 32;
-    uint64_t last_pib_parity_fail : 1;
-    uint64_t last_ret_code_prv : 3;
-    uint64_t i2c_bad_status0 : 1;
-    uint64_t i2c_bad_status1 : 1;
-    uint64_t i2c_bad_status2 : 1;
-    uint64_t i2c_bad_status3 : 1;
-    uint64_t group_parity_error0 : 1;
-    uint64_t group_parity_error1 : 1;
-    uint64_t group_parity_error2 : 1;
-    uint64_t group_parity_error3 : 1;
-    uint64_t group_parity_error4 : 1;
-    uint64_t interrupt_counter : 8;
-    uint64_t _reserved0 : 11;
-#else
-    uint64_t _reserved0 : 11;
-    uint64_t interrupt_counter : 8;
-    uint64_t group_parity_error4 : 1;
-    uint64_t group_parity_error3 : 1;
-    uint64_t group_parity_error2 : 1;
-    uint64_t group_parity_error1 : 1;
-    uint64_t group_parity_error0 : 1;
-    uint64_t i2c_bad_status3 : 1;
-    uint64_t i2c_bad_status2 : 1;
-    uint64_t i2c_bad_status1 : 1;
-    uint64_t i2c_bad_status0 : 1;
-    uint64_t last_ret_code_prv : 3;
-    uint64_t last_pib_parity_fail : 1;
-    uint64_t last_completed_address : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_dbg0_t;
-
-
-
-typedef union pore_dbg1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_last_access : 48;
-    uint64_t oci_master_rd_parity_err : 1;
-    uint64_t last_ret_code_oci : 3;
-    uint64_t bad_instr_parity : 1;
-    uint64_t invalid_instr_code : 1;
-    uint64_t pc_overflow_underrun : 1;
-    uint64_t bad_scan_crc : 1;
-    uint64_t pc_stack_ovflw_undrn_err : 1;
-    uint64_t instruction_fetch_error : 1;
-    uint64_t invalid_instruction_operand : 1;
-    uint64_t invalid_instruction_path : 1;
-    uint64_t invalid_start_vector : 1;
-    uint64_t fast_i2c_protocol_hang : 1;
-    uint64_t spare : 1;
-    uint64_t debug_regs_locked : 1;
-#else
-    uint64_t debug_regs_locked : 1;
-    uint64_t spare : 1;
-    uint64_t fast_i2c_protocol_hang : 1;
-    uint64_t invalid_start_vector : 1;
-    uint64_t invalid_instruction_path : 1;
-    uint64_t invalid_instruction_operand : 1;
-    uint64_t instruction_fetch_error : 1;
-    uint64_t pc_stack_ovflw_undrn_err : 1;
-    uint64_t bad_scan_crc : 1;
-    uint64_t pc_overflow_underrun : 1;
-    uint64_t invalid_instr_code : 1;
-    uint64_t bad_instr_parity : 1;
-    uint64_t last_ret_code_oci : 3;
-    uint64_t oci_master_rd_parity_err : 1;
-    uint64_t pc_last_access : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_dbg1_t;
-
-
-
-typedef union pore_pc_stack0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack0 : 48;
-    uint64_t _reserved0 : 11;
-    uint64_t set_new_stack_pointer : 1;
-    uint64_t new_stack_pointer : 4;
-#else
-    uint64_t new_stack_pointer : 4;
-    uint64_t set_new_stack_pointer : 1;
-    uint64_t _reserved0 : 11;
-    uint64_t pc_stack0 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_pc_stack0_t;
-
-
-
-typedef union pore_pc_stack1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack1 : 48;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t pc_stack1 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_pc_stack1_t;
-
-
-
-typedef union pore_pc_stack2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack2 : 48;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t pc_stack2 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_pc_stack2_t;
-
-
-
-typedef union pore_id_flags {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 32;
-    uint64_t pib_parity_fail : 1;
-    uint64_t pib_status : 3;
-    uint64_t oci_parity_fail : 1;
-    uint64_t oci_status : 3;
-    uint64_t reserved1 : 8;
-    uint64_t ugt : 1;
-    uint64_t ult : 1;
-    uint64_t sgt : 1;
-    uint64_t slt : 1;
-    uint64_t c : 1;
-    uint64_t o : 1;
-    uint64_t n : 1;
-    uint64_t z : 1;
-    uint64_t reserved2 : 4;
-    uint64_t ibuf_id : 4;
-#else
-    uint64_t ibuf_id : 4;
-    uint64_t reserved2 : 4;
-    uint64_t z : 1;
-    uint64_t n : 1;
-    uint64_t o : 1;
-    uint64_t c : 1;
-    uint64_t slt : 1;
-    uint64_t sgt : 1;
-    uint64_t ult : 1;
-    uint64_t ugt : 1;
-    uint64_t reserved1 : 8;
-    uint64_t oci_status : 3;
-    uint64_t oci_parity_fail : 1;
-    uint64_t pib_status : 3;
-    uint64_t pib_parity_fail : 1;
-    uint64_t reserved0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_id_flags_t;
-
-
-
-typedef union pore_data0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t data0 : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t data0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_data0_t;
-
-
-
-typedef union pore_memory_reloc {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 30;
-    uint64_t memory_reloc_region : 2;
-    uint64_t memory_reloc_base : 20;
-    uint64_t _reserved1 : 12;
-#else
-    uint64_t _reserved1 : 12;
-    uint64_t memory_reloc_base : 20;
-    uint64_t memory_reloc_region : 2;
-    uint64_t _reserved0 : 30;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_memory_reloc_t;
-
-
-
-typedef union pore_i2c_en_param {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t i2c_engine_identifier : 4;
-    uint64_t reserved0 : 1;
-    uint64_t i2c_engine_address_range : 3;
-    uint64_t reserved1 : 3;
-    uint64_t i2c_engine_port : 5;
-    uint64_t reserved2 : 1;
-    uint64_t i2c_engine_device_id : 7;
-    uint64_t reserved3 : 2;
-    uint64_t i2c_engine_speed : 2;
-    uint64_t i2c_poll_threshold : 4;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t i2c_poll_threshold : 4;
-    uint64_t i2c_engine_speed : 2;
-    uint64_t reserved3 : 2;
-    uint64_t i2c_engine_device_id : 7;
-    uint64_t reserved2 : 1;
-    uint64_t i2c_engine_port : 5;
-    uint64_t reserved1 : 3;
-    uint64_t i2c_engine_address_range : 3;
-    uint64_t reserved0 : 1;
-    uint64_t i2c_engine_identifier : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_i2c_en_param_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PORE_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/pore_register_addresses.h b/src/ssx/pgp/registers/pore_register_addresses.h
deleted file mode 100755
index 0fc769b..0000000
--- a/src/ssx/pgp/registers/pore_register_addresses.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef __PORE_REGISTER_ADDRESSES_H__
-#define __PORE_REGISTER_ADDRESSES_H__
-
-// $Id: pore_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file pore_register_addresses.h
-/// \brief Symbolic addresses for the PORE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PORE_GPE0_OCI_BASE 0x40000000
-#define PORE_GPE1_OCI_BASE 0x40000100
-#define PORE_SLW_OCI_BASE 0x40040000
-#define PORE_STATUS_OFFSET 0x00000000
-#define PORE_GPE0_STATUS 0x40000000
-#define PORE_GPE1_STATUS 0x40000100
-#define PORE_SLW_STATUS 0x40040000
-#define PORE_CONTROL_OFFSET 0x00000008
-#define PORE_GPE0_CONTROL 0x40000008
-#define PORE_GPE1_CONTROL 0x40000108
-#define PORE_SLW_CONTROL 0x40040008
-#define PORE_RESET_OFFSET 0x00000010
-#define PORE_GPE0_RESET 0x40000010
-#define PORE_GPE1_RESET 0x40000110
-#define PORE_SLW_RESET 0x40040010
-#define PORE_ERROR_MASK_OFFSET 0x00000018
-#define PORE_GPE0_ERROR_MASK 0x40000018
-#define PORE_GPE1_ERROR_MASK 0x40000118
-#define PORE_SLW_ERROR_MASK 0x40040018
-#define PORE_PRV_BASE_ADDRESS0_OFFSET 0x00000020
-#define PORE_GPE0_PRV_BASE_ADDRESS0 0x40000020
-#define PORE_GPE1_PRV_BASE_ADDRESS0 0x40000120
-#define PORE_SLW_PRV_BASE_ADDRESS0 0x40040020
-#define PORE_PRV_BASE_ADDRESS1_OFFSET 0x00000028
-#define PORE_GPE0_PRV_BASE_ADDRESS1 0x40000028
-#define PORE_GPE1_PRV_BASE_ADDRESS1 0x40000128
-#define PORE_SLW_PRV_BASE_ADDRESS1 0x40040028
-#define PORE_OCI_BASE_ADDRESS0_OFFSET 0x00000030
-#define PORE_GPE0_OCI_BASE_ADDRESS0 0x40000030
-#define PORE_GPE1_OCI_BASE_ADDRESS0 0x40000130
-#define PORE_SLW_OCI_BASE_ADDRESS0 0x40040030
-#define PORE_OCI_BASE_ADDRESS1_OFFSET 0x00000038
-#define PORE_GPE0_OCI_BASE_ADDRESS1 0x40000038
-#define PORE_GPE1_OCI_BASE_ADDRESS1 0x40000138
-#define PORE_SLW_OCI_BASE_ADDRESS1 0x40040038
-#define PORE_TABLE_BASE_ADDR_OFFSET 0x00000040
-#define PORE_GPE0_TABLE_BASE_ADDR 0x40000040
-#define PORE_GPE1_TABLE_BASE_ADDR 0x40000140
-#define PORE_SLW_TABLE_BASE_ADDR 0x40040040
-#define PORE_EXE_TRIGGER_OFFSET 0x00000048
-#define PORE_GPE0_EXE_TRIGGER 0x40000048
-#define PORE_GPE1_EXE_TRIGGER 0x40000148
-#define PORE_SLW_EXE_TRIGGER 0x40040048
-#define PORE_SCRATCH0_OFFSET 0x00000050
-#define PORE_GPE0_SCRATCH0 0x40000050
-#define PORE_GPE1_SCRATCH0 0x40000150
-#define PORE_SLW_SCRATCH0 0x40040050
-#define PORE_SCRATCH1_OFFSET 0x00000058
-#define PORE_GPE0_SCRATCH1 0x40000058
-#define PORE_GPE1_SCRATCH1 0x40000158
-#define PORE_SLW_SCRATCH1 0x40040058
-#define PORE_SCRATCH2_OFFSET 0x00000060
-#define PORE_GPE0_SCRATCH2 0x40000060
-#define PORE_GPE1_SCRATCH2 0x40000160
-#define PORE_SLW_SCRATCH2 0x40040060
-#define PORE_IBUF_01_OFFSET 0x00000068
-#define PORE_GPE0_IBUF_01 0x40000068
-#define PORE_GPE1_IBUF_01 0x40000168
-#define PORE_SLW_IBUF_01 0x40040068
-#define PORE_IBUF_2_OFFSET 0x00000070
-#define PORE_GPE0_IBUF_2 0x40000070
-#define PORE_GPE1_IBUF_2 0x40000170
-#define PORE_SLW_IBUF_2 0x40040070
-#define PORE_DBG0_OFFSET 0x00000078
-#define PORE_GPE0_DBG0 0x40000078
-#define PORE_GPE1_DBG0 0x40000178
-#define PORE_SLW_DBG0 0x40040078
-#define PORE_DBG1_OFFSET 0x00000080
-#define PORE_GPE0_DBG1 0x40000080
-#define PORE_GPE1_DBG1 0x40000180
-#define PORE_SLW_DBG1 0x40040080
-#define PORE_PC_STACK0_OFFSET 0x00000088
-#define PORE_GPE0_PC_STACK0 0x40000088
-#define PORE_GPE1_PC_STACK0 0x40000188
-#define PORE_SLW_PC_STACK0 0x40040088
-#define PORE_PC_STACK1_OFFSET 0x00000090
-#define PORE_GPE0_PC_STACK1 0x40000090
-#define PORE_GPE1_PC_STACK1 0x40000190
-#define PORE_SLW_PC_STACK1 0x40040090
-#define PORE_PC_STACK2_OFFSET 0x00000098
-#define PORE_GPE0_PC_STACK2 0x40000098
-#define PORE_GPE1_PC_STACK2 0x40000198
-#define PORE_SLW_PC_STACK2 0x40040098
-#define PORE_ID_FLAGS_OFFSET 0x000000a0
-#define PORE_GPE0_ID_FLAGS 0x400000a0
-#define PORE_GPE1_ID_FLAGS 0x400001a0
-#define PORE_SLW_ID_FLAGS 0x400400a0
-#define PORE_DATA0_OFFSET 0x000000a8
-#define PORE_GPE0_DATA0 0x400000a8
-#define PORE_GPE1_DATA0 0x400001a8
-#define PORE_SLW_DATA0 0x400400a8
-#define PORE_MEMORY_RELOC_OFFSET 0x000000b0
-#define PORE_GPE0_MEMORY_RELOC 0x400000b0
-#define PORE_GPE1_MEMORY_RELOC 0x400001b0
-#define PORE_SLW_MEMORY_RELOC 0x400400b0
-#define PORE_I2C_E0_PARAM_OFFSET 0x000000b8
-#define PORE_I2C_E1_PARAM_OFFSET 0x000000c0
-#define PORE_I2C_E2_PARAM_OFFSET 0x000000c8
-#define PORE_GPE0_I2C_EN_PARAM(n) (PORE_GPE0_I2C_E0_PARAM + ((PORE_GPE0_I2C_E1_PARAM - PORE_GPE0_I2C_E0_PARAM) * (n)))
-#define PORE_GPE1_I2C_EN_PARAM(n) (PORE_GPE1_I2C_E0_PARAM + ((PORE_GPE1_I2C_E1_PARAM - PORE_GPE1_I2C_E0_PARAM) * (n)))
-#define PORE_SLW_I2C_EN_PARAM(n) (PORE_SLW_I2C_E0_PARAM + ((PORE_SLW_I2C_E1_PARAM - PORE_SLW_I2C_E0_PARAM) * (n)))
-#define PORE_GPE0_I2C_E0_PARAM 0x400000b8
-#define PORE_GPE1_I2C_E0_PARAM 0x400001b8
-#define PORE_SLW_I2C_E0_PARAM 0x400400b8
-#define PORE_GPE0_I2C_E1_PARAM 0x400000c0
-#define PORE_GPE1_I2C_E1_PARAM 0x400001c0
-#define PORE_SLW_I2C_E1_PARAM 0x400400c0
-#define PORE_GPE0_I2C_E2_PARAM 0x400000c8
-#define PORE_GPE1_I2C_E2_PARAM 0x400001c8
-#define PORE_SLW_I2C_E2_PARAM 0x400400c8
-
-#endif // __PORE_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/sbe_firmware_registers.h b/src/ssx/pgp/registers/sbe_firmware_registers.h
deleted file mode 100644
index 8175c11..0000000
--- a/src/ssx/pgp/registers/sbe_firmware_registers.h
+++ /dev/null
@@ -1,906 +0,0 @@
-#ifndef __SBE_FIRMWARE_REGISTERS_H__
-#define __SBE_FIRMWARE_REGISTERS_H__
-
-// $Id: sbe_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sbe_firmware_registers.h
-/// \brief C register structs for the SBE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union pore_sbe_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cur_state : 8;
-    uint64_t freeze_action : 1;
-    uint64_t interrupt_pending : 1;
-    uint64_t spare : 2;
-    uint64_t stack_pointer : 4;
-    uint64_t pc : 48;
-#else
-    uint64_t pc : 48;
-    uint64_t stack_pointer : 4;
-    uint64_t spare : 2;
-    uint64_t interrupt_pending : 1;
-    uint64_t freeze_action : 1;
-    uint64_t cur_state : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_status_t;
-
-#endif // __ASSEMBLER__
-#define PORE_SBE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000)
-#define PORE_SBE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_SBE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_SBE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000)
-#define PORE_SBE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000)
-#define PORE_SBE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_sbe_control {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t start_stop : 1;
-    uint64_t continue_step : 1;
-    uint64_t skip : 1;
-    uint64_t set_pc : 1;
-    uint64_t set_tp_scan_clk : 3;
-    uint64_t lock_exe_trig : 1;
-    uint64_t freeze_mask : 1;
-    uint64_t check_parity : 1;
-    uint64_t prv_parity : 1;
-    uint64_t trap_enable : 1;
-    uint64_t narrow_mode_trace : 1;
-    uint64_t interruptible : 1;
-    uint64_t pore_done_override : 1;
-    uint64_t interruptible_en : 1;
-    uint64_t pc_brk_pt : 48;
-#else
-    uint64_t pc_brk_pt : 48;
-    uint64_t interruptible_en : 1;
-    uint64_t pore_done_override : 1;
-    uint64_t interruptible : 1;
-    uint64_t narrow_mode_trace : 1;
-    uint64_t trap_enable : 1;
-    uint64_t prv_parity : 1;
-    uint64_t check_parity : 1;
-    uint64_t freeze_mask : 1;
-    uint64_t lock_exe_trig : 1;
-    uint64_t set_tp_scan_clk : 3;
-    uint64_t set_pc : 1;
-    uint64_t skip : 1;
-    uint64_t continue_step : 1;
-    uint64_t start_stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_control_t;
-
-#endif // __ASSEMBLER__
-#define PORE_SBE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PORE_SBE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PORE_SBE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PORE_SBE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PORE_SBE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000)
-#define PORE_SBE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PORE_SBE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_SBE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_SBE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PORE_SBE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PORE_SBE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PORE_SBE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PORE_SBE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PORE_SBE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PORE_SBE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_sbe_reset {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t fn_reset : 1;
-    uint64_t oci_reset : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t oci_reset : 1;
-    uint64_t fn_reset : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_reset_t;
-
-
-
-typedef union pore_sbe_error_mask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t enable_err_handler0 : 1;
-    uint64_t enable_err_handler1 : 1;
-    uint64_t enable_err_handler2 : 1;
-    uint64_t enable_err_handler3 : 1;
-    uint64_t enable_err_handler4 : 1;
-    uint64_t enable_err_output0 : 1;
-    uint64_t enable_err_output1 : 1;
-    uint64_t enable_err_output2 : 1;
-    uint64_t enable_err_output3 : 1;
-    uint64_t enable_err_output4 : 1;
-    uint64_t enable_fatal_err_output0 : 1;
-    uint64_t enable_fatal_err_output1 : 1;
-    uint64_t enable_fatal_err_output2 : 1;
-    uint64_t enable_fatal_err_output3 : 1;
-    uint64_t enable_fatal_err_output4 : 1;
-    uint64_t stop_exe_on_error0 : 1;
-    uint64_t stop_exe_on_error1 : 1;
-    uint64_t stop_exe_on_error2 : 1;
-    uint64_t stop_exe_on_error3 : 1;
-    uint64_t stop_exe_on_error4 : 1;
-    uint64_t gate_chiplet_offline_err : 1;
-    uint64_t i2c_bad_status_0 : 1;
-    uint64_t i2c_bad_status_1 : 1;
-    uint64_t i2c_bad_status_2 : 1;
-    uint64_t i2c_bad_status_3 : 1;
-    uint64_t group_parity_error_0 : 1;
-    uint64_t group_parity_error_1 : 1;
-    uint64_t group_parity_error_2 : 1;
-    uint64_t group_parity_error_3 : 1;
-    uint64_t group_parity_error_4 : 1;
-    uint64_t _reserved0 : 34;
-#else
-    uint64_t _reserved0 : 34;
-    uint64_t group_parity_error_4 : 1;
-    uint64_t group_parity_error_3 : 1;
-    uint64_t group_parity_error_2 : 1;
-    uint64_t group_parity_error_1 : 1;
-    uint64_t group_parity_error_0 : 1;
-    uint64_t i2c_bad_status_3 : 1;
-    uint64_t i2c_bad_status_2 : 1;
-    uint64_t i2c_bad_status_1 : 1;
-    uint64_t i2c_bad_status_0 : 1;
-    uint64_t gate_chiplet_offline_err : 1;
-    uint64_t stop_exe_on_error4 : 1;
-    uint64_t stop_exe_on_error3 : 1;
-    uint64_t stop_exe_on_error2 : 1;
-    uint64_t stop_exe_on_error1 : 1;
-    uint64_t stop_exe_on_error0 : 1;
-    uint64_t enable_fatal_err_output4 : 1;
-    uint64_t enable_fatal_err_output3 : 1;
-    uint64_t enable_fatal_err_output2 : 1;
-    uint64_t enable_fatal_err_output1 : 1;
-    uint64_t enable_fatal_err_output0 : 1;
-    uint64_t enable_err_output4 : 1;
-    uint64_t enable_err_output3 : 1;
-    uint64_t enable_err_output2 : 1;
-    uint64_t enable_err_output1 : 1;
-    uint64_t enable_err_output0 : 1;
-    uint64_t enable_err_handler4 : 1;
-    uint64_t enable_err_handler3 : 1;
-    uint64_t enable_err_handler2 : 1;
-    uint64_t enable_err_handler1 : 1;
-    uint64_t enable_err_handler0 : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_error_mask_t;
-
-#endif // __ASSEMBLER__
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define PORE_SBE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pore_sbe_prv_base_address0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 25;
-    uint64_t mc : 1;
-    uint64_t chiplet_id : 6;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t chiplet_id : 6;
-    uint64_t mc : 1;
-    uint64_t spare : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_prv_base_address0_t;
-
-
-
-typedef union pore_sbe_prv_base_address1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 25;
-    uint64_t mc : 1;
-    uint64_t chiplet_id : 6;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t chiplet_id : 6;
-    uint64_t mc : 1;
-    uint64_t spare : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_prv_base_address1_t;
-
-
-
-typedef union pore_sbe_oci_base_address0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 18;
-    uint64_t oci_mem_route : 14;
-    uint64_t oci_base_address : 32;
-#else
-    uint64_t oci_base_address : 32;
-    uint64_t oci_mem_route : 14;
-    uint64_t spare : 18;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_oci_base_address0_t;
-
-
-
-typedef union pore_sbe_oci_base_address1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t spare : 18;
-    uint64_t oci_mem_route : 14;
-    uint64_t oci_base_address : 32;
-#else
-    uint64_t oci_base_address : 32;
-    uint64_t oci_mem_route : 14;
-    uint64_t spare : 18;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_oci_base_address1_t;
-
-
-
-typedef union pore_sbe_table_base_addr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved : 16;
-    uint64_t memory_space : 16;
-    uint64_t table_base_address : 32;
-#else
-    uint64_t table_base_address : 32;
-    uint64_t memory_space : 16;
-    uint64_t reserved : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_table_base_addr_t;
-
-
-
-typedef union pore_sbe_exe_trigger {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved : 8;
-    uint64_t start_vector : 4;
-    uint64_t zeroes : 8;
-    uint64_t unused : 12;
-    uint64_t mc_chiplet_select_mask : 32;
-#else
-    uint64_t mc_chiplet_select_mask : 32;
-    uint64_t unused : 12;
-    uint64_t zeroes : 8;
-    uint64_t start_vector : 4;
-    uint64_t reserved : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_exe_trigger_t;
-
-
-
-typedef union pore_sbe_scratch0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t zeroes : 8;
-    uint64_t scratch0 : 24;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t scratch0 : 24;
-    uint64_t zeroes : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_scratch0_t;
-
-
-
-typedef union pore_sbe_scratch1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t scratch1 : 64;
-#else
-    uint64_t scratch1 : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_scratch1_t;
-
-
-
-typedef union pore_sbe_scratch2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t scratch2 : 64;
-#else
-    uint64_t scratch2 : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_scratch2_t;
-
-
-
-typedef union pore_sbe_ibuf_01 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ibuf0 : 32;
-    uint64_t ibuf1 : 32;
-#else
-    uint64_t ibuf1 : 32;
-    uint64_t ibuf0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_ibuf_01_t;
-
-
-
-typedef union pore_sbe_ibuf_2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t ibuf2 : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t ibuf2 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_ibuf_2_t;
-
-
-
-typedef union pore_sbe_dbg0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t last_completed_address : 32;
-    uint64_t last_pib_parity_fail : 1;
-    uint64_t last_ret_code_prv : 3;
-    uint64_t i2c_bad_status0 : 1;
-    uint64_t i2c_bad_status1 : 1;
-    uint64_t i2c_bad_status2 : 1;
-    uint64_t i2c_bad_status3 : 1;
-    uint64_t group_parity_error0 : 1;
-    uint64_t group_parity_error1 : 1;
-    uint64_t group_parity_error2 : 1;
-    uint64_t group_parity_error3 : 1;
-    uint64_t group_parity_error4 : 1;
-    uint64_t interrupt_counter : 8;
-    uint64_t _reserved0 : 11;
-#else
-    uint64_t _reserved0 : 11;
-    uint64_t interrupt_counter : 8;
-    uint64_t group_parity_error4 : 1;
-    uint64_t group_parity_error3 : 1;
-    uint64_t group_parity_error2 : 1;
-    uint64_t group_parity_error1 : 1;
-    uint64_t group_parity_error0 : 1;
-    uint64_t i2c_bad_status3 : 1;
-    uint64_t i2c_bad_status2 : 1;
-    uint64_t i2c_bad_status1 : 1;
-    uint64_t i2c_bad_status0 : 1;
-    uint64_t last_ret_code_prv : 3;
-    uint64_t last_pib_parity_fail : 1;
-    uint64_t last_completed_address : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_dbg0_t;
-
-
-
-typedef union pore_sbe_dbg1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_last_access : 48;
-    uint64_t oci_master_rd_parity_err : 1;
-    uint64_t last_ret_code_oci : 3;
-    uint64_t bad_instr_parity : 1;
-    uint64_t invalid_instr_code : 1;
-    uint64_t pc_overflow_underrun : 1;
-    uint64_t bad_scan_crc : 1;
-    uint64_t pc_stack_ovflw_undrn_err : 1;
-    uint64_t instruction_fetch_error : 1;
-    uint64_t invalid_instruction_operand : 1;
-    uint64_t invalid_instruction_path : 1;
-    uint64_t invalid_start_vector : 1;
-    uint64_t fast_i2c_protocol_hang : 1;
-    uint64_t spare : 1;
-    uint64_t debug_regs_locked : 1;
-#else
-    uint64_t debug_regs_locked : 1;
-    uint64_t spare : 1;
-    uint64_t fast_i2c_protocol_hang : 1;
-    uint64_t invalid_start_vector : 1;
-    uint64_t invalid_instruction_path : 1;
-    uint64_t invalid_instruction_operand : 1;
-    uint64_t instruction_fetch_error : 1;
-    uint64_t pc_stack_ovflw_undrn_err : 1;
-    uint64_t bad_scan_crc : 1;
-    uint64_t pc_overflow_underrun : 1;
-    uint64_t invalid_instr_code : 1;
-    uint64_t bad_instr_parity : 1;
-    uint64_t last_ret_code_oci : 3;
-    uint64_t oci_master_rd_parity_err : 1;
-    uint64_t pc_last_access : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_dbg1_t;
-
-
-
-typedef union pore_sbe_pc_stack0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack0 : 48;
-    uint64_t _reserved0 : 11;
-    uint64_t set_new_stack_pointer : 1;
-    uint64_t new_stack_pointer : 4;
-#else
-    uint64_t new_stack_pointer : 4;
-    uint64_t set_new_stack_pointer : 1;
-    uint64_t _reserved0 : 11;
-    uint64_t pc_stack0 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_pc_stack0_t;
-
-
-
-typedef union pore_sbe_pc_stack1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack1 : 48;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t pc_stack1 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_pc_stack1_t;
-
-
-
-typedef union pore_sbe_pc_stack2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t pc_stack2 : 48;
-    uint64_t _reserved0 : 16;
-#else
-    uint64_t _reserved0 : 16;
-    uint64_t pc_stack2 : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_pc_stack2_t;
-
-
-
-typedef union pore_sbe_id_flags {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 32;
-    uint64_t pib_parity_fail : 1;
-    uint64_t pib_status : 3;
-    uint64_t oci_parity_fail : 1;
-    uint64_t oci_status : 3;
-    uint64_t reserved1 : 8;
-    uint64_t ugt : 1;
-    uint64_t ult : 1;
-    uint64_t sgt : 1;
-    uint64_t slt : 1;
-    uint64_t c : 1;
-    uint64_t o : 1;
-    uint64_t n : 1;
-    uint64_t z : 1;
-    uint64_t reserved2 : 4;
-    uint64_t ibuf_id : 4;
-#else
-    uint64_t ibuf_id : 4;
-    uint64_t reserved2 : 4;
-    uint64_t z : 1;
-    uint64_t n : 1;
-    uint64_t o : 1;
-    uint64_t c : 1;
-    uint64_t slt : 1;
-    uint64_t sgt : 1;
-    uint64_t ult : 1;
-    uint64_t ugt : 1;
-    uint64_t reserved1 : 8;
-    uint64_t oci_status : 3;
-    uint64_t oci_parity_fail : 1;
-    uint64_t pib_status : 3;
-    uint64_t pib_parity_fail : 1;
-    uint64_t reserved0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_id_flags_t;
-
-
-
-typedef union pore_sbe_data0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t data0 : 32;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t data0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_data0_t;
-
-
-
-typedef union pore_sbe_memory_reloc {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 30;
-    uint64_t memory_reloc_region : 2;
-    uint64_t memory_reloc_base : 20;
-    uint64_t _reserved1 : 12;
-#else
-    uint64_t _reserved1 : 12;
-    uint64_t memory_reloc_base : 20;
-    uint64_t memory_reloc_region : 2;
-    uint64_t _reserved0 : 30;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_memory_reloc_t;
-
-
-
-typedef union pore_sbe_i2c_en_param {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t i2c_engine_identifier : 4;
-    uint64_t reserved0 : 1;
-    uint64_t i2c_engine_address_range : 3;
-    uint64_t reserved1 : 3;
-    uint64_t i2c_engine_port : 5;
-    uint64_t reserved2 : 1;
-    uint64_t i2c_engine_device_id : 7;
-    uint64_t reserved3 : 2;
-    uint64_t i2c_engine_speed : 2;
-    uint64_t i2c_poll_threshold : 4;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t i2c_poll_threshold : 4;
-    uint64_t i2c_engine_speed : 2;
-    uint64_t reserved3 : 2;
-    uint64_t i2c_engine_device_id : 7;
-    uint64_t reserved2 : 1;
-    uint64_t i2c_engine_port : 5;
-    uint64_t reserved1 : 3;
-    uint64_t i2c_engine_address_range : 3;
-    uint64_t reserved0 : 1;
-    uint64_t i2c_engine_identifier : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pore_sbe_i2c_en_param_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __SBE_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/sbe_register_addresses.h b/src/ssx/pgp/registers/sbe_register_addresses.h
deleted file mode 100644
index 794acea..0000000
--- a/src/ssx/pgp/registers/sbe_register_addresses.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __SBE_REGISTER_ADDRESSES_H__
-#define __SBE_REGISTER_ADDRESSES_H__
-
-// $Id: sbe_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sbe_register_addresses.h
-/// \brief Symbolic addresses for the SBE unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define PORE_SBE_PIB_BASE 0x000e0000
-#define PORE_SBE_STATUS 0x000e0000
-#define PORE_SBE_CONTROL 0x000e0001
-#define PORE_SBE_RESET 0x000e0002
-#define PORE_SBE_ERROR_MASK 0x000e0003
-#define PORE_SBE_PRV_BASE_ADDRESS0 0x000e0004
-#define PORE_SBE_PRV_BASE_ADDRESS1 0x000e0005
-#define PORE_SBE_OCI_BASE_ADDRESS0 0x000e0006
-#define PORE_SBE_OCI_BASE_ADDRESS1 0x000e0007
-#define PORE_SBE_TABLE_BASE_ADDR 0x000e0008
-#define PORE_SBE_EXE_TRIGGER 0x000e0009
-#define PORE_SBE_SCRATCH0 0x000e000a
-#define PORE_SBE_SCRATCH1 0x000e000b
-#define PORE_SBE_SCRATCH2 0x000e000c
-#define PORE_SBE_IBUF_01 0x000e000d
-#define PORE_SBE_IBUF_2 0x000e000e
-#define PORE_SBE_DBG0 0x000e000f
-#define PORE_SBE_DBG1 0x000e0010
-#define PORE_SBE_PC_STACK0 0x000e0011
-#define PORE_SBE_PC_STACK1 0x000e0012
-#define PORE_SBE_PC_STACK2 0x000e0013
-#define PORE_SBE_ID_FLAGS 0x000e0014
-#define PORE_SBE_DATA0 0x000e0015
-#define PORE_SBE_MEMORY_RELOC 0x000e0016
-#define PORE_SBE_I2C_EN_PARAM(n) (PORE_SBE_I2C_E0_PARAM + ((PORE_SBE_I2C_E1_PARAM - PORE_SBE_I2C_E0_PARAM) * (n)))
-#define PORE_SBE_I2C_E0_PARAM 0x000e0017
-#define PORE_SBE_I2C_E1_PARAM 0x000e0018
-#define PORE_SBE_I2C_E2_PARAM 0x000e0019
-
-#endif // __SBE_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/sensors_firmware_registers.h b/src/ssx/pgp/registers/sensors_firmware_registers.h
deleted file mode 100755
index 9cb252e..0000000
--- a/src/ssx/pgp/registers/sensors_firmware_registers.h
+++ /dev/null
@@ -1,668 +0,0 @@
-#ifndef __SENSORS_FIRMWARE_REGISTERS_H__
-#define __SENSORS_FIRMWARE_REGISTERS_H__
-
-// $Id: sensors_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sensors_firmware_registers.h
-/// \brief C register structs for the SENSORS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union sensors_v0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts0 : 12;
-    uint64_t thermal_trip0 : 2;
-    uint64_t spare0 : 1;
-    uint64_t valid0 : 1;
-    uint64_t dts1 : 12;
-    uint64_t thermal_trip1 : 2;
-    uint64_t spare1 : 1;
-    uint64_t valid1 : 1;
-    uint64_t dts2 : 12;
-    uint64_t thermal_trip2 : 2;
-    uint64_t spare2 : 1;
-    uint64_t valid2 : 1;
-    uint64_t dts3 : 12;
-    uint64_t thermal_trip3 : 2;
-    uint64_t spare3 : 1;
-    uint64_t valid3 : 1;
-#else
-    uint64_t valid3 : 1;
-    uint64_t spare3 : 1;
-    uint64_t thermal_trip3 : 2;
-    uint64_t dts3 : 12;
-    uint64_t valid2 : 1;
-    uint64_t spare2 : 1;
-    uint64_t thermal_trip2 : 2;
-    uint64_t dts2 : 12;
-    uint64_t valid1 : 1;
-    uint64_t spare1 : 1;
-    uint64_t thermal_trip1 : 2;
-    uint64_t dts1 : 12;
-    uint64_t valid0 : 1;
-    uint64_t spare0 : 1;
-    uint64_t thermal_trip0 : 2;
-    uint64_t dts0 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v0_t;
-
-
-
-typedef union sensors_v1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts4 : 12;
-    uint64_t thermal_trip4 : 2;
-    uint64_t spare4 : 1;
-    uint64_t valid4 : 1;
-    uint64_t dts5 : 12;
-    uint64_t thermal_trip5 : 2;
-    uint64_t spare5 : 1;
-    uint64_t valid5 : 1;
-    uint64_t dts6 : 12;
-    uint64_t thermal_trip6 : 2;
-    uint64_t spare6 : 1;
-    uint64_t valid6 : 1;
-    uint64_t dts7 : 12;
-    uint64_t thermal_trip7 : 2;
-    uint64_t spare7 : 1;
-    uint64_t valid7 : 1;
-#else
-    uint64_t valid7 : 1;
-    uint64_t spare7 : 1;
-    uint64_t thermal_trip7 : 2;
-    uint64_t dts7 : 12;
-    uint64_t valid6 : 1;
-    uint64_t spare6 : 1;
-    uint64_t thermal_trip6 : 2;
-    uint64_t dts6 : 12;
-    uint64_t valid5 : 1;
-    uint64_t spare5 : 1;
-    uint64_t thermal_trip5 : 2;
-    uint64_t dts5 : 12;
-    uint64_t valid4 : 1;
-    uint64_t spare4 : 1;
-    uint64_t thermal_trip4 : 2;
-    uint64_t dts4 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v1_t;
-
-
-
-typedef union sensors_v2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts8 : 12;
-    uint64_t thermal_trip8 : 2;
-    uint64_t spare8 : 1;
-    uint64_t valid8 : 1;
-    uint64_t dts9 : 12;
-    uint64_t thermal_trip9 : 2;
-    uint64_t spare9 : 1;
-    uint64_t valid9 : 1;
-    uint64_t dts10 : 12;
-    uint64_t thermal_trip10 : 2;
-    uint64_t spare10 : 1;
-    uint64_t valid10 : 1;
-    uint64_t dts12 : 12;
-    uint64_t thermal_trip12 : 2;
-    uint64_t spare12 : 1;
-    uint64_t valid12 : 1;
-#else
-    uint64_t valid12 : 1;
-    uint64_t spare12 : 1;
-    uint64_t thermal_trip12 : 2;
-    uint64_t dts12 : 12;
-    uint64_t valid10 : 1;
-    uint64_t spare10 : 1;
-    uint64_t thermal_trip10 : 2;
-    uint64_t dts10 : 12;
-    uint64_t valid9 : 1;
-    uint64_t spare9 : 1;
-    uint64_t thermal_trip9 : 2;
-    uint64_t dts9 : 12;
-    uint64_t valid8 : 1;
-    uint64_t spare8 : 1;
-    uint64_t thermal_trip8 : 2;
-    uint64_t dts8 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v2_t;
-
-
-
-typedef union sensors_v3 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t unknown : 64;
-#else
-    uint64_t unknown : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v3_t;
-
-
-
-typedef union sensors_v5 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t raw_cpm0 : 12;
-    uint64_t spare0 : 4;
-    uint64_t raw_cpm1 : 12;
-    uint64_t spare1 : 4;
-    uint64_t raw_cpm2 : 12;
-    uint64_t spare2 : 4;
-    uint64_t raw_cpm3 : 12;
-    uint64_t spare3 : 4;
-#else
-    uint64_t spare3 : 4;
-    uint64_t raw_cpm3 : 12;
-    uint64_t spare2 : 4;
-    uint64_t raw_cpm2 : 12;
-    uint64_t spare1 : 4;
-    uint64_t raw_cpm1 : 12;
-    uint64_t spare0 : 4;
-    uint64_t raw_cpm0 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v5_t;
-
-
-
-typedef union sensors_v6 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t raw_cpm4 : 12;
-    uint64_t spare4 : 4;
-    uint64_t raw_cpm5 : 12;
-    uint64_t spare5 : 4;
-    uint64_t raw_cpm6 : 12;
-    uint64_t spare6 : 4;
-    uint64_t raw_cpm7 : 12;
-    uint64_t spare7 : 4;
-#else
-    uint64_t spare7 : 4;
-    uint64_t raw_cpm7 : 12;
-    uint64_t spare6 : 4;
-    uint64_t raw_cpm6 : 12;
-    uint64_t spare5 : 4;
-    uint64_t raw_cpm5 : 12;
-    uint64_t spare4 : 4;
-    uint64_t raw_cpm4 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v6_t;
-
-
-
-typedef union sensors_v7 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t raw_cpm8 : 12;
-    uint64_t spare8 : 4;
-    uint64_t raw_cpm9 : 12;
-    uint64_t spare9 : 4;
-    uint64_t raw_cpm10 : 12;
-    uint64_t spare10 : 4;
-    uint64_t raw_cpm11 : 12;
-    uint64_t spare11 : 4;
-#else
-    uint64_t spare11 : 4;
-    uint64_t raw_cpm11 : 12;
-    uint64_t spare10 : 4;
-    uint64_t raw_cpm10 : 12;
-    uint64_t spare9 : 4;
-    uint64_t raw_cpm9 : 12;
-    uint64_t spare8 : 4;
-    uint64_t raw_cpm8 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v7_t;
-
-
-
-typedef union sensors_v8 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts0 : 12;
-    uint64_t thermal_trip0 : 2;
-    uint64_t spare0 : 1;
-    uint64_t valid0 : 1;
-    uint64_t dts1 : 12;
-    uint64_t thermal_trip1 : 2;
-    uint64_t spare1 : 1;
-    uint64_t valid1 : 1;
-    uint64_t dts2 : 12;
-    uint64_t thermal_trip2 : 2;
-    uint64_t spare2 : 1;
-    uint64_t valid2 : 1;
-    uint64_t encoded_cpm0 : 4;
-    uint64_t encoded_cpm1 : 4;
-    uint64_t encoded_cpm2 : 4;
-    uint64_t encoded_cpm3 : 4;
-#else
-    uint64_t encoded_cpm3 : 4;
-    uint64_t encoded_cpm2 : 4;
-    uint64_t encoded_cpm1 : 4;
-    uint64_t encoded_cpm0 : 4;
-    uint64_t valid2 : 1;
-    uint64_t spare2 : 1;
-    uint64_t thermal_trip2 : 2;
-    uint64_t dts2 : 12;
-    uint64_t valid1 : 1;
-    uint64_t spare1 : 1;
-    uint64_t thermal_trip1 : 2;
-    uint64_t dts1 : 12;
-    uint64_t valid0 : 1;
-    uint64_t spare0 : 1;
-    uint64_t thermal_trip0 : 2;
-    uint64_t dts0 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v8_t;
-
-
-
-typedef union sensors_v9 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts4 : 12;
-    uint64_t thermal_trip4 : 2;
-    uint64_t spare4 : 1;
-    uint64_t valid4 : 1;
-    uint64_t dts5 : 12;
-    uint64_t thermal_trip5 : 2;
-    uint64_t spare5 : 1;
-    uint64_t valid5 : 1;
-    uint64_t dts6 : 12;
-    uint64_t thermal_trip6 : 2;
-    uint64_t spare6 : 1;
-    uint64_t valid6 : 1;
-    uint64_t encoded_cpm4 : 4;
-    uint64_t encoded_cpm5 : 4;
-    uint64_t encoded_cpm6 : 4;
-    uint64_t encoded_cpm7 : 4;
-#else
-    uint64_t encoded_cpm7 : 4;
-    uint64_t encoded_cpm6 : 4;
-    uint64_t encoded_cpm5 : 4;
-    uint64_t encoded_cpm4 : 4;
-    uint64_t valid6 : 1;
-    uint64_t spare6 : 1;
-    uint64_t thermal_trip6 : 2;
-    uint64_t dts6 : 12;
-    uint64_t valid5 : 1;
-    uint64_t spare5 : 1;
-    uint64_t thermal_trip5 : 2;
-    uint64_t dts5 : 12;
-    uint64_t valid4 : 1;
-    uint64_t spare4 : 1;
-    uint64_t thermal_trip4 : 2;
-    uint64_t dts4 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v9_t;
-
-
-
-typedef union sensors_v10 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dts8 : 12;
-    uint64_t thermal_trip8 : 2;
-    uint64_t spare8 : 1;
-    uint64_t valid8 : 1;
-    uint64_t dts9 : 12;
-    uint64_t thermal_trip9 : 2;
-    uint64_t spare9 : 1;
-    uint64_t valid9 : 1;
-    uint64_t dts10 : 12;
-    uint64_t thermal_trip10 : 2;
-    uint64_t spare10 : 1;
-    uint64_t valid10 : 1;
-    uint64_t encoded_cpm8 : 4;
-    uint64_t encoded_cpm9 : 4;
-    uint64_t encoded_cpm10 : 4;
-    uint64_t encoded_cpm11 : 4;
-#else
-    uint64_t encoded_cpm11 : 4;
-    uint64_t encoded_cpm10 : 4;
-    uint64_t encoded_cpm9 : 4;
-    uint64_t encoded_cpm8 : 4;
-    uint64_t valid10 : 1;
-    uint64_t spare10 : 1;
-    uint64_t thermal_trip10 : 2;
-    uint64_t dts10 : 12;
-    uint64_t valid9 : 1;
-    uint64_t spare9 : 1;
-    uint64_t thermal_trip9 : 2;
-    uint64_t dts9 : 12;
-    uint64_t valid8 : 1;
-    uint64_t spare8 : 1;
-    uint64_t thermal_trip8 : 2;
-    uint64_t dts8 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v10_t;
-
-
-
-typedef union sensors_v11 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dvs0 : 12;
-    uint64_t spare00 : 1;
-    uint64_t trip0 : 1;
-    uint64_t spare01 : 1;
-    uint64_t valid0 : 1;
-    uint64_t dvs1 : 12;
-    uint64_t spare10 : 1;
-    uint64_t trip1 : 1;
-    uint64_t spare11 : 1;
-    uint64_t valid1 : 1;
-    uint64_t dvs2 : 12;
-    uint64_t spare20 : 1;
-    uint64_t trip2 : 1;
-    uint64_t spare21 : 1;
-    uint64_t valid2 : 1;
-    uint64_t dvs3 : 12;
-    uint64_t spare30 : 1;
-    uint64_t trip3 : 1;
-    uint64_t spare31 : 1;
-    uint64_t valid3 : 1;
-#else
-    uint64_t valid3 : 1;
-    uint64_t spare31 : 1;
-    uint64_t trip3 : 1;
-    uint64_t spare30 : 1;
-    uint64_t dvs3 : 12;
-    uint64_t valid2 : 1;
-    uint64_t spare21 : 1;
-    uint64_t trip2 : 1;
-    uint64_t spare20 : 1;
-    uint64_t dvs2 : 12;
-    uint64_t valid1 : 1;
-    uint64_t spare11 : 1;
-    uint64_t trip1 : 1;
-    uint64_t spare10 : 1;
-    uint64_t dvs1 : 12;
-    uint64_t valid0 : 1;
-    uint64_t spare01 : 1;
-    uint64_t trip0 : 1;
-    uint64_t spare00 : 1;
-    uint64_t dvs0 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v11_t;
-
-
-
-typedef union sensors_v12 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dvs4 : 12;
-    uint64_t spare40 : 1;
-    uint64_t trip4 : 1;
-    uint64_t spare41 : 1;
-    uint64_t valid4 : 1;
-    uint64_t dvs5 : 12;
-    uint64_t spare50 : 1;
-    uint64_t trip5 : 1;
-    uint64_t spare51 : 1;
-    uint64_t valid5 : 1;
-    uint64_t dvs6 : 12;
-    uint64_t spare60 : 1;
-    uint64_t trip6 : 1;
-    uint64_t spare61 : 1;
-    uint64_t valid6 : 1;
-    uint64_t dvs7 : 12;
-    uint64_t spare70 : 1;
-    uint64_t trip7 : 1;
-    uint64_t spare71 : 1;
-    uint64_t valid7 : 1;
-#else
-    uint64_t valid7 : 1;
-    uint64_t spare71 : 1;
-    uint64_t trip7 : 1;
-    uint64_t spare70 : 1;
-    uint64_t dvs7 : 12;
-    uint64_t valid6 : 1;
-    uint64_t spare61 : 1;
-    uint64_t trip6 : 1;
-    uint64_t spare60 : 1;
-    uint64_t dvs6 : 12;
-    uint64_t valid5 : 1;
-    uint64_t spare51 : 1;
-    uint64_t trip5 : 1;
-    uint64_t spare50 : 1;
-    uint64_t dvs5 : 12;
-    uint64_t valid4 : 1;
-    uint64_t spare41 : 1;
-    uint64_t trip4 : 1;
-    uint64_t spare40 : 1;
-    uint64_t dvs4 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v12_t;
-
-
-
-typedef union sensors_v13 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t dvs8 : 12;
-    uint64_t spare80 : 1;
-    uint64_t trip8 : 1;
-    uint64_t spare81 : 1;
-    uint64_t valid8 : 1;
-    uint64_t dvs9 : 12;
-    uint64_t spare90 : 1;
-    uint64_t trip9 : 1;
-    uint64_t spare91 : 1;
-    uint64_t valid9 : 1;
-    uint64_t dvs10 : 12;
-    uint64_t spare100 : 1;
-    uint64_t trip10 : 1;
-    uint64_t spare101 : 1;
-    uint64_t valid10 : 1;
-    uint64_t dvs11 : 12;
-    uint64_t spare110 : 1;
-    uint64_t trip11 : 1;
-    uint64_t spare111 : 1;
-    uint64_t valid11 : 1;
-#else
-    uint64_t valid11 : 1;
-    uint64_t spare111 : 1;
-    uint64_t trip11 : 1;
-    uint64_t spare110 : 1;
-    uint64_t dvs11 : 12;
-    uint64_t valid10 : 1;
-    uint64_t spare101 : 1;
-    uint64_t trip10 : 1;
-    uint64_t spare100 : 1;
-    uint64_t dvs10 : 12;
-    uint64_t valid9 : 1;
-    uint64_t spare91 : 1;
-    uint64_t trip9 : 1;
-    uint64_t spare90 : 1;
-    uint64_t dvs9 : 12;
-    uint64_t valid8 : 1;
-    uint64_t spare81 : 1;
-    uint64_t trip8 : 1;
-    uint64_t spare80 : 1;
-    uint64_t dvs8 : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} sensors_v13_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __SENSORS_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/sensors_register_addresses.h b/src/ssx/pgp/registers/sensors_register_addresses.h
deleted file mode 100755
index c815ace..0000000
--- a/src/ssx/pgp/registers/sensors_register_addresses.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __SENSORS_REGISTER_ADDRESSES_H__
-#define __SENSORS_REGISTER_ADDRESSES_H__
-
-// $Id: sensors_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sensors_register_addresses.h
-/// \brief Symbolic addresses for the SENSORS unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define SENSORS_CORE_PCB_BASE 0x10050000
-#define SENSORS_V0_OFFSET 0x00000000
-#define SENSORS_CORE_V0 0x10050000
-#define SENSORS_V1_OFFSET 0x00000001
-#define SENSORS_CORE_V1 0x10050001
-#define SENSORS_V2_OFFSET 0x00000002
-#define SENSORS_CORE_V2 0x10050002
-#define SENSORS_V3_OFFSET 0x00000003
-#define SENSORS_CORE_V3 0x10050003
-#define SENSORS_V5_OFFSET 0x00000005
-#define SENSORS_CORE_V5 0x10050005
-#define SENSORS_V6_OFFSET 0x00000006
-#define SENSORS_CORE_V6 0x10050006
-#define SENSORS_V7_OFFSET 0x00000007
-#define SENSORS_CORE_V7 0x10050007
-#define SENSORS_V8_OFFSET 0x00000008
-#define SENSORS_CORE_V8 0x10050008
-#define SENSORS_V9_OFFSET 0x00000009
-#define SENSORS_CORE_V9 0x10050009
-#define SENSORS_V10_OFFSET 0x0000000a
-#define SENSORS_CORE_V10 0x1005000a
-#define SENSORS_V11_OFFSET 0x0000000b
-#define SENSORS_CORE_V11 0x1005000b
-#define SENSORS_V12_OFFSET 0x0000000c
-#define SENSORS_CORE_V12 0x1005000c
-#define SENSORS_V13_OFFSET 0x0000000d
-#define SENSORS_CORE_V13 0x1005000d
-
-#endif // __SENSORS_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/sramctl_firmware_registers.h b/src/ssx/pgp/registers/sramctl_firmware_registers.h
deleted file mode 100755
index c8a7c26..0000000
--- a/src/ssx/pgp/registers/sramctl_firmware_registers.h
+++ /dev/null
@@ -1,211 +0,0 @@
-#ifndef __SRAMCTL_FIRMWARE_REGISTERS_H__
-#define __SRAMCTL_FIRMWARE_REGISTERS_H__
-
-// $Id: sramctl_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sramctl_firmware_registers.h
-/// \brief C register structs for the SRAMCTL unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union sramctl_srbar {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t sram_region_qualifier : 2;
-    uint32_t reserved : 3;
-    uint32_t sram_bar_region : 8;
-    uint32_t _reserved0 : 19;
-#else
-    uint32_t _reserved0 : 19;
-    uint32_t sram_bar_region : 8;
-    uint32_t reserved : 3;
-    uint32_t sram_region_qualifier : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srbar_t;
-
-
-
-typedef union sramctl_srmr {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t sram_enable_remap : 1;
-    uint32_t sram_arb_en_send_all_writes : 1;
-    uint32_t sram_disable_lfsr : 1;
-    uint32_t sram_lfsr_fairness_mask : 5;
-    uint32_t sram_error_inject_enable : 1;
-    uint32_t sram_ctl_trace_en : 1;
-    uint32_t sram_ctl_trace_sel : 1;
-    uint32_t reserved : 5;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t reserved : 5;
-    uint32_t sram_ctl_trace_sel : 1;
-    uint32_t sram_ctl_trace_en : 1;
-    uint32_t sram_error_inject_enable : 1;
-    uint32_t sram_lfsr_fairness_mask : 5;
-    uint32_t sram_disable_lfsr : 1;
-    uint32_t sram_arb_en_send_all_writes : 1;
-    uint32_t sram_enable_remap : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srmr_t;
-
-
-
-typedef union sramctl_srmap {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t reserved : 1;
-    uint32_t sram_remap_source : 12;
-    uint32_t _reserved0 : 1;
-    uint32_t reserved1 : 3;
-    uint32_t sram_remap_dest : 13;
-    uint32_t reserved2 : 2;
-#else
-    uint32_t reserved2 : 2;
-    uint32_t sram_remap_dest : 13;
-    uint32_t reserved1 : 3;
-    uint32_t _reserved0 : 1;
-    uint32_t sram_remap_source : 12;
-    uint32_t reserved : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srmap_t;
-
-
-
-typedef union sramctl_srear {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t sram_error_address : 16;
-    uint32_t _reserved0 : 16;
-#else
-    uint32_t _reserved0 : 16;
-    uint32_t sram_error_address : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srear_t;
-
-
-
-typedef union sramctl_srbv0 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t boot_vector_word0 : 32;
-#else
-    uint32_t boot_vector_word0 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srbv0_t;
-
-
-
-typedef union sramctl_srbv1 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t boot_vector_word1 : 32;
-#else
-    uint32_t boot_vector_word1 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srbv1_t;
-
-
-
-typedef union sramctl_srbv2 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t boot_vector_word2 : 32;
-#else
-    uint32_t boot_vector_word2 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srbv2_t;
-
-
-
-typedef union sramctl_srbv3 {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t boot_vector_word3 : 32;
-#else
-    uint32_t boot_vector_word3 : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srbv3_t;
-
-
-
-typedef union sramctl_srchsw {
-
-    uint32_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint32_t chksw_wrfsm_dly_dis : 1;
-    uint32_t chksw_allow1_rd : 1;
-    uint32_t chksw_allow1_wr : 1;
-    uint32_t chksw_allow1_rdwr : 1;
-    uint32_t chksw_oci_parchk_dis : 1;
-    uint32_t chksw_tank_rddata_parchk_dis : 1;
-    uint32_t chksw_tank_sr_rderr_dis : 1;
-    uint32_t chksw_val_be_addr_chk_dis : 1;
-    uint32_t chksw_so_spare : 2;
-    uint32_t _reserved0 : 22;
-#else
-    uint32_t _reserved0 : 22;
-    uint32_t chksw_so_spare : 2;
-    uint32_t chksw_val_be_addr_chk_dis : 1;
-    uint32_t chksw_tank_sr_rderr_dis : 1;
-    uint32_t chksw_tank_rddata_parchk_dis : 1;
-    uint32_t chksw_oci_parchk_dis : 1;
-    uint32_t chksw_allow1_rdwr : 1;
-    uint32_t chksw_allow1_wr : 1;
-    uint32_t chksw_allow1_rd : 1;
-    uint32_t chksw_wrfsm_dly_dis : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} sramctl_srchsw_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __SRAMCTL_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/sramctl_register_addresses.h b/src/ssx/pgp/registers/sramctl_register_addresses.h
deleted file mode 100755
index baec5d5..0000000
--- a/src/ssx/pgp/registers/sramctl_register_addresses.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __SRAMCTL_REGISTER_ADDRESSES_H__
-#define __SRAMCTL_REGISTER_ADDRESSES_H__
-
-// $Id: sramctl_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file sramctl_register_addresses.h
-/// \brief Symbolic addresses for the SRAMCTL unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define SRAMCTL_OCI_BASE 0x40030000
-#define SRAMCTL_SRBAR 0x40030000
-#define SRAMCTL_SRMR 0x40030008
-#define SRAMCTL_SRMAP 0x40030010
-#define SRAMCTL_SREAR 0x40030018
-#define SRAMCTL_SRBV0 0x40030020
-#define SRAMCTL_SRBV1 0x40030028
-#define SRAMCTL_SRBV2 0x40030030
-#define SRAMCTL_SRBV3 0x40030038
-#define SRAMCTL_SRCHSW 0x40030040
-
-#endif // __SRAMCTL_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/tod_firmware_registers.h b/src/ssx/pgp/registers/tod_firmware_registers.h
deleted file mode 100755
index 7a700d7..0000000
--- a/src/ssx/pgp/registers/tod_firmware_registers.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef __TOD_FIRMWARE_REGISTERS_H__
-#define __TOD_FIRMWARE_REGISTERS_H__
-
-// $Id: tod_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file tod_firmware_registers.h
-/// \brief C register structs for the TOD unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union tod_value_reg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t tod_incrementer : 60;
-    uint64_t tod_wof : 4;
-#else
-    uint64_t tod_wof : 4;
-    uint64_t tod_incrementer : 60;
-#endif // _BIG_ENDIAN
-    } fields;
-} tod_value_reg_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __TOD_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/tod_register_addresses.h b/src/ssx/pgp/registers/tod_register_addresses.h
deleted file mode 100755
index ac7d136..0000000
--- a/src/ssx/pgp/registers/tod_register_addresses.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef __TOD_REGISTER_ADDRESSES_H__
-#define __TOD_REGISTER_ADDRESSES_H__
-
-// $Id: tod_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file tod_register_addresses.h
-/// \brief Symbolic addresses for the TOD unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define TOD_PIB_BASE 0x00040000
-#define TOD_VALUE_REG 0x00040020
-
-#endif // __TOD_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/registers/tpc_firmware_registers.h b/src/ssx/pgp/registers/tpc_firmware_registers.h
deleted file mode 100644
index 62f1c42..0000000
--- a/src/ssx/pgp/registers/tpc_firmware_registers.h
+++ /dev/null
@@ -1,213 +0,0 @@
-#ifndef __TPC_FIRMWARE_REGISTERS_H__
-#define __TPC_FIRMWARE_REGISTERS_H__
-
-// $Id: tpc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_firmware_registers.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file tpc_firmware_registers.h
-/// \brief C register structs for the TPC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-
-
-
-typedef union tpc_perv_gp3 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t tp_chiplet_chiplet_en_dc : 1;
-    uint64_t put_in_later0 : 25;
-    uint64_t tp_chiplet_fence_pcb_dc : 1;
-    uint64_t put_in_later1 : 37;
-#else
-    uint64_t put_in_later1 : 37;
-    uint64_t tp_chiplet_fence_pcb_dc : 1;
-    uint64_t put_in_later0 : 25;
-    uint64_t tp_chiplet_chiplet_en_dc : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_perv_gp3_t;
-
-
-
-typedef union tpc_gp0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t put_in_later0 : 40;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t put_in_later1 : 18;
-#else
-    uint64_t put_in_later1 : 18;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t put_in_later0 : 40;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_gp0_t;
-
-
-
-typedef union tpc_gp0_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t put_in_later0 : 40;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t put_in_later1 : 18;
-#else
-    uint64_t put_in_later1 : 18;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t put_in_later0 : 40;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_gp0_and_t;
-
-
-
-typedef union tpc_gp0_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t put_in_later0 : 40;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t put_in_later1 : 18;
-#else
-    uint64_t put_in_later1 : 18;
-    uint64_t tc_chip_id_dc : 3;
-    uint64_t tc_node_id_dc : 3;
-    uint64_t put_in_later0 : 40;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_gp0_or_t;
-
-
-
-typedef union tpc_hpr2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t hang_pulse_reg : 6;
-    uint64_t suppress_hang : 1;
-    uint64_t _reserved0 : 57;
-#else
-    uint64_t _reserved0 : 57;
-    uint64_t suppress_hang : 1;
-    uint64_t hang_pulse_reg : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_hpr2_t;
-
-
-
-typedef union tpc_device_id {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-    uint64_t cfam_id : 32;
-    uint64_t fuse_nx_allow_crypto : 1;
-    uint64_t fuse_vmx_crypto_dis : 1;
-    uint64_t fuse_fp_throttle_en : 1;
-    uint64_t reserved32 : 1;
-    uint64_t socket_id : 3;
-    uint64_t chippos_id : 1;
-    uint64_t _reserved0 : 24;
-#else
-    uint64_t _reserved0 : 24;
-    uint64_t chippos_id : 1;
-    uint64_t socket_id : 3;
-    uint64_t reserved32 : 1;
-    uint64_t fuse_fp_throttle_en : 1;
-    uint64_t fuse_vmx_crypto_dis : 1;
-    uint64_t fuse_nx_allow_crypto : 1;
-    uint64_t cfam_id : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} tpc_device_id_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __TPC_FIRMWARE_REGISTERS_H__
-
diff --git a/src/ssx/pgp/registers/tpc_register_addresses.h b/src/ssx/pgp/registers/tpc_register_addresses.h
deleted file mode 100644
index 50c7e97..0000000
--- a/src/ssx/pgp/registers/tpc_register_addresses.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __TPC_REGISTER_ADDRESSES_H__
-#define __TPC_REGISTER_ADDRESSES_H__
-
-// $Id: tpc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_register_addresses.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file tpc_register_addresses.h
-/// \brief Symbolic addresses for the TPC unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-
-#define TPC_PERVPIB_BASE 0x00050000
-#define TPC_PERV_GP3 0x0005001b
-#define TPC_PIB_BASE 0x01000000
-#define TPC_GP0 0x01000000
-#define TPC_GP0_AND 0x01000004
-#define TPC_GP0_OR 0x01000005
-#define TPC_MISCPIB_BASE 0x010f0000
-#define TPC_HPR2 0x010f0022
-#define TPC_TPCHIP_BASE 0x000f0000
-#define TPC_DEVICE_ID 0x000f000f
-
-#endif // __TPC_REGISTER_ADDRESSES_H__
-
diff --git a/src/ssx/pgp/ssx.mk b/src/ssx/pgp/ssx.mk
deleted file mode 100755
index 402f153..0000000
--- a/src/ssx/pgp/ssx.mk
+++ /dev/null
@@ -1,442 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/ssx/pgp/ssx.mk $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2014,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-# $Id: ssx.mk,v 1.2 2014/06/26 12:55:39 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssx.mk,v $
-#  Make header for PgP SSX builds
-#
-# The application may define the following variables to control the
-# build process:
-#
-# APP_INCLUDES       : Aplication-specific header search paths
-#
-# DEFS               : A string of -D<symbol>[=<value>] to control compilation
-#
-# SSX                : Default ..; The path to the SSX source code.
-#                      The default is set for building the SSX
-#                      subdirectories. 
-#
-# SSX_THREAD_SUPPORT : (0/1, default 1); Compile SSX thread and
-#                      semaphore suppprt 
-#
-# SSX_TIMER_SUPPORT  : (0/1, default 1); Compile SSX timer suppprt
-#
-# PPC405_MMU_SUPPORT : (0/1, default 1); Compile for PPC405 simple MMU protection
-#
-# SIMICS_ENVIRONMENT : (0/1, current default 0); Compile for Simics
-#
-# SIMICS_MAGIC_PANIC : (0/1, current default 0); Use Simics Magic
-#                      breakpoint for SSX_PANIC() instead of PowerPC trap.
-#                      Note that Simics does not model trap correctly in
-#                      external debug mode.
-#
-# GCC-O-LEVEL        : The optimization level passed to GCC (default -Os). May
-#                      also be defined empty (GCC-O-LEVEL=) to disable
-#                      optimization. This variable can also be used to pass
-#                      any other non-default setting to GCC, e.g.
-#                      make GCC-O-LEVEL="-Os -fno-branch-count-reg"
-#
-# GCC-TOOL-PREFIX    : The full path (including executable file prefixes) to
-#                      the GCC cross-development tools to use.  The default is 
-#                      "ppcnf-mcp5-"
-#
-# POREPATH           : Overrideable path to the PORE binutils
-
-export OCCROOT = $(dir $(lastword $(MAKEFILE_LIST)))../../
-
-ifndef SIMICS_ENVIRONMENT
-SIMICS_ENVIRONMENT=0
-endif
-
-ifndef GCC-TOOL-PREFIX
-
-# CROSS_PREFIX may be set by
-# op-build/openpower/package/occ/occ.mk
-
-ifdef CROSS_PREFIX
-GCC-TOOL-PREFIX = $(CROSS_PREFIX)
-else
-GCC-TOOL-PREFIX = powerpc64-unknown-linux-gnu-
-endif
-
-endif
-
-ifndef HOST-PREFIX
-HOST-PREFIX = x86_64-pc-linux-gnu-
-endif
-
-CC_ASM  = $(GCC-TOOL-PREFIX)gcc
-CC      = $(TRACEPP) $(GCC-TOOL-PREFIX)gcc
-LD      = $(GCC-TOOL-PREFIX)ld
-OBJDUMP = $(GCC-TOOL-PREFIX)objdump
-
-JAIL    = $(HOST-PREFIX)jail
-
-ifndef OCC_OP_BUILD
-AS      = $(JAIL) /usr/bin/as
-AR      = $(JAIL) /usr/bin/ar
-OBJCOPY = $(JAIL) /usr/bin/objcopy
-CPP     = $(JAIL) /usr/bin/cpp
-else
-AS      = $(GCC-TOOL-PREFIX)as
-AR      = $(GCC-TOOL-PREFIX)ar
-OBJCOPY = $(GCC-TOOL-PREFIX)objcopy
-CPP     = $(GCC-TOOL-PREFIX)cpp
-endif
-
-ifndef POREPATH
-$(warning The POREPATH variable is not defined; Defaulting to current PATH)
-endif
-
-PORE-AS      = $(POREPATH)pore-elf64-as
-PORE-AS      = $(POREPATH)pore-elf64-as
-PORE-LD      = $(POREPATH)pore-elf64-ld
-PORE-OBJCOPY = $(POREPATH)pore-elf64-objcopy
-
-ifeq "$(SSX)" ""
-SSX = ..
-endif
-
-ifeq "$(LIB)" ""
-LIB = ../../lib
-endif
-
-ifeq "$(SSX_TIMER_SUPPORT)" ""
-SSX_TIMER_SUPPORT  = 1
-endif
-
-ifeq "$(SSX_THREAD_SUPPORT)" ""
-SSX_THREAD_SUPPORT = 1
-endif
-
-ifeq "$(PPC405_MMU_SUPPORT)" ""
-PPC405_MMU_SUPPORT = 1
-endif
-
-ifeq "$(PGP_ASYNC_SUPPORT)" ""
-PGP_ASYNC_SUPPORT = 1
-endif
-
-ifndef GCC-O-LEVEL
-GCC-O-LEVEL = -Os
-endif
-
-GCC-DEFS += -DSIMICS_ENVIRONMENT=$(SIMICS_ENVIRONMENT)
-GCC-DEFS += -DSSX_TIMER_SUPPORT=$(SSX_TIMER_SUPPORT) 
-GCC-DEFS += -DSSX_THREAD_SUPPORT=$(SSX_THREAD_SUPPORT) 
-GCC-DEFS += -DPPC405_MMU_SUPPORT=$(PPC405_MMU_SUPPORT)
-DEFS += $(GCC-DEFS) -DPGAS_PPC=1 -DCONFIGURE_PTS_SLW=0
-PORE-DEFS += $(GCC-DEFS)
-
-############################################################################
-
-INCLUDES += $(APP_INCLUDES) \
-	-I$(SSX)/ssx -I$(SSX)/ppc32 -I$(SSX)/ppc405 \
-	-I$(SSX)/pgp -I$(SSX)/pgp/registers \
-	-I$(LIB)
-
-PIPE-CFLAGS = -pipe -Wa,-m405
-
-GCC-CFLAGS += -g -Wall -fsigned-char -msoft-float  \
-	-m32 -mbig-endian -mcpu=405 -mmultiple -mstring \
-	-meabi -msdata=eabi -ffreestanding -fno-common \
-	-fno-inline-functions-called-once
-
-CFLAGS      =  -c $(GCC-CFLAGS) $(PIPE-CFLAGS) $(GCC-O-LEVEL) $(INCLUDES) 
-PORE-CFLAGS =  -E $(GCC-CFLAGS) $(OPT) $(INCLUDES) 
-CPPFLAGS += -m32 -mcpu=405 -msdata=eabi -meabi -mstring -mmultiple
-
-############################################################################
-
-# Build object code
-#
-# %.o: %.c - Compile C code
-#
-# %.o: %.S - Compile PowerPC assembler (including PGAS-PPC assembly)
-
-%.o: %.c
-	$(CC) $(CFLAGS) $(DEFS) -o $@ $<
-
-%.o: %.S
-	$(CC_ASM) $(CFLAGS) $(DEFS) -o $@ $<
-
-#Temporary always use PGAS PPC Assembler for compiling .pS files.
-#relocatable symbols are being added to the GPE (.pS) files and
-#so need new way to compile using GNU assembler.
-PGAS_PPC=1
-
-# use "make PGAS_PPC=1" to compile .pS file using PGAS PPC assembler.
-# If PGAS_PPC=1 is not part of the make command, then GNU assembler is
-# used for compiling .pS files.
-ifdef PGAS_PPC
-
-ifneq ($(MAKE_PORE_HOOKS),)
-
-# This Makefile included here defines how to convert *.pS into both the object
-# file and the hooks object file.
-
-include $(MAKE_PORE_HOOKS)
-
-else
-
-%.o: %.pS
-	$(CC_ASM) -x assembler-with-cpp $(PORE-CFLAGS) $(PORE-DEFS)  $< | $(PORE-AS) - -o $@
-endif
-
-%.lst: %.pS
-	$(CC_ASM) -x assembler-with-cpp  $(CFLAGS) $(DEFS) \
-		-Wa,-al -Wa,--listing-cont-lines=20 $< > $@
-
-else
-%.o: %.pS
-	$(CPP_ASM) -x assembler-with-cpp $(PORE-CFLAGS) $(PORE-DEFS)  $< | $(PORE-AS) - -o $@
-endif
-
-# Other useful targets
-#
-# %.S: %.c - See what the assembler produces from the C code, however you can
-# also just look at the final disassembly.
-#
-# %.lst: %.S - Get an assembler listing
-#
-# %.cpp: %.S - Preprocess PowerPC assembler source to stdout
-#
-# %.cpp: %.pS - Preprocess PORE assembler source to stdout
-#
-# %.cpp: %.c - Preprocess C source to stdout
-
-%.S: %.c
-	$(CC) $(CFLAGS) $(DEFS) -S -o $@ $<
-
-%.lst: %.S
-	$(CC_ASM) $(CFLAGS) $(DEFS) -Wa,-al -Wa,--listing-cont-lines=20 $< > $@
-
-%.cpp: %.S
-	$(CC_ASM) $(CFLAGS) $(DEFS) -E $<
-
-%.cpp: %.pS
-	$(CC) -x assembler-with-cpp $(CFLAGS) $(DEFS) -E $<
-
-%.cpp: %.c
-	$(CC) $(CFLAGS) $(DEFS) -E $<
-
-# From the GNU 'Make' manual - these scripts uses the preprocessor to
-# create dependency files (*.d), then mungs them slightly to make them
-# work as Make targets. The *.d files are include-ed in the
-# subdirectory Makefiles.
-
-%.d: %.c
-	@set -e; rm -f $@; \
-	$(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< > $@.$$$$; \
-	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
-	rm -f $@.$$$$
-
-%.d: %.S
-	@set -e; rm -f $@; \
-	$(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< > $@.$$$$; \
-	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
-	rm -f $@.$$$$
-
-%.d: %.pS
-	@set -e; rm -f $@; \
-	$(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) -x assembler-with-cpp $(DEFS) $< > $@.$$$$; \
-	sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
-	rm -f $@.$$$$
-
-############################################################################
-#
-# GCC Compiler flags used in these builds.  Comments, or reasons for
-# non-obvious choices appear in [] after the GCC documentation.
-#
-#`-Os'
-#     Optimize for size.  `-Os' enables all `-O2' optimizations that do
-#     not typically increase code size.  It also performs further
-#     optimizations designed to reduce code size.
-#
-#     `-Os' disables the following optimization flags:
-#          -falign-functions  -falign-jumps  -falign-loops
-#          -falign-labels  -freorder-blocks  -freorder-blocks-and-partition
-#          -fprefetch-loop-arrays  -ftree-vect-loop-version
-#
-#     If you use multiple `-O' options, with or without level numbers,
-#     the last such option is the one that is effective.
-#
-#`-g'
-#     Produce debugging information in the operating system's native
-#     format (stabs, COFF, XCOFF, or DWARF 2).  GDB can work with this
-#     debugging information.
-#
-#     On most systems that use stabs format, `-g' enables use of extra
-#     debugging information that only GDB can use; this extra information
-#     makes debugging work better in GDB but will probably make other
-#     debuggers crash or refuse to read the program.  If you want to
-#     control for certain whether to generate the extra information, use
-#     `-gstabs+', `-gstabs', `-gxcoff+', `-gxcoff', or `-gvms' (see
-#     below).
-#
-#     GCC allows you to use `-g' with `-O'.  The shortcuts taken by
-#     optimized code may occasionally produce surprising results: some
-#     variables you declared may not exist at all; flow of control may
-#     briefly move where you did not expect it; some statements may not
-#     be executed because they compute constant results or their values
-#     were already at hand; some statements may execute in different
-#     places because they were moved out of loops.
-#
-#     Nevertheless it proves possible to debug optimized output.  This
-#     makes it reasonable to use the optimizer for programs that might
-#     have bugs.
-#
-#`-Wall'
-#     Turns on all optional warnings which are desirable for normal code.
-#     At present this is `-Wcomment', `-Wtrigraphs', `-Wmultichar' and a
-#     warning about integer promotion causing a change of sign in `#if'
-#     expressions.  Note that many of the preprocessor's warnings are on
-#     by default and have no options to control them.
-#
-#`-Werror'
-#     Make all warnings into errors.
-#  
-#`-fsigned-char'
-#     Let the type `char' be signed, like `signed char'.
-#
-#     Note that this is equivalent to `-fno-unsigned-char', which is the
-#     negative form of `-funsigned-char'.  Likewise, the option
-#     `-fno-signed-char' is equivalent to `-funsigned-char'.
-#
-#`-msoft-float'
-#     Generate output containing library calls for floating point.
-#     *Warning:* the requisite libraries are not available for all ARM
-#     targets.  Normally the facilities of the machine's usual C
-#     compiler are used, but this cannot be done directly in
-#     cross-compilation.  You must make your own arrangements to provide
-#     suitable library functions for cross-compilation.
-#
-#     `-msoft-float' changes the calling convention in the output file;
-#     therefore, it is only useful if you compile _all_ of a program with
-#     this option.  In particular, you need to compile `libgcc.a', the
-#     library that comes with GCC, with `-msoft-float' in order for this
-#     to work.
-#
-#`-pipe'
-#     Use pipes rather than temporary files for communication between the
-#     various stages of compilation.  This fails to work on some systems
-#     where the assembler is unable to read from a pipe; but the GNU
-#     assembler has no trouble.
-#
-#`-mmultiple'
-#`-mno-multiple'
-#     Generate code that uses (does not use) the load multiple word
-#     instructions and the store multiple word instructions.  These
-#     instructions are generated by default on POWER systems, and not
-#     generated on PowerPC systems.  Do not use `-mmultiple' on little
-#     endian PowerPC systems, since those instructions do not work when
-#     the processor is in little endian mode.  The exceptions are PPC740
-#     and PPC750 which permit the instructions usage in little endian
-#     mode.
-#
-#`-mstring'
-#`-mno-string'
-#     Generate code that uses (does not use) the load string instructions
-#     and the store string word instructions to save multiple registers
-#     and do small block moves.  These instructions are generated by
-#     default on POWER systems, and not generated on PowerPC systems.
-#     Do not use `-mstring' on little endian PowerPC systems, since those
-#     instructions do not work when the processor is in little endian
-#     mode.  The exceptions are PPC740 and PPC750 which permit the
-#     instructions usage in little endian mode.
-#
-#`-meabi'
-#`-mno-eabi'
-#     On System V.4 and embedded PowerPC systems do (do not) adhere to
-#     the Embedded Applications Binary Interface (eabi) which is a set of
-#     modifications to the System V.4 specifications.  Selecting `-meabi'
-#     means that the stack is aligned to an 8 byte boundary, a function
-#     `__eabi' is called to from `main' to set up the eabi environment,
-#     and the `-msdata' option can use both `r2' and `r13' to point to
-#     two separate small data areas.  Selecting `-mno-eabi' means that
-#     the stack is aligned to a 16 byte boundary, do not call an
-#     initialization function from `main', and the `-msdata' option will
-#     only use `r13' to point to a single small data area.  The `-meabi'
-#     option is on by default if you configured GCC using one of the
-#     `powerpc*-*-eabi*' options.
-#
-# [We elected to use the EABI to reduce stack requirements and possibly reduce
-# code size and improve performance.  In practice it probably has little real
-# effect since the code size and performance improvements only apply to global
-# variables <= 8 bytes, and our applications will not have deeply nested call
-# trees. Still, much of the assembler code requires/assumes the EABI is in
-# place, and it certainly doesn't hurt anything to use it.]
-#
-#`-msdata=eabi'
-#     On System V.4 and embedded PowerPC systems, put small initialized
-#     `const' global and static data in the `.sdata2' section, which is
-#     pointed to by register `r2'.  Put small initialized non-`const'
-#     global and static data in the `.sdata' section, which is pointed
-#     to by register `r13'.  Put small uninitialized global and static
-#     data in the `.sbss' section, which is adjacent to the `.sdata'
-#     section.  The `-msdata=eabi' option is incompatible with the
-#     `-mrelocatable' option.  The `-msdata=eabi' option also sets the
-#     `-memb' option.
-#
-#`-memb'
-#     On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags
-#     header to indicate that `eabi' extended relocations are used.
-#
-#`-ffreestanding'
-#     Assert that compilation takes place in a freestanding environment.
-#     This implies `-fno-builtin'.  A freestanding environment is one
-#     in which the standard library may not exist, and program startup
-#     may not necessarily be at `main'.  The most obvious example is an
-#     OS kernel.  This is equivalent to `-fno-hosted'.
-#
-#`-fno-common'
-#     In C, allocate even uninitialized global variables in the data
-#     section of the object file, rather than generating them as common
-#     blocks.  This has the effect that if the same variable is declared
-#     (without `extern') in two different compilations, you will get an
-#     error when you link them.  The only reason this might be useful is
-#     if you wish to verify that the program will work on other systems
-#     which always work this way.
-#
-# [It is always assumed to be an error if two C source files declare global
-# variables of the same name, since it is not clear whether this was intended
-# or not.]
-# 
-#`-finline-functions-called-once'
-#`-fno-inline-functions-called-once'
-#     Consider all `static' functions called once for inlining into their
-#     caller even if they are not marked `inline'.  If a call to a given
-#     function is integrated, then the function is not output as
-#     assembler code in its own right.
-#
-#     Enabled if `-funit-at-a-time' is enabled.
-#
-# [There is a 'bug' in GCC related to inlining static, called-once
-# functions. GCC allocates stack space in the caller for the stacks of ALL
-# inlined functions of this type, even if they are called sequentially,
-# leading in some cases to kilobytes of wasted stack space. If you want to
-# inline a static called-once function you will need to explicity declare it
-# as 'inline'.]
-
-
diff --git a/src/ssx/pgp/ssx_port.h b/src/ssx/pgp/ssx_port.h
deleted file mode 100755
index 613ac43..0000000
--- a/src/ssx/pgp/ssx_port.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __SSX_PORT_H__
-#define __SSX_PORT_H__
-
-// $Id: ssx_port.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssx_port.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//-----------------------------------------------------------------------------
-
-/// \file ssx_port.h
-/// \brief The top-level PGP environment header for SSX.
-
-#define CHIP_PGP
-
-#include "ppc405.h"
-
-#endif /* __SSX_PORT_H__ */
diff --git a/src/ssx/pgp/ssxpgpfiles.mk b/src/ssx/pgp/ssxpgpfiles.mk
deleted file mode 100755
index dd12da1..0000000
--- a/src/ssx/pgp/ssxpgpfiles.mk
+++ /dev/null
@@ -1,37 +0,0 @@
-# $Id: ssxpgpfiles.mk,v 1.4 2014/06/26 12:56:28 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssxpgpfiles.mk,v $
-#  @file ssxpgpfiles.mk
-#
-#  @brief mk for including pgp object files
-#
-#  @page ChangeLogs Change Logs
-#  @section ssxpgpfiles.mk
-#  @verbatim
-#
-#
-# Change Log ******************************************************************
-# Flag     Defect/Feature  User        Date         Description
-# ------   --------------  ----------  ------------ -----------
-# @pb00E                   pbavari     03/11/2012   Makefile ODE support
-#
-# @endverbatim
-#
-##########################################################################
-# Object Files
-##########################################################################
-PGP-C-SOURCES = pgp_init.c pgp_irq_init.c pgp_pmc.c pgp_ocb.c pgp_pba.c \
-	pgp_id.c pgp_centaur.c
-PGP-S-SOURCES = pgp_cache.S
-
-PGP-TIMER-C-SOURCES = 
-PGP-TIMER-S-SOURCES = 
-
-PGP-THREAD-C-SOURCES = 
-PGP-THREAD-S-SOURCES = 
-
-PGP-ASYNC-C-SOURCES = pgp_async.c pgp_async_pore.c pgp_async_ocb.c \
-	pgp_async_pba.c
-PGP-ASYNC-S-SOURCES =
-
-PGP_OBJECTS += $(PGP-C-SOURCES:.c=.o) $(PGP-S-SOURCES:.S=.o)
-
diff --git a/src/ssx/ppc32/Makefile b/src/ssx/ppc32/Makefile
index 81776dd..67541ac 100755..100644
--- a/src/ssx/ppc32/Makefile
+++ b/src/ssx/ppc32/Makefile
@@ -1,30 +1,44 @@
-# $Id: Makefile,v 1.2 2013/12/12 16:12:37 bcbrock Exp $
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ppc32/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 
 # This Makefile is designed to be invoked with the -I argument set to
-# the location of the "ssx.mk" for the build.
+# the location of the "img_defs.mk" for the build.
 #
-# This makefile creates the libppc32.a library.
-
-SSX = ..
-PGP = $(SSX)/pgp
-
-include $(PGP)/ssx.mk
+include img_defs.mk
 include ssxppc32files.mk
 
+OBJS := $(addprefix $(OBJDIR)/, $(PPC32_OBJECTS))
 
+all: $(OBJS)
 
-libppc32.a: ${PPC32_OBJECTS}
-	$(AR) crs libppc32.a ${PPC32_OBJECTS}
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
 
-.PHONY : clean
-clean:
-	rm -f *.o *.a *.d *.d.*
-
-
-#  This clause prevents the dependencies from creating errors during a clean.
-#  Whenever a header file is added or deleted it will likely be necessary to
-#  'make clean' to force recomputation of dependencies.
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
 
 ifneq ($(MAKECMDGOALS),clean)
-include $(PPC32_OBJECTS:.o=.d) 
-endif
\ No newline at end of file
+include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/ssx/ppc32/div64.S b/src/ssx/ppc32/div64.S
index 04ee008..cc6309b 100755..100644
--- a/src/ssx/ppc32/div64.S
+++ b/src/ssx/ppc32/div64.S
@@ -1,7 +1,29 @@
-// $Id: div64.S,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/div64.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/div64.S $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/gnu/stubs-32.h b/src/ssx/ppc32/gnu/stubs-32.h
deleted file mode 100644
index 3da2fb2..0000000
--- a/src/ssx/ppc32/gnu/stubs-32.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* This file is automatically generated.
-   It defines a symbol `__stub_FUNCTION' for each function
-   in the C library which is a stub, meaning it will fail
-   every time called, usually setting errno to ENOSYS.  */
-
-#ifdef _LIBC
- #error Applications may not define the macro _LIBC
-#endif
-
-#define __stub___kernel_rem_pio2l
-#define __stub_chflags
-#define __stub_fattach
-#define __stub_fchflags
-#define __stub_fdetach
-#define __stub_gtty
-#define __stub_lchmod
-#define __stub_revoke
-#define __stub_setlogin
-#define __stub_sigreturn
-#define __stub_sstk
-#define __stub_stty
diff --git a/src/ssx/ppc32/ppc32.h b/src/ssx/ppc32/ppc32.h
index e7f7bf8..0ba8a46 100755..100644
--- a/src/ssx/ppc32/ppc32.h
+++ b/src/ssx/ppc32/ppc32.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/ppc32.h $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC32_H__
 #define __PPC32_H__
 
-// $Id: ppc32.h,v 1.2 2014/03/14 15:11:46 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/ppc32_asm.h b/src/ssx/ppc32/ppc32_asm.h
index 0207c22..b681e88 100755..100644
--- a/src/ssx/ppc32/ppc32_asm.h
+++ b/src/ssx/ppc32/ppc32_asm.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/ppc32_asm.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC32_ASM_H__
 #define __PPC32_ASM_H__
 
-// $Id: ppc32_asm.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_asm.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/ppc32_gcc.c b/src/ssx/ppc32/ppc32_gcc.c
index a00ab48..8fe9bf5 100755..100644
--- a/src/ssx/ppc32/ppc32_gcc.c
+++ b/src/ssx/ppc32/ppc32_gcc.c
@@ -1,7 +1,29 @@
-// $Id: ppc32_gcc.c,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_gcc.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/ppc32_gcc.c $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/ppc32_gcc.h b/src/ssx/ppc32/ppc32_gcc.h
index 1925107..7931fcd 100755..100644
--- a/src/ssx/ppc32/ppc32_gcc.h
+++ b/src/ssx/ppc32/ppc32_gcc.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/ppc32_gcc.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC32_GCC_H__
 #define __PPC32_GCC_H__
 
-// $Id: ppc32_gcc.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_gcc.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/savegpr.S b/src/ssx/ppc32/savegpr.S
index 854f22b..4dbfef0 100755..100644
--- a/src/ssx/ppc32/savegpr.S
+++ b/src/ssx/ppc32/savegpr.S
@@ -1,7 +1,29 @@
-// $Id: savegpr.S,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/savegpr.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc32/savegpr.S $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc32/ssxppc32files.mk b/src/ssx/ppc32/ssxppc32files.mk
index 8697550..7987265 100755..100644
--- a/src/ssx/ppc32/ssxppc32files.mk
+++ b/src/ssx/ppc32/ssxppc32files.mk
@@ -1,5 +1,27 @@
-# $Id: ssxppc32files.mk,v 1.2 2014/06/26 12:58:31 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ssxppc32files.mk,v $
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ppc32/ssxppc32files.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 #  @file ssxppc32files.mk
 #
 #  @brief mk for including ppc32 object files
diff --git a/src/ssx/ppc405/Makefile b/src/ssx/ppc405/Makefile
index 0391504..82391e2 100755..100644
--- a/src/ssx/ppc405/Makefile
+++ b/src/ssx/ppc405/Makefile
@@ -1,12 +1,30 @@
-# $Id: Makefile,v 1.2 2013/12/12 16:12:38 bcbrock Exp $
-
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ppc405/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 # This Makefile is designed to be invoked with the -I argument set to
-# the location of the "ssx.mk" for the build
-
-SSX = ..
-PGP = $(SSX)/pgp
-
-include $(PGP)/ssx.mk
+# the location of the "img_defs.mk" for the build
+include img_defs.mk
 include ssxppc405files.mk
 
 ifeq "$(SSX_TIMER_SUPPORT)" "1"
@@ -21,17 +39,16 @@ ifeq "$(PPC405_MMU_SUPPORT)" "1"
 PPC405_OBJECTS += ${PPC405-MMU-C-SOURCES:.c=.o} ${PPC405-MMU-S-SOURCES:.S=.o}
 endif
 
+OBJS := $(addprefix $(OBJDIR)/, $(PPC405_OBJECTS))
 
-all: local
-	$(MAKE) -I ../pgp -C ../ppc32
+all: $(OBJS)
 
-local: $(PPC405_OBJECTS)
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
 
-.PHONY : clean
-clean:
-	rm -f *.o *.d *.d.*
-	$(MAKE) -I ../pgp -C ../ppc32 clean
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
 
 ifneq ($(MAKECMDGOALS),clean)
-include $(PPC405_OBJECTS:.o=.d) 
-endif
\ No newline at end of file
+include $(OBJS:.o=.d) 
+endif
+
diff --git a/src/ssx/ppc405/ppc405.h b/src/ssx/ppc405/ppc405.h
index 18b0c53..079831d 100755..100644
--- a/src/ssx/ppc405/ppc405.h
+++ b/src/ssx/ppc405/ppc405.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405.h $                                     */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_H__
 #define __PPC405_H__
 
-// $Id: ppc405.h,v 1.3 2014/02/03 01:30:42 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -19,7 +41,7 @@
 // documentation on the D-cache tag sizes doesn't make any sense to me - it
 // claims the tag size is constant regardless of the size of the cache.
 // However the Xilinx documentation for their 405 core (which has the same
-// 16KB cache as PgP) is consistent with the way the DCACHE_TAG_MASK is
+// 16KB cache as OCCHW) is consistent with the way the DCACHE_TAG_MASK is
 // defined here.
 
 #define CACHE_LINE_SIZE     32
@@ -37,7 +59,7 @@
 #define DCACHE_TAG_MASK \
     ((0xffffffff << (LOG_DCACHE_SIZE - LOG_DCACHE_WAYS)) & 0xffffffff)
 
-#ifdef CHIP_PGP
+#ifdef HWMACRO_OCC
 
 #define ICACHE_SIZE  (16 * 1024)
 #define DCACHE_SIZE  (16 * 1024)
@@ -68,8 +90,8 @@
 #endif
 
 
-#ifdef CHIP_PGP
-#include "pgp.h"
+#ifdef HWMACRO_OCC
+#include "occhw.h"
 #endif
 
 #include "ppc32.h"
diff --git a/src/ssx/ppc405/ppc405_boot.S b/src/ssx/ppc405/ppc405_boot.S
index 1f4a4f9..7ffe7dd 100755..100644
--- a/src/ssx/ppc405/ppc405_boot.S
+++ b/src/ssx/ppc405/ppc405_boot.S
@@ -1,7 +1,29 @@
-// $Id: ppc405_boot.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_boot.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_boot.S $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_breakpoint.S b/src/ssx/ppc405/ppc405_breakpoint.S
index 3adbd13..ce3aef2 100644
--- a/src/ssx/ppc405/ppc405_breakpoint.S
+++ b/src/ssx/ppc405/ppc405_breakpoint.S
@@ -1,7 +1,29 @@
-// $Id: ppc405_breakpoint.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_breakpoint.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_breakpoint.S $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_cache.h b/src/ssx/ppc405/ppc405_cache.h
index 02bd4f5..2d78425 100755..100644
--- a/src/ssx/ppc405/ppc405_cache.h
+++ b/src/ssx/ppc405/ppc405_cache.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_cache.h $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_CACHE_H__
 #define __PPC405_CACHE_H__
 
-// $Id: ppc405_cache.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_cache_core.c b/src/ssx/ppc405/ppc405_cache_core.c
index a03f5e2..36056e2 100755..100644
--- a/src/ssx/ppc405/ppc405_cache_core.c
+++ b/src/ssx/ppc405/ppc405_cache_core.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_cache_core.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_cache_core.c $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_cache_init.S b/src/ssx/ppc405/ppc405_cache_init.S
index c4bed0e..a8ef79c 100755..100644
--- a/src/ssx/ppc405/ppc405_cache_init.S
+++ b/src/ssx/ppc405/ppc405_cache_init.S
@@ -1,7 +1,29 @@
-// $Id: ppc405_cache_init.S,v 1.3 2014/06/26 12:59:35 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache_init.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_cache_init.S $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_context.h b/src/ssx/ppc405/ppc405_context.h
index 3019358..a820a99 100755..100644
--- a/src/ssx/ppc405/ppc405_context.h
+++ b/src/ssx/ppc405/ppc405_context.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_context.h $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_CONTEXT_H__
 #define __PPC405_CONTEXT_H__
 
-// $Id: ppc405_context.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_context.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -105,7 +127,7 @@
 //
 // When SSX is initialized USPRG0 is initialized to 0.  When thread-mode is
 // entered (by ssx_start_threads()) bit 24 is set to 1.  In order to support
-// PgP/OCC firmware, once initialized (with ssx_initialize()) SSX can simply
+// OCC firmware, once initialized (with ssx_initialize()) SSX can simply
 // handle interrupts, reverting back to the non-thread-mode idle loop when
 // there's nothing to do.
 //      
@@ -337,11 +359,11 @@
 
         .macro  _save_update_kernel_context critical, irqreg, ctxreg
 
-        .if     \critical
-        SSX_TRACE_CRITICAL_IRQ_ENTRY \irqreg, \ctxreg
-        .else
-        SSX_TRACE_NONCRITICAL_IRQ_ENTRY \irqreg, \ctxreg
-        .endif          
+        //.if     \critical
+        //SSX_TRACE_CRITICAL_IRQ_ENTRY \irqreg, \ctxreg
+        //.else
+        //SSX_TRACE_NONCRITICAL_IRQ_ENTRY \irqreg, \ctxreg
+        //.endif          
 
         mfusprg0 \ctxreg
         stw     \ctxreg, SSX_FAST_CTX_KERNEL_CTX(%r1)
@@ -363,13 +385,13 @@
 
         .macro  _ssx_fast_ctx_pop_exit critical
 
-        .if     SSX_KERNEL_TRACE_ENABLE
-        .if     \critical
-        bl      __ssx_trace_critical_irq_exit
-        .else
-        bl      __ssx_trace_noncritical_irq_exit
-        .endif
-        .endif
+        //.if     SSX_KERNEL_TRACE_ENABLE
+        //.if     \critical
+        //bl      __ssx_trace_critical_irq_exit
+        //.else
+        //bl      __ssx_trace_noncritical_irq_exit
+        //.endif
+        //.endif
 
         lwz     %r3, SSX_FAST_CTX_KERNEL_CTX(%r1)
         mtusprg0 %r3
diff --git a/src/ssx/ppc405/ppc405_core.c b/src/ssx/ppc405/ppc405_core.c
index 5df0967..c3a82d3 100755..100644
--- a/src/ssx/ppc405/ppc405_core.c
+++ b/src/ssx/ppc405/ppc405_core.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_core.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_core.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -17,6 +39,57 @@
 
 #include "ssx.h"
 
+// Even though the external timebase is only a 32 bit register, we emulate
+// a 64 bit timebase by keeping the upper 32 bits in SRAM.
+volatile SsxTimebase  ppc405_64bit_ext_timebase = 0;
+
+#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE
+typedef union
+{
+    struct
+    {
+        uint32_t tbu;
+        uint32_t tbl;
+    };
+    SsxTimebase tb64;
+} SsxExtTimebase;
+
+
+SsxTimebase ssx_ext_timebase_get(void)
+{
+    SsxExtTimebase              snapshot;
+    volatile SsxExtTimebase     *cur_tb = (SsxExtTimebase*)&ppc405_64bit_ext_timebase;
+    uint32_t                    tbr;
+    uint32_t                    high;
+
+    //read our in-memory timebase accumulator.
+    //NOTE: 64 bit reads are not atomic on the ppc405.  This means that the
+    //accumulator can be updated between reading the upper 32 bits and lower
+    //32 bits.  It's ok if only the lower 32 bits changed, but if the upper
+    //32 bits changed, then we will report the wrong time stamp.  Therefore,
+    //we check the upper 32 bits after reading the lower 32 bits to make sure
+    //it hasn't changed.
+    do
+    {
+        snapshot.tbu = cur_tb->tbu;
+        snapshot.tbl = cur_tb->tbl; 
+        high = cur_tb->tbu;
+    }while(snapshot.tbu != high);
+
+    //Now read the external timebase register
+    tbr = in32(OCB_OTBR);
+
+    //Check if we need to increment the upper 32 bits
+    if(tbr < snapshot.tbl)
+    {
+        snapshot.tbu++;
+    }
+    snapshot.tbl = tbr;
+    return snapshot.tb64;
+}
+
+#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */
+
 /// Get the 64-bit timebase following the PowerPC protocol
 ///
 /// Note that the only way to guarantee that the value returned is the value
@@ -161,6 +234,10 @@ __ssx_schedule_hardware_timeout(SsxTimebase timeout)
         }
 
         mtspr(SPRN_PIT, pit);
+
+#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE
+        ppc405_64bit_ext_timebase = ssx_ext_timebase_get();
+#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */
     }
 }
 
diff --git a/src/ssx/ppc405/ppc405_dcr.h b/src/ssx/ppc405/ppc405_dcr.h
index 1f389bf..b7e6207 100755..100644
--- a/src/ssx/ppc405/ppc405_dcr.h
+++ b/src/ssx/ppc405/ppc405_dcr.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_dcr.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_DCR_H__
 #define __PPC405_DCR_H__
 
-// $Id: ppc405_dcr.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_dcr.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_exceptions.S b/src/ssx/ppc405/ppc405_exceptions.S
index c8be2e3..b4a1419 100755..100644
--- a/src/ssx/ppc405/ppc405_exceptions.S
+++ b/src/ssx/ppc405/ppc405_exceptions.S
@@ -1,7 +1,29 @@
-// $Id: ppc405_exceptions.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_exceptions.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_exceptions.S $                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -24,7 +46,7 @@
 ///
 /// .vectors_0000 - Empty section for adding image header
 ///
-/// .vectors_0100 - From 0x0100 to 0x0bff.  The beginning of the table through
+/// .vectors_0100 - From 0x0100 to 0x081f.  The beginning of the table through
 ///                 the large space prior to the system call vector.
 /// 
 /// .vectors_0c00 - From 0x0c00 to 0x0eff.  This is a moderately large area
@@ -47,6 +69,9 @@
         .nolist
 #include "ssx.h"
         .list
+
+## declare and initializes global variables that hold external irq config data
+        .occhw_irq_cfg_bitmaps
         
 ### ****************************************************************************
 ### .vectors_0000 - Empty section ( Image header will be placed in this section
@@ -59,6 +84,10 @@
 __vectors:
 __vectors_0000:
 
+        // FIXME: This is just a quick hack to get SSX running on simics -- grm
+        .global __ssx_boot
+        b __ssx_boot
+
 ### ****************************************************************************
 ### .vectors_0100
 ### ****************************************************************************
@@ -341,7 +370,7 @@ __ssx_idle_thread:
 __ssx_idle_thread_from_bootloader:      
 
         li      %r3, SSX_THREADS
-        SSX_TRACE_THREAD_SWITCH %r3, %r4
+        //SSX_TRACE_THREAD_SWITCH %r3, %r4
         _lwzsd  %r3, __ssx_thread_machine_context_default
         _oriwa  %r3, %r3, MSR_WE
         mtmsr   %r3
@@ -587,6 +616,11 @@ __fpu_unavailable:
 
         .org    __fpu_unavailable + 0x20
 
+### ****************************************************************************
+### .irq_exit_traces
+### ****************************************************************************
+
+        .section .irq_exit_traces, "ax", @progbits
 
         ## Exit traces are moved here because the code area (0x100 bytes)
         ## reserved for individual interrupts is overflowing when tracing is
@@ -595,11 +629,11 @@ __fpu_unavailable:
         ## where we can use any of the fast registers.
 
 __ssx_trace_critical_irq_exit:  
-        SSX_TRACE_CRITICAL_IRQ_EXIT %r3, %r4
+        //SSX_TRACE_CRITICAL_IRQ_EXIT %r3, %r4
         blr
         
 __ssx_trace_noncritical_irq_exit:       
-        SSX_TRACE_NONCRITICAL_IRQ_EXIT %r3, %r4
+        //SSX_TRACE_NONCRITICAL_IRQ_EXIT %r3, %r4
         blr
         
         ## >>>>>>>>>> Pack .vectors_0100 here. Room for ~900 bytes. <<<<<<<<<<
@@ -673,7 +707,7 @@ __ssx_next_thread_resume:
         _ssx_vol_fast_ctx_pop   SSX_THREAD_CONTEXT, SSX_NONCRITICAL
         
         _lbzsd  %r3, __ssx_next_priority
-        SSX_TRACE_THREAD_SWITCH %r3, %r4
+        //SSX_TRACE_THREAD_SWITCH %r3, %r4
         ori     %r3, %r3, PPC405_THREAD_MODE            
         mtusprg0 %r3
 
diff --git a/src/ssx/ppc405/ppc405_init.c b/src/ssx/ppc405/ppc405_init.c
index e818737..8405a4a 100755..100644
--- a/src/ssx/ppc405/ppc405_init.c
+++ b/src/ssx/ppc405/ppc405_init.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_init.c,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_init.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -14,6 +36,7 @@
 /// no longer needed by the application after initialization.
 
 #include "ssx.h"
+#include "ssx_trace.h"
 
 // Note that __ppc405_system_setup() is called from the SSX bootloader early
 // in the initialization, at a point before the aplication has enabled
@@ -26,7 +49,7 @@ __ppc405_system_setup()
 
     // Initialize the interrupt vectors.
 
-    for (irq = 0; irq < PPC405_IRQS; irq++) {
+    for (irq = 0; irq < EXTERNAL_IRQS; irq++) {
         __ppc405_irq_handlers[irq].handler = __ppc405_default_irq_handler;      
         __ppc405_irq_handlers[irq].arg = 0;
     }
@@ -53,11 +76,18 @@ __ppc405_system_setup()
 
     or_spr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
 
-    //  Call system-specific setup
+#if SSX_TIMER_SUPPORT
+#if SSX_TRACE_SUPPORT
+extern SsxTraceBuffer g_ssx_trace_buf;
+    //set the instance id
+    g_ssx_trace_buf.instance_id = OCCHW_INST_ID_PPC;
+#endif  /* SSX_TRACE_SUPPORT */
+#endif  /* SSX_TIMER_SUPPORT */
 
-#ifdef CHIP_PGP
-    void __pgp_setup();
-    __pgp_setup();
+#ifdef HWMACRO_OCC
+    //  Call system-specific setup
+    void __occhw_setup();
+    __occhw_setup();
 #endif
 
 }
diff --git a/src/ssx/ppc405/ppc405_irq.h b/src/ssx/ppc405/ppc405_irq.h
index d85e9ce..0ffd2c1 100755..100644
--- a/src/ssx/ppc405/ppc405_irq.h
+++ b/src/ssx/ppc405/ppc405_irq.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_irq.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_IRQ_H__
 #define __PPC405_IRQ_H__
 
-// $Id: ppc405_irq.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -16,7 +38,7 @@
 /// inherently non-portable, however SSX defines APIs that may be useful among
 /// different machines.
 ///
-/// The interrupt controllers in PPC405 ASICS and PGP allow interrupts to be
+/// The interrupt controllers in PPC405 ASICS and OCCHW allow interrupts to be
 /// programmed as critical or non-critical, with programmable polarity and
 /// edge or level sensitivity.
 
@@ -259,8 +281,8 @@ asm("b __ssx_irq_full_mode_exit");
 //  It's hard to be portable and get all of the definitions and headers in the
 //  correct order.  We need to bring in the system IRQ header here.
 
-#ifdef CHIP_PGP
-#include "pgp_irq.h"
+#ifdef HWMACRO_OCC
+#include "occhw_irq.h"
 #endif
 
 /// \page ppc405_irq_macros_page PPC405 SSX IRQ Assembler Macros
@@ -323,7 +345,7 @@ typedef struct {
 /// Interrupt handlers for real (implemented interrupts)
 
 UNLESS__PPC405_IRQ_CORE_C__(extern)
-Ppc405IrqHandler __ppc405_irq_handlers[PPC405_IRQS];
+Ppc405IrqHandler __ppc405_irq_handlers[EXTERNAL_IRQS];
 
 
 /// The 'phantom interrupt' handler
diff --git a/src/ssx/ppc405/ppc405_irq_core.c b/src/ssx/ppc405/ppc405_irq_core.c
index 3cd7469..ce1c924 100755..100644
--- a/src/ssx/ppc405/ppc405_irq_core.c
+++ b/src/ssx/ppc405/ppc405_irq_core.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_irq_core.c,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_irq_core.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_irq_init.c b/src/ssx/ppc405/ppc405_irq_init.c
index da33947..321d238 100755..100644
--- a/src/ssx/ppc405/ppc405_irq_init.c
+++ b/src/ssx/ppc405/ppc405_irq_init.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_irq_init.c,v 1.2 2014/02/03 01:30:42 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_irq_init.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_lib_core.c b/src/ssx/ppc405/ppc405_lib_core.c
index 3086efb..334f08b 100755..100644
--- a/src/ssx/ppc405/ppc405_lib_core.c
+++ b/src/ssx/ppc405/ppc405_lib_core.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_lib_core.c,v 1.2 2014/06/26 13:00:11 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_lib_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_lib_core.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_mmu.c b/src/ssx/ppc405/ppc405_mmu.c
index 1affc67..3509c36 100755..100644
--- a/src/ssx/ppc405/ppc405_mmu.c
+++ b/src/ssx/ppc405/ppc405_mmu.c
@@ -1,7 +1,29 @@
-// $Id: ppc405_mmu.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_mmu.c $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -349,7 +371,7 @@ ppc405_mmu_unmap(Ppc405MmuMap *map)
 /// \param[in] i_map An optional pointer.  If NULL (0) then a full report is
 /// printed.  If non-null then only the entries recorded in the \a i_map are
 /// printed.
-
+#if 0
 void
 ppc405_mmu_report(FILE* i_stream, Ppc405MmuMap* i_map)
 {
@@ -418,7 +440,7 @@ ppc405_mmu_report(FILE* i_stream, Ppc405MmuMap* i_map)
 
     fprintf(i_stream, "------------------------------------------------------------------------------\n");
 }
-
+#endif
 
 /// Perform a memcpy() without address translation (protection)
 ///
diff --git a/src/ssx/ppc405/ppc405_mmu.h b/src/ssx/ppc405/ppc405_mmu.h
index cd7e249..058143c 100755..100644
--- a/src/ssx/ppc405/ppc405_mmu.h
+++ b/src/ssx/ppc405/ppc405_mmu.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_mmu.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_MMU_H__
 #define __PPC405_MMU_H__
 
-// $Id: ppc405_mmu.h,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_mmu_asm.S b/src/ssx/ppc405/ppc405_mmu_asm.S
index 1118779..d5fefd3 100755..100644
--- a/src/ssx/ppc405/ppc405_mmu_asm.S
+++ b/src/ssx/ppc405/ppc405_mmu_asm.S
@@ -1,7 +1,29 @@
-// $Id: ppc405_mmu_asm.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu_asm.S,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_mmu_asm.S $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_msr.h b/src/ssx/ppc405/ppc405_msr.h
index 645a052..213058f 100755..100644
--- a/src/ssx/ppc405/ppc405_msr.h
+++ b/src/ssx/ppc405/ppc405_msr.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_msr.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_MSR_H__
 #define __PPC405_MSR_H__
 
-// $Id: ppc405_msr.h,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_msr.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_spr.h b/src/ssx/ppc405/ppc405_spr.h
index ede91cb..b73eb90 100755..100644
--- a/src/ssx/ppc405/ppc405_spr.h
+++ b/src/ssx/ppc405/ppc405_spr.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ppc405_spr.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PPC405_SPR_H__
 #define __PPC405_SPR_H__
 
-// $Id: ppc405_spr.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_spr.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ppc405_thread_init.S b/src/ssx/ppc405/ppc405_thread_init.S
index 47f5813..dca6184 100755..100644
--- a/src/ssx/ppc405/ppc405_thread_init.S
+++ b/src/ssx/ppc405/ppc405_thread_init.S
@@ -1,4 +1,27 @@
-// $Id: ppc405_thread_init.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ppc405/ppc405_thread_init.S $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 
 /// \file ppc405_thread_init.S
 /// \brief PPC405-specific thread initialization
@@ -26,9 +49,9 @@ void
 __ssx_thread_context_initialize(SsxThread        *thread, 
                                 SsxThreadRoutine thread_routine, 
                                 void             *private);
-#endif// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_thread_init.S,v $
+#endif
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ssx_port_types.h b/src/ssx/ppc405/ssx_port_types.h
index f57951d..4040b4a 100755..100644
--- a/src/ssx/ppc405/ssx_port_types.h
+++ b/src/ssx/ppc405/ssx_port_types.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ppc405/ssx_port_types.h $                             */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_PORT_TYPES_H__
 #define __SSX_PORT_TYPES_H__
 
-// $Id: ssx_port_types.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ssx_port_types.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ppc405/ssxppc405files.mk b/src/ssx/ppc405/ssxppc405files.mk
index 72d5ecb..c91560e 100755..100644
--- a/src/ssx/ppc405/ssxppc405files.mk
+++ b/src/ssx/ppc405/ssxppc405files.mk
@@ -1,5 +1,27 @@
-# $Id: ssxppc405files.mk,v 1.2 2014/06/26 13:00:55 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ssxppc405files.mk,v $
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ppc405/ssxppc405files.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 #  @file ssxppc405files.mk
 #
 #  @brief mk for including ppc405 object files
diff --git a/src/ssx/ssx/Makefile b/src/ssx/ssx/Makefile
index ce1116f..e149e7f 100755..100644
--- a/src/ssx/ssx/Makefile
+++ b/src/ssx/ssx/Makefile
@@ -1,9 +1,32 @@
-# $Id: Makefile,v 1.2 2013/12/12 16:12:38 bcbrock Exp $
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/ssx/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
 
 # This Makefile is designed to be invoked with the -I argument set to
-# the location of the "ssx.mk" for the build
+# the location of the "img_defs.mk" file for the build
 
-include ../pgp/ssx.mk
+include img_defs.mk
 include ssxssxfiles.mk
 
 ifeq "$(SSX_TIMER_SUPPORT)" "1"
@@ -14,12 +37,15 @@ ifeq "$(SSX_THREAD_SUPPORT)" "1"
 SSX_OBJECTS += ${SSX-THREAD-C-SOURCES:.c=.o} 
 endif
 
-all: $(SSX_OBJECTS)
+OBJS := $(addprefix $(OBJDIR)/, $(SSX_OBJECTS))
 
-.PHONY : clean
-clean:
-	rm -f *.o *.d *.d.*
+all: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
 
 ifneq ($(MAKECMDGOALS),clean)
-include $(SSX_OBJECTS:.o=.d)
+include $(OBJS:.o=.d)
 endif
diff --git a/src/ssx/ssx/ssx.h b/src/ssx/ssx/ssx.h
index 5470968..ff6c947 100755..100644
--- a/src/ssx/ssx/ssx.h
+++ b/src/ssx/ssx/ssx.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx.h $                                           */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_H__
 #define __SSX_H__
 
-// $Id: ssx.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -22,7 +44,9 @@
 #include <stddef.h>
 #endif  /* __ASSEMBLER__ */
 
-#define __SSX__
+#ifndef __SSX__
+#define __SSX__ 1
+#endif
 
 /// The application environment specifies whether or not it will provide an
 /// application configuration file, which must be named "ssx_app_cfg.h".
diff --git a/src/ssx/ssx/ssx_api.h b/src/ssx/ssx/ssx_api.h
index c9657e4..e4f6a10 100755..100644
--- a/src/ssx/ssx/ssx_api.h
+++ b/src/ssx/ssx/ssx_api.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_api.h $                                       */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_API_H__
 #define __SSX_API_H__
 
-// $Id: ssx_api.h,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_api.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -341,39 +363,79 @@
 #endif
 
 
-// Application and kernel tracing.  Tracing can only be enabled if the port
-// defines the trace macros in that case.
-
-/// Enable SSX application tracing
+/// Enable SSX application tracing (enabled by default)
 #ifndef SSX_TRACE_ENABLE
-#define SSX_TRACE_ENABLE 0
+#define SSX_TRACE_ENABLE 1
 #endif
 
-/// Enable SSX kernel tracing
+/// Enable SSX kernel tracing (disabled by default)
 #ifndef SSX_KERNEL_TRACE_ENABLE
 #define SSX_KERNEL_TRACE_ENABLE 0
 #endif
 
 #if !SSX_TRACE_ENABLE
-#define SSX_TRACE(event)
+#define SSX_TRACE(...)
+#define SSX_TRACE_BIN(str, bufp, buf_size)
+#else
+#define SSX_TRACE(...) SSXTRACE(__VA_ARGS__)
+#define SSX_TRACE_BIN(str, bufp, buf_size) SSXTRACE_BIN(str, bufp, buf_size)
 #endif
 
+//Kernel trace macros
 #if !SSX_KERNEL_TRACE_ENABLE
+#define SSX_KERN_TRACE(...)
+#define SSX_KERN_TRACE_ASM16(...)
+#else
+#define SSX_KERN_TRACE(...) SSX_TRACE(__VA_ARGS__)
+#define SSX_KERN_TRACE_ASM16(...) SSX_TRACE_ASM16(__VA_ARGS__)
+#endif  /* SSX_KERNEL_TRACE_ENABLE */
 
-#define SSX_TRACE_THREAD_SLEEP(priority)
-#define SSX_TRACE_THREAD_WAKEUP(priority)
-#define SSX_TRACE_THREAD_SEMAPHORE_PEND(priority)
-#define SSX_TRACE_THREAD_SEMAPHORE_POST(priority)
-#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT(priority)
-#define SSX_TRACE_THREAD_SUSPENDED(priority)
-#define SSX_TRACE_THREAD_DELETED(priority)
-#define SSX_TRACE_THREAD_COMPLETED(priority)
-#define SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority)
-#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority)
-#define SSX_TRACE_THREAD_MAPPED_SLEEPING(priority)
 
+/// Add a string to the trace buffer with an optional register holding a 16bit value
+/// WARNING: This calls a c function which may clobber any of the volatile registers
+#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+#define SSX_TRACE_ASM16(...) TRACE_ASM_HELPER16(VARG_COUNT(__VA_ARGS__), __VA_ARGS__)
+#else
+#define SSX_TRACE_ASM16(...)
+#endif /* SSX_TRACE_SUPPORT */
+
+/// The following macros are helper macros for tracing.  They should not be called
+/// directly.
+#define VARG_COUNT_HELPER(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
+#define VARG_COUNT(...) VARG_COUNT_HELPER(, ##__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
+
+#ifdef __ASSEMBLER__
+#define TRACE_ASM_HELPER16_CALL(count, ...) TINY_TRACE_ASM ## count (__VA_ARGS__)
+#define TRACE_ASM_HELPER16(count, ...) TRACE_ASM_HELPER16_CALL(count, __VA_ARGS__)
+
+#define TINY_TRACE_ASM0()   .error "format string required"
+#define TINY_TRACE_ASM1(str) \
+    .tiny_trace_asm1 trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX)
+#define TINY_TRACE_ASM2(str, reg) \
+    .tiny_trace_asm2 trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX), reg
+#define TINY_TRACE_ASM3()   .error "too many parameters"
+#define TINY_TRACE_ASM4()   .error "too many parameters"
+#define TINY_TRACE_ASM5()   .error "too many parameters"
+#define TINY_TRACE_ASM6()   .error "too many parameters"
+#define TINY_TRACE_ASM7()   .error "too many parameters"
+
+//TODO: add support for tracing more than 1 parameter and binary data in assembly
+
+    .global ssx_trace_tiny
+
+    .macro  .tiny_trace_asm1 hash16
+        lis     %r3, \hash16
+        bl      ssx_trace_tiny
+    .endm
+
+    .macro .tiny_trace_asm2 hash16, parm16
+        clrlwi  %r3, \parm16, 16
+        oris    %r3, %r3, \hash16
+        bl      ssx_trace_tiny
+    .endm
+        
+#endif /*__ASSEMBLER__*/
 
-#endif  /* SSX_KERNEL_TRACE_ENABLE */
 
 
 #ifndef __ASSEMBLER__
@@ -436,6 +498,45 @@ typedef struct {
 #define SSX_SEMAPHORE(sem, initial_count, max_count)                    \
     SsxSemaphore sem = SSX_SEMAPHORE_INITIALIZATION(initial_count, max_count)
 
+/// Trace macros for C functions
+#define HASH_ARG_COMBO(str, arg) \
+    ((((uint32_t)trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX)) << 16) | ((uint32_t)(arg) & 0x0000ffff))
+
+#define SSXTRACE0(...) ssx_trace_tiny() //will fail at compile time
+
+#define SSXTRACE1(str) \
+    ssx_trace_tiny((trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX) << 16))
+
+#define SSXTRACE2(str, parm0) \
+    ((sizeof(parm0) <= 2)? \
+        ssx_trace_tiny(HASH_ARG_COMBO(str, parm0)): \
+        ssx_trace_big(HASH_ARG_COMBO(str, 1), ((uint64_t)parm0) << 32, 0))
+
+#define SSXTRACE3(str, parm0, parm1) \
+        ssx_trace_big(HASH_ARG_COMBO(str, 2), ((((uint64_t)parm0) << 32) | parm1), 0)
+
+#define SSXTRACE4(str, parm0, parm1, parm2) \
+        ssx_trace_big(HASH_ARG_COMBO(str, 3), ((((uint64_t)parm0) << 32) | parm1),\
+                                             ((uint64_t)parm2) << 32 )
+        
+#define SSXTRACE5(str, parm0, parm1, parm2, parm3) \
+        ssx_trace_big(HASH_ARG_COMBO(str, 4), ((((uint64_t)parm0) << 32) | parm1),\
+                                             ((((uint64_t)parm2) << 32) | parm3) )
+
+#define SSXTRACE6(...) ssx_trace_tiny() //will fail at compile time
+#define SSXTRACE7(...) ssx_trace_tiny() //will fail at compile time
+
+#define SSXTRACE_HELPER2(count, ...) SSXTRACE ## count (__VA_ARGS__)
+#define SSXTRACE_HELPER(count, ...) SSXTRACE_HELPER2(count, __VA_ARGS__)
+
+#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+#define SSXTRACE(...) SSXTRACE_HELPER(VARG_COUNT(__VA_ARGS__), __VA_ARGS__)
+#define SSXTRACE_BIN(str, bufp, buf_size) \
+        ssx_trace_binary(((buf_size < 255)? HASH_ARG_COMBO(str, buf_size): HASH_ARG_COMBO(str, 255)), bufp)
+#else
+#define SSXTRACE(...)
+#define SSXTRACE_BIN(str, bufp, buf_size)
+#endif //SSX_TRACE_SUPPORT
 
 /// A generic doubly-linked list object
 ///
@@ -578,6 +679,18 @@ ssx_initialize(SsxAddress  noncritical_stack,
 SsxTimebase
 ssx_timebase_get(void);
 
+#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE
+// Retrieve an external timebase
+SsxTimebase
+ssx_ext_timebase_get(void);
+#else
+static inline SsxTimebase
+ssx_ext_timebase_get(void)
+{
+    return ssx_timebase_get();
+}
+#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */
+
 void
 ssx_timebase_set(SsxTimebase timebase);
 
@@ -707,9 +820,27 @@ ssx_halt() __attribute__ ((noreturn));
 int 
 ssx_deque_sentinel_create(SsxDeque *deque);
 
+#define SSX_DEQUE_SENTINEL_INIT(dq_addr) \
+{\
+    .next = dq_addr, \
+    .previous = dq_addr \
+}
+
+#define SSX_DEQUE_SENTINEL_STATIC_CREATE(deque) \
+    SsxDeque deque = SSX_DEQUE_SENTINEL_INIT(&deque)
+
 int 
 ssx_deque_element_create(SsxDeque *element);
 
+#define SSX_DEQUE_ELEMENT_INIT() \
+{\
+    .next = 0, \
+    .previous = 0 \
+}
+
+#define SSX_DEQUE_ELEMENT_STATIC_CREATE(deque) \
+    SsxDeque deque = SSX_DEQUE_ELEMENT_INIT()
+
 
 /// Check for an empty SsxDeque
 ///
@@ -822,10 +953,29 @@ ssx_deque_delete(SsxDeque *element)
 }
 
 
+//Trace function prototypes
+void ssx_trace_tiny(uint32_t i_parm);
+void ssx_trace_big(uint32_t i_hash_and_count,
+                   uint64_t i_parm1, uint64_t i_parm2);
+void ssx_trace_binary(uint32_t i_hash_and_size, void* bufp);
+void ssx_trace_set_timebase(SsxTimebase timebase);
+void ssx_trace_init(uint32_t timebase_frequency_hz,
+                    SsxTimebase initial_timebase);
+
+
+
 /// Cast a pointer to another type, in a way that won't cause warnings
 
 #define SSX_CAST_POINTER(t, p) ((t)((SsxAddress)(p)))
         
+// Static Assert Macro for Compile time assertions.
+//   - This macro can be used both inside and outside of a function.
+//   - A value of false will cause the ASSERT to produce this error
+//   - This will show up on a compile fail as:
+//      <file>:<line> error: size of array '_static_assert' is negative
+//   - It would be trivial to use the macro to paste a more descriptive
+//     array name for each assert, but we will leave it like this for now.
+#define SSX_STATIC_ASSERT(cond) extern uint8_t _static_assert[(cond) ? 1 : -1]  __attribute__ ((unused))
 
 /// \page ssx_errors SSX API and Kernel Error Handling
 ///
diff --git a/src/ssx/ssx/ssx_core.c b/src/ssx/ssx/ssx_core.c
index 7fa484a..78fffbc 100755..100644
--- a/src/ssx/ssx/ssx_core.c
+++ b/src/ssx/ssx/ssx_core.c
@@ -1,7 +1,29 @@
-// $Id: ssx_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_core.c $                                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_debug_ptrs.c b/src/ssx/ssx/ssx_debug_ptrs.c
new file mode 100644
index 0000000..9247273
--- /dev/null
+++ b/src/ssx/ssx/ssx_debug_ptrs.c
@@ -0,0 +1,78 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_debug_ptrs.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_debug_ptrs.c
+/// \brief Defines a table of pointers to important kernel debug data.
+///
+/// This table is placed in a special section named .debug_ptrs which can be
+/// placed at a well-known memory location for tools to find.
+///
+
+#include "ssx.h"
+#include "ssx_trace.h" 
+#include "ssx_debug_ptrs.h"
+
+
+extern SsxTimebase ppc405_64bit_ext_timebase;
+
+#if SSX_TRACE_SUPPORT
+extern SsxTraceBuffer g_ssx_trace_buf;
+#endif
+
+ssx_debug_ptrs_t ssx_debug_ptrs SECTION_ATTRIBUTE(".debug_ptrs") =
+{
+    .debug_ptrs_size            = sizeof(ssx_debug_ptrs),
+    .debug_ptrs_version         = SSX_DEBUG_PTRS_VERSION,
+
+#if SSX_TRACE_SUPPORT
+    .debug_trace_ptr            = &g_ssx_trace_buf,
+    .debug_trace_size           = sizeof(g_ssx_trace_buf),
+#else
+    .debug_trace_ptr            = 0,
+    .debug_trace_size           = 0,
+#endif /* SSX_TRACE_SUPPORT */
+
+#if SSX_THREAD_SUPPORT
+    .debug_thread_table_ptr     = &__ssx_priority_map,
+    .debug_thread_table_size    = sizeof(__ssx_priority_map),
+    .debug_thread_runq_ptr      = (void*)&__ssx_run_queue,
+    .debug_thread_runq_size     = sizeof(__ssx_run_queue),
+#else
+    .debug_thread_table_ptr     = 0,
+    .debug_thread_table_size    = 0,
+    .debug_thread_runq_ptr      = 0,
+    .debug_thread_runq_size     = 0,
+#endif /* SSX_THREAD_SUPPORT */
+
+    .debug_timebase_ptr         = &ppc405_64bit_ext_timebase,
+    .debug_timebase_size        = sizeof(ppc405_64bit_ext_timebase),
+
+};
+
diff --git a/src/ssx/ssx/ssx_debug_ptrs.h b/src/ssx/ssx/ssx_debug_ptrs.h
new file mode 100644
index 0000000..0ff8097
--- /dev/null
+++ b/src/ssx/ssx/ssx_debug_ptrs.h
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_debug_ptrs.h $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SSX_DEBUG_PTRS_H__
+#define __SSX_DEBUG_PTRS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_debug_ptrs.h
+/// \brief Structure for a table of pointers to kernel debug data
+///
+
+#define SSX_DEBUG_PTRS_VERSION  1
+
+typedef struct
+{
+    // The size and version of this structure
+    unsigned short   debug_ptrs_size;
+    unsigned short   debug_ptrs_version;
+
+    // Trace buffer location and size
+    void*           debug_trace_ptr;
+    unsigned long   debug_trace_size;
+
+    // Thread table location and size
+    void*           debug_thread_table_ptr;
+    unsigned long   debug_thread_table_size;
+
+    // Thread run queue location and size
+    void*           debug_thread_runq_ptr;
+    unsigned long   debug_thread_runq_size;
+
+    // Emulated timebase location and size
+    void*           debug_timebase_ptr;
+    unsigned long   debug_timebase_size;
+
+} ssx_debug_ptrs_t;
+
+#endif /*__SSX_DEBUG_PTRS_H__*/
diff --git a/src/ssx/ssx/ssx_init.c b/src/ssx/ssx/ssx_init.c
index fc12a9b..e2212da 100755..100644
--- a/src/ssx/ssx/ssx_init.c
+++ b/src/ssx/ssx/ssx_init.c
@@ -1,7 +1,29 @@
-// $Id: ssx_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_init.c $                                      */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_kernel.h b/src/ssx/ssx/ssx_kernel.h
index c6a70ca..940fd31 100755..100644
--- a/src/ssx/ssx/ssx_kernel.h
+++ b/src/ssx/ssx/ssx_kernel.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_kernel.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_KERNEL_H__
 #define __SSX_KERNEL_H__
 
-// $Id: ssx_kernel.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_kernel.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_macros.h b/src/ssx/ssx/ssx_macros.h
index 76d3ba7..b20ac83 100755..100644
--- a/src/ssx/ssx/ssx_macros.h
+++ b/src/ssx/ssx/ssx_macros.h
@@ -1,10 +1,32 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_macros.h $                                    */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __SSX_MACROS_H__
 #define __SSX_MACROS_H__
 
-// $Id: ssx_macros.h,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_macros.h,v $
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_semaphore_core.c b/src/ssx/ssx/ssx_semaphore_core.c
index f1f64e8..300628e 100755..100644
--- a/src/ssx/ssx/ssx_semaphore_core.c
+++ b/src/ssx/ssx/ssx_semaphore_core.c
@@ -1,7 +1,29 @@
-// $Id: ssx_semaphore_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_semaphore_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_semaphore_core.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -61,7 +83,7 @@ ssx_semaphore_post(SsxSemaphore *semaphore)
         __ssx_thread_queue_delete(&(semaphore->pending_threads), priority);
         __ssx_thread_queue_insert(&__ssx_run_queue, priority);
 
-        SSX_TRACE_THREAD_SEMAPHORE_POST(priority);
+        SSX_KERN_TRACE("THREAD_SEMAPHORE_POST(%d)", priority);
 
         __ssx_schedule();
 
@@ -183,7 +205,7 @@ ssx_semaphore_pend(SsxSemaphore *semaphore,
         thread->semaphore = semaphore;
         thread->flags |= SSX_THREAD_FLAG_SEMAPHORE_PEND;
 
-        SSX_TRACE_THREAD_SEMAPHORE_PEND(priority);
+        SSX_KERN_TRACE("THREAD_SEMAPHORE_PEND(%d)", priority);
 
         if (timeout != SSX_WAIT_FOREVER) {
             timer = &(thread->timer);
@@ -200,6 +222,7 @@ ssx_semaphore_pend(SsxSemaphore *semaphore,
         if (thread->flags & SSX_THREAD_FLAG_TIMER_PEND) {
             if (thread->flags & SSX_THREAD_FLAG_TIMED_OUT) {
                 rc = -SSX_SEMAPHORE_PEND_TIMED_OUT;
+                __ssx_thread_queue_delete(&(semaphore->pending_threads), thread->priority);
             } else {
                 __ssx_timer_cancel(timer);
             }
diff --git a/src/ssx/ssx/ssx_semaphore_init.c b/src/ssx/ssx/ssx_semaphore_init.c
index 98bba89..9d0c099 100755..100644
--- a/src/ssx/ssx/ssx_semaphore_init.c
+++ b/src/ssx/ssx/ssx_semaphore_init.c
@@ -1,7 +1,29 @@
-// $Id: ssx_semaphore_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_semaphore_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_semaphore_init.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_stack_init.c b/src/ssx/ssx/ssx_stack_init.c
index 9d6331a..ef81fb1 100755..100644
--- a/src/ssx/ssx/ssx_stack_init.c
+++ b/src/ssx/ssx/ssx_stack_init.c
@@ -1,7 +1,29 @@
-// $Id: ssx_stack_init.c,v 1.1.1.1 2013/12/11 21:03:28 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_stack_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_stack_init.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_thread_core.c b/src/ssx/ssx/ssx_thread_core.c
index d6124e8..f6d8a62 100755..100644
--- a/src/ssx/ssx/ssx_thread_core.c
+++ b/src/ssx/ssx/ssx_thread_core.c
@@ -1,7 +1,29 @@
-// $Id: ssx_thread_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_thread_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_thread_core.c $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -98,11 +120,11 @@ __ssx_thread_map(SsxThread* thread)
 
     if (SSX_KERNEL_TRACE_ENABLE) {
         if (__ssx_thread_is_runnable(thread)) {
-            SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority);
+            SSX_KERN_TRACE("THREAD_MAPPED_RUNNABLE(%d)", priority);
         } else if (thread->flags & SSX_THREAD_FLAG_SEMAPHORE_PEND) {
-            SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority);
+            SSX_KERN_TRACE("THREAD_MAPPED_SEMAPHORE_PEND(%d)", priority);
         } else {
-            SSX_TRACE_THREAD_MAPPED_SLEEPING(priority);
+            SSX_KERN_TRACE("THREAD_MAPPED_SLEEPING(%d)", priority);
         }
     }
 }            
@@ -216,9 +238,9 @@ __ssx_thread_delete(SsxThread *thread, SsxThreadState final_state)
 
         if (SSX_KERNEL_TRACE_ENABLE) {
             if (final_state == SSX_THREAD_STATE_DELETED) {
-                SSX_TRACE_THREAD_DELETED(thread->priority);
+                SSX_KERN_TRACE("THREAD_DELETED(%d)", thread->priority);
             } else {
-                SSX_TRACE_THREAD_COMPLETED(thread->priority);
+                SSX_KERN_TRACE("THREAD_COMPLETED(%d)", thread->priority);
             }
         }                
     
@@ -471,7 +493,7 @@ ssx_thread_suspend(SsxThread *thread)
 
     if (__ssx_thread_is_mapped(thread)) {
 
-        SSX_TRACE_THREAD_SUSPENDED(thread->priority);
+        SSX_KERN_TRACE("THREAD_SUSPENDED(%d)", thread->priority);
         __ssx_thread_unmap(thread);
         __ssx_schedule();
     }
@@ -606,7 +628,7 @@ ssx_sleep_absolute(SsxTimebase time)
 
     current->flags |= SSX_THREAD_FLAG_TIMER_PEND;
 
-    SSX_TRACE_THREAD_SLEEP(current->priority);
+    SSX_KERN_TRACE("THREAD_SLEEP(%d)", current->priority);
 
     __ssx_thread_queue_delete(&__ssx_run_queue, current->priority);
     __ssx_schedule();
diff --git a/src/ssx/ssx/ssx_thread_init.c b/src/ssx/ssx/ssx_thread_init.c
index c1a71b5..3fca442 100755..100644
--- a/src/ssx/ssx/ssx_thread_init.c
+++ b/src/ssx/ssx/ssx_thread_init.c
@@ -1,7 +1,29 @@
-// $Id: ssx_thread_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_thread_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_thread_init.c $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_timer_core.c b/src/ssx/ssx/ssx_timer_core.c
index 8153acf..d51c166 100755..100644
--- a/src/ssx/ssx/ssx_timer_core.c
+++ b/src/ssx/ssx/ssx_timer_core.c
@@ -1,7 +1,29 @@
-// $Id: ssx_timer_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_timer_core.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_timer_core.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssx_timer_init.c b/src/ssx/ssx/ssx_timer_init.c
index 6c35ea6..e944fd1 100755..100644
--- a/src/ssx/ssx/ssx_timer_init.c
+++ b/src/ssx/ssx/ssx_timer_init.c
@@ -1,7 +1,29 @@
-// $Id: ssx_timer_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_timer_init.c,v $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/ssx/ssx_timer_init.c $                                */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2014
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
diff --git a/src/ssx/ssx/ssxssxfiles.mk b/src/ssx/ssx/ssxssxfiles.mk
index e78e986..fc5db57 100755..100644
--- a/src/ssx/ssx/ssxssxfiles.mk
+++ b/src/ssx/ssx/ssxssxfiles.mk
@@ -1,11 +1,33 @@
-# $Id: ssxssxfiles.mk,v 1.2 2014/06/26 13:02:00 cmolsen Exp $
-# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssxssxfiles.mk,v $
-#  @file ssxpgpfiles.mk
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
 #
-#  @brief mk for including pgp object files
+# $Source: src/ssx/ssx/ssxssxfiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2014,2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file ssxssxfiles.mk
+#
+#  @brief mk for including ssx object files
 #
 #  @page ChangeLogs Change Logs
-#  @section ssxpgpfiles.mk
+#  @section ssxssxfiles.mk
 #  @verbatim
 #
 #
@@ -24,7 +46,7 @@
 ##########################################################################
 # Object Files 
 ##########################################################################
-SSX-C-SOURCES = ssx_core.c ssx_init.c ssx_stack_init.c
+SSX-C-SOURCES = ssx_core.c ssx_init.c ssx_stack_init.c ssx_debug_ptrs.c
 
 SSX-TIMER-C-SOURCES += ssx_timer_core.c ssx_timer_init.c
 
diff --git a/src/ssx/trace/Makefile b/src/ssx/trace/Makefile
new file mode 100644
index 0000000..5506b32
--- /dev/null
+++ b/src/ssx/trace/Makefile
@@ -0,0 +1,50 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/trace/Makefile $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile is designed to be invoked with the -I argument set to
+# the location of the "ssx.mk" for the build
+
+include img_defs.mk
+include ssxtracefiles.mk
+
+ifeq "$(SSX_TIMER_SUPPORT)" "1"
+SSXTRACE_OBJECTS += ${SSXTRACE-TIMER-C-SOURCES:.c=.o} ${SSXTRACE-TIMER-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(SSX_THREAD_SUPPORT)" "1"
+SSXTRACE_OBJECTS += ${SSXTRACE-THREAD-C-SOURCES:.c=.o} ${SSXTRACE-THREAD-S-SOURCES:.S=.o}
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(SSXTRACE_OBJECTS))
+
+all: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
diff --git a/src/ssx/trace/ssx_trace.h b/src/ssx/trace/ssx_trace.h
new file mode 100644
index 0000000..c79452b
--- /dev/null
+++ b/src/ssx/trace/ssx_trace.h
@@ -0,0 +1,303 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/trace/ssx_trace.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __SSX_TRACE_H__
+#define __SSX_TRACE_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_trace.h
+/// \brief Macros and declarations for the SSX Firmware Tracing Facility.
+/// 
+
+#include <stdint.h>
+
+#define SSX_TRACE_VERSION 2
+
+#ifndef SSX_TRACE_SZ
+#define SSX_TRACE_SZ 256
+#endif
+
+//Fail compilation if size is not a power of 2
+#if ((SSX_TRACE_SZ - 1) & SSX_TRACE_SZ)
+#error "SSX_TRACE_SZ is not a power of two!!!"
+#endif
+
+//Fail compilation if size is smaller than 64 bytes
+#if (SSX_TRACE_SZ < 64)
+#error "SSX_TRACE_SZ must be at least 64 bytes!!!"
+#endif
+
+//Mask for calculating offsets into the trace circular buffer
+#define SSX_TRACE_CB_MASK (SSX_TRACE_SZ - 1)
+
+#define STRINGIFY_HELPER(x) #x
+#define STRINGIFY(x) STRINGIFY_HELPER(x)
+
+#define PPC_IMG_STRING STRINGIFY(IMAGE_NAME)
+
+#ifdef SSX_TRACE_HASH_PREFIX
+#if (SSX_TRACE_HASH_PREFIX > 0xffff)
+#error SSX_TRACE_HASH_PREFIX must be defined as a 16 bit constant value
+#endif
+#endif //SSX_TRACE_HASH_PREFIX
+
+//This provides a 128ns tick (assuming a 32ns clock period)
+//and 4 different format values
+#define SSX_TRACE_TS_BITS 30
+
+#define SSX_TRACE_FORMAT_BITS (32 - SSX_TRACE_TS_BITS)
+
+#define SSX_TRACE_TS_MASK (0xfffffffful << SSX_TRACE_FORMAT_BITS)
+#define SSX_TRACE_FORMAT_MASK (~SSX_TRACE_TS_MASK)
+
+#define SSX_GET_TRACE_FORMAT(w32) (SSX_TRACE_FORMAT_MASK & w32)
+#define SSX_GET_TRACE_TIME(w32) (SSX_TRACE_TS_MASK & w32)
+
+//Set the trace timer period to be the maximum
+//32 bit time minus 2 seconds (assuming a 32ns tick)
+//This allows for up to 1 second of interrupt latency +
+//1 second for SSX_TRACE_MTBT while only requiring a trace
+//every 135 seconds in order to maintain the 64bit timebase.
+#define SSX_TRACE_TIMER_PERIOD (0xfffffffful - 62500000)
+
+//The Maximum Time Between Traces. In order to reduce the time that interrupts
+//are disabled for tracing, reading of the time stamp is not done atomically
+//with alocating an entry in the circular buffer.  This means that the
+//timestamps might not appear in order in the trace buffer. This is a
+//problem because our calculation of the 64 bit timebase uses the unsigned
+//difference of the current 32bit timestamp and the previous one and if they
+//are out of order it will result in a very large difference.  To solve this
+//problem, any time that the parser code sees a very large difference (larger
+//than SSX_TRACE_MTBT) it will treat it as a negative number.
+#define SSX_TRACE_MTBT (0xfffffffful - 31250000) 
+
+#define SSX_TRACE_MAX_PARMS  4
+
+//This is the maximum number of bytes allowed to be traced in a binary trace
+//entry.
+//The trace version needs to change if this changes.
+#define SSX_TRACE_MAX_BINARY 256
+
+//clip the largest binary trace according to the trace buffer size.
+//(The trace version does not need to change if this changes as long
+// as it remains less than SSX_TRACE_MAX_BINARY)
+#if (SSX_TRACE_SZ <= 256)
+#define SSX_TRACE_CLIPPED_BINARY_SZ SSX_TRACE_SZ / 2
+#else
+#define SSX_TRACE_CLIPPED_BINARY_SZ SSX_TRACE_MAX_BINARY
+#endif
+
+//Trace formats that are supported
+typedef enum
+{
+    SSX_TRACE_FORMAT_EMPTY,
+    SSX_TRACE_FORMAT_TINY,
+    SSX_TRACE_FORMAT_BIG,
+    SSX_TRACE_FORMAT_BINARY,
+}SsxTraceFormat;
+
+//This combines the timestamp and the format bits into a
+//single 32 bit word.
+typedef union
+{
+    struct
+    {
+        uint32_t    timestamp   : SSX_TRACE_TS_BITS;
+        uint32_t    format      : SSX_TRACE_FORMAT_BITS;
+    };
+    uint32_t word32;
+}SsxTraceTime;
+
+//SSX trace uses a 16 bit string format hash value
+typedef uint16_t SsxTraceHash;
+
+//The constant 16 bit hash value is combined with a
+//16 bit parameter value when doing a tiny trace
+typedef union
+{
+    struct
+    {
+        SsxTraceHash        string_id;
+        uint16_t            parm;
+    };
+    uint32_t    word32;
+}SsxTraceTinyParms;
+
+//A tiny trace fits within a single 8 byte word. This includes
+//the timestamp, format bits, hash id, and a 16 bit parameter.
+typedef union
+{
+    struct
+    {
+        SsxTraceTinyParms   parms;
+        SsxTraceTime        time_format; 
+    };
+    uint64_t    word64;
+}SsxTraceTiny;
+
+//Larger traces that require a 32 bit parameter or more than one
+//parameter use the big trace format.  The number of parms and
+//the 'complete' flag are combined with the hash id. 'complete'
+//is set to 0 initially and set to one only after all of the trace
+//data has been written.
+typedef union
+{
+    struct
+    {
+        SsxTraceHash        string_id;
+        uint8_t             complete;
+        uint8_t             num_parms;
+    };
+    uint32_t    word32;
+}SsxTraceBigParms;
+
+typedef union
+{
+    struct
+    {
+        SsxTraceBigParms    parms;
+        SsxTraceTime        time_format; 
+    };
+    uint64_t    word64;
+}SsxTraceBig;
+
+//Binary traces are handled in a similar fashion to big traces, except
+//that instead of having a number of parameters, we have number of bytes.
+typedef union
+{
+    struct
+    {
+        SsxTraceHash        string_id;
+        uint8_t             complete;
+        uint8_t             num_bytes;
+    };
+    uint32_t    word32;
+}SsxTraceBinaryParms;
+
+typedef union
+{
+    struct
+    {
+        SsxTraceBinaryParms  parms;
+        SsxTraceTime         time_format;
+    };
+    uint64_t    word64;
+}SsxTraceBinary;
+
+//This is a generic structure that can be used to retrieve data
+//for tiny, big, and binary formatted entries.
+typedef union
+{
+    struct
+    {
+        SsxTraceHash        string_id;
+        union
+        {
+            uint16_t        parm16;
+            struct
+            {
+                uint8_t     complete;
+                uint8_t     bytes_or_parms_count;
+            };
+        };
+        SsxTraceTime        time_format;
+    };
+    uint64_t    word64;
+}SsxTraceGeneric;
+
+//This is a format that might be used in the future for tracing
+//a 64 bit timestamp so that we don't fill up the buffer with periodic
+//timer traces.  It is not currently used.
+#if 0
+typedef union
+{
+    struct
+    {
+        uint32_t            upper32;
+        SsxTraceTime        time_format;
+    };
+    uint64_t    word64;
+}SsxTraceTime64;
+#endif
+
+//It would probably be more accurate to call this a footer since it
+//actually resides at the highest address of each trace entry. These eight
+//bytes contain information that allow us to walk the trace buffer from the
+//most recent entry to the oldest entry.
+typedef union
+{
+    SsxTraceGeneric      generic;
+    SsxTraceBinary       binary;
+    SsxTraceBig          big;
+    SsxTraceTiny         small;
+}SsxTraceEntryFooter;
+
+
+//This is the data that is updated (in the buffer header) every time we add
+//a new entry to the buffer.
+typedef union
+{
+    struct
+    {
+        uint32_t  tbu32;
+        uint32_t  offset;
+    };
+    uint64_t word64;
+}SsxTraceState;
+
+#define SSX_TRACE_IMG_STR_SZ 16
+
+//Header data for the trace buffer that is used for parsing the data.
+//Note: SsxTraceState contains a uint64_t which is required to be
+//placed on an 8-byte boundary according to the EABI Spec.  This also
+//causes cb to start on an 8-byte boundary.
+typedef struct
+{
+    //these values are needed by the parser
+    uint16_t            version;
+    uint16_t            rsvd;
+    char                image_str[SSX_TRACE_IMG_STR_SZ];
+    uint16_t            instance_id;
+    uint16_t            partial_trace_hash;
+    uint16_t            hash_prefix;
+    uint16_t            size;
+    uint32_t            max_time_change;
+    uint32_t            hz;
+    uint32_t            pad;
+    uint64_t            time_adj64;
+
+    //updated with each new trace entry
+    SsxTraceState       state;
+
+    //circular trace buffer
+    uint8_t             cb[SSX_TRACE_SZ];
+}SsxTraceBuffer;
+
+extern SsxTraceBuffer g_ssx_trace_buf;
+
+#endif /* __SSX_TRACE_H__ */
diff --git a/src/ssx/trace/ssx_trace_big.c b/src/ssx/trace/ssx_trace_big.c
new file mode 100644
index 0000000..4a9bdb5
--- /dev/null
+++ b/src/ssx/trace/ssx_trace_big.c
@@ -0,0 +1,116 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/trace/ssx_trace_big.c $                               */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_trace_big.c
+/// \brief SSX Trace function that supports up to four 32-bit parameters
+///
+/// The ssx_trace_big function is only called (via some macro magic) if the
+/// caller passes in a single parameter (not including the format string)
+/// that is larger than 16 bits to the SSX_TRACE(...) macro.
+///
+
+#include "ssx.h"
+#include "ssx_trace.h"
+
+#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+void ssx_trace_big(uint32_t i_hash_and_count,
+                  uint64_t i_parm1, uint64_t i_parm2)
+{
+    SsxTraceBig         footer;
+    SsxTraceBig*        footer_ptr;
+    SsxTraceState       state;
+    uint64_t*           ptr64;
+    uint64_t            tb64;
+    SsxMachineContext   ctx;
+    uint32_t            parm_size;
+    uint32_t            cur_offset;
+    uint32_t            footer_offset;
+
+    //fill in the footer data
+    tb64 = ssx_ext_timebase_get();
+    footer.parms.word32 = i_hash_and_count; //this has the parm count and hash
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+    footer.time_format.format = SSX_TRACE_FORMAT_BIG;
+
+    //round up to 8 byte boundary
+    if(footer.parms.num_parms <= 2)
+    {
+        parm_size = 8;
+    }
+    else
+    {
+        parm_size = 16;
+    }
+
+    //*****The following operations must be done atomically*****
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    //load in the offset in the cb for the entry we are adding
+    cur_offset = g_ssx_trace_buf.state.offset;
+
+    //Find the offset for the footer (at the end of the entry)
+    footer_offset = cur_offset + parm_size;
+
+    //calculate the address of the footer
+    ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[footer_offset & SSX_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = footer_offset + sizeof(SsxTraceBig);
+
+    //update the cb state (tbu and offset)
+    g_ssx_trace_buf.state.word64 = state.word64;
+
+    //write the data to the circular buffer including the
+    //timesamp, string hash, and 16bit parameter
+    *ptr64 = footer.word64;
+
+    //*******************exit the critical section***************
+    ssx_critical_section_exit(&ctx);
+
+
+    //write parm values to the circular buffer
+    footer_ptr = (SsxTraceBig*)ptr64;
+    ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[cur_offset & SSX_TRACE_CB_MASK];
+    *ptr64 = i_parm1;
+    if(parm_size > 8)
+    {
+        ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[(cur_offset + 8) & SSX_TRACE_CB_MASK];
+        *ptr64 = i_parm2;
+    }
+
+    //Mark the trace entry update as being completed
+    footer_ptr->parms.complete = 1;
+
+}
+
+#endif
+
+
diff --git a/src/ssx/trace/ssx_trace_binary.c b/src/ssx/trace/ssx_trace_binary.c
new file mode 100644
index 0000000..f1d1db6
--- /dev/null
+++ b/src/ssx/trace/ssx_trace_binary.c
@@ -0,0 +1,115 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/trace/ssx_trace_binary.c $                            */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_trace_binary.c
+/// \brief SSX Trace function for dumping memory contents
+///
+/// The ssx_trace_binary function is called by the SSX_TRACE_BINARY() macro.
+///
+
+
+#include "ssx.h"
+#include "ssx_trace.h"
+
+#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+void ssx_trace_binary(uint32_t i_hash_and_size, void* bufp)
+{
+    SsxTraceBinary          footer;
+    SsxTraceBinary*         footer_ptr;
+    SsxTraceState           state;
+    uint64_t*               ptr64;
+    uint64_t                tb64;
+    SsxMachineContext       ctx;
+    uint32_t                data_size;
+    uint32_t                cb_offset;
+    uint32_t                footer_offset;
+    uint8_t*                dest;
+    uint8_t*                src;
+    uint32_t                index;
+
+    //fill in the footer data
+    tb64 = ssx_ext_timebase_get();
+    footer.parms.word32 = i_hash_and_size; //this has the size and hash
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+    footer.time_format.format = SSX_TRACE_FORMAT_BINARY;
+
+    //round up to 8 byte boundary
+    data_size = (footer.parms.num_bytes + 7) & ~0x00000007ul;
+
+    //limit data size
+    if(data_size > SSX_TRACE_CLIPPED_BINARY_SZ)
+    {
+        data_size = SSX_TRACE_CLIPPED_BINARY_SZ;
+    }
+
+    //*****The following operations must be done atomically*****
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    //load in the offset in the cb for the entry we are adding
+    cb_offset = g_ssx_trace_buf.state.offset;
+
+    //Find the offset for the footer (at the end of the entry)
+    footer_offset = cb_offset + data_size;
+
+    //calculate the address of the footer
+    ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[footer_offset & SSX_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = footer_offset + sizeof(SsxTraceBinary);
+
+    //update the cb state (tbu and offset)
+    g_ssx_trace_buf.state.word64 = state.word64;
+
+    //write the footer data to the circular buffer including the
+    //timesamp, string hash and data size
+    *ptr64 = footer.word64;
+
+    //*******************exit the critical section***************
+    ssx_critical_section_exit(&ctx);
+
+    //write data to the circular buffer
+    for(src = bufp, index = 0;
+        index < data_size;
+        index++)
+    {
+        dest = &g_ssx_trace_buf.cb[(cb_offset + index) & SSX_TRACE_CB_MASK];
+        *dest = *(src++);
+    }
+
+    //Mark the trace entry update as being completed
+    footer_ptr = (SsxTraceBinary*)ptr64;
+    footer_ptr->parms.complete = 1;
+
+}
+
+#endif
+
+
diff --git a/src/ssx/trace/ssx_trace_core.c b/src/ssx/trace/ssx_trace_core.c
new file mode 100644
index 0000000..a2db4b8
--- /dev/null
+++ b/src/ssx/trace/ssx_trace_core.c
@@ -0,0 +1,165 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/ssx/trace/ssx_trace_core.c $                              */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ssx_trace_core.c
+/// \brief SSX Trace core data and code.
+///
+/// This file includes the minimal code/data required to do minimal tracing.
+/// This includes the periodic timer initialization and the ssx_trace_tiny
+/// function.  The ssx_trace_tiny function is called by the SSX_TRACE() macro
+/// when there is one or less parameters (not including the format string)
+/// and the parameter size is 16 bits or smaller.
+///
+
+#include "ssx.h"
+#include "ssx_trace.h"
+
+void ssx_trace_timer_callback(void* arg);
+
+#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+
+//Static initialization of the trace timer
+SsxTimer g_ssx_trace_timer = {
+    .deque = SSX_DEQUE_ELEMENT_INIT(),
+    .timeout = 0,
+    .callback = ssx_trace_timer_callback,
+    .arg = 0,
+    .options = SSX_TIMER_CALLBACK_PREEMPTIBLE,
+};
+
+//Static initialization of the ssx trace buffer
+SsxTraceBuffer g_ssx_trace_buf =
+{
+    .version            = SSX_TRACE_VERSION,
+    .image_str          = PPC_IMG_STRING,
+    .hash_prefix        = SSX_TRACE_HASH_PREFIX,
+    .partial_trace_hash = trace_ppe_hash("PARTIAL TRACE ENTRY. HASH_ID = %d", SSX_TRACE_HASH_PREFIX),
+    .size               = SSX_TRACE_SZ,
+    .max_time_change    = SSX_TRACE_MTBT,
+    .hz                 = 500000000, //default value. Actual value is set in ssx_init.c
+    .time_adj64         = 0,
+    .state.word64       = 0,
+    .cb                 = {0}
+};
+
+//Needed for buffer extraction in simics for now
+SsxTraceBuffer* g_ssx_trace_buf_ptr = &g_ssx_trace_buf;
+
+// Creates an 8 byte entry in the trace buffer that includes a timestamp,
+// a format string hash value and a 16 bit parameter.
+//
+// i_parm has the hash value combined with the 16 bit parameter
+void ssx_trace_tiny(uint32_t i_parm)
+{
+    SsxTraceTiny        footer;
+    SsxTraceState       state;
+    uint64_t*           ptr64;
+    uint64_t            tb64;
+    SsxMachineContext   ctx;
+
+    //fill in the footer data
+    footer.parms.word32 = i_parm;
+    tb64 = ssx_ext_timebase_get();
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+    
+    footer.time_format.format = SSX_TRACE_FORMAT_TINY;
+
+    //The following operations must be done atomically
+    ssx_critical_section_enter(SSX_NONCRITICAL, &ctx);
+
+    //load the current byte count and calculate the address for this
+    //entry in the cb
+    ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[g_ssx_trace_buf.state.offset & SSX_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = g_ssx_trace_buf.state.offset + sizeof(SsxTraceTiny);
+
+    //update the cb state (tbu and offset)
+    g_ssx_trace_buf.state.word64 = state.word64;
+
+    //write the data to the circular buffer including the
+    //timesamp, string hash, and 16bit parameter
+    *ptr64 = footer.word64;
+
+    //exit the critical section
+    ssx_critical_section_exit(&ctx);
+}
+
+
+// This function is called periodically in order to ensure that the max ticks
+// between trace entries is no more than what will fit inside a 32bit value.
+void ssx_trace_timer_callback(void* arg)
+{
+
+    // guarantee at least one trace before the lower 32bit timebase flips
+    SSX_TRACE("PERIODIC TIMESTAMPING TRACE");
+
+    // restart the timer
+    ssx_timer_schedule(&g_ssx_trace_timer,
+                      SSX_TRACE_TIMER_PERIOD,
+                      0);
+}
+
+// Use this function to synchronize the timebase between multiple Processors.
+// proc A can send proc B it's current timebase and then proc B can set that
+// as the current timebase for tracing purposes.  It can also be used
+// to set the current time to 0.  This function changes the timebase for
+// all entries that are currently in the trace buffer.  Setting the current
+// timebase to 0 will cause previous traces to have very large timestamps.
+void ssx_trace_set_timebase(SsxTimebase timebase)
+{
+    g_ssx_trace_buf.time_adj64 = timebase - ssx_ext_timebase_get();
+}
+
+void ssx_trace_init(uint32_t    timebase_frequency_hz,
+                    SsxTimebase initial_timebase)
+{
+    //set the trace timebase HZ (used by parsing tools)
+    g_ssx_trace_buf.hz = timebase_frequency_hz;
+
+    if(initial_timebase != SSX_TIMEBASE_CONTINUES)
+    {
+        //Set the timebase adjustment.  The external timebase
+        //is not adjustable so we use a software adjustment instead.
+        //Typically, this should only be used by the first processor to come
+        //up in order to set the timebase to 0.  Other processors
+        //will want to synchronize with the first processor's timebase.
+        ssx_trace_set_timebase(initial_timebase);
+    }
+
+    // Schedule the timer that puts a timestamp in the trace buffer
+    // periodically.  This allows us to use 32bit timestamps.
+    ssx_timer_schedule(&g_ssx_trace_timer,
+                       SSX_TRACE_TIMER_PERIOD,
+                       0);
+}
+
+#endif
diff --git a/src/ssx/trace/ssxtracefiles.mk b/src/ssx/trace/ssxtracefiles.mk
new file mode 100644
index 0000000..dc3d058
--- /dev/null
+++ b/src/ssx/trace/ssxtracefiles.mk
@@ -0,0 +1,63 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/ssx/trace/ssxtracefiles.mk $
+#
+# OpenPOWER OnChipController Project
+#
+# Contributors Listed Below - COPYRIGHT 2015
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file ssxtracefiles.mk
+#
+#  @brief mk for including SSX trace object files
+#
+#  @page ChangeLogs Change Logs
+#  @section ssxtracefiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Include Files
+##########################################################################
+
+			
+
+##########################################################################
+# Object Files
+##########################################################################
+SSXTRACE-C-SOURCES = ssx_trace_core.c ssx_trace_big.c ssx_trace_binary.c
+				   
+SSXTRACE-S-SOURCES = 
+
+SSXTRACE-TIMER-C-SOURCES = 
+SSXTRACE-TIMER-S-SOURCES = 
+
+SSXTRACE-THREAD-C-SOURCES += 
+SSXTRACE-THREAD-S-SOURCES += 
+
+
+SSXTRACE_OBJECTS += $(SSXTRACE-C-SOURCES:.c=.o) $(SSXTRACE-S-SOURCES:.S=.o)
+
+
+