Fix Ping Pong and HOMER addresses, usign new P9 pba_region default value.

The new P9 pba_region field in the PBA_MODE register is now 0b10
contrary to the P8 pba_region setting of 0b00.

Addresses have been corrected for Ping Pong communications,
HOMER Host Data, Sapphire Table, and HTMGT send and receive Buffers.

Replaced Sapphire legacy term with OPAL.

Defined COMMON_BASE_ADDRESS, and offset addresses relative to it.

modified HOMER_HD_OFFSET, OCC_HTMGT_CMD_OFFSET_HOMER,
OCC_HTMGT_RSP_OFFSET_HOMER, and OPAL_OFFSET_HOMER according
to new P9 specifications.

Change-Id: Ib233181c4ad1837b57c45144d1256b87799dc5bc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24085
Tested-by: FSP CI Jenkins
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

15 files changed, 123 insertions, 98 deletions

diff --git a/src/occ_405/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index 20578fa..d497223 100755
--- a/src/occ_405/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
@@ -38,6 +38,7 @@
 #include "cmdh_tunable_parms.h"
 #include "cmdh_snapshot.h"
 #include "scom.h"
+#include "homer.h"
 
 // OCB Channel Setup Defines
 const int      OCB_CHANNEL_FSP_LINEAR          = 0;
@@ -469,7 +470,7 @@ errlHndl_t cmdh_fsp_cmd_hndler(void)
             // Set up a copy request
             l_ssxrc = bce_request_create(&pba_copy,                           // block copy object
                                          &G_pba_bcde_queue,                   // mainstore to sram copy engine
-                                         OCC_HTMGT_CMD_OFFSET_HOMER,          // mainstore address
+                                         OCC_HTMGT_CMD_ADDRESS_HOMER,         // mainstore address
                                          (uint32_t) &G_htmgt_cmd_buffer,      // sram starting address
                                          (size_t) sizeof(G_htmgt_cmd_buffer), // size of copy
                                          SSX_WAIT_FOREVER,                    // no timeout
@@ -530,7 +531,7 @@ errlHndl_t cmdh_fsp_cmd_hndler(void)
             // Need to write the response to HOMER. Set up a copy request
             l_ssxrc = bce_request_create(&pba_copy,                           // block copy object
                                          &G_pba_bcue_queue,                   // sram to mainstore copy engine
-                                         OCC_HTMGT_RSP_OFFSET_HOMER,          // mainstore address
+                                         OCC_HTMGT_RSP_ADDRESS_HOMER,         // mainstore address
                                          (uint32_t) &G_htmgt_rsp_buffer,      // sram starting address
                                          (size_t) sizeof(G_htmgt_rsp_buffer), // size of copy
                                          SSX_WAIT_FOREVER,                    // no timeout
@@ -630,7 +631,7 @@ errlHndl_t cmdh_fsp_cmd_hndler(void)
             // Need to write the final response to HOMER. Set up a copy request
             l_ssxrc = bce_request_create(&pba_copy,                           // block copy object
                                          &G_pba_bcue_queue,                   // sram to mainstore copy engine
-                                         OCC_HTMGT_RSP_OFFSET_HOMER,          // mainstore address
+                                         OCC_HTMGT_RSP_ADDRESS_HOMER,         // mainstore address
                                          (uint32_t) &G_htmgt_rsp_buffer,      // sram starting address
                                          (size_t) sizeof(G_htmgt_rsp_buffer), // size of copy
                                          SSX_WAIT_FOREVER,                    // no timeout
diff --git a/src/occ_405/cmdh/cmdh_fsp.h b/src/occ_405/cmdh/cmdh_fsp.h
index 486f447..49d7fc9 100755
--- a/src/occ_405/cmdh/cmdh_fsp.h
+++ b/src/occ_405/cmdh/cmdh_fsp.h
@@ -90,11 +90,6 @@
 // Attention type of an attention to the OCC
 #define ATTN_TYPE_CMD_WRITE       0x01
 
-// OCC/HTMGT command buffer offset in HOMER
-#define OCC_HTMGT_CMD_OFFSET_HOMER    0x001EE000
-// OCC/HTMGT response buffer offset in HOMER
-#define OCC_HTMGT_RSP_OFFSET_HOMER    0x001EF000
-
 // Typedef of the various reasons why the cmdh thread wakes up
 typedef enum
 {
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c
index c437f9b..3b7da38 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c
@@ -45,6 +45,7 @@
 #include "chom.h"
 #include "amec_master_smh.h"
 #include <proc_data.h>
+#include "homer.h"
 
 // This table contains tunable parameter information that can be exposed to
 // customers (only Master OCC should access/control this table)
@@ -561,7 +562,7 @@ errlHndl_t cmdh_reset_prep (const cmdh_fsp_cmd_t * i_cmd_ptr,
 
         if (G_sysConfigData.system_type.kvm && isSafeStateRequested())
         {
-            // Notify dcom thread to update sapphire table
+            // Notify dcom thread to update opal table
             ssx_semaphore_post(&G_dcomThreadWakeupSem);
         }
         if (CURRENT_STATE() != OCC_STATE_STANDBY)
@@ -807,8 +808,6 @@ void cmdh_dbug_peek (const cmdh_fsp_cmd_t * i_cmd_ptr,
     uint8_t            l_type    = l_cmd_ptr->type;
     uint32_t           l_addr    = l_cmd_ptr->oci_address;
 
-// Needed because otherwise we get warnings about
-// unused variables when building for Simics
 #if PPC405_MMU_SUPPORT
     static Ppc405MmuMap       L_mmuMapHomer;
     static Ppc405MmuMap       L_mmuMapCommon;
@@ -848,19 +847,19 @@ void cmdh_dbug_peek (const cmdh_fsp_cmd_t * i_cmd_ptr,
             // Map mainstore to oci space so that we can peek at it
 
             // HOMER Image
-            ppc405_mmu_map(0x00000000, // Mainstore address (BAR0, offset 0)
-                           0x00000000, // OCI address 0x0 (BAR0)
-                           0x400000,   // Size = 4 MB
-                           0,          // TLB hi flags
-                           0,          // TLB lo flags
+            ppc405_mmu_map(HOMER_BASE_ADDRESS, // Mainstore address (BAR0, offset 0)
+                           HOMER_BASE_ADDRESS, // OCI address 0x0 (BAR0)
+                           HOMER_SPACE_SIZE,   // Size
+                           0,                  // TLB hi flags
+                           0,                  // TLB lo flags
                            &L_mmuMapHomer); // map pointer
 
             // COMMON Image = Communal OCC Memory Map On Node
-            ppc405_mmu_map(0x30000000, // Mainstore address (BAR3, offset 0)
-                           0x30000000, // OCI address 0x30000000
-                           0x00800000, // Size = 8 MB
-                           0,          // TLB hi flags
-                           0,          // TLB lo flags
+            ppc405_mmu_map(COMMON_BASE_ADDRESS, // Mainstore address (BAR2, offset 0)
+                           COMMON_BASE_ADDRESS, // OCI address 0xA0000000
+                           COMMON_SPACE_SIZE,   // Size
+                           0,                              // TLB hi flags
+                           0,                              // TLB lo flags
                            &L_mmuMapCommon); // map pointer
             l_len = 0;
             break;
@@ -1090,7 +1089,7 @@ errlHndl_t cmdh_tmgt_setmodestate(const cmdh_fsp_cmd_t * i_cmd_ptr,
     OCC_STATE                       l_pre_state    = CURRENT_STATE();
     OCC_MODE                        l_pre_mode     = CURRENT_MODE();
 
-    // SAPPHIRE only accepts DPS-FE mode. In case OCC gets other modes, it should accept the request
+    // OPAL only accepts DPS-FE mode. In case OCC gets other modes, it should accept the request
     // and keep reporting back that it is in that mode.
     if(G_sysConfigData.system_type.kvm)
     {
diff --git a/src/occ_405/dcom/dcom.h b/src/occ_405/dcom/dcom.h
index 55f59e3..dc960d0 100755
--- a/src/occ_405/dcom/dcom.h
+++ b/src/occ_405/dcom/dcom.h
@@ -49,9 +49,18 @@
 #define OCC_DCM_SLAVE     0
 #define OCC_DCM_MASTER    1
 
-// OCC Master to Slave Messages (inbox ping/pong) - Moved to BAR2
-#define ADDR_SLAVE_INBOX_MAIN_MEM_PING 0x20000000
-#define ADDR_SLAVE_INBOX_MAIN_MEM_PONG 0x20000800
+// Memory address space where DCOM, sensor data, OPAL communications,
+// etc take place. Uses BAR2, with pba_region = 0b10
+#define COMMON_BASE_ADDRESS 0xA0000000
+#define COMMON_SPACE_SIZE   0x00800000     // 8 MB
+
+// Occ Master to Slave Messages (inbox ping/pong)
+#define SLAVE_INBOX_PING_COMMON_OFFSET     0x00000000
+#define SLAVE_INBOX_PING_COMMON_ADDRESS    (COMMON_BASE_ADDRESS+SLAVE_INBOX_PING_COMMON_OFFSET)
+
+#define SLAVE_INBOX_PONG_COMMON_OFFSET     0x00000800
+#define SLAVE_INBOX_PONG_COMMON_ADDRESS    (COMMON_BASE_ADDRESS+SLAVE_INBOX_PONG_COMMON_OFFSET)
+
 #define NUM_BYTES_IN_SLAVE_INBOX              256
 
 // Magic Number used to denote the end of Master->Slave Broadcast packets
@@ -66,9 +75,13 @@
 #define PBAX_BROADCAST_GROUP          PBAX_GROUP_MASK_MAX
 
 
-// OCC Slave to Master Messages (inbox ping/pong) - Moved to BAR2
-#define ADDR_SLAVE_OUTBOX_MAIN_MEM_PING 0x20001000
-#define ADDR_SLAVE_OUTBOX_MAIN_MEM_PONG 0x20003000
+// OCC Slave to Master Messages (inbox ping/pong)
+#define SLAVE_OUTBOX_PING_COMMON_OFFSET     0x00001000
+#define SLAVE_OUTBOX_PING_COMMON_ADDRESS    (COMMON_BASE_ADDRESS+SLAVE_OUTBOX_PING_COMMON_OFFSET)
+
+#define SLAVE_OUTBOX_PONG_COMMON_OFFSET     0x00003000
+#define SLAVE_OUTBOX_PONG_COMMON_ADDRESS    (COMMON_BASE_ADDRESS+SLAVE_OUTBOX_PONG_COMMON_OFFSET)
+
 #define NUM_BYTES_IN_SLAVE_OUTBOX             1024
 
 // GP REG0
diff --git a/src/occ_405/dcom/dcomMasterRx.c b/src/occ_405/dcom/dcomMasterRx.c
index fcd6662..e1a7d30 100644
--- a/src/occ_405/dcom/dcomMasterRx.c
+++ b/src/occ_405/dcom/dcomMasterRx.c
@@ -133,8 +133,8 @@ void task_dcom_rx_slv_outboxes( task_t *i_self)
             l_slv_response_mask |= (0x01 << l_slv);
 
             // Check valid address (should be inside inbox addresses range)
-            if ( (ADDR_SLAVE_OUTBOX_MAIN_MEM_PING <= l_addr) &&
-                 ((ADDR_SLAVE_OUTBOX_MAIN_MEM_PONG+(sizeof(dcom_slv_outbox_t)*MAX_OCCS)) > l_addr) )
+            if ( (SLAVE_OUTBOX_PING_COMMON_ADDRESS <= l_addr) &&
+                 ((SLAVE_OUTBOX_PONG_COMMON_ADDRESS+(sizeof(dcom_slv_outbox_t)*MAX_OCCS)) > l_addr) )
             {
                 DCOM_DBG("2.X. Copy down Slave Outboxes from %x\n",l_addr);
                 uint32_t l_ssxrc = 0;
diff --git a/src/occ_405/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index d166aef..8d660c0 100644
--- a/src/occ_405/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -210,12 +210,12 @@ uint32_t dcom_build_slv_inbox(void)
 uint32_t dcom_which_buffer(void)
 {
     //Locals
-    uint32_t l_mem_address = ADDR_SLAVE_INBOX_MAIN_MEM_PONG;
+    uint32_t l_mem_address = SLAVE_INBOX_PONG_COMMON_ADDRESS;
 
     // Switch back and forth based on tick
     if( CURRENT_TICK & 1 )
     {
-        l_mem_address = ADDR_SLAVE_INBOX_MAIN_MEM_PING;
+        l_mem_address = SLAVE_INBOX_PING_COMMON_ADDRESS;
     }
 
     return l_mem_address;
diff --git a/src/occ_405/dcom/dcomSlaveRx.c b/src/occ_405/dcom/dcomSlaveRx.c
index dd9bb82..10af964 100644
--- a/src/occ_405/dcom/dcomSlaveRx.c
+++ b/src/occ_405/dcom/dcomSlaveRx.c
@@ -135,8 +135,8 @@ void task_dcom_rx_slv_inbox( task_t *i_self)
             uint32_t l_addr_in_mem = dcom_calc_slv_inbox_addr();
 
             // Check valid address (should be inside inbox addresses range)
-            if ( (ADDR_SLAVE_INBOX_MAIN_MEM_PING <= l_addr_in_mem) &&
-                 ((ADDR_SLAVE_INBOX_MAIN_MEM_PONG+(sizeof(dcom_slv_inbox_t)*MAX_OCCS)) > l_addr_in_mem) )
+            if ( (SLAVE_INBOX_PING_COMMON_ADDRESS <= l_addr_in_mem) &&
+                 ((SLAVE_INBOX_PONG_COMMON_ADDRESS+(sizeof(dcom_slv_inbox_t)*MAX_OCCS)) > l_addr_in_mem) )
             {
                 uint32_t l_ssxrc = 0;
 
diff --git a/src/occ_405/dcom/dcomSlaveTx.c b/src/occ_405/dcom/dcomSlaveTx.c
index b083ff0..e6cf2d2 100755
--- a/src/occ_405/dcom/dcomSlaveTx.c
+++ b/src/occ_405/dcom/dcomSlaveTx.c
@@ -108,12 +108,12 @@ uint32_t dcom_build_slv_outbox(void)
 uint32_t dcom_which_buffer_slv_outbox(void)
 {
     // Locals
-    uint32_t l_mem_address = ADDR_SLAVE_OUTBOX_MAIN_MEM_PONG;
+    uint32_t l_mem_address = SLAVE_OUTBOX_PONG_COMMON_ADDRESS;
 
     // Switch back and forth based on tick
     if( CURRENT_TICK & 1 )
     {
-        l_mem_address = ADDR_SLAVE_OUTBOX_MAIN_MEM_PING;
+        l_mem_address = SLAVE_OUTBOX_PING_COMMON_ADDRESS;
     }
 
     return l_mem_address;
diff --git a/src/occ_405/dcom/dcom_thread.c b/src/occ_405/dcom/dcom_thread.c
index 3d1bad9..61606b1 100755
--- a/src/occ_405/dcom/dcom_thread.c
+++ b/src/occ_405/dcom/dcom_thread.c
@@ -99,11 +99,11 @@ void Dcom_thread_routine(void *arg)
 // NOTE: Temporary system config must say we are FSP system so
 // that we don't try to access main memory here.
         // --------------------------------------------------
-        // Check if we need to update the sapphire table
+        // Check if we need to update the opal table
         // --------------------------------------------------
         if(G_sysConfigData.system_type.kvm)
         {
-            proc_check_for_sapphire_updates();
+            proc_check_for_opal_updates();
         }
 
         // --------------------------------------------------
diff --git a/src/occ_405/homer.c b/src/occ_405/homer.c
index 823cbfa..3107006 100755
--- a/src/occ_405/homer.c
+++ b/src/occ_405/homer.c
@@ -66,7 +66,7 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
 #endif
 
     homer_rc_t l_rc = HOMER_SUCCESS;
-    occHostConfigDataArea_t *l_hdcfg_data = 0x00000000;
+    occHostConfigDataArea_t *l_hdcfg_data = (occHostConfigDataArea_t *) HOMER_BASE_ADDRESS;
 
     // Validate the pointers
     if (!o_host_data || !o_ssx_rc || ((uint32_t)o_host_data % 4))
@@ -86,7 +86,7 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
          * where the data is located.
          */
         *o_ssx_rc = ppc405_mmu_map((SsxAddress)l_hdcfg_data,
-                                   HOMER_HD_OFFSET,
+                                   (SsxAddress)(HOMER_HD_ADDRESS),
                                    sizeof(occHostConfigDataArea_t),
                                    0,
                                    0,
diff --git a/src/occ_405/homer.h b/src/occ_405/homer.h
index b4d94ee..15ecede 100755
--- a/src/occ_405/homer.h
+++ b/src/occ_405/homer.h
@@ -30,10 +30,27 @@
 
 
 // Offset into the HOMER of the host data section and the size
-#define HOMER_HD_OFFSET       0x00100000
+#define HOMER_BASE_ADDRESS    0x80000000
+#define HOMER_SPACE_SIZE      0x00400000       // 4 MB
+
+#define HOMER_HD_OFFSET       0x000C0000
+#define HOMER_HD_ADDRESS     (HOMER_BASE_ADDRESS+HOMER_HD_OFFSET)
 #define HOMER_HD_SZ           (128 * 1024)
 #define HOMER_FIR_PARM_SIZE   (3 * 1024)
 
+// OPAL table address in HOMER
+#define OPAL_OFFSET_HOMER  0x000E2000
+#define OPAL_ADDRESS_HOMER (HOMER_BASE_ADDRESS+OPAL_OFFSET_HOMER)
+
+// OCC/HTMGT command buffer offset in HOMER
+#define OCC_HTMGT_CMD_OFFSET_HOMER  0x000E0000
+#define OCC_HTMGT_CMD_ADDRESS_HOMER (HOMER_BASE_ADDRESS+OCC_HTMGT_CMD_OFFSET_HOMER)
+
+// OCC/HTMGT response buffer offset in HOMER
+#define OCC_HTMGT_RSP_OFFSET_HOMER  0x000E1000
+#define OCC_HTMGT_RSP_ADDRESS_HOMER (HOMER_BASE_ADDRESS+OCC_HTMGT_RSP_OFFSET_HOMER)
+
+
 // Version(s) of HOMER host data currently supported
 typedef enum homer_version
 {
diff --git a/src/occ_405/mode.c b/src/occ_405/mode.c
index 19338a3..fc533b5 100755
--- a/src/occ_405/mode.c
+++ b/src/occ_405/mode.c
@@ -173,7 +173,7 @@ errlHndl_t SMGR_set_mode(const OCC_MODE i_mode,
              break;
          }
 
-         // SAPPHIRE only accepts DPS-FE mode. In case OCC gets other modes, it should accept the request
+         // OPAL only accepts DPS-FE mode. In case OCC gets other modes, it should accept the request
          // and keep reporting back that it is in that mode. However, internally we should not
          // initiate any mode transition, i.e., OCC should remain internally in DPS-FE mode.
          if(G_sysConfigData.system_type.kvm)
@@ -181,7 +181,7 @@ errlHndl_t SMGR_set_mode(const OCC_MODE i_mode,
              G_occ_external_req_mode_kvm = l_mode;
              if (l_mode !=  OCC_MODE_DYN_POWER_SAVE)
              {
-                 TRAC_ERR("SAPPHIRE only accepts DPS-FE mode(6) but requested mode is : %d", l_mode);
+                 TRAC_ERR("OPAL only accepts DPS-FE mode(6) but requested mode is : %d", l_mode);
                  l_mode = OCC_MODE_DYN_POWER_SAVE;
              }
          }
diff --git a/src/occ_405/proc/proc_data_control.c b/src/occ_405/proc/proc_data_control.c
index 9f55d91..c68b422 100755
--- a/src/occ_405/proc/proc_data_control.c
+++ b/src/occ_405/proc/proc_data_control.c
@@ -220,12 +220,12 @@ void task_core_data_control( task_t * i_task )
         G_core_data_control_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32);
         if(G_sysConfigData.system_type.kvm)
         {
-            //Set the chiplet bounds (pmax/pmin) only on sapphire
+            //Set the chiplet bounds (pmax/pmin) only on opal
             G_core_data_control_parms.select = GPE_SET_PSTATES_PMBR;
         }
         else
         {
-            //Set the chiplet pstate request on non-sapphire systems
+            //Set the chiplet pstate request on non-opal systems
             G_core_data_control_parms.select = GPE_SET_PSTATES_PMCR;
         }
 
diff --git a/src/occ_405/proc/proc_pstate.c b/src/occ_405/proc/proc_pstate.c
index a52132a..1d4d65e 100755
--- a/src/occ_405/proc/proc_pstate.c
+++ b/src/occ_405/proc/proc_pstate.c
@@ -38,6 +38,7 @@
 #include "proc_data.h"
 #include "proc_pstate.h"
 #include "scom.h"
+#include "homer.h"
 
 // GPSM DCM Synchronization States
 typedef enum
@@ -74,8 +75,8 @@ int8_t   G_proc_gpst_pmax = 0;
 // Remembers if we are a DCM, for DCOM's sake
 bool G_isDcm      = FALSE;
 
-// Used for Sapphire
-DMA_BUFFER( sapphire_table_t G_sapphire_table ) = {{0}};
+// Used for OPAL
+DMA_BUFFER( opal_table_t G_opal_table ) = {{0}};
 
 //KVM throttle reason coming from the frequency voting box.
 extern uint8_t G_amec_kvm_throt_reason;
@@ -571,11 +572,11 @@ void proc_pstate_kvm_setup()
         TRAC_IMP("pmin clip pstate = %d, pmax clip pstate = %d", prbr.fields.pmin_rail, prbr.fields.pmax_rail);
         out32(PMC_RAIL_BOUNDS_REGISTER, prbr.value);
 
-        // Initialize the sapphire table in SRAM (sets valid bit)
-        populate_pstate_to_sapphire_tbl();
+        // Initialize the opal table in SRAM (sets valid bit)
+        populate_pstate_to_opal_tbl();
 
         // copy sram image into mainstore HOMER
-        populate_sapphire_tbl_to_mem();
+        populate_opal_tbl_to_mem();
         TRAC_IMP("proc_pstate_kvm_setup: RUNNING IN KVM MODE");
     }while(0);
 
@@ -919,46 +920,46 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void)
 
 // Function Specification
 //
-// Name:  populate_pstate_to_sapphire_tbl
+// Name:  populate_pstate_to_opal_tbl
 //
 // Description:
 //
 // End Function Specification
-void populate_pstate_to_sapphire_tbl()
+void populate_pstate_to_opal_tbl()
 {
     uint8_t i = 0;
     GlobalPstateTable * l_gpst_ptr = NULL;
 
-    memset(&G_sapphire_table, 0, sizeof(sapphire_table_t));
+    memset(&G_opal_table, 0, sizeof(opal_table_t));
 
     l_gpst_ptr = gpsm_gpst();
     const int8_t l_pmax = (int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1;
-    G_sapphire_table.config.valid = 1; // default 0x01
-    G_sapphire_table.config.version = 1; // default 0x01
-    G_sapphire_table.config.throttle = NO_THROTTLE; // default 0x00
-    G_sapphire_table.config.pmin = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang
-    G_sapphire_table.config.pnominal = (int8_t)proc_freq2pstate(G_sysConfigData.sys_mode_freq.table[OCC_MODE_NOMINAL]);
-    G_sapphire_table.config.pmax = gpst_pmax(&G_global_pstate_table);
-    const uint16_t l_entries = G_sapphire_table.config.pmax - G_sapphire_table.config.pmin + 1;
+    G_opal_table.config.valid = 1; // default 0x01
+    G_opal_table.config.version = 1; // default 0x01
+    G_opal_table.config.throttle = NO_THROTTLE; // default 0x00
+    G_opal_table.config.pmin = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang
+    G_opal_table.config.pnominal = (int8_t)proc_freq2pstate(G_sysConfigData.sys_mode_freq.table[OCC_MODE_NOMINAL]);
+    G_opal_table.config.pmax = gpst_pmax(&G_global_pstate_table);
+    const uint16_t l_entries = G_opal_table.config.pmax - G_opal_table.config.pmin + 1;
     const uint8_t l_idx = l_gpst_ptr->entries-1;
 
     for (i = 0; i < l_entries; i++)
     {
-        G_sapphire_table.data[i].pstate = (int8_t) l_pmax - i;
-        G_sapphire_table.data[i].flag = 0; // default 0x00
+        G_opal_table.data[i].pstate = (int8_t) l_pmax - i;
+        G_opal_table.data[i].flag = 0; // default 0x00
         if (i < l_gpst_ptr->entries)
         {
-            G_sapphire_table.data[i].evid_vdd = l_gpst_ptr->pstate[i].fields.evid_vdd;
-            G_sapphire_table.data[i].evid_vcs = l_gpst_ptr->pstate[i].fields.evid_vcs;
+            G_opal_table.data[i].evid_vdd = l_gpst_ptr->pstate[i].fields.evid_vdd;
+            G_opal_table.data[i].evid_vcs = l_gpst_ptr->pstate[i].fields.evid_vcs;
         }
         else
         {
             // leave the VDD & VCS Vids the same as the "Pstate Table Pmin"
-            G_sapphire_table.data[i].evid_vdd = l_gpst_ptr->pstate[l_idx].fields.evid_vdd;
-            G_sapphire_table.data[i].evid_vcs = l_gpst_ptr->pstate[l_idx].fields.evid_vcs;
+            G_opal_table.data[i].evid_vdd = l_gpst_ptr->pstate[l_idx].fields.evid_vdd;
+            G_opal_table.data[i].evid_vcs = l_gpst_ptr->pstate[l_idx].fields.evid_vcs;
         }
         // extrapolate the frequency
-        G_sapphire_table.data[i].freq_khz = l_gpst_ptr->pstate0_frequency_khz + (G_sapphire_table.data[i].pstate * l_gpst_ptr->frequency_step_khz);
+        G_opal_table.data[i].freq_khz = l_gpst_ptr->pstate0_frequency_khz + (G_opal_table.data[i].pstate * l_gpst_ptr->frequency_step_khz);
     }
 }
 
@@ -966,12 +967,12 @@ void populate_pstate_to_sapphire_tbl()
 
 // Function Specification
 //
-// Name:  populate_sapphire_tbl_to_mem
+// Name:  populate_opal_tbl_to_mem
 //
 // Description:
 //
 // End Function Specification
-void populate_sapphire_tbl_to_mem()
+void populate_opal_tbl_to_mem()
 {
     int l_ssxrc = SSX_OK;
     uint32_t l_reasonCode = 0;
@@ -979,14 +980,13 @@ void populate_sapphire_tbl_to_mem()
 
     do
     {
-#define SAPPHIRE_OFFSET_IN_HOMER 0x001F8000
         BceRequest pba_copy;
         // Set up copy request
         l_ssxrc = bce_request_create(&pba_copy,                          // block copy object
                                      &G_pba_bcue_queue,                  // sram to mainstore copy engine
-                                     SAPPHIRE_OFFSET_IN_HOMER,           // mainstore address
-                                     (uint32_t) &G_sapphire_table,       // sram starting address
-                                     (size_t) sizeof(G_sapphire_table),  // size of copy
+                                     OPAL_ADDRESS_HOMER,             // mainstore address
+                                     (uint32_t) &G_opal_table,       // sram starting address
+                                     (size_t) sizeof(G_opal_table),  // size of copy
                                      SSX_WAIT_FOREVER,                   // no timeout
                                      NULL,                               // call back
                                      NULL,                               // call back arguments
@@ -995,7 +995,7 @@ void populate_sapphire_tbl_to_mem()
 
         if(l_ssxrc != SSX_OK)
         {
-            TRAC_ERR("populate_sapphire_tbl_to_mem: PBA request create failure rc=[%08X]", -l_ssxrc);
+            TRAC_ERR("populate_opal_tbl_to_mem: PBA request create failure rc=[%08X]", -l_ssxrc);
             /*
              * @errortype
              * @moduleid    MAIN_STATE_TRANSITION_MID
@@ -1014,7 +1014,7 @@ void populate_sapphire_tbl_to_mem()
 
         if(l_ssxrc != SSX_OK)
         {
-            TRAC_ERR("populate_sapphire_tbl_to_mem: PBA request schedule failure rc=[%08X]", -l_ssxrc);
+            TRAC_ERR("populate_opal_tbl_to_mem: PBA request schedule failure rc=[%08X]", -l_ssxrc);
             /*
              * @errortype
              * @moduleid    MAIN_STATE_TRANSITION_MID
@@ -1052,13 +1052,13 @@ void populate_sapphire_tbl_to_mem()
 
 // Function Specification
 //
-// Name: proc_check_for_sapphire_updates
+// Name: proc_check_for_opal_updates
 //
-// Description: Checks if the sapphire table needs an update
+// Description: Checks if the opal table needs an update
 //              and updates if necessary.
 //
 // End Function Specification
-void proc_check_for_sapphire_updates()
+void proc_check_for_opal_updates()
 {
     uint8_t l_latest_throttle_reason;
 
@@ -1073,12 +1073,12 @@ void proc_check_for_sapphire_updates()
     }
 
     //If the throttle reason changed, update it in the HOMER
-    if(G_sapphire_table.config.throttle != l_latest_throttle_reason)
+    if(G_opal_table.config.throttle != l_latest_throttle_reason)
     {
-        TRAC_INFO("proc_check_for_sapphire_updates: throttle reason changed to %d", l_latest_throttle_reason);
-        G_sapphire_table.config.throttle = l_latest_throttle_reason;
-        G_sapphire_table.config.version = 1; // default 0x01
-        G_sapphire_table.config.valid = 1; //default 0x01
-        populate_sapphire_tbl_to_mem();
+        TRAC_INFO("proc_check_for_opal_updates: throttle reason changed to %d", l_latest_throttle_reason);
+        G_opal_table.config.throttle = l_latest_throttle_reason;
+        G_opal_table.config.version = 1; // default 0x01
+        G_opal_table.config.valid = 1; //default 0x01
+        populate_opal_tbl_to_mem();
     }
 }
diff --git a/src/occ_405/proc/proc_pstate.h b/src/occ_405/proc/proc_pstate.h
index b8be793..8ca02ea 100755
--- a/src/occ_405/proc/proc_pstate.h
+++ b/src/occ_405/proc/proc_pstate.h
@@ -59,7 +59,7 @@ typedef struct __attribute__ ((packed))
     int8_t               pnominal;
     int8_t               pmax;
     uint16_t             spare;
-} sapphire_config_t;
+} opal_config_t;
 
 typedef struct __attribute__ ((packed))
 {
@@ -68,17 +68,17 @@ typedef struct __attribute__ ((packed))
     uint8_t              evid_vdd;
     uint8_t              evid_vcs;
     uint32_t             freq_khz;
-} sapphire_data_t; 
+} opal_data_t;
 
 #define PSTATE_ENTRY_NUMBER 256
 // This size must be a multiple of 128
 typedef struct __attribute__ ((packed))
 {
-    sapphire_config_t    config;
+    opal_config_t        config;
     uint64_t             reserved;
-    sapphire_data_t      data[PSTATE_ENTRY_NUMBER];
+    opal_data_t          data[PSTATE_ENTRY_NUMBER];
     uint8_t              pad[112];
-} sapphire_table_t __attribute__ ((aligned (128)));
+} opal_table_t __attribute__ ((aligned (128)));
 
 enum {
     NO_THROTTLE = 0x00,
@@ -89,11 +89,11 @@ enum {
     OCC_RESET = 0x05,
 }; 
 
-//extern GlobalPstateTable G_global_pstate_table; 
+//extern GlobalPstateTable G_global_pstate_table;
 
-extern uint32_t    G_mhz_per_pstate;            
+extern uint32_t    G_mhz_per_pstate;
 
-extern sapphire_table_t G_sapphire_table;       
+extern opal_table_t G_opal_table;
 
 // Initialize PState Table
 // TEMP -- PstateSuperStructure no longer exists
@@ -122,12 +122,12 @@ inline bool proc_is_dcm();
 // Helper function to determine if we are in HW Pstate mode
 inline bool proc_is_hwpstate_enabled(void);
 
-// Copy pstate data to sapphire table
-void populate_pstate_to_sapphire_tbl();
+// Copy pstate data to opal table
+void populate_pstate_to_opal_tbl();
 
-// Copy sapphire table to mainstore memory at SAPPHIRE_OFFSET_IN_HOMER
-void populate_sapphire_tbl_to_mem(); 
+// Copy opal table to mainstore memory at OPAL_OFFSET_HOMER
+void populate_opal_tbl_to_mem();
 
-// Check if sapphire table needs update
-void proc_check_for_sapphire_updates();
+// Check if opal table needs update
+void proc_check_for_opal_updates();
 #endif