diff options
author | Chris Cain <cjcain@us.ibm.com> | 2017-03-17 11:16:56 -0500 |
---|---|---|
committer | Christopher J. Cain <cjcain@us.ibm.com> | 2017-04-13 14:07:23 -0400 |
commit | 1f9e535d685528d666561d71518f85a571af057c (patch) | |
tree | 788de4b115c2a27fdf60a8ac6b25c4b12d9fcc98 /src | |
parent | 031e2dacb210a1a16626e7c1b4235dea393119d4 (diff) | |
download | talos-occ-1f9e535d685528d666561d71518f85a571af057c.tar.gz talos-occ-1f9e535d685528d666561d71518f85a571af057c.zip |
Merge latest hcode headers into OCC
Change-Id: I1365d14bee48c287fcfd0faab8ba8a1a517e5bcb
RTC: 169886
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38107
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/include/p9_pstates_cmeqm.h | 336 | ||||
-rw-r--r-- | src/include/p9_pstates_common.h | 227 | ||||
-rw-r--r-- | src/include/p9_pstates_occ.h | 40 | ||||
-rw-r--r-- | src/include/p9_pstates_pgpe.h | 256 | ||||
-rw-r--r-- | src/include/pstate_pgpe_occ_api.h | 89 | ||||
-rwxr-xr-x | src/occ_405/amec/amec_freq.c | 12 | ||||
-rwxr-xr-x | src/occ_405/amec/amec_parm_table.c | 16 | ||||
-rwxr-xr-x | src/occ_405/amec/amec_sys.h | 4 | ||||
-rwxr-xr-x | src/occ_405/cmdh/cmdh_mnfg_intf.c | 2 | ||||
-rwxr-xr-x | src/occ_405/cmdh/cmdh_mnfg_intf.h | 4 | ||||
-rwxr-xr-x | src/occ_405/occbuildname.c | 2 | ||||
-rw-r--r-- | src/occ_405/pgpe/pgpe_interface.c | 2 | ||||
-rwxr-xr-x | src/occ_405/proc/proc_data_control.c | 2 | ||||
-rwxr-xr-x | src/occ_405/state.c | 2 | ||||
-rw-r--r-- | src/occ_405/wof/wof.c | 20 | ||||
-rw-r--r-- | src/occ_405/wof/wof.h | 18 | ||||
-rw-r--r-- | src/ssx/occhw/occhw_pba.c | 1 |
17 files changed, 892 insertions, 141 deletions
diff --git a/src/include/p9_pstates_cmeqm.h b/src/include/p9_pstates_cmeqm.h new file mode 100644 index 0000000..f7047cb --- /dev/null +++ b/src/include/p9_pstates_cmeqm.h @@ -0,0 +1,336 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/p9_pstates_cmeqm.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_cmeqm.h +/// @brief Pstate structures and support routines for CME Hcode +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : CME:PGPE + +#ifndef __P9_PSTATES_CME_H__ +#define __P9_PSTATES_CME_H__ + +#include <p9_pstates_common.h> + +/// \defgroup QM Flags +/// +/// These are flag bits for the \a Quad Manager field. +/// +/// @{ + +/// qmflag() - Disable Resonant Clock use. +#define PSTATE_RESCLK_DISABLE 0x8000 + +/// qmflag() - Disable IVRM use. +#define PSTATE_IVRMS_DISABLE 0x4000 + +/// qmflag() - Disable VDM use. +#define PSTATE_VDM_DISABLE 0x2000 + +/// qmflag() - Disable WOF. +#define PSTATE_WOF_DISABLE 0x1000 + +/// qmflag() - dpll_dynamic_fmax_enable +#define PSTATE_DPLL_DYNAMIC_FMAX_ENABLE 0x0800 + +/// qmflag() - dpll_dynamic_fmin_enable +#define PSTATE_DPLL_DYNAMIC_FMIN_ENABLE 0x0400 + +/// qmflag() - dpll_droop_protect_enable +#define PSTATE_DPLL_DROOP_PROTECT_ENABLE 0x0200 + +/// @} + +#ifndef __ASSEMBLER__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/// LocalParmsBlock Magic Number +/// +/// This magic number identifies a particular version of the +/// PstateParmsBlock and its substructures. The version number should be +/// kept up to date as changes are made to the layout or contents of the +/// structure. + +#define LOCAL_PARMSBLOCK_MAGIC 0x434d455050423030ull /* CMEPPB00 */ + +/// Quad Manager Flags +/// + +typedef union +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t resclk_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t wof_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_droop_protect_enable : 1; + uint16_t reserved : 10; +#else + uint16_t reserved : 10; + uint16_t dpll_droop_protect_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t wof_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t resclk_enable : 1; +#endif // _BIG_ENDIAN + } fields; + +} QuadManagerFlags; + +/// Resonant Clock Stepping Entry +/// +typedef union +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t sector_buffer : 4; + uint16_t spare1 : 1; + uint16_t pulse_enable : 1; + uint16_t pulse_mode : 2; + uint16_t resonant_switch : 4; + uint16_t spare4 : 4; +#else + uint16_t spare4 : 4; + uint16_t resonant_switch : 4; + uint16_t pulse_mode : 2; + uint16_t pulse_enable : 1; + uint16_t spare1 : 1; + uint16_t sector_buffer : 4; +#endif // _BIG_ENDIAN + } fields; + +} ResonantClockingStepEntry; + +#define RESCLK_FREQ_REGIONS 8 +#define RESCLK_STEPS 64 +#define RESCLK_L3_STEPS 4 + +typedef struct ResonantClockControl +{ + uint8_t resclk_freq[RESCLK_FREQ_REGIONS]; // Lower frequency of Resclk Regions + + uint8_t resclk_index[RESCLK_FREQ_REGIONS]; // Index into value array for the + // respective Resclk Region + + /// Array containing the transition steps + ResonantClockingStepEntry steparray[RESCLK_STEPS]; + + /// Delay between steps (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t step_delay_ns; + + /// L3 Clock Stepping Array + uint8_t l3_steparray[RESCLK_L3_STEPS]; + + /// Resonant Clock Voltage Threshold (in millivolts) + /// This value is used to choose the appropriate L3 clock region setting. + uint16_t l3_threshold_mv; + +} ResonantClockingSetup; + +// #W data points (version 2) +typedef struct +{ + uint16_t ivdd_tdp_ac_current_10ma; + uint16_t ivdd_tdp_dc_current_10ma; + uint8_t vdm_overvold_small_thresholds; + uint8_t vdm_large_extreme_thresholds; + uint8_t vdm_small_frequency_drop; + uint8_t vdm_large_frequency_drop; + uint16_t vdm_spare; +} poundw_entry_t; + +typedef struct +{ + uint16_t r_package_common; + uint16_t r_quad; + uint16_t r_core; + uint16_t r_quad_header; + uint16_t r_core_header; +} resistance_entry_t; + +typedef struct +{ + poundw_entry_t poundw_nominal; + poundw_entry_t poundw_powersave; + poundw_entry_t poundw_turbo; + poundw_entry_t poundw_ultraturbo; + resistance_entry_t resistance_data; + uint64_t reserved1; + uint16_t reserved2; +} PoundW_data; +/// VDM/Droop Parameter Block +/// +typedef struct +{ + uint8_t vid_compare_override_mv_enable; + uint8_t vid_compare_override_mv[VPD_PV_POINTS]; + uint8_t vdm_response; + + // For the following *_enable fields, bits are defined to indicate + // which of the respective *override* array entries are valid. + // bit 0: UltraTurbo; bit 1: Turbo; bit 2: Nominal; bit 3: PowSave + uint8_t droop_small_override_enable; + uint8_t droop_large_override_enable; + uint8_t droop_extreme_override_enable; + uint8_t overvolt_override_enable; + uint16_t fmin_override_khz_enable; + uint16_t fmax_override_khz_enable; + + // The respecitve *_enable above indicate which index values are valid + uint8_t droop_small_override[VPD_PV_POINTS]; + uint8_t droop_large_override[VPD_PV_POINTS]; + uint8_t droop_extreme_override[VPD_PV_POINTS]; + uint8_t overvolt_override[VPD_PV_POINTS]; + uint16_t fmin_override_khz[VPD_PV_POINTS]; + uint16_t fmax_override_khz[VPD_PV_POINTS]; + + /// Pad structure to 8-byte alignment + /// @todo pad once fully structure is complete. + // uint8_t pad[1]; + +} VDMParmBlock; + + +/// The layout of the data created by the Pstate table creation firmware for +/// comsumption by the Pstate GPE. This data will reside in the Quad +/// Power Management Region (QPMR). +/// + +/// Standard options controlling Pstate setup procedures + +/// System Power Distribution Paramenters +/// +/// Parameters set by system design that influence the power distribution +/// for a rail to the processor module. This values are typically set in the +/// system machine readable workbook and are used in the generation of the +/// Global Pstate Table. This values are carried in the Pstate SuperStructure +/// for use and/or reference by OCC firmware (eg the WOF algorithm) + + +/// IVRM Parameter Block +/// +/// @todo Major work item. Largely will seed the CME Quad Manager to perform +/// iVRM voltage calculations + +#define IVRM_ARRAY_SIZE 64 +typedef struct iVRMInfo +{ + + /// Pwidth from 0.03125 to 1.96875 in 1/32 increments at Vin=Vin_Max + uint8_t strength_lookup[IVRM_ARRAY_SIZE]; // Each entry is a six bit value, right justified + + /// Scaling factor for the Vin_Adder calculation. + uint8_t vin_multiplier[IVRM_ARRAY_SIZE]; // Each entry is from 0 to 255. + + /// Vin_Max used in Vin_Adder calculation (in millivolts) + uint16_t vin_max_mv; + + /// Delay between steps (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t step_delay_ns; + + /// Stabilization delay once target voltage has been reached (in nanoseconds) + /// Maximum delay: 65.536us + uint16_t stablization_delay_ns; + + /// Deadzone (in millivolts) + /// Maximum: 255mV. If this value is 0, 50mV is assumed. + uint8_t deadzone_mv; + + /// Pad to 8B + uint8_t pad; + +} IvrmParmBlock; + + +/// The layout of the data created by the Pstate table creation firmware for +/// comsumption by the CME Quad Manager. This data will reside in the Core +/// Power Management Region (CPMR). +/// +typedef struct +{ + + /// Magic Number + uint64_t magic; // the last byte of this number the structure's version. + + // QM Flags + QuadManagerFlags qmflags; + + /// Operating points + /// + /// VPD operating points are stored without load-line correction. Frequencies + /// are in MHz, voltages are specified in units of 5mV, and currents are + /// in units of 500mA. + VpdOperatingPoint operating_points[VPD_PV_POINTS]; + + /// Loadlines and Distribution values for the VDD rail + SysPowerDistParms vdd_sysparm; + + /// External Biases + /// + /// Biases applied to the VPD operating points prior to load-line correction + /// in setting the external voltages. This is used to recompute the Vin voltage + /// based on the Global Actual Pstate . + /// Values in 0.5% + VpdBias ext_biases[VPD_PV_POINTS]; + + /// Internal Biases + /// + /// Biases applied to the VPD operating points that are used for interpolation + /// in setting the internal voltages (eg Vout to the iVRMs) as part of the + /// Local Actual Pstate. + /// Values in 0.5% + VpdBias int_biases[VPD_PV_POINTS]; + + /// IVRM Data + IvrmParmBlock ivrm; + + /// Resonant Clock Grid Management Setup + ResonantClockingSetup resclk; + + /// VDM Data + VDMParmBlock vdm; + +} LocalPstateParmBlock; + +#ifdef __cplusplus +} // end extern C +#endif +#endif /* __ASSEMBLER__ */ +#endif /* __P9_PSTATES_CME_H__ */ diff --git a/src/include/p9_pstates_common.h b/src/include/p9_pstates_common.h index 4ccabc3..003021c 100644 --- a/src/include/p9_pstates_common.h +++ b/src/include/p9_pstates_common.h @@ -35,13 +35,13 @@ #ifndef __P9_PSTATES_COMMON_H__ #define __P9_PSTATES_COMMON_H__ -/// The minimum Pstate (knowing the increasing Pstates numbers represent +/// The maximum Pstate (knowing the increasing Pstates numbers represent /// decreasing frequency) -#define PSTATE_MIN 255 +#define PSTATE_MAX 255 -/// The maximum Pstate (knowing the increasing Pstates numbers represent +/// The minimum Pstate (knowing the increasing Pstates numbers represent /// decreasing frequency) -#define PSTATE_MAX 0 +#define PSTATE_MIN 0 /// The minimum \e legal DPLL frequency code /// @@ -83,35 +83,65 @@ #define IVID_STEP_UV 4000 /// Maximum number of Quads (4 cores plus associated caches) -#define MAX_QUADS 6 +#define MAXIMUM_QUADS 6 // Constants associated with VRM stepping // @todo Determine what is needed here (eg Attribute mapping) and if any constants // are warrented -/// VPD #V Operating Points +/// VPD #V Data from keyword (eg VPD order) #define VPD_PV_POINTS 4 -#define VPD_PV_ORDER_STR {"PowerSave ", "Nominal ", "Turbo ", "UltraTurbo"} -#define POWERSAVE 1 -#define NOMINAL 0 +#define VPD_PV_POWERSAVE 1 +#define VPD_PV_NOMINAL 0 +#define VPD_PV_TURBO 2 +#define VPD_PV_ULTRA 3 +#define VPD_PV_ORDER {VPD_PV_POWERSAVE, VPD_PV_NOMINAL, VPD_PV_TURBO, VPD_PV_ULTRA} +#define VPD_PV_ORDER_STR {"Nominal ","PowerSave ", "Turbo ", "UltraTurbo"} + +/// VPD #V Operating Points (eg Natureal order) +#define POWERSAVE 0 +#define NOMINAL 1 #define TURBO 2 #define ULTRA 3 #define POWERBUS 4 -#define VPD_PV_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA} +#define PV_OP_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA} +#define PV_OP_ORDER_STR {"PowerSave ", "Nominal ","Turbo ", "UltraTurbo"} + +#define VPD_PV_CORE_FREQ_MHZ 0 +#define VPD_PV_VDD_MV 1 +#define VPD_PV_IDD_100MA 2 +#define VPD_PV_VCS_MV 3 +#define VPD_PV_ICS_100MA 4 +#define VPD_PV_PB_FREQ_MHZ 0 +#define VPD_PV_VDN_MV 1 +#define VPD_PV_IDN_100MA 2 + #define VPD_NUM_SLOPES_SET 2 #define VPD_SLOPES_RAW 0 #define VPD_SLOPES_BIASED 1 #define VPD_NUM_SLOPES_REGION 3 -#define REGION_POWERSAVE_NOMINAL 1 -#define REGION_NOMINAL_TURBO 0 +#define REGION_POWERSAVE_NOMINAL 0 +#define REGION_NOMINAL_TURBO 1 #define REGION_TURBO_ULTRA 2 +// Different points considered for calculating slopes +#define NUM_VPD_PTS_SET 4 +#define VPD_PT_SET_RAW 0 +#define VPD_PT_SET_SYSP 1 +#define VPD_PT_SET_BIASED 2 +#define VPD_PT_SET_BIASED_SYSP 3 +#define VPD_PT_SET_ORDER {VPD_PT_SET_RAW, VPD_PT_SET_SYSP, VPD_PT_SET_BIASED, VPD_PT_SET_BIASED_SYSP} +#define VPD_PT_SET_ORDER_STR {"Raw ", "SysParam ","Biased ", "Biased/SysParam"} + +#define EVID_SLOPE_FP_SHIFT 13 + /// IDDQ readings, #define IDDQ_MEASUREMENTS 6 #define MEASUREMENT_ELEMENTS 6 // Number of Quads for P9 #define IDDQ_READINGS_PER_IQ 2 -#define IDDQ_ARRAY_VOLTAGES {0.60, 0.70, 0.80, 0.90, 1.00, 1.10} +#define IDDQ_ARRAY_VOLTAGES { 0.60 , 0.70 , 0.80 , 0.90 , 1.00 , 1.10} +#define IDDQ_ARRAY_VOLTAGES_STR {"0.60", "0.70", "0.80", "0.90", "1.00", "1.10"} /// WOF Items #define NUM_ACTIVE_CORES 24 @@ -151,6 +181,7 @@ #define LPST_GPST_WARNING 0x00477902 #define LPST_INCR_CLIP_ERROR 0x00477903 +#ifndef __ASSEMBLER__ #ifdef __cplusplus extern "C" { #endif @@ -179,15 +210,13 @@ typedef uint16_t VidAVS; /// typedef struct { - uint32_t vdd_mv; uint32_t vcs_mv; uint32_t idd_100ma; uint32_t ics_100ma; uint32_t frequency_mhz; uint8_t pstate; // Pstate of this VpdOperating - uint8_t pad[3]; - + uint8_t pad[3]; // Alignment padding } VpdOperatingPoint; /// VPD Biases. @@ -234,77 +263,147 @@ typedef struct } SysPowerDistParms; + +// +// WOF Voltage, Frequency Ratio Tables // -/// UltraTurbo Segment VIDs by Core Count + +// VFRT Header + typedef struct { - /// Number of Segment Pstates - uint8_t ut_segment_pstates; + /// Magic Number + /// Set to ASCII "VT" + uint16_t magic_number; + + /// Indicator + /// Space for generation tools to be anything unique necessary to ID this + /// VFRT + uint16_t indicator; + + union + { + uint8_t value; + struct + { + uint8_t type : 4; + uint8_t version : 4; + } fields; + } typever; + + uint8_t reserved; + + union + { + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t reserved: 4; + uint16_t vdn_id : 4; + uint16_t vdd_id : 4; + uint16_t qa_id : 4; +#else + uint16_t qa_id : 4; + uint16_t vdd_id : 4; + uint16_t vdn_id : 4; + uint16_t reserved: 4; +#endif // _BIG_ENDIAN + + } fields; + } ids; + +} VFRTHeader_t; + +// WOF Tables Header - /// Maximum number of core possibly active - uint8_t ut_max_cores; +typedef struct +{ - /// VDD VID modification - /// 1 core active = offset 0 - /// 2 cores active = offset 1 - /// ... - /// 12 cores active = offset 11 - uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + /// Magic Number + /// Set to ASCII "VFRT___x" where x is the version of the VFRT structure + uint64_t magic_number; - /// VCS VID modification - /// 1 core active = offset 0 - /// 2 cores active = offset 1 - /// ... - /// 12 cores active = offset 11 - uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + /// VFRT Size + /// Length, in bytes, of a VFRT + uint8_t vfrt_size; -} VIDModificationTable; + /// VFRT Data Size + /// Length, in bytes, of the data field. + uint8_t vfrt_data_size; -/// Workload Optimized Frequency (WOF) Elements -/// -/// Structure defining various control elements needed by the WOF algorithm -/// firmware running on the OCC. -/// -typedef struct -{ + uint8_t reserved; - /// WOF Enablement - uint8_t wof_enabled; + /// Quad Active Size + /// Total number of Active Quads + uint8_t quads_active_size; - /// TDP<>RDP Current Factor - /// Value read from ??? VPD - /// Defines the scaling factor that converts current (amperage) value from - /// the Thermal Design Point to the Regulator Design Point (RDP) as input - /// to the Workload Optimization Frequency (WOF) OCC algorithm. - /// - /// This is a ratio value and has a granularity of 0.01 decimal. Data - /// is held in hexidecimal (eg 1.22 is represented as 122 and then converted - /// to hex 0x7A). - uint32_t tdp_rdp_factor; + /// Ceff Vdn Start + /// CeffVdn value represented by index 0 (in percent) + uint8_t vdn_start; - /// UltraTurbo Segment VIDs by Core Count - VIDModificationTable ut_vid_mod; + /// Ceff Vdn Step + /// CeffVdn step value for each CeffVdn index (in percent) + uint8_t vdn_step; - uint8_t pad[4]; + /// Ceff Vdn Size + /// Number of CeffVdn indexes + uint8_t vdn_size; -} WOFElements; + /// Ceff Vdd Start + /// CeffVdd value represented by index 0 (in percent) + uint8_t vdd_start; + + /// Ceff Vdd Step + /// CeffVdd step value for each CeffVdd index (in percent) + uint8_t vdd_step; + + /// Ceff Vdd Size + /// Number of CeffVdd indexes + uint8_t vdd_size; + + /// Vratio Start + /// Vratio value represented by index 0 (in percent) + uint8_t vratio_start; + + /// Vratio Step + /// Vratio step value for each CeffVdd index (in percent) + uint8_t vratio_step; + + /// Vratio Size + /// Number of Vratio indexes + uint8_t vratio_size; + + /// Fratio Start + /// Fratio value represented by index 0 (in percent) + uint8_t fratio_start; + + /// Fratio Step + /// Fratio step value for each CeffVdd index (in percent) + uint8_t fratio_step; + + /// Fratio Size + /// Number of Fratio indexes + uint8_t fratio_size; + +} WofTablesHeader_t; -// -// WOF Voltage, Frequency Ratio Tables -// // VDN // Data is provided in 12ths (eg 12 core pairs on a 24 core chip) #define VFRT_VRATIO_SIZE 12 -// 100%/10% steps + 1 (for 0) -#define VFRT_FRATIO_SIZE 11 +// 100%/10% steps +#define VFRT_FRATIO_SIZE 10 -typedef uint16_t VFRT_Circuit_t; // Holds a frequency in MHz +// Holds a frequency that is 1000MHz + 16.667*VFRT_Circuit_t +typedef uint8_t VFRT_Circuit_t; typedef Pstate VFRT_Hcode_t; + + extern VFRT_Circuit_t VFRTCircuitTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE]; extern VFRT_Hcode_t VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE]; @@ -313,5 +412,5 @@ extern VFRT_Hcode_t VFRTInputTable[VFRT_FRATIO_SIZE][VFRT_FRATIO_SIZE]; #ifdef __cplusplus } // end extern C #endif - +#endif /* __ASSEMBLER__ */ #endif /* __P9_PSTATES_COMMON_H__ */ diff --git a/src/include/p9_pstates_occ.h b/src/include/p9_pstates_occ.h index e69e500..26b97eb 100644 --- a/src/include/p9_pstates_occ.h +++ b/src/include/p9_pstates_occ.h @@ -36,11 +36,22 @@ #define __P9_PSTATES_OCC_H__ #include <p9_pstates_common.h> +#include <p9_pstates_pgpe.h> +#ifndef __ASSEMBLER__ #ifdef __cplusplus extern "C" { #endif +/// PstateParmsBlock Magic Number +/// +/// This magic number identifies a particular version of the +/// PstateParmsBlock and its substructures. The version number should be +/// kept up to date as changes are made to the layout or contents of the +/// structure. + +#define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */ + /// IDDQ Reading Type /// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a /// maximum value of 409.6A to be represented. @@ -51,7 +62,7 @@ typedef uint16_t iddq_entry_t; /// Each entry is 1 byte. The values are in 0.5degC units; this allow for a /// maximum value of 127degC to be represented. /// -typedef uint16_t avgtemp_entry_t; +typedef uint8_t avgtemp_entry_t; /// Iddq Table /// @@ -76,10 +87,10 @@ typedef struct uint8_t good_caches_per_sort; /// Good Normal Cores - uint8_t good_normal_cores[MAX_QUADS]; + uint8_t good_normal_cores[MAXIMUM_QUADS]; /// Good Caches - uint8_t good_caches[MAX_QUADS]; + uint8_t good_caches[MAXIMUM_QUADS]; /// RDP to TDP Scaling Factor in 0.01% units uint16_t rdp_to_tdp_scale_factor; @@ -103,10 +114,10 @@ typedef struct iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS]; /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units - iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAX_QUADS][IDDQ_MEASUREMENTS]; + iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS]; - /// IVDDN ; 6.25mA units - iddq_entry_t ivdn; + /// IVDDN 6.25mA units + iddq_entry_t ivdn[IDDQ_MEASUREMENTS]; /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units @@ -119,11 +130,14 @@ typedef struct avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS]; /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units - avgtemp_entry_t avgtemp_quad_good_cores_on[MAX_QUADS][IDDQ_MEASUREMENTS]; + avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS]; /// avgtempN ; 6.25mA units avgtemp_entry_t avgtemp_vdn; + /// spare (per MVPD documentation + uint8_t spare_1[43]; + } IddqTable; @@ -132,6 +146,9 @@ typedef struct /// comsumption by the OCC firmware. This data will reside in the Quad /// Power Management Region (QPMR). /// +/// This structure is aligned to 128B to allow for easy downloading using the +/// OCC block copy engine +/// typedef struct { @@ -168,13 +185,12 @@ typedef struct // Minimum Pstate; Maximum is always 0. uint32_t pstate_min; // Comes from PowerSave #V point after biases - // TODO: Temporary hack untill interface is finalized. - uint8_t pad[88]; // total size = 0xE00, devisible by 128 -} OCCPstateParmBlock; - + /// Nest frequency in Mhz. This is used by FIT interrupt + uint32_t nest_frequency_mhz; +} __attribute__((aligned(128))) OCCPstateParmBlock; #ifdef __cplusplus } // end extern C #endif - +#endif /* __ASSEMBLER__ */ #endif /* __P9_PSTATES_OCC_H__ */ diff --git a/src/include/p9_pstates_pgpe.h b/src/include/p9_pstates_pgpe.h new file mode 100644 index 0000000..f523328 --- /dev/null +++ b/src/include/p9_pstates_pgpe.h @@ -0,0 +1,256 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/p9_pstates_pgpe.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pstates_pgpe.h +/// @brief Pstate structures and support routines for PGPE Hcode +/// +// *HWP HW Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP HW Owner : Michael Floyd <mfloyd@us.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : PGPE:HS + + +#ifndef __P9_PSTATES_PGPE_H__ +#define __P9_PSTATES_PGPE_H__ + +#include <p9_pstates_common.h> +#include <p9_pstates_cmeqm.h> + +/// PstateParmsBlock Magic Number +/// +/// This magic number identifies a particular version of the +/// PstateParmsBlock and its substructures. The version number should be +/// kept up to date as changes are made to the layout or contents of the +/// structure. + +#define PSTATE_PARMSBLOCK_MAGIC 0x5053544154453030ull /* PSTATE00 */ + +#ifndef __ASSEMBLER__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +/// Standard options controlling Pstate setup and installation procedures +typedef struct +{ + + /// Option flags; See \ref pstate_options + uint32_t options; + + /// Pad structure to 8 bytes. Could also be used for other options later. + uint32_t pad; + +} PGPEOptions; + +/// UltraTurbo Segment VIDs by Core Count +typedef struct +{ + + /// Number of Segment Pstates + uint8_t ut_segment_pstates; + + /// Maximum number of core possibly active + uint8_t ut_max_cores; + + /// VDD VID modification + /// 1 core active = offset 0 + /// 2 cores active = offset 1 + /// ... + /// 12 cores active = offset 11 + uint8_t ut_segment_vdd_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + + /// VCS VID modification + /// 1 core active = offset 0 + /// 2 cores active = offset 1 + /// ... + /// 12 cores active = offset 11 + uint8_t ut_segment_vcs_vid[MAX_UT_PSTATES][NUM_ACTIVE_CORES]; + +} VIDModificationTable; + +/// Workload Optimized Frequency (WOF) Elements +/// +/// Structure defining various control elements needed by the WOF algorithm +/// firmware running on the OCC. +/// +typedef struct +{ + + /// WOF Enablement + uint8_t wof_enabled; + + /// TDP<>RDP Current Factor + /// Value read from ??? VPD + /// Defines the scaling factor that converts current (amperage) value from + /// the Thermal Design Point to the Regulator Design Point (RDP) as input + /// to the Workload Optimization Frequency (WOF) OCC algorithm. + /// + /// This is a ratio value and has a granularity of 0.01 decimal. Data + /// is held in hexidecimal (eg 1.22 is represented as 122 and then converted + /// to hex 0x7A). + uint32_t tdp_rdp_factor; + + /// UltraTurbo Segment VIDs by Core Count + VIDModificationTable ut_vid_mod; + +} WOFElements; + + +/// Global Pstate Parameter Block +/// +/// The GlobalPstateParameterBlock is an abstraction of a set of voltage/frequency +/// operating points along with hardware limits. Besides the hardware global +/// Pstate table, the abstract table contains enough extra information to make +/// it the self-contained source for setting up and managing voltage and +/// frequency in either Hardware or Firmware Pstate mode. +/// +/// When installed in PMC, Global Pstate table indices are adjusted such that +/// the defined Pstates begin with table entry 0. The table need not be full - +/// the \a pmin and \a entries fields define the minimum and maximum Pstates +/// represented in the table. However at least 1 entry must be defined to +/// create a legal table. +/// +/// Note that Global Pstate table structures to be mapped into PMC hardware +/// must be 1KB-aligned. This requirement is fullfilled by ensuring that +/// instances of this structure are 1KB-aligned. +typedef struct +{ + + + /// Magic Number + uint64_t magic; // the last byte of this number the structure's version. + + /// Pstate options + /// + /// The options are included as part of the GlobalPstateTable so that they + /// are available to upon PGPE initialization. + PGPEOptions options; + + /// The frequency associated with Pstate[0] in KHz + uint32_t reference_frequency_khz; + + /// The frequency step in KHz + uint32_t frequency_step_khz; + + /// Operating points + /// + /// VPD operating points are stored without load-line correction. Frequencies + /// are in MHz, voltages are specified in units of 5mV, and currents are + /// in units of 500mA. + VpdOperatingPoint operating_points[VPD_PV_POINTS]; + + /// Biases + /// + /// Biases applied to the VPD operating points prior to load-line correction + /// in setting the external voltages. + /// Values in 0.5% + VpdBias ext_biases[VPD_PV_POINTS]; + + /// Loadlines and Distribution values for the VDD rail + SysPowerDistParms vdd_sysparm; + + /// Loadlines and Distribution values for the VCS rail + SysPowerDistParms vcs_sysparm; + + /// Loadlines and Distribution values for the VDN rail + SysPowerDistParms vdn_sysparm; + + /// The "Safe" Voltage + /// + /// A voltage to be used when safe-mode is activated + /// @todo Need to detail this out yet. + uint32_t safe_voltage_mv; + + /// The "Safe" Frequency + /// + /// A voltage to be used when safe-mode is activated + /// @todo Need to detail this out yet. + uint32_t safe_frequency_khz; + + /// The exponent of the exponential encoding of Pstate stepping delay + uint8_t vrm_stepdelay_range; + + /// The significand of the exponential encoding of Pstate stepping delay + uint8_t vrm_stepdelay_value; + + /// VDM Data + VDMParmBlock vdm; + + /// The following are needed to generated the Pstate Table to HOMER. + + /// Internal Biases + /// + /// Biases applied to the VPD operating points that are used for interpolation + /// in setting the internal voltages (eg Vout to the iVRMs) as part of the + /// Local Actual Pstate. + /// Values in 0.5% + VpdBias int_biases[VPD_PV_POINTS]; + + /// IVRM Data + IvrmParmBlock ivrm; + + /// Resonant Clock Grid Management Setup + ResonantClockingSetup resclk; + + /// Time b/w ext VRM detects write voltage cmd and when voltage begins to move + uint32_t ext_vrm_transition_start_ns; + + /// Transition rate for an increasing VDD voltage excursion + uint32_t ext_vrm_transition_rate_inc_uv_per_us; + + /// Transition rate for an decreasing VDD voltage excursion + uint32_t ext_vrm_transition_rate_dec_uv_per_us; + + /// Delay to account for VDD rail setting + uint32_t ext_vrm_stabilization_time_us; + + /// External VRM transition step size + uint32_t ext_vrm_step_size_mv; + + /// Nest frequency in Mhz. This is used by FIT interrupt + uint32_t nest_frequency_mhz; + + /// Precalculated Pstate-Voltage Slopes + uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION]; + + /// Precalculated Voltage-Pstates Slopes + uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION]; + + /// All operating points + VpdOperatingPoint operating_points_set[NUM_VPD_PTS_SET][VPD_PV_POINTS]; + + // @todo DPLL Droop Settings. These need communication to SGPE for STOP + +} GlobalPstateParmBlock; + + +#ifdef __cplusplus +} // end extern C +#endif +#endif /* __ASSEMBLER__ */ +#endif /* __P9_PSTATES_PGPE_H__ */ diff --git a/src/include/pstate_pgpe_occ_api.h b/src/include/pstate_pgpe_occ_api.h index e1c18f9..6768617 100644 --- a/src/include/pstate_pgpe_occ_api.h +++ b/src/include/pstate_pgpe_occ_api.h @@ -1,19 +1,25 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h $ */ +/* $Source: src/include/pstate_pgpe_occ_api.h $ */ /* */ -/* IBM CONFIDENTIAL */ +/* OpenPOWER OnChipController Project */ /* */ -/* EKB Project */ -/* */ -/* COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ -/* The source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// @file p9_pstates_pgpe_occ_api.h @@ -53,9 +59,6 @@ enum MESSAGE_ID_IPI2HI // // Return Codes // -//\todo -//Get feedback from Martha and Greg on these return codes -// #define PGPE_RC_SUCCESS 0x01 #define PGPE_WOF_RC_NOT_ENABLED 0x10 #define PGPE_RC_PSTATES_DISABLED 0x11 @@ -101,8 +104,8 @@ typedef struct ipcmsg_start_stop typedef struct ipcmsg_clip_update { ipcmsg_base_t msg_cb; - uint8_t ps_val_clip_min[MAX_QUADS]; - uint8_t ps_val_clip_max[MAX_QUADS]; + uint8_t ps_val_clip_min[MAXIMUM_QUADS]; + uint8_t ps_val_clip_max[MAXIMUM_QUADS]; uint8_t pad[2]; } ipcmsg_clip_update_t; @@ -111,7 +114,7 @@ typedef struct ipcmsg_set_pmcr { ipcmsg_base_t msg_cb; uint8_t pad[6]; - uint64_t pmcr[MAX_QUADS]; + uint64_t pmcr[MAXIMUM_QUADS]; } ipcmsg_set_pmcr_t; @@ -269,10 +272,10 @@ typedef union quad_state0 uint64_t quad1_pstate : 8; // Pstate of Quad 1; 0xFF indicates EQ is off uint64_t quad2_pstate : 8; // Pstate of Quad 2; 0xFF indicates EQ is off uint64_t quad3_pstate : 8; // Pstate of Quad 3; 0xFF indicates EQ is off - uint64_t core_poweron_state : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15 - uint64_t ivrm_state : 4; // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3 - uint64_t ivrm_state_rsvd : 4; - uint64_t external_vrm_setpoint : 8; // set point in mV + uint64_t active_cores : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15 + uint64_t ivrm_state : + 8; // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3, 4: quad4, 5: quad5, 6-7:reserved + uint64_t reserved : 8; // reserved for future use } fields; } quad_state0_t; @@ -288,15 +291,47 @@ typedef union quad_state1 { uint64_t quad4_pstate : 8; // Pstate of Quad 4; 0xFF indicates EQ is off uint64_t quad5_pstate : 8; // Pstate of Quad 5; 0xFF indicates EQ is off - uint64_t reserved : 16; - uint64_t ivrm_state : 2; // ivrm state: bit vector 0:quad4, 1:quad5 - uint64_t ivrm_state_rsvd : 6; - uint64_t core_poweron_state : 8; // bit vector: 0:core16, 1:core17, ..., 7:core23 - uint64_t requested_active_quad : 8; - uint64_t external_vrm_setpoint : 8; // set point in mV + uint64_t reserved0 : 16; + uint64_t active_cores : 16; // bit vector: 0:core16, 1:core17, ..., 7:core23 + uint64_t ivrm_state : + 8; // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3, 4: quad4, 5: quad5, 6-7:reserved + uint64_t reserved1 : 8; // reserved for future use } fields; } quad_state1_t; +typedef union pgpe_wof_state +{ + uint64_t value; + struct + { + uint32_t high_order; + uint32_t low_order; + } words; + struct + { + uint64_t reserved0 : 8; + uint64_t fclip_ps : 8; + uint64_t vclip_mv : 16; + uint64_t fratio : 16; + uint64_t vratio : 16; + } fields; +} pgpe_wof_state_t; + +typedef union requested_active_quads +{ + uint64_t value; + struct + { + uint32_t high_order; + uint32_t low_order; + } words; + struct + { + uint64_t reserved : 56; + uint64_t requested_active_quads : 8; + } fields; +} requested_active_quads_t; + // End Quad State // ----------------------------------------------------------------------------- @@ -315,6 +350,12 @@ typedef struct /// Actual Pstate 1 - Quads 4, 5 quad_state1_t quad_pstate_1; + ///PGPE WOF State + pgpe_wof_state_t pgpe_wof_state; + + ///Requested Active Quads + requested_active_quads_t req_active_quads; + /// FFDC Address list Hcode_FFDC_list_t ffdc_list; diff --git a/src/occ_405/amec/amec_freq.c b/src/occ_405/amec/amec_freq.c index 6b33d1e..06f3e64 100755 --- a/src/occ_405/amec/amec_freq.c +++ b/src/occ_405/amec/amec_freq.c @@ -533,18 +533,18 @@ void amec_slv_freq_smh(void) uint8_t quad = 0; // loop through quads uint8_t core_num = 0; // core ID uint8_t core_idx = 0; // loop through cores within each quad - Pstate pmax[MAX_QUADS] = {0}; // max pstate (min frequency) within each quad + Pstate pmax[MAXIMUM_QUADS] = {0}; // max pstate (min frequency) within each quad Pstate pmax_chip = 0; // highest Pstate (lowest frequency) across all quads - bool l_atLeast1Core[MAX_QUADS] = {FALSE}; // at least 1 core present in quad - static bool L_mfg_set_trace[MAX_QUADS] = {FALSE}; - static bool L_mfg_clear_trace[MAX_QUADS] = {FALSE}; + bool l_atLeast1Core[MAXIMUM_QUADS] = {FALSE}; // at least 1 core present in quad + static bool L_mfg_set_trace[MAXIMUM_QUADS] = {FALSE}; + static bool L_mfg_clear_trace[MAXIMUM_QUADS] = {FALSE}; /*------------------------------------------------------------------------*/ /* Code */ /*------------------------------------------------------------------------*/ // loop through all quads, get f_requests, translate to pstates and determine pmax across chip - for (quad = 0; quad < MAX_QUADS; quad++) + for (quad = 0; quad < MAXIMUM_QUADS; quad++) { for (core_idx=0; core_idx<NUM_CORES_PER_QUAD; core_idx++) // loop thru all cores in quad { @@ -566,7 +566,7 @@ void amec_slv_freq_smh(void) } // check for mfg quad Pstate request and set Pstate for each quad - for (quad = 0; quad < MAX_QUADS; quad++) + for (quad = 0; quad < MAXIMUM_QUADS; quad++) { // set quad with no cores present to lowest frequency for the chip if(l_atLeast1Core[quad] == FALSE) diff --git a/src/occ_405/amec/amec_parm_table.c b/src/occ_405/amec/amec_parm_table.c index 73291ad..9328e19 100755 --- a/src/occ_405/amec/amec_parm_table.c +++ b/src/occ_405/amec/amec_parm_table.c @@ -155,16 +155,16 @@ amec_parm_t g_amec_parm_list[] = { AMEC_PARM_UINT16(PARM_VDD_STEP_FROM_START, "vdd_stp_frm_strt", &g_amec_sys.wof.vdd_step_from_start), AMEC_PARM_UINT16(PARM_VDN_STEP_FROM_START, "vdn_stp_frm_strt", &g_amec_sys.wof.vdn_step_from_start), AMEC_PARM_UINT8(PARM_QUAD_STEP_FROM_START, "quadStpFrmStrt", &g_amec_sys.wof.quad_step_from_start), - AMEC_PARM_UINT32_ARRAY(PARM_V_CORE, "v_core_100uV", &g_amec_sys.wof.v_core_100uV, MAX_QUADS), + AMEC_PARM_UINT32_ARRAY(PARM_V_CORE, "v_core_100uV", &g_amec_sys.wof.v_core_100uV, MAXIMUM_QUADS), AMEC_PARM_UINT32(PARM_CORE_PWR_ON, "core_pwr_on", &g_amec_sys.wof.core_pwr_on), - AMEC_PARM_UINT8_ARRAY(PARM_CORES_ON_PER_QUAD, "coreson_per_quad", &g_amec_sys.wof.cores_on_per_quad, MAX_QUADS), + AMEC_PARM_UINT8_ARRAY(PARM_CORES_ON_PER_QUAD, "coreson_per_quad", &g_amec_sys.wof.cores_on_per_quad, MAXIMUM_QUADS), AMEC_PARM_UINT16(PARM_WOF_DISABLED, "wof_disabled", &g_amec_sys.wof.wof_disabled), AMEC_PARM_UINT32(PARM_VOLT_VDD_SENSE, "voltvddsense", &g_amec_sys.wof.voltvddsense_sensor), AMEC_PARM_UINT16_ARRAY(PARM_TEMPPROCTHERMC, "tempprocthrmc", &g_amec_sys.wof.tempprocthrmc, MAX_NUM_CORES), AMEC_PARM_UINT16(PARM_TEMPNEST, "tempnest_sensor", &g_amec_sys.wof.tempnest_sensor), - AMEC_PARM_UINT16_ARRAY(PARM_TEMPQ, "tempq", &g_amec_sys.wof.tempq, MAX_QUADS), + AMEC_PARM_UINT16_ARRAY(PARM_TEMPQ, "tempq", &g_amec_sys.wof.tempq, MAXIMUM_QUADS), AMEC_PARM_UINT16(PARM_VOLTVDN, "voltvdn_sensor", &g_amec_sys.wof.voltvdn_sensor), - AMEC_PARM_UINT8_ARRAY(PARM_QUAD_X_PSTATES, "quad_x_pstates", &g_amec_sys.wof.quad_x_pstates, MAX_QUADS), + AMEC_PARM_UINT8_ARRAY(PARM_QUAD_X_PSTATES, "quad_x_pstates", &g_amec_sys.wof.quad_x_pstates, MAXIMUM_QUADS), AMEC_PARM_UINT8(PARM_IVRM_STATES, "quad_ivrm_states", &g_amec_sys.wof.quad_ivrm_states), AMEC_PARM_UINT32(PARM_IDC_VDD, "idc_vdd", &g_amec_sys.wof.idc_vdd), AMEC_PARM_UINT32(PARM_IDC_VDN, "idc_vdn", &g_amec_sys.wof.idc_vdn), @@ -187,12 +187,12 @@ amec_parm_t g_amec_parm_list[] = { AMEC_PARM_UINT8(PARM_VOLTAGE_IDX, "voltage_idx", &g_amec_sys.wof.voltage_idx), AMEC_PARM_UINT32(PARM_ALL_CORES_OFF_ISO, "allcores_off_iso", &g_amec_sys.wof.all_cores_off_iso), AMEC_PARM_UINT32(PARM_ALL_CACHES_ON_ISO, "allcaches_on_iso", &g_amec_sys.wof.all_caches_on_iso), - AMEC_PARM_UINT16_ARRAY(PARM_QUAD_GOOD_CORES_ONLY, "quad_good_cores", &g_amec_sys.wof.quad_good_cores_only, MAX_QUADS), - AMEC_PARM_UINT16_ARRAY(PARM_QUAD_ON_CORES, "quad_on_cores", &g_amec_sys.wof.quad_on_cores, MAX_QUADS), - AMEC_PARM_UINT16_ARRAY(PARM_QUAD_BAD_OFF_CORES,"quadBadOffCores", &g_amec_sys.wof.quad_on_cores, MAX_QUADS), + AMEC_PARM_UINT16_ARRAY(PARM_QUAD_GOOD_CORES_ONLY, "quad_good_cores", &g_amec_sys.wof.quad_good_cores_only, MAXIMUM_QUADS), + AMEC_PARM_UINT16_ARRAY(PARM_QUAD_ON_CORES, "quad_on_cores", &g_amec_sys.wof.quad_on_cores, MAXIMUM_QUADS), + AMEC_PARM_UINT16_ARRAY(PARM_QUAD_BAD_OFF_CORES,"quadBadOffCores", &g_amec_sys.wof.quad_on_cores, MAXIMUM_QUADS), AMEC_PARM_UINT32(PARM_NEST_MULT, "nest_mult", &g_amec_sys.wof.nest_mult), AMEC_PARM_UINT32_ARRAY(PARM_CORE_MULT, "core_mult", &g_amec_sys.wof.core_mult, MAX_NUM_CORES), - AMEC_PARM_UINT32_ARRAY(PARM_QUAD_MULT, "quad_mult", &g_amec_sys.wof.quad_mult, MAX_QUADS), + AMEC_PARM_UINT32_ARRAY(PARM_QUAD_MULT, "quad_mult", &g_amec_sys.wof.quad_mult, MAXIMUM_QUADS), AMEC_PARM_INT16(PARM_NEST_DELTA_TEMP, "nest_delta_temp", &g_amec_sys.wof.nest_delta_temp), AMEC_PARM_INT16_ARRAY(PARM_CORE_DELTA_TEMP, "core_delta_temp", &g_amec_sys.wof.core_delta_temp, MAX_NUM_CORES), AMEC_PARM_INT16_ARRAY(PARM_QUAD_DELTA_TEMP, "quad_delta_temp", &g_amec_sys.wof.quad_delta_temp, MAX_NUM_CORES), diff --git a/src/occ_405/amec/amec_sys.h b/src/occ_405/amec/amec_sys.h index 0757466..68fd52a 100755 --- a/src/occ_405/amec/amec_sys.h +++ b/src/occ_405/amec/amec_sys.h @@ -438,7 +438,7 @@ typedef struct amec_memctl_t memctl[MAX_NUM_MEM_CONTROLLERS]; amec_vrm_t vrm[NUM_PROC_VRMS]; amec_proc_pwr_votes_t pwr_votes; - amec_quad_t quad[MAX_QUADS]; + amec_quad_t quad[MAXIMUM_QUADS]; // Processor Sensors sensor_t freqa4ms; @@ -527,7 +527,7 @@ typedef struct amec_mnfg ///memory slewing count uint32_t mem_slew_counter; ///Per Quad Pstate request: 0xFF=no request - uint8_t quad_pstate[MAX_QUADS]; + uint8_t quad_pstate[MAXIMUM_QUADS]; } amec_mnfg_t; //------------------------------------------------------------- diff --git a/src/occ_405/cmdh/cmdh_mnfg_intf.c b/src/occ_405/cmdh/cmdh_mnfg_intf.c index a270b76..d6fe0d3 100755 --- a/src/occ_405/cmdh/cmdh_mnfg_intf.c +++ b/src/occ_405/cmdh/cmdh_mnfg_intf.c @@ -675,7 +675,7 @@ uint8_t cmdh_mnfg_request_quad_pstate(const cmdh_fsp_cmd_t * i_cmd_ptr, // Process each quad Pstate request, clip any request to min/max // 0xFF has special meaning that OCC is in control - for(l_quad = 0; l_quad < MAX_QUADS; l_quad++) + for(l_quad = 0; l_quad < MAXIMUM_QUADS; l_quad++) { l_pstate_request = l_cmd_ptr->quad_pstate_in[l_quad]; if(l_pstate_request != 0xFF) diff --git a/src/occ_405/cmdh/cmdh_mnfg_intf.h b/src/occ_405/cmdh/cmdh_mnfg_intf.h index e96ce0c..d46ce3c 100755 --- a/src/occ_405/cmdh/cmdh_mnfg_intf.h +++ b/src/occ_405/cmdh/cmdh_mnfg_intf.h @@ -177,14 +177,14 @@ typedef struct __attribute__ ((packed)) struct cmdh_fsp_cmd_header; uint8_t sub_cmd; uint8_t version; - uint8_t quad_pstate_in[MAX_QUADS]; + uint8_t quad_pstate_in[MAXIMUM_QUADS]; }mnfg_quad_pstate_cmd_t; // Used by OCC firmware to respond to mnfg request quad pstate command typedef struct __attribute__ ((packed)) { struct cmdh_fsp_rsp_header; - uint8_t quad_pstate_out[MAX_QUADS]; + uint8_t quad_pstate_out[MAXIMUM_QUADS]; }mnfg_quad_pstate_rsp_t; errlHndl_t cmdh_mnfg_test_parse (const cmdh_fsp_cmd_t * i_cmd_ptr, diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c index 859144f..d3d243d 100755 --- a/src/occ_405/occbuildname.c +++ b/src/occ_405/occbuildname.c @@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = #else -volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_170322a\0" /*</BuildName>*/ ; +volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_170413a\0" /*</BuildName>*/ ; #endif diff --git a/src/occ_405/pgpe/pgpe_interface.c b/src/occ_405/pgpe/pgpe_interface.c index bb94efa..0aeee12 100644 --- a/src/occ_405/pgpe/pgpe_interface.c +++ b/src/occ_405/pgpe/pgpe_interface.c @@ -585,7 +585,7 @@ int pgpe_set_clip_ranges(Pstate i_pstate) Pstate pmax = i_pstate; // Set clip bounds - for(quad=0; quad<MAX_QUADS; quad++) + for(quad=0; quad<MAXIMUM_QUADS; quad++) { // Minimum pstate G_clip_update_parms_ptr->ps_val_clip_min[quad] = pmin; diff --git a/src/occ_405/proc/proc_data_control.c b/src/occ_405/proc/proc_data_control.c index 0733e66..a22fd43 100755 --- a/src/occ_405/proc/proc_data_control.c +++ b/src/occ_405/proc/proc_data_control.c @@ -109,7 +109,7 @@ void task_core_data_control( task_t * i_task ) // Only if last clip update sent to PGPE is larger than legacy turbo, // send new clips with legacy turbo values, otherwise, no action needed. - for (quad = 0; quad < MAX_QUADS; quad++) + for (quad = 0; quad < MAXIMUM_QUADS; quad++) { if(G_clip_update_parms_ptr->ps_val_clip_max[quad] < pclip) { diff --git a/src/occ_405/state.c b/src/occ_405/state.c index 36c1ec3..b38b18e 100755 --- a/src/occ_405/state.c +++ b/src/occ_405/state.c @@ -590,7 +590,7 @@ errlHndl_t SMGR_observation_to_active() Pstate l_pstate; // clear mnfg quad pstate request to default OCC to control all quads - memset(&g_amec->mnfg_parms.quad_pstate[0], 0xFF, MAX_QUADS); + memset(&g_amec->mnfg_parms.quad_pstate[0], 0xFF, MAXIMUM_QUADS); do { diff --git a/src/occ_405/wof/wof.c b/src/occ_405/wof/wof.c index 7e3d800..c1ed77b 100644 --- a/src/occ_405/wof/wof.c +++ b/src/occ_405/wof/wof.c @@ -587,13 +587,14 @@ void read_shared_sram( void ) // merge the 16-bit power-on field from quad state 0 and the 16-bit power-on // field from quad state 1 and save it to amec. - g_wof->core_pwr_on = - (((uint32_t)G_quad_state_0.fields.core_poweron_state) << 16) - | ((uint32_t)G_quad_state_1.fields.core_poweron_state); + // TODO: core_poweron_state not in new structure + //g_wof->core_pwr_on = + // (((uint32_t)G_quad_state_0.fields.core_poweron_state) << 16) + // | ((uint32_t)G_quad_state_1.fields.core_poweron_state); // Clear out current quad pstates - memset(g_wof->quad_x_pstates, 0 , MAX_QUADS); + memset(g_wof->quad_x_pstates, 0 , MAXIMUM_QUADS); // Add the quad states to the global quad state array for easy looping. g_wof->quad_x_pstates[0] = (uint8_t)G_quad_state_0.fields.quad0_pstate; @@ -622,7 +623,7 @@ void calculate_core_voltage( void ) uint32_t l_voltage; uint8_t l_quad_mask; int l_quad_idx = 0; - for(; l_quad_idx < MAX_QUADS; l_quad_idx++) + for(; l_quad_idx < MAXIMUM_QUADS; l_quad_idx++) { // Adjust current mask. (IVRM_STATE_QUAD_MASK = 0x80) l_quad_mask = IVRM_STATE_QUAD_MASK >> l_quad_idx; @@ -731,7 +732,7 @@ void calculate_core_leakage( void ) // Divide by 6 to get just one quad g_wof->idc_quad = G_oppb.iddq.ivdd_all_cores_off_caches_off[l_chip_v_idx] / - MAX_QUADS; + MAXIMUM_QUADS; @@ -758,7 +759,7 @@ void calculate_core_leakage( void ) G_oppb.iddq.ivdd_all_good_cores_off_good_caches_on[l_chip_v_idx] - g_wof->all_cores_off_iso; - l_quad_x_cache = g_wof->all_caches_on_iso / MAX_QUADS; + l_quad_x_cache = g_wof->all_caches_on_iso / MAXIMUM_QUADS; // Loop through all Quads and their respective Cores to calculate // leakage. @@ -768,7 +769,7 @@ void calculate_core_leakage( void ) - for(quad_idx = 0; quad_idx < MAX_QUADS; quad_idx++) + for(quad_idx = 0; quad_idx < MAXIMUM_QUADS; quad_idx++) { if(g_wof->quad_x_pstates[quad_idx] == QUAD_POWERED_OFF) { @@ -935,7 +936,8 @@ void calculate_nest_leakage( void ) uint32_t nest_mult = calculate_multiplier( nest_delta_temp ); // Save nest leakage to amec structure - g_wof->idc_vdn = (G_oppb.iddq.ivdn*nest_mult) >> 10; + // TODO: ivdn is now an array and need to handle + g_wof->idc_vdn = (G_oppb.iddq.ivdn[0]*nest_mult) >> 10; } diff --git a/src/occ_405/wof/wof.h b/src/occ_405/wof/wof.h index ffe3e71..2a680ee 100644 --- a/src/occ_405/wof/wof.h +++ b/src/occ_405/wof/wof.h @@ -96,11 +96,11 @@ typedef struct // Calculated step from start for quads uint8_t quad_step_from_start; // Array to hold the core voltages per quad (in 100uV) - uint32_t v_core_100uV[MAX_QUADS]; + uint32_t v_core_100uV[MAXIMUM_QUADS]; // Bit vector to hold the power on status of all 24 cores uint32_t core_pwr_on; // Number of cores on per quad - uint8_t cores_on_per_quad[MAX_QUADS]; + uint8_t cores_on_per_quad[MAXIMUM_QUADS]; // The most recently read value in the sensor VOLTVDDSENSE uint32_t voltvddsense_sensor; // The most recently read value in the sensor TEMPPROCTHRMCy where y is core num @@ -108,7 +108,7 @@ typedef struct // The most recently read value in the sensor TEMPNEST uint16_t tempnest_sensor; // The most recently read value in the sensor TEMPQx where x is the quad num - uint16_t tempq[MAX_QUADS]; + uint16_t tempq[MAXIMUM_QUADS]; // The most recently read value in the sensor CURVDD uint16_t curvdd_sensor; // The most recently read value in the sensor CURVDN @@ -116,7 +116,7 @@ typedef struct // The most recently read value in the sensor VOLTVDN uint16_t voltvdn_sensor; // Array to hold the current 1-byte pstate values read from SRAM. 0xFF=off - uint8_t quad_x_pstates[MAX_QUADS]; + uint8_t quad_x_pstates[MAXIMUM_QUADS]; // Bit vector to hold the ivrm states of the quads. 0=BYPASS, 1=REGULATION uint8_t quad_ivrm_states; // Contains the estimated core leakage based on temp, voltage, and vpd-leak @@ -160,17 +160,17 @@ typedef struct // Contains the final calculated value of ALL_CACHES_ON_ISO uint32_t all_caches_on_iso; // Contains good_cores_only (per_quad) - uint16_t quad_good_cores_only[MAX_QUADS]; + uint16_t quad_good_cores_only[MAXIMUM_QUADS]; // Contains on_cores - uint16_t quad_on_cores[MAX_QUADS]; + uint16_t quad_on_cores[MAXIMUM_QUADS]; // Contains BAD_OFF_cores - uint16_t quad_bad_off_cores[MAX_QUADS]; + uint16_t quad_bad_off_cores[MAXIMUM_QUADS]; // Contains the multiplier(m) used in y ~=(T*m)>>10 for nest leak calc uint32_t nest_mult; // Contains the multiplier(m) used in y ~=(T*m)>>10 for core leak calc 0-23 uint32_t core_mult[MAX_NUM_CORES]; // Contains the multiplier(m) used in y ~=(T*m)>>10 for quad leak calc 0-5 - uint32_t quad_mult[MAX_QUADS]; + uint32_t quad_mult[MAXIMUM_QUADS]; // Contains the delta temp used for nest leakage calc (see G_wof_iddq_mult_table) // TEMPNEST - tvpd_leak_off int16_t nest_delta_temp; @@ -179,7 +179,7 @@ typedef struct int16_t core_delta_temp[MAX_NUM_CORES]; // Contains the delta temp used for quad leakage calc // TEMPQx - tvpd_leak_cache (where x is the quad number) - int16_t quad_delta_temp[MAX_QUADS]; + int16_t quad_delta_temp[MAXIMUM_QUADS]; // tvpd leak to use when either the core is off, or the entire quad is off uint32_t tvpd_leak_off; // tvpd leak to use when the core is on diff --git a/src/ssx/occhw/occhw_pba.c b/src/ssx/occhw/occhw_pba.c index 15b4c35..cfdaa51 100644 --- a/src/ssx/occhw/occhw_pba.c +++ b/src/ssx/occhw/occhw_pba.c @@ -337,6 +337,7 @@ pbax_target_create(PbaxTarget* target, target->target.fields.snd_groupid = group; target->target.fields.snd_chipid = chip_or_group; target->target.fields.snd_cnt = cnt; + target->target.fields.vg_targe = 0xffff; return 0; } |