Enable Master-slave OCC communication

Change-Id: I445072e20d599e30f80cc8059b3f3b2a956c453e
RTC: 133154
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22005
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

38 files changed, 1625 insertions, 2025 deletions

diff --git a/src/include/registers/pba_firmware_constants.h b/src/include/registers/pba_firmware_constants.h
new file mode 100644
index 0000000..d4b66fb
--- /dev/null
+++ b/src/include/registers/pba_firmware_constants.h
@@ -0,0 +1,51 @@
+#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
+#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
+#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
+#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
+#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
+#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
+#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
+#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
+#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
+#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
+#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
+#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
+#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
+#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
+#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
+#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
+#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
+#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
+#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
+#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
+#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
+#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
+#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
+#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
+#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
+#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
+#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
+#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
+#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
+#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
+#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
+#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
+#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
+#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
+#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
+#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
+#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
+#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
+#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
+#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
+#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
+#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000)
+#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
+#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000)
+
diff --git a/src/include/registers/pba_firmware_registers.h b/src/include/registers/pba_firmware_registers.h
index e1b9f24..96e0b63 100644
--- a/src/include/registers/pba_firmware_registers.h
+++ b/src/include/registers/pba_firmware_registers.h
@@ -1,34 +1,10 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/include/registers/pba_firmware_registers.h $              */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PBA_FIRMWARE_REGISTERS_H__
 #define __PBA_FIRMWARE_REGISTERS_H__
 
-// $Id: pba_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_firmware_registers.h,v $
+// $Id$
+// $Source$
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2015
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -49,11 +25,11 @@
 #ifndef __ASSEMBLER__
 
 #include <stdint.h>
+#include "pba_firmware_constants.h"
 
 
 
-
-typedef union pba_barn {
+typedef union pba_mode {
 
     uint64_t value;
     struct {
@@ -67,28 +43,74 @@ typedef union pba_barn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t cmd_scope : 3;
-    uint64_t reserved0 : 1;
-    uint64_t reserved1 : 10;
-    uint64_t addr : 30;
-    uint64_t _reserved0 : 20;
-#else
-    uint64_t _reserved0 : 20;
-    uint64_t addr : 30;
-    uint64_t reserved1 : 10;
-    uint64_t reserved0 : 1;
-    uint64_t cmd_scope : 3;
+    uint64_t reserved1 : 4;
+    uint64_t dis_rearb : 1;
+    uint64_t dis_mstid_match_pref_inv : 1;
+    uint64_t dis_slave_rdpipe : 1;
+    uint64_t dis_slave_wrpipe : 1;
+    uint64_t en_marker_ack : 1;
+    uint64_t reserved2 : 1;
+    uint64_t en_second_wrbuf : 1;
+    uint64_t dis_rerequest_to : 1;
+    uint64_t inject_type : 2;
+    uint64_t inject_mode : 2;
+    uint64_t pba_region : 2;
+    uint64_t oci_marker_space : 3;
+    uint64_t bcde_ocitrans : 2;
+    uint64_t bcue_ocitrans : 2;
+    uint64_t dis_master_rd_pipe : 1;
+    uint64_t dis_master_wr_pipe : 1;
+    uint64_t en_slv_fairness : 1;
+    uint64_t en_event_count : 1;
+    uint64_t pb_noci_event_sel : 1;
+    uint64_t slv_event_mux : 2;
+    uint64_t enable_debug_bus : 1;
+    uint64_t debug_pb_not_oci : 1;
+    uint64_t debug_oci_mode : 5;
+    uint64_t reserved3 : 1;
+    uint64_t ocislv_fairness_mask : 5;
+    uint64_t ocislv_rereq_hang_div : 5;
+    uint64_t dis_chgrate_count : 1;
+    uint64_t pbreq_event_mux : 2;
+    uint64_t reserved4 : 11;
+#else
+    uint64_t reserved4 : 11;
+    uint64_t pbreq_event_mux : 2;
+    uint64_t dis_chgrate_count : 1;
+    uint64_t ocislv_rereq_hang_div : 5;
+    uint64_t ocislv_fairness_mask : 5;
+    uint64_t reserved3 : 1;
+    uint64_t debug_oci_mode : 5;
+    uint64_t debug_pb_not_oci : 1;
+    uint64_t enable_debug_bus : 1;
+    uint64_t slv_event_mux : 2;
+    uint64_t pb_noci_event_sel : 1;
+    uint64_t en_event_count : 1;
+    uint64_t en_slv_fairness : 1;
+    uint64_t dis_master_wr_pipe : 1;
+    uint64_t dis_master_rd_pipe : 1;
+    uint64_t bcue_ocitrans : 2;
+    uint64_t bcde_ocitrans : 2;
+    uint64_t oci_marker_space : 3;
+    uint64_t pba_region : 2;
+    uint64_t inject_mode : 2;
+    uint64_t inject_type : 2;
+    uint64_t dis_rerequest_to : 1;
+    uint64_t en_second_wrbuf : 1;
+    uint64_t reserved2 : 1;
+    uint64_t en_marker_ack : 1;
+    uint64_t dis_slave_wrpipe : 1;
+    uint64_t dis_slave_rdpipe : 1;
+    uint64_t dis_mstid_match_pref_inv : 1;
+    uint64_t dis_rearb : 1;
+    uint64_t reserved1 : 4;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_barn_t;
+} pba_mode_t;
 
-#endif // __ASSEMBLER__
-#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
-#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
-#ifndef __ASSEMBLER__
 
 
-typedef union pba_barmskn {
+typedef union pba_slvrst {
 
     uint64_t value;
     struct {
@@ -102,23 +124,26 @@ typedef union pba_barmskn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 23;
-    uint64_t mask : 21;
-    uint64_t _reserved0 : 20;
+    uint64_t set : 3;
+    uint64_t reserved1 : 1;
+    uint64_t in_prog : 4;
+    uint64_t busy_status : 4;
+    uint64_t scope_attn_bar : 2;
+    uint64_t reserved2 : 50;
 #else
-    uint64_t _reserved0 : 20;
-    uint64_t mask : 21;
-    uint64_t reserved0 : 23;
+    uint64_t reserved2 : 50;
+    uint64_t scope_attn_bar : 2;
+    uint64_t busy_status : 4;
+    uint64_t in_prog : 4;
+    uint64_t reserved1 : 1;
+    uint64_t set : 3;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_barmskn_t;
+} pba_slvrst_t;
 
-#endif // __ASSEMBLER__
-#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
-#ifndef __ASSEMBLER__
 
 
-typedef union pba_fir {
+typedef union pba_slvctln {
 
     uint64_t value;
     struct {
@@ -132,149 +157,54 @@ typedef union pba_fir {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t enable : 1;
+    uint64_t mid_match_value : 3;
+    uint64_t reserved1 : 1;
+    uint64_t mid_care_mask : 3;
+    uint64_t write_ttype : 3;
+    uint64_t reserved2 : 4;
+    uint64_t read_ttype : 1;
+    uint64_t read_prefetch_ctl : 2;
+    uint64_t buf_invalidate_ctl : 1;
+    uint64_t buf_alloc_w : 1;
+    uint64_t buf_alloc_a : 1;
+    uint64_t buf_alloc_b : 1;
+    uint64_t buf_alloc_c : 1;
+    uint64_t reserved3 : 1;
+    uint64_t dis_write_gather : 1;
+    uint64_t wr_gather_timeout : 3;
+    uint64_t write_tsize : 8;
+    uint64_t extaddr : 14;
+    uint64_t reserved4 : 1;
+    uint64_t reserved5 : 13;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved5 : 13;
+    uint64_t reserved4 : 1;
+    uint64_t extaddr : 14;
+    uint64_t write_tsize : 8;
+    uint64_t wr_gather_timeout : 3;
+    uint64_t dis_write_gather : 1;
+    uint64_t reserved3 : 1;
+    uint64_t buf_alloc_c : 1;
+    uint64_t buf_alloc_b : 1;
+    uint64_t buf_alloc_a : 1;
+    uint64_t buf_alloc_w : 1;
+    uint64_t buf_invalidate_ctl : 1;
+    uint64_t read_prefetch_ctl : 2;
+    uint64_t read_ttype : 1;
+    uint64_t reserved2 : 4;
+    uint64_t write_ttype : 3;
+    uint64_t mid_care_mask : 3;
+    uint64_t reserved1 : 1;
+    uint64_t mid_match_value : 3;
+    uint64_t enable : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_fir_t;
+} pba_slvctln_t;
 
-#endif // __ASSEMBLER__
-#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
-#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
-#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
-#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
-#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
-#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
-#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
-#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
-#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
-#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000)
-#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
-#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000)
-#ifndef __ASSEMBLER__
 
 
-typedef union pba_fir_and {
+typedef union pba_bcde_ctl {
 
     uint64_t value;
     struct {
@@ -288,104 +218,20 @@ typedef union pba_fir_and {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t stop : 1;
+    uint64_t start : 1;
+    uint64_t reserved1 : 62;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved1 : 62;
+    uint64_t start : 1;
+    uint64_t stop : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_fir_and_t;
+} pba_bcde_ctl_t;
 
 
 
-typedef union pba_fir_or {
+typedef union pba_bcde_set {
 
     uint64_t value;
     struct {
@@ -399,104 +245,20 @@ typedef union pba_fir_or {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t reserved1 : 2;
+    uint64_t copy_length : 6;
+    uint64_t reserved2 : 56;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved2 : 56;
+    uint64_t copy_length : 6;
+    uint64_t reserved1 : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_fir_or_t;
+} pba_bcde_set_t;
 
 
 
-typedef union pba_firmask {
+typedef union pba_bcde_stat {
 
     uint64_t value;
     struct {
@@ -510,104 +272,34 @@ typedef union pba_firmask {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t running : 1;
+    uint64_t waiting : 1;
+    uint64_t wrcmp : 6;
+    uint64_t reserved1 : 6;
+    uint64_t rdcmp : 6;
+    uint64_t debug : 9;
+    uint64_t stopped : 1;
+    uint64_t error : 1;
+    uint64_t done : 1;
+    uint64_t reserved2 : 32;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved2 : 32;
+    uint64_t done : 1;
+    uint64_t error : 1;
+    uint64_t stopped : 1;
+    uint64_t debug : 9;
+    uint64_t rdcmp : 6;
+    uint64_t reserved1 : 6;
+    uint64_t wrcmp : 6;
+    uint64_t waiting : 1;
+    uint64_t running : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_firmask_t;
+} pba_bcde_stat_t;
 
 
 
-typedef union pba_firmask_and {
+typedef union pba_bcde_pbadr {
 
     uint64_t value;
     struct {
@@ -621,104 +313,26 @@ typedef union pba_firmask_and {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t reserved1 : 2;
+    uint64_t pb_offset : 23;
+    uint64_t reserved2 : 2;
+    uint64_t extaddr : 14;
+    uint64_t reserved3 : 2;
+    uint64_t reserved4 : 21;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved4 : 21;
+    uint64_t reserved3 : 2;
+    uint64_t extaddr : 14;
+    uint64_t reserved2 : 2;
+    uint64_t pb_offset : 23;
+    uint64_t reserved1 : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_firmask_and_t;
+} pba_bcde_pbadr_t;
 
 
 
-typedef union pba_firmask_or {
+typedef union pba_bcde_ocibar {
 
     uint64_t value;
     struct {
@@ -732,104 +346,18 @@ typedef union pba_firmask_or {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t addr : 25;
+    uint64_t reserved1 : 39;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved1 : 39;
+    uint64_t addr : 25;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_firmask_or_t;
+} pba_bcde_ocibar_t;
 
 
 
-typedef union pba_firact0 {
+typedef union pba_bcue_ctl {
 
     uint64_t value;
     struct {
@@ -843,104 +371,20 @@ typedef union pba_firact0 {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t stop : 1;
+    uint64_t start : 1;
+    uint64_t reserved1 : 62;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved1 : 62;
+    uint64_t start : 1;
+    uint64_t stop : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_firact0_t;
+} pba_bcue_ctl_t;
 
 
 
-typedef union pba_firact1 {
+typedef union pba_bcue_set {
 
     uint64_t value;
     struct {
@@ -954,104 +398,20 @@ typedef union pba_firact1 {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t reserved1 : 2;
+    uint64_t copy_length : 6;
+    uint64_t reserved2 : 56;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved2 : 56;
+    uint64_t copy_length : 6;
+    uint64_t reserved1 : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_firact1_t;
+} pba_bcue_set_t;
 
 
 
-typedef union pba_occact {
+typedef union pba_bcue_stat {
 
     uint64_t value;
     struct {
@@ -1065,104 +425,34 @@ typedef union pba_occact {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t oci_apar_err : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t internal_err : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t reserved41 : 3;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t fir_parity_err : 1;
-    uint64_t _reserved0 : 18;
+    uint64_t running : 1;
+    uint64_t waiting : 1;
+    uint64_t wrcmp : 6;
+    uint64_t reserved1 : 6;
+    uint64_t rdcmp : 6;
+    uint64_t debug : 9;
+    uint64_t stopped : 1;
+    uint64_t error : 1;
+    uint64_t done : 1;
+    uint64_t reserved2 : 32;
 #else
-    uint64_t _reserved0 : 18;
-    uint64_t fir_parity_err : 1;
-    uint64_t fir_parity_err2 : 1;
-    uint64_t reserved41 : 3;
-    uint64_t pb_ackdead_fw_wr : 1;
-    uint64_t axsnd_rsverr : 1;
-    uint64_t axsnd_rsvto : 1;
-    uint64_t axsnd_dlo_rtyto : 1;
-    uint64_t axsnd_dhi_rtyto : 1;
-    uint64_t axflow_err : 1;
-    uint64_t axrcv_rsvdata_to : 1;
-    uint64_t axrcv_dlo_to : 1;
-    uint64_t axrcv_dlo_err : 1;
-    uint64_t axpush_wrerr : 1;
-    uint64_t oci_bad_reg_addr : 1;
-    uint64_t illegal_cache_op : 1;
-    uint64_t internal_err : 1;
-    uint64_t bcde_oci_dataerr : 1;
-    uint64_t bcde_ce : 1;
-    uint64_t bcde_ue_err : 1;
-    uint64_t bcde_sue_err : 1;
-    uint64_t bcde_rddatato_err : 1;
-    uint64_t bcde_pb_adrerr : 1;
-    uint64_t bcde_pb_ack_dead : 1;
-    uint64_t bcde_setup_err : 1;
-    uint64_t bcue_oci_dataerr : 1;
-    uint64_t bcue_pb_adrerr : 1;
-    uint64_t bcue_pb_ack_dead : 1;
-    uint64_t bcue_setup_err : 1;
-    uint64_t pb_crespto : 1;
-    uint64_t pb_ackdead_fw : 1;
-    uint64_t pb_badcresp : 1;
-    uint64_t pb_wradrerr_fw : 1;
-    uint64_t pb_parity_err : 1;
-    uint64_t pb_unexpdata : 1;
-    uint64_t pb_unexpcresp : 1;
-    uint64_t oci_rereqto : 1;
-    uint64_t oci_wrpar_err : 1;
-    uint64_t oci_slave_init : 1;
-    uint64_t pb_ce_fw : 1;
-    uint64_t pb_ue_fw : 1;
-    uint64_t pb_sue_fw : 1;
-    uint64_t pb_rddatato_fw : 1;
-    uint64_t pb_rdadrerr_fw : 1;
-    uint64_t oci_apar_err : 1;
+    uint64_t reserved2 : 32;
+    uint64_t done : 1;
+    uint64_t error : 1;
+    uint64_t stopped : 1;
+    uint64_t debug : 9;
+    uint64_t rdcmp : 6;
+    uint64_t reserved1 : 6;
+    uint64_t wrcmp : 6;
+    uint64_t waiting : 1;
+    uint64_t running : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_occact_t;
+} pba_bcue_stat_t;
 
 
 
-typedef union pba_cfg {
+typedef union pba_bcue_pbadr {
 
     uint64_t value;
     struct {
@@ -1176,62 +466,26 @@ typedef union pba_cfg {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t pbreq_slvfw_max_priority : 2;
-    uint64_t pbreq_bce_max_priority : 2;
-    uint64_t pbreq_data_hang_div : 5;
-    uint64_t pbreq_oper_hang_div : 5;
-    uint64_t pbreq_drop_priority_mask : 6;
-    uint64_t reserved20 : 4;
-    uint64_t chsw_hang_on_adrerror : 1;
-    uint64_t chsw_dis_ociabuspar_check : 1;
-    uint64_t chsw_dis_ocibepar_check : 1;
-    uint64_t chsw_hang_on_derror : 1;
-    uint64_t chsw_hang_on_rereq_timeout : 1;
-    uint64_t chsw_dis_write_match_rearb : 1;
-    uint64_t chsw_dis_ocidatapar_gen : 1;
-    uint64_t chsw_dis_ocidatapar_check : 1;
-    uint64_t chsw_dis_oper_hang : 1;
-    uint64_t chsw_dis_data_hang : 1;
-    uint64_t chsw_dis_ecc_check : 1;
-    uint64_t chsw_dis_retry_backoff : 1;
-    uint64_t chsw_hang_on_invalid_cresp : 1;
-    uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
-    uint64_t chsw_dis_group_scope : 1;
-    uint64_t chsw_dis_rtag_parity_chk : 1;
-    uint64_t chsw_dis_pb_parity_chk : 1;
-    uint64_t _reserved0 : 23;
+    uint64_t reserved1 : 2;
+    uint64_t pb_offset : 23;
+    uint64_t reserved2 : 2;
+    uint64_t extaddr : 14;
+    uint64_t reserved3 : 2;
+    uint64_t reserved4 : 21;
 #else
-    uint64_t _reserved0 : 23;
-    uint64_t chsw_dis_pb_parity_chk : 1;
-    uint64_t chsw_dis_rtag_parity_chk : 1;
-    uint64_t chsw_dis_group_scope : 1;
-    uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
-    uint64_t chsw_hang_on_invalid_cresp : 1;
-    uint64_t chsw_dis_retry_backoff : 1;
-    uint64_t chsw_dis_ecc_check : 1;
-    uint64_t chsw_dis_data_hang : 1;
-    uint64_t chsw_dis_oper_hang : 1;
-    uint64_t chsw_dis_ocidatapar_check : 1;
-    uint64_t chsw_dis_ocidatapar_gen : 1;
-    uint64_t chsw_dis_write_match_rearb : 1;
-    uint64_t chsw_hang_on_rereq_timeout : 1;
-    uint64_t chsw_hang_on_derror : 1;
-    uint64_t chsw_dis_ocibepar_check : 1;
-    uint64_t chsw_dis_ociabuspar_check : 1;
-    uint64_t chsw_hang_on_adrerror : 1;
-    uint64_t reserved20 : 4;
-    uint64_t pbreq_drop_priority_mask : 6;
-    uint64_t pbreq_oper_hang_div : 5;
-    uint64_t pbreq_data_hang_div : 5;
-    uint64_t pbreq_bce_max_priority : 2;
-    uint64_t pbreq_slvfw_max_priority : 2;
+    uint64_t reserved4 : 21;
+    uint64_t reserved3 : 2;
+    uint64_t extaddr : 14;
+    uint64_t reserved2 : 2;
+    uint64_t pb_offset : 23;
+    uint64_t reserved1 : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_cfg_t;
+} pba_bcue_pbadr_t;
 
 
 
-typedef union pba_errpt0 {
+typedef union pba_bcue_ocibar {
 
     uint64_t value;
     struct {
@@ -1245,30 +499,18 @@ typedef union pba_errpt0 {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t cerr_pb_rddatato_fw : 6;
-    uint64_t cerr_pb_rdadrerr_fw : 6;
-    uint64_t cerr_pb_wradrerr_fw : 4;
-    uint64_t cerr_pb_ackdead_fw_rd : 6;
-    uint64_t cerr_pb_ackdead_fw_wr : 2;
-    uint64_t cerr_pb_unexpcresp : 11;
-    uint64_t cerr_pb_unexpdata : 6;
-    uint64_t _reserved0 : 23;
+    uint64_t addr : 25;
+    uint64_t reserved1 : 39;
 #else
-    uint64_t _reserved0 : 23;
-    uint64_t cerr_pb_unexpdata : 6;
-    uint64_t cerr_pb_unexpcresp : 11;
-    uint64_t cerr_pb_ackdead_fw_wr : 2;
-    uint64_t cerr_pb_ackdead_fw_rd : 6;
-    uint64_t cerr_pb_wradrerr_fw : 4;
-    uint64_t cerr_pb_rdadrerr_fw : 6;
-    uint64_t cerr_pb_rddatato_fw : 6;
+    uint64_t reserved1 : 39;
+    uint64_t addr : 25;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_errpt0_t;
+} pba_bcue_ocibar_t;
 
 
 
-typedef union pba_errpt1 {
+typedef union pba_pbocrn {
 
     uint64_t value;
     struct {
@@ -1282,28 +524,22 @@ typedef union pba_errpt1 {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t cerr_pb_badcresp : 12;
-    uint64_t cerr_pb_crespto : 12;
-    uint64_t cerr_oci_rereqto : 6;
-    uint64_t cerr_bcde_setup_err : 2;
-    uint64_t cerr_bcue_setup_err : 2;
-    uint64_t cerr_bcue_oci_dataerr : 2;
-    uint64_t _reserved0 : 28;
+    uint64_t reserved1 : 16;
+    uint64_t event : 16;
+    uint64_t reserved2 : 12;
+    uint64_t accum : 20;
 #else
-    uint64_t _reserved0 : 28;
-    uint64_t cerr_bcue_oci_dataerr : 2;
-    uint64_t cerr_bcue_setup_err : 2;
-    uint64_t cerr_bcde_setup_err : 2;
-    uint64_t cerr_oci_rereqto : 6;
-    uint64_t cerr_pb_crespto : 12;
-    uint64_t cerr_pb_badcresp : 12;
+    uint64_t accum : 20;
+    uint64_t reserved2 : 12;
+    uint64_t event : 16;
+    uint64_t reserved1 : 16;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_errpt1_t;
+} pba_pbocrn_t;
 
 
 
-typedef union pba_errpt2 {
+typedef union pba_xsndtx {
 
     uint64_t value;
     struct {
@@ -1317,36 +553,38 @@ typedef union pba_errpt2 {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t cerr_slv_internal_err : 8;
-    uint64_t cerr_bcde_internal_err : 4;
-    uint64_t cerr_bcue_internal_err : 4;
-    uint64_t cerr_bar_parity_err : 1;
-    uint64_t cerr_scomtb_err : 1;
-    uint64_t reserved18 : 2;
-    uint64_t cerr_pbdout_parity_err : 1;
-    uint64_t cerr_pb_parity_err : 3;
-    uint64_t cerr_axflow_err : 5;
-    uint64_t cerr_axpush_wrerr : 2;
-    uint64_t _reserved0 : 33;
-#else
-    uint64_t _reserved0 : 33;
-    uint64_t cerr_axpush_wrerr : 2;
-    uint64_t cerr_axflow_err : 5;
-    uint64_t cerr_pb_parity_err : 3;
-    uint64_t cerr_pbdout_parity_err : 1;
-    uint64_t reserved18 : 2;
-    uint64_t cerr_scomtb_err : 1;
-    uint64_t cerr_bar_parity_err : 1;
-    uint64_t cerr_bcue_internal_err : 4;
-    uint64_t cerr_bcde_internal_err : 4;
-    uint64_t cerr_slv_internal_err : 8;
+    uint64_t snd_scope : 3;
+    uint64_t snd_qid : 1;
+    uint64_t snd_type : 1;
+    uint64_t snd_reservation : 1;
+    uint64_t reserved1 : 2;
+    uint64_t snd_groupid : 4;
+    uint64_t snd_chipid : 3;
+    uint64_t reserved2 : 1;
+    uint64_t vg_targe : 16;
+    uint64_t reserved3 : 27;
+    uint64_t snd_stop : 1;
+    uint64_t snd_cnt : 4;
+#else
+    uint64_t snd_cnt : 4;
+    uint64_t snd_stop : 1;
+    uint64_t reserved3 : 27;
+    uint64_t vg_targe : 16;
+    uint64_t reserved2 : 1;
+    uint64_t snd_chipid : 3;
+    uint64_t snd_groupid : 4;
+    uint64_t reserved1 : 2;
+    uint64_t snd_reservation : 1;
+    uint64_t snd_type : 1;
+    uint64_t snd_qid : 1;
+    uint64_t snd_scope : 3;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_errpt2_t;
+} pba_xsndtx_t;
 
 
 
-typedef union pba_rbufvaln {
+typedef union pba_xcfg {
 
     uint64_t value;
     struct {
@@ -1360,36 +598,42 @@ typedef union pba_rbufvaln {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t rd_slvnum : 2;
-    uint64_t cur_rd_addr : 23;
-    uint64_t spare1 : 3;
-    uint64_t prefetch : 1;
-    uint64_t spare2 : 2;
-    uint64_t abort : 1;
-    uint64_t spare3 : 1;
-    uint64_t buffer_status : 7;
-    uint64_t spare4 : 1;
-    uint64_t masterid : 3;
-    uint64_t _reserved0 : 20;
+    uint64_t pbax_en : 1;
+    uint64_t reservation_en : 1;
+    uint64_t snd_reset : 1;
+    uint64_t rcv_reset : 1;
+    uint64_t rcv_groupid : 4;
+    uint64_t rcv_chipid : 3;
+    uint64_t reserved1 : 1;
+    uint64_t rcv_brdcst_group : 8;
+    uint64_t rcv_datato_div : 5;
+    uint64_t reserved2 : 2;
+    uint64_t snd_retry_count_overcom : 1;
+    uint64_t snd_retry_thresh : 8;
+    uint64_t snd_rsvto_div : 5;
+    uint64_t reserved3 : 23;
 #else
-    uint64_t _reserved0 : 20;
-    uint64_t masterid : 3;
-    uint64_t spare4 : 1;
-    uint64_t buffer_status : 7;
-    uint64_t spare3 : 1;
-    uint64_t abort : 1;
-    uint64_t spare2 : 2;
-    uint64_t prefetch : 1;
-    uint64_t spare1 : 3;
-    uint64_t cur_rd_addr : 23;
-    uint64_t rd_slvnum : 2;
+    uint64_t reserved3 : 23;
+    uint64_t snd_rsvto_div : 5;
+    uint64_t snd_retry_thresh : 8;
+    uint64_t snd_retry_count_overcom : 1;
+    uint64_t reserved2 : 2;
+    uint64_t rcv_datato_div : 5;
+    uint64_t rcv_brdcst_group : 8;
+    uint64_t reserved1 : 1;
+    uint64_t rcv_chipid : 3;
+    uint64_t rcv_groupid : 4;
+    uint64_t rcv_reset : 1;
+    uint64_t snd_reset : 1;
+    uint64_t reservation_en : 1;
+    uint64_t pbax_en : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_rbufvaln_t;
+} pba_xcfg_t;
 
 
 
-typedef union pba_wbufvaln {
+typedef union pba_xsndstat {
 
     uint64_t value;
     struct {
@@ -1403,28 +647,26 @@ typedef union pba_wbufvaln {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t wr_slvnum : 2;
-    uint64_t start_wr_addr : 30;
-    uint64_t spare1 : 3;
-    uint64_t wr_buffer_status : 5;
-    uint64_t spare2 : 1;
-    uint64_t wr_byte_count : 7;
-    uint64_t spare3 : 16;
+    uint64_t snd_in_progress : 1;
+    uint64_t snd_error : 1;
+    uint64_t snd_phase_status : 2;
+    uint64_t snd_cnt_status : 4;
+    uint64_t snd_retry_count : 8;
+    uint64_t reserved1 : 48;
 #else
-    uint64_t spare3 : 16;
-    uint64_t wr_byte_count : 7;
-    uint64_t spare2 : 1;
-    uint64_t wr_buffer_status : 5;
-    uint64_t spare1 : 3;
-    uint64_t start_wr_addr : 30;
-    uint64_t wr_slvnum : 2;
+    uint64_t reserved1 : 48;
+    uint64_t snd_retry_count : 8;
+    uint64_t snd_cnt_status : 4;
+    uint64_t snd_phase_status : 2;
+    uint64_t snd_error : 1;
+    uint64_t snd_in_progress : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_wbufvaln_t;
+} pba_xsndstat_t;
 
 
 
-typedef union pba_mode {
+typedef union pba_xsnddat {
 
     uint64_t value;
     struct {
@@ -1438,74 +680,18 @@ typedef union pba_mode {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t reserved0 : 4;
-    uint64_t dis_rearb : 1;
-    uint64_t dis_mstid_match_pref_inv : 1;
-    uint64_t dis_slave_rdpipe : 1;
-    uint64_t dis_slave_wrpipe : 1;
-    uint64_t en_marker_ack : 1;
-    uint64_t dis_slvmatch_order : 1;
-    uint64_t en_second_wrbuf : 1;
-    uint64_t dis_rerequest_to : 1;
-    uint64_t inject_type : 2;
-    uint64_t inject_mode : 2;
-    uint64_t pba_region : 2;
-    uint64_t oci_marker_space : 3;
-    uint64_t bcde_ocitrans : 2;
-    uint64_t bcue_ocitrans : 2;
-    uint64_t dis_master_rd_pipe : 1;
-    uint64_t dis_master_wr_pipe : 1;
-    uint64_t en_slave_fairness : 1;
-    uint64_t en_event_count : 1;
-    uint64_t pb_noci_event_sel : 1;
-    uint64_t slv_event_mux : 2;
-    uint64_t enable_debug_bus : 1;
-    uint64_t debug_pb_not_oci : 1;
-    uint64_t debug_oci_mode : 5;
-    uint64_t reserved2 : 1;
-    uint64_t ocislv_fairness_mask : 5;
-    uint64_t ocislv_rereq_hang_div : 5;
-    uint64_t dis_chgrate_count : 1;
-    uint64_t pbreq_event_mux : 2;
-    uint64_t _reserved0 : 11;
+    uint64_t pbax_datahi : 32;
+    uint64_t pbax_datalo : 32;
 #else
-    uint64_t _reserved0 : 11;
-    uint64_t pbreq_event_mux : 2;
-    uint64_t dis_chgrate_count : 1;
-    uint64_t ocislv_rereq_hang_div : 5;
-    uint64_t ocislv_fairness_mask : 5;
-    uint64_t reserved2 : 1;
-    uint64_t debug_oci_mode : 5;
-    uint64_t debug_pb_not_oci : 1;
-    uint64_t enable_debug_bus : 1;
-    uint64_t slv_event_mux : 2;
-    uint64_t pb_noci_event_sel : 1;
-    uint64_t en_event_count : 1;
-    uint64_t en_slave_fairness : 1;
-    uint64_t dis_master_wr_pipe : 1;
-    uint64_t dis_master_rd_pipe : 1;
-    uint64_t bcue_ocitrans : 2;
-    uint64_t bcde_ocitrans : 2;
-    uint64_t oci_marker_space : 3;
-    uint64_t pba_region : 2;
-    uint64_t inject_mode : 2;
-    uint64_t inject_type : 2;
-    uint64_t dis_rerequest_to : 1;
-    uint64_t en_second_wrbuf : 1;
-    uint64_t dis_slvmatch_order : 1;
-    uint64_t en_marker_ack : 1;
-    uint64_t dis_slave_wrpipe : 1;
-    uint64_t dis_slave_rdpipe : 1;
-    uint64_t dis_mstid_match_pref_inv : 1;
-    uint64_t dis_rearb : 1;
-    uint64_t reserved0 : 4;
+    uint64_t pbax_datalo : 32;
+    uint64_t pbax_datahi : 32;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_mode_t;
+} pba_xsnddat_t;
 
 
 
-typedef union pba_slvrst {
+typedef union pba_xrcvstat {
 
     uint64_t value;
     struct {
@@ -1519,24 +705,26 @@ typedef union pba_slvrst {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t set : 3;
-    uint64_t notimp1 : 1;
-    uint64_t in_prog : 4;
-    uint64_t busy_status : 4;
-    uint64_t _reserved0 : 52;
+    uint64_t rcv_in_progress : 1;
+    uint64_t rcv_error : 1;
+    uint64_t rcv_write_in_progress : 1;
+    uint64_t rcv_reservation_set : 1;
+    uint64_t rcv_capture : 16;
+    uint64_t reserved1 : 44;
 #else
-    uint64_t _reserved0 : 52;
-    uint64_t busy_status : 4;
-    uint64_t in_prog : 4;
-    uint64_t notimp1 : 1;
-    uint64_t set : 3;
+    uint64_t reserved1 : 44;
+    uint64_t rcv_capture : 16;
+    uint64_t rcv_reservation_set : 1;
+    uint64_t rcv_write_in_progress : 1;
+    uint64_t rcv_error : 1;
+    uint64_t rcv_in_progress : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_slvrst_t;
+} pba_xrcvstat_t;
 
 
 
-typedef union pba_slvctln {
+typedef union pba_xshbrn {
 
     uint64_t value;
     struct {
@@ -1550,52 +738,18 @@ typedef union pba_slvctln {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t enable : 1;
-    uint64_t mid_match_value : 3;
-    uint64_t _reserved0 : 1;
-    uint64_t mid_care_mask : 3;
-    uint64_t write_ttype : 3;
-    uint64_t _reserved1 : 4;
-    uint64_t read_ttype : 1;
-    uint64_t read_prefetch_ctl : 2;
-    uint64_t buf_invalidate_ctl : 1;
-    uint64_t buf_alloc_w : 1;
-    uint64_t buf_alloc_a : 1;
-    uint64_t buf_alloc_b : 1;
-    uint64_t buf_alloc_c : 1;
-    uint64_t _reserved2 : 1;
-    uint64_t dis_write_gather : 1;
-    uint64_t wr_gather_timeout : 3;
-    uint64_t write_tsize : 7;
-    uint64_t extaddr : 14;
-    uint64_t _reserved3 : 15;
+    uint64_t push_start : 29;
+    uint64_t reserved1 : 35;
 #else
-    uint64_t _reserved3 : 15;
-    uint64_t extaddr : 14;
-    uint64_t write_tsize : 7;
-    uint64_t wr_gather_timeout : 3;
-    uint64_t dis_write_gather : 1;
-    uint64_t _reserved2 : 1;
-    uint64_t buf_alloc_c : 1;
-    uint64_t buf_alloc_b : 1;
-    uint64_t buf_alloc_a : 1;
-    uint64_t buf_alloc_w : 1;
-    uint64_t buf_invalidate_ctl : 1;
-    uint64_t read_prefetch_ctl : 2;
-    uint64_t read_ttype : 1;
-    uint64_t _reserved1 : 4;
-    uint64_t write_ttype : 3;
-    uint64_t mid_care_mask : 3;
-    uint64_t _reserved0 : 1;
-    uint64_t mid_match_value : 3;
-    uint64_t enable : 1;
+    uint64_t reserved1 : 35;
+    uint64_t push_start : 29;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_slvctln_t;
+} pba_xshbrn_t;
 
 
 
-typedef union pba_bcde_ctl {
+typedef union pba_xshcsn {
 
     uint64_t value;
     struct {
@@ -1609,24 +763,38 @@ typedef union pba_bcde_ctl {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t stop : 1;
-    uint64_t start : 1;
-    uint64_t _reserved0 : 62;
+    uint64_t push_full : 1;
+    uint64_t push_empty : 1;
+    uint64_t reserved1 : 2;
+    uint64_t push_intr_action : 2;
+    uint64_t push_length : 5;
+    uint64_t reserved2 : 2;
+    uint64_t push_write_ptr : 5;
+    uint64_t reserved3 : 3;
+    uint64_t push_read_ptr : 5;
+    uint64_t reserved4 : 5;
+    uint64_t push_enable : 1;
+    uint64_t reserved5 : 32;
 #else
-    uint64_t _reserved0 : 62;
-    uint64_t start : 1;
-    uint64_t stop : 1;
+    uint64_t reserved5 : 32;
+    uint64_t push_enable : 1;
+    uint64_t reserved4 : 5;
+    uint64_t push_read_ptr : 5;
+    uint64_t reserved3 : 3;
+    uint64_t push_write_ptr : 5;
+    uint64_t reserved2 : 2;
+    uint64_t push_length : 5;
+    uint64_t push_intr_action : 2;
+    uint64_t reserved1 : 2;
+    uint64_t push_empty : 1;
+    uint64_t push_full : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcde_ctl_t;
+} pba_xshcsn_t;
 
-#endif // __ASSEMBLER__
-#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
 
 
-typedef union pba_bcde_set {
+typedef union pba_xshincn {
 
     uint64_t value;
     struct {
@@ -1640,20 +808,16 @@ typedef union pba_bcde_set {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t copy_length : 6;
-    uint64_t _reserved1 : 56;
+    uint64_t reserved1 : 64;
 #else
-    uint64_t _reserved1 : 56;
-    uint64_t copy_length : 6;
-    uint64_t _reserved0 : 2;
+    uint64_t reserved1 : 64;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcde_set_t;
+} pba_xshincn_t;
 
 
 
-typedef union pba_bcde_stat {
+typedef union pba_fir {
 
     uint64_t value;
     struct {
@@ -1667,34 +831,108 @@ typedef union pba_bcde_stat {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t running : 1;
-    uint64_t waiting : 1;
-    uint64_t wrcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t rdcmp : 6;
-    uint64_t debug : 9;
-    uint64_t stopped : 1;
-    uint64_t error : 1;
-    uint64_t done : 1;
-    uint64_t _reserved1 : 32;
+    uint64_t oci_apar_err : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_operto : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t internal_err : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t reserved2 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t fir_parity_err : 1;
+    uint64_t reserved5 : 18;
 #else
-    uint64_t _reserved1 : 32;
-    uint64_t done : 1;
-    uint64_t error : 1;
-    uint64_t stopped : 1;
-    uint64_t debug : 9;
-    uint64_t rdcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t wrcmp : 6;
-    uint64_t waiting : 1;
-    uint64_t running : 1;
+    uint64_t reserved5 : 18;
+    uint64_t fir_parity_err : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved2 : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t internal_err : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t pb_operto : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t oci_apar_err : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcde_stat_t;
+} pba_fir_t;
 
 
 
-typedef union pba_bcde_pbadr {
+typedef union pba_fir_and {
 
     uint64_t value;
     struct {
@@ -1708,24 +946,108 @@ typedef union pba_bcde_pbadr {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved1 : 2;
-    uint64_t extaddr : 14;
-    uint64_t _reserved2 : 23;
+    uint64_t oci_apar_err : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_operto : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t internal_err : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t reserved2 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t fir_parity_err : 1;
+    uint64_t reserved5 : 18;
 #else
-    uint64_t _reserved2 : 23;
-    uint64_t extaddr : 14;
-    uint64_t _reserved1 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved0 : 2;
+    uint64_t reserved5 : 18;
+    uint64_t fir_parity_err : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved2 : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t internal_err : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t pb_operto : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t oci_apar_err : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcde_pbadr_t;
+} pba_fir_and_t;
 
 
 
-typedef union pba_bcde_ocibar {
+typedef union pba_fir_or {
 
     uint64_t value;
     struct {
@@ -1739,18 +1061,108 @@ typedef union pba_bcde_ocibar {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t addr : 25;
-    uint64_t _reserved0 : 39;
+    uint64_t oci_apar_err : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_operto : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t internal_err : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t reserved2 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t fir_parity_err : 1;
+    uint64_t reserved5 : 18;
 #else
-    uint64_t _reserved0 : 39;
-    uint64_t addr : 25;
+    uint64_t reserved5 : 18;
+    uint64_t fir_parity_err : 1;
+    uint64_t fir_parity_err2 : 1;
+    uint64_t reserved4 : 1;
+    uint64_t reserved3 : 1;
+    uint64_t reserved2 : 1;
+    uint64_t pb_ackdead_fw_wr : 1;
+    uint64_t axsnd_rsverr : 1;
+    uint64_t axsnd_rsvto : 1;
+    uint64_t axsnd_dlo_rtyto : 1;
+    uint64_t axsnd_dhi_rtyto : 1;
+    uint64_t axflow_err : 1;
+    uint64_t axrcv_rsvdata_to : 1;
+    uint64_t axrcv_dlo_to : 1;
+    uint64_t axrcv_dlo_err : 1;
+    uint64_t axpush_wrerr : 1;
+    uint64_t oci_bad_reg_addr : 1;
+    uint64_t illegal_cache_op : 1;
+    uint64_t internal_err : 1;
+    uint64_t bcde_oci_daterr : 1;
+    uint64_t bcde_ce : 1;
+    uint64_t bcde_ue_err : 1;
+    uint64_t bcde_sue_err : 1;
+    uint64_t bcde_rddatato_err : 1;
+    uint64_t bcde_pb_adrerr : 1;
+    uint64_t bcde_pb_ack_dead : 1;
+    uint64_t bcde_setup_err : 1;
+    uint64_t bcue_oci_daterr : 1;
+    uint64_t bcue_pb_adrerr : 1;
+    uint64_t bcue_pb_ack_dead : 1;
+    uint64_t bcue_setup_err : 1;
+    uint64_t pb_operto : 1;
+    uint64_t pb_ackdead_fw_rd : 1;
+    uint64_t pb_badcresp : 1;
+    uint64_t pb_wradrerr_fw : 1;
+    uint64_t pb_parity_err : 1;
+    uint64_t pb_unexpdata : 1;
+    uint64_t pb_unexpcresp : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err : 1;
+    uint64_t oci_slave_init : 1;
+    uint64_t pb_ce_fw : 1;
+    uint64_t pb_ue_fw : 1;
+    uint64_t pb_sue_fw : 1;
+    uint64_t pb_rddatato_fw : 1;
+    uint64_t pb_rdadrerr_fw : 1;
+    uint64_t oci_apar_err : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcde_ocibar_t;
+} pba_fir_or_t;
 
 
 
-typedef union pba_bcue_ctl {
+typedef union pba_firmask {
 
     uint64_t value;
     struct {
@@ -1764,24 +1176,104 @@ typedef union pba_bcue_ctl {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t stop : 1;
-    uint64_t start : 1;
-    uint64_t _reserved0 : 62;
-#else
-    uint64_t _reserved0 : 62;
-    uint64_t start : 1;
-    uint64_t stop : 1;
+    uint64_t oci_apar_err_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t reserved3 : 18;
+#else
+    uint64_t reserved3 : 18;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t oci_apar_err_mask : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcue_ctl_t;
+} pba_firmask_t;
 
-#endif // __ASSEMBLER__
-#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
 
 
-typedef union pba_bcue_set {
+typedef union pba_firmask_and {
 
     uint64_t value;
     struct {
@@ -1795,20 +1287,104 @@ typedef union pba_bcue_set {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t copy_length : 6;
-    uint64_t _reserved1 : 56;
-#else
-    uint64_t _reserved1 : 56;
-    uint64_t copy_length : 6;
-    uint64_t _reserved0 : 2;
+    uint64_t oci_apar_err_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t reserved3 : 18;
+#else
+    uint64_t reserved3 : 18;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t oci_apar_err_mask : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcue_set_t;
+} pba_firmask_and_t;
 
 
 
-typedef union pba_bcue_stat {
+typedef union pba_firmask_or {
 
     uint64_t value;
     struct {
@@ -1822,34 +1398,104 @@ typedef union pba_bcue_stat {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t running : 1;
-    uint64_t waiting : 1;
-    uint64_t wrcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t rdcmp : 6;
-    uint64_t debug : 9;
-    uint64_t stopped : 1;
-    uint64_t error : 1;
-    uint64_t done : 1;
-    uint64_t _reserved1 : 32;
-#else
-    uint64_t _reserved1 : 32;
-    uint64_t done : 1;
-    uint64_t error : 1;
-    uint64_t stopped : 1;
-    uint64_t debug : 9;
-    uint64_t rdcmp : 6;
-    uint64_t _reserved0 : 6;
-    uint64_t wrcmp : 6;
-    uint64_t waiting : 1;
-    uint64_t running : 1;
+    uint64_t oci_apar_err_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t reserved3 : 18;
+#else
+    uint64_t reserved3 : 18;
+    uint64_t fir_parity_err_mask : 1;
+    uint64_t fir_parity_err2_mask : 1;
+    uint64_t reserved2 : 3;
+    uint64_t pb_ackdead_fw_wr_mask : 1;
+    uint64_t axsnd_rsverr_mask : 1;
+    uint64_t axsnd_rsvto_mask : 1;
+    uint64_t axsnd_dlo_rtyto_mask : 1;
+    uint64_t axsnd_dhi_rtyto_mask : 1;
+    uint64_t axflow_err_mask : 1;
+    uint64_t axrcv_rsvdata_to_mask : 1;
+    uint64_t axrcv_dlo_to_mask : 1;
+    uint64_t axrcv_dlo_err_mask : 1;
+    uint64_t axpush_wrerr_mask : 1;
+    uint64_t oci_bad_reg_addr_mask : 1;
+    uint64_t illegal_cache_op_mask : 1;
+    uint64_t internal_err_mask : 1;
+    uint64_t bcde_oci_daterr_mask : 1;
+    uint64_t bcde_ce_mask : 1;
+    uint64_t bcde_ue_err_mask : 1;
+    uint64_t bcde_sue_err_mask : 1;
+    uint64_t bcde_rddatato_err_mask : 1;
+    uint64_t bcde_pb_adrerr_mask : 1;
+    uint64_t bcde_pb_ack_dead_mask : 1;
+    uint64_t bcde_setup_err_mask : 1;
+    uint64_t bcue_oci_daterr_mask : 1;
+    uint64_t bcue_pb_adrerr_mask : 1;
+    uint64_t bcue_pb_ack_dead_mask : 1;
+    uint64_t bcue_setup_err_mask : 1;
+    uint64_t pb_operto_mask : 1;
+    uint64_t pb_ackdead_fw_rd_mask : 1;
+    uint64_t pb_badcresp_mask : 1;
+    uint64_t pb_wradrerr_fw_mask : 1;
+    uint64_t pb_parity_err_mask : 1;
+    uint64_t pb_unexpdata_mask : 1;
+    uint64_t pb_unexpcresp_mask : 1;
+    uint64_t reserved1 : 1;
+    uint64_t oci_wrpar_err_mask : 1;
+    uint64_t oci_slave_init_mask : 1;
+    uint64_t pb_ce_fw_mask : 1;
+    uint64_t pb_ue_fw_mask : 1;
+    uint64_t pb_sue_fw_mask : 1;
+    uint64_t pb_rddatato_fw_mask : 1;
+    uint64_t pb_rdadrerr_fw_mask : 1;
+    uint64_t oci_apar_err_mask : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcue_stat_t;
+} pba_firmask_or_t;
 
 
 
-typedef union pba_bcue_pbadr {
+typedef union pba_firact0 {
 
     uint64_t value;
     struct {
@@ -1863,24 +1509,18 @@ typedef union pba_bcue_pbadr {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved1 : 2;
-    uint64_t extaddr : 14;
-    uint64_t _reserved2 : 23;
+    uint64_t fir_action0 : 46;
+    uint64_t reserved1 : 18;
 #else
-    uint64_t _reserved2 : 23;
-    uint64_t extaddr : 14;
-    uint64_t _reserved1 : 2;
-    uint64_t pb_offset : 23;
-    uint64_t _reserved0 : 2;
+    uint64_t reserved1 : 18;
+    uint64_t fir_action0 : 46;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcue_pbadr_t;
+} pba_firact0_t;
 
 
 
-typedef union pba_bcue_ocibar {
+typedef union pba_firact1 {
 
     uint64_t value;
     struct {
@@ -1894,18 +1534,18 @@ typedef union pba_bcue_ocibar {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t addr : 25;
-    uint64_t _reserved0 : 39;
+    uint64_t fir_action1 : 46;
+    uint64_t reserved1 : 18;
 #else
-    uint64_t _reserved0 : 39;
-    uint64_t addr : 25;
+    uint64_t reserved1 : 18;
+    uint64_t fir_action1 : 46;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_bcue_ocibar_t;
+} pba_firact1_t;
 
 
 
-typedef union pba_pbocrn {
+typedef union pba_occact {
 
     uint64_t value;
     struct {
@@ -1919,22 +1559,18 @@ typedef union pba_pbocrn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t _reserved0 : 16;
-    uint64_t event : 16;
-    uint64_t _reserved1 : 12;
-    uint64_t accum : 20;
+    uint64_t occ_action_set : 44;
+    uint64_t reserved1 : 20;
 #else
-    uint64_t accum : 20;
-    uint64_t _reserved1 : 12;
-    uint64_t event : 16;
-    uint64_t _reserved0 : 16;
+    uint64_t reserved1 : 20;
+    uint64_t occ_action_set : 44;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_pbocrn_t;
+} pba_occact_t;
 
 
 
-typedef union pba_xsndtx {
+typedef union pba_cfg {
 
     uint64_t value;
     struct {
@@ -1948,32 +1584,74 @@ typedef union pba_xsndtx {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t snd_scope : 3;
-    uint64_t snd_qid : 1;
-    uint64_t snd_type : 1;
-    uint64_t snd_reservation : 1;
-    uint64_t spare6 : 2;
-    uint64_t snd_nodeid : 3;
-    uint64_t snd_chipid : 3;
-    uint64_t spare14 : 2;
-    uint64_t _reserved0 : 48;
-#else
-    uint64_t _reserved0 : 48;
-    uint64_t spare14 : 2;
-    uint64_t snd_chipid : 3;
-    uint64_t snd_nodeid : 3;
-    uint64_t spare6 : 2;
-    uint64_t snd_reservation : 1;
-    uint64_t snd_type : 1;
-    uint64_t snd_qid : 1;
-    uint64_t snd_scope : 3;
+    uint64_t pbreq_slvfw_max_priority : 1;
+    uint64_t pbreq_exit_on_hang : 1;
+    uint64_t pbreq_bce_max_priority : 1;
+    uint64_t pbreq_exit_on_hang_pbax : 1;
+    uint64_t pbreq_data_hang_div : 5;
+    uint64_t pbreq_oper_hang_div : 5;
+    uint64_t pbreq_drop_priority_mask : 6;
+    uint64_t pbreq_exit_hang_div : 4;
+    uint64_t chsw_hang_on_adrerror : 1;
+    uint64_t chsw_dis_ociabuspar_check : 1;
+    uint64_t chsw_dis_ocibepar_check : 1;
+    uint64_t chsw_hang_on_derror : 1;
+    uint64_t reserved1 : 1;
+    uint64_t chsw_dis_write_match_rearb : 1;
+    uint64_t chsw_dis_ocidatapar_gen : 1;
+    uint64_t chsw_dis_ocidatapar_check : 1;
+    uint64_t chsw_dis_oper_hang : 1;
+    uint64_t chsw_dis_data_hang : 1;
+    uint64_t chsw_dis_ecc_check : 1;
+    uint64_t chsw_dis_retry_backoff : 1;
+    uint64_t chsw_exit_on_invalid_cresp : 1;
+    uint64_t reserved2 : 1;
+    uint64_t chsw_dis_group_scope : 1;
+    uint64_t chsw_dis_rtag_parity_chk : 1;
+    uint64_t chsw_dis_pb_parity_chk : 1;
+    uint64_t chsw_skip_group_scope : 1;
+    uint64_t chsw_use_pr_dma_inj : 1;
+    uint64_t chsw_use_cl_dma_inj : 1;
+    uint64_t reserved3 : 4;
+    uint64_t reserved4 : 16;
+#else
+    uint64_t reserved4 : 16;
+    uint64_t reserved3 : 4;
+    uint64_t chsw_use_cl_dma_inj : 1;
+    uint64_t chsw_use_pr_dma_inj : 1;
+    uint64_t chsw_skip_group_scope : 1;
+    uint64_t chsw_dis_pb_parity_chk : 1;
+    uint64_t chsw_dis_rtag_parity_chk : 1;
+    uint64_t chsw_dis_group_scope : 1;
+    uint64_t reserved2 : 1;
+    uint64_t chsw_exit_on_invalid_cresp : 1;
+    uint64_t chsw_dis_retry_backoff : 1;
+    uint64_t chsw_dis_ecc_check : 1;
+    uint64_t chsw_dis_data_hang : 1;
+    uint64_t chsw_dis_oper_hang : 1;
+    uint64_t chsw_dis_ocidatapar_check : 1;
+    uint64_t chsw_dis_ocidatapar_gen : 1;
+    uint64_t chsw_dis_write_match_rearb : 1;
+    uint64_t reserved1 : 1;
+    uint64_t chsw_hang_on_derror : 1;
+    uint64_t chsw_dis_ocibepar_check : 1;
+    uint64_t chsw_dis_ociabuspar_check : 1;
+    uint64_t chsw_hang_on_adrerror : 1;
+    uint64_t pbreq_exit_hang_div : 4;
+    uint64_t pbreq_drop_priority_mask : 6;
+    uint64_t pbreq_oper_hang_div : 5;
+    uint64_t pbreq_data_hang_div : 5;
+    uint64_t pbreq_exit_on_hang_pbax : 1;
+    uint64_t pbreq_bce_max_priority : 1;
+    uint64_t pbreq_exit_on_hang : 1;
+    uint64_t pbreq_slvfw_max_priority : 1;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xsndtx_t;
+} pba_cfg_t;
 
 
 
-typedef union pba_xcfg {
+typedef union pba_errrpt0 {
 
     uint64_t value;
     struct {
@@ -1987,42 +1665,30 @@ typedef union pba_xcfg {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t pbax_en : 1;
-    uint64_t reservation_en : 1;
-    uint64_t snd_reset : 1;
-    uint64_t rcv_reset : 1;
-    uint64_t rcv_nodeid : 3;
-    uint64_t rcv_chipid : 3;
-    uint64_t spare10 : 2;
-    uint64_t rcv_brdcst_group : 8;
-    uint64_t rcv_datato_div : 5;
-    uint64_t spare25 : 2;
-    uint64_t snd_retry_count_overcom : 1;
-    uint64_t snd_retry_thresh : 8;
-    uint64_t snd_rsvto_div : 5;
-    uint64_t _reserved0 : 23;
+    uint64_t cerr_pb_rddatato_fw : 6;
+    uint64_t cerr_pb_rdadrerr_fw : 6;
+    uint64_t cerr_pb_wradrerr_fw : 4;
+    uint64_t cerr_pb_ackdead_fw_rd : 6;
+    uint64_t cerr_pb_ackdead_fw_wr : 2;
+    uint64_t cerr_pb_unexpcresp : 11;
+    uint64_t cerr_pb_unexpdata : 6;
+    uint64_t reserved1 : 23;
 #else
-    uint64_t _reserved0 : 23;
-    uint64_t snd_rsvto_div : 5;
-    uint64_t snd_retry_thresh : 8;
-    uint64_t snd_retry_count_overcom : 1;
-    uint64_t spare25 : 2;
-    uint64_t rcv_datato_div : 5;
-    uint64_t rcv_brdcst_group : 8;
-    uint64_t spare10 : 2;
-    uint64_t rcv_chipid : 3;
-    uint64_t rcv_nodeid : 3;
-    uint64_t rcv_reset : 1;
-    uint64_t snd_reset : 1;
-    uint64_t reservation_en : 1;
-    uint64_t pbax_en : 1;
+    uint64_t reserved1 : 23;
+    uint64_t cerr_pb_unexpdata : 6;
+    uint64_t cerr_pb_unexpcresp : 11;
+    uint64_t cerr_pb_ackdead_fw_wr : 2;
+    uint64_t cerr_pb_ackdead_fw_rd : 6;
+    uint64_t cerr_pb_wradrerr_fw : 4;
+    uint64_t cerr_pb_rdadrerr_fw : 6;
+    uint64_t cerr_pb_rddatato_fw : 6;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xcfg_t;
+} pba_errrpt0_t;
 
 
 
-typedef union pba_xsndstat {
+typedef union pba_errrpt1 {
 
     uint64_t value;
     struct {
@@ -2036,24 +1702,28 @@ typedef union pba_xsndstat {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t snd_in_progress : 1;
-    uint64_t snd_error : 1;
-    uint64_t snd_status : 6;
-    uint64_t snd_retry_count : 8;
-    uint64_t _reserved0 : 48;
+    uint64_t cerr_pb_badcresp : 12;
+    uint64_t cerr_pb_operto : 12;
+    uint64_t reserved1 : 6;
+    uint64_t cerr_bcde_setup_err : 2;
+    uint64_t cerr_bcue_setup_err : 2;
+    uint64_t cerr_bcue_oci_dataerr : 2;
+    uint64_t reserved2 : 28;
 #else
-    uint64_t _reserved0 : 48;
-    uint64_t snd_retry_count : 8;
-    uint64_t snd_status : 6;
-    uint64_t snd_error : 1;
-    uint64_t snd_in_progress : 1;
+    uint64_t reserved2 : 28;
+    uint64_t cerr_bcue_oci_dataerr : 2;
+    uint64_t cerr_bcue_setup_err : 2;
+    uint64_t cerr_bcde_setup_err : 2;
+    uint64_t reserved1 : 6;
+    uint64_t cerr_pb_operto : 12;
+    uint64_t cerr_pb_badcresp : 12;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xsndstat_t;
+} pba_errrpt1_t;
 
 
 
-typedef union pba_xsnddat {
+typedef union pba_errrpt2 {
 
     uint64_t value;
     struct {
@@ -2067,18 +1737,36 @@ typedef union pba_xsnddat {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t pbax_datahi : 32;
-    uint64_t pbax_datalo : 32;
+    uint64_t cerr_slv_internal_err : 8;
+    uint64_t cerr_bcde_internal_err : 4;
+    uint64_t cerr_bcue_internal_err : 4;
+    uint64_t cerr_bar_parity_err : 1;
+    uint64_t cerr_scomtb_err : 1;
+    uint64_t cerr_spare : 2;
+    uint64_t cerr_pbdout_parity_err : 1;
+    uint64_t cerr_pb_parity_err : 3;
+    uint64_t cerr_axflow_err : 5;
+    uint64_t cerr_axpush_wrerr : 2;
+    uint64_t reserved1 : 33;
 #else
-    uint64_t pbax_datalo : 32;
-    uint64_t pbax_datahi : 32;
+    uint64_t reserved1 : 33;
+    uint64_t cerr_axpush_wrerr : 2;
+    uint64_t cerr_axflow_err : 5;
+    uint64_t cerr_pb_parity_err : 3;
+    uint64_t cerr_pbdout_parity_err : 1;
+    uint64_t cerr_spare : 2;
+    uint64_t cerr_scomtb_err : 1;
+    uint64_t cerr_bar_parity_err : 1;
+    uint64_t cerr_bcue_internal_err : 4;
+    uint64_t cerr_bcde_internal_err : 4;
+    uint64_t cerr_slv_internal_err : 8;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xsnddat_t;
+} pba_errrpt2_t;
 
 
 
-typedef union pba_xrcvstat {
+typedef union pba_rbufvaln {
 
     uint64_t value;
     struct {
@@ -2092,26 +1780,36 @@ typedef union pba_xrcvstat {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t rcv_in_progress : 1;
-    uint64_t rcv_error : 1;
-    uint64_t rcv_write_in_progress : 1;
-    uint64_t rcv_reservation_set : 1;
-    uint64_t rcv_capture : 14;
-    uint64_t _reserved0 : 46;
+    uint64_t rd_slvnum : 2;
+    uint64_t cur_rd_addr : 23;
+    uint64_t reserved1 : 3;
+    uint64_t prefetch : 1;
+    uint64_t reserved2 : 2;
+    uint64_t abort : 1;
+    uint64_t reserved3 : 1;
+    uint64_t buffer_status : 7;
+    uint64_t reserved4 : 1;
+    uint64_t masterid : 3;
+    uint64_t reserved5 : 20;
 #else
-    uint64_t _reserved0 : 46;
-    uint64_t rcv_capture : 14;
-    uint64_t rcv_reservation_set : 1;
-    uint64_t rcv_write_in_progress : 1;
-    uint64_t rcv_error : 1;
-    uint64_t rcv_in_progress : 1;
+    uint64_t reserved5 : 20;
+    uint64_t masterid : 3;
+    uint64_t reserved4 : 1;
+    uint64_t buffer_status : 7;
+    uint64_t reserved3 : 1;
+    uint64_t abort : 1;
+    uint64_t reserved2 : 2;
+    uint64_t prefetch : 1;
+    uint64_t reserved1 : 3;
+    uint64_t cur_rd_addr : 23;
+    uint64_t rd_slvnum : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xrcvstat_t;
+} pba_rbufvaln_t;
 
 
 
-typedef union pba_xshbrn {
+typedef union pba_wbufvaln {
 
     uint64_t value;
     struct {
@@ -2125,18 +1823,28 @@ typedef union pba_xshbrn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t push_start : 29;
-    uint64_t _reserved0 : 35;
+    uint64_t wr_slvnum : 2;
+    uint64_t start_wr_addr : 30;
+    uint64_t reserved1 : 3;
+    uint64_t wr_buffer_status : 5;
+    uint64_t reserved2 : 1;
+    uint64_t wr_byte_count : 7;
+    uint64_t reserved3 : 16;
 #else
-    uint64_t _reserved0 : 35;
-    uint64_t push_start : 29;
+    uint64_t reserved3 : 16;
+    uint64_t wr_byte_count : 7;
+    uint64_t reserved2 : 1;
+    uint64_t wr_buffer_status : 5;
+    uint64_t reserved1 : 3;
+    uint64_t start_wr_addr : 30;
+    uint64_t wr_slvnum : 2;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xshbrn_t;
+} pba_wbufvaln_t;
 
 
 
-typedef union pba_xshcsn {
+typedef union pba_barn {
 
     uint64_t value;
     struct {
@@ -2150,38 +1858,26 @@ typedef union pba_xshcsn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t push_full : 1;
-    uint64_t push_empty : 1;
-    uint64_t spare1 : 2;
-    uint64_t push_intr_action : 2;
-    uint64_t push_length : 5;
-    uint64_t notimp1 : 2;
-    uint64_t push_write_ptr : 5;
-    uint64_t notimp2 : 3;
-    uint64_t push_read_ptr : 5;
-    uint64_t notimp3 : 5;
-    uint64_t push_enable : 1;
-    uint64_t _reserved0 : 32;
-#else
-    uint64_t _reserved0 : 32;
-    uint64_t push_enable : 1;
-    uint64_t notimp3 : 5;
-    uint64_t push_read_ptr : 5;
-    uint64_t notimp2 : 3;
-    uint64_t push_write_ptr : 5;
-    uint64_t notimp1 : 2;
-    uint64_t push_length : 5;
-    uint64_t push_intr_action : 2;
-    uint64_t spare1 : 2;
-    uint64_t push_empty : 1;
-    uint64_t push_full : 1;
+    uint64_t cmd_scope : 3;
+    uint64_t reserved1 : 1;
+    uint64_t reserved2 : 4;
+    uint64_t addr : 36;
+    uint64_t reserved3 : 4;
+    uint64_t vtarget : 16;
+#else
+    uint64_t vtarget : 16;
+    uint64_t reserved3 : 4;
+    uint64_t addr : 36;
+    uint64_t reserved2 : 4;
+    uint64_t reserved1 : 1;
+    uint64_t cmd_scope : 3;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xshcsn_t;
+} pba_barn_t;
 
 
 
-typedef union pba_xshincn {
+typedef union pba_barmskn {
 
     uint64_t value;
     struct {
@@ -2195,12 +1891,16 @@ typedef union pba_xshincn {
     } words;
     struct {
 #ifdef _BIG_ENDIAN
-    uint64_t reserved : 64;
+    uint64_t reserved1 : 23;
+    uint64_t mask : 21;
+    uint64_t reserved2 : 20;
 #else
-    uint64_t reserved : 64;
+    uint64_t reserved2 : 20;
+    uint64_t mask : 21;
+    uint64_t reserved1 : 23;
 #endif // _BIG_ENDIAN
     } fields;
-} pba_xshincn_t;
+} pba_barmskn_t;
 
 
 #endif // __ASSEMBLER__
diff --git a/src/include/registers/pba_register_addresses.h b/src/include/registers/pba_register_addresses.h
index 7ebf9f1..064062e 100644
--- a/src/include/registers/pba_register_addresses.h
+++ b/src/include/registers/pba_register_addresses.h
@@ -1,34 +1,10 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/include/registers/pba_register_addresses.h $              */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
 #ifndef __PBA_REGISTER_ADDRESSES_H__
 #define __PBA_REGISTER_ADDRESSES_H__
 
-// $Id: pba_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_register_addresses.h,v $
+// $Id$
+// $Source$
 //-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
+// *! (C) Copyright International Business Machines Corp. 2015
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //-----------------------------------------------------------------------------
@@ -39,80 +15,80 @@
 // *** WARNING *** - This file is generated automatically, do not edit.
 
 
-#define TRUSTEDPIB_BASE 0x02013f00
-#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
-#define PBA_BAR0 0x02013f00
-#define PBA_BAR1 0x02013f01
-#define PBA_BAR2 0x02013f02
-#define PBA_BAR3 0x02013f03
-#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
-#define PBA_BARMSK0 0x02013f04
-#define PBA_BARMSK1 0x02013f05
-#define PBA_BARMSK2 0x02013f06
-#define PBA_BARMSK3 0x02013f07
-#define PIB_BASE 0x02010840
-#define PBA_FIR 0x02010840
-#define PBA_FIR_AND 0x02010841
-#define PBA_FIR_OR 0x02010842
-#define PBA_FIRMASK 0x02010843
-#define PBA_FIRMASK_AND 0x02010844
-#define PBA_FIRMASK_OR 0x02010845
-#define PBA_FIRACT0 0x02010846
-#define PBA_FIRACT1 0x02010847
-#define PBA_OCCACT 0x0201084a
-#define PBA_CFG 0x0201084b
-#define PBA_ERRPT0 0x0201084c
-#define PBA_ERRPT1 0x0201084d
-#define PBA_ERRPT2 0x0201084e
-#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
-#define PBA_RBUFVAL0 0x02010850
-#define PBA_RBUFVAL1 0x02010851
-#define PBA_RBUFVAL2 0x02010852
-#define PBA_RBUFVAL3 0x02010853
-#define PBA_RBUFVAL4 0x02010854
-#define PBA_RBUFVAL5 0x02010855
-#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
-#define PBA_WBUFVAL0 0x02010858
-#define PBA_WBUFVAL1 0x02010859
-#define OCI_BASE 0x40020000
-#define PBA_MODE 0x40020000
-#define PBA_SLVRST 0x40020008
+#define PBA_OCI_BASE 0xC0040000
+#define PBA_MODE 0xc0040000
+#define PBA_SLVRST 0xc0040008
 #define PBA_SLVCTLN(n) (PBA_SLVCTL0 + ((PBA_SLVCTL1 - PBA_SLVCTL0) * (n)))
-#define PBA_SLVCTL0 0x40020020
-#define PBA_SLVCTL1 0x40020028
-#define PBA_SLVCTL2 0x40020030
-#define PBA_SLVCTL3 0x40020038
-#define PBA_BCDE_CTL 0x40020080
-#define PBA_BCDE_SET 0x40020088
-#define PBA_BCDE_STAT 0x40020090
-#define PBA_BCDE_PBADR 0x40020098
-#define PBA_BCDE_OCIBAR 0x400200a0
-#define PBA_BCUE_CTL 0x400200a8
-#define PBA_BCUE_SET 0x400200b0
-#define PBA_BCUE_STAT 0x400200b8
-#define PBA_BCUE_PBADR 0x400200c0
-#define PBA_BCUE_OCIBAR 0x400200c8
+#define PBA_SLVCTL0 0xc0040020
+#define PBA_SLVCTL1 0xc0040028
+#define PBA_SLVCTL2 0xc0040030
+#define PBA_SLVCTL3 0xc0040038
+#define PBA_BCDE_CTL 0xc0040080
+#define PBA_BCDE_SET 0xc0040088
+#define PBA_BCDE_STAT 0xc0040090
+#define PBA_BCDE_PBADR 0xc0040098
+#define PBA_BCDE_OCIBAR 0xc00400a0
+#define PBA_BCUE_CTL 0xc00400a8
+#define PBA_BCUE_SET 0xc00400b0
+#define PBA_BCUE_STAT 0xc00400b8
+#define PBA_BCUE_PBADR 0xc00400c0
+#define PBA_BCUE_OCIBAR 0xc00400c8
 #define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n)))
-#define PBA_PBOCR0 0x400200d0
-#define PBA_PBOCR1 0x400200d8
-#define PBA_PBOCR2 0x400200e0
-#define PBA_PBOCR3 0x400200e8
-#define PBA_PBOCR4 0x400200f0
-#define PBA_PBOCR5 0x400200f8
-#define PBA_XSNDTX 0x40020100
-#define PBA_XCFG 0x40020108
-#define PBA_XSNDSTAT 0x40020110
-#define PBA_XSNDDAT 0x40020118
-#define PBA_XRCVSTAT 0x40020120
+#define PBA_PBOCR0 0xc00400d0
+#define PBA_PBOCR1 0xc00400d8
+#define PBA_PBOCR2 0xc00400e0
+#define PBA_PBOCR3 0xc00400e8
+#define PBA_PBOCR4 0xc00400f0
+#define PBA_PBOCR5 0xc00400f8
+#define PBA_XSNDTX 0xc0040100
+#define PBA_XCFG 0xc0040108
+#define PBA_XSNDSTAT 0xc0040110
+#define PBA_XSNDDAT 0xc0040118
+#define PBA_XRCVSTAT 0xc0040120
 #define PBA_XSHBRN(n) (PBA_XSHBR0 + ((PBA_XSHBR1 - PBA_XSHBR0) * (n)))
-#define PBA_XSHBR0 0x40020130
-#define PBA_XSHBR1 0x40020150
+#define PBA_XSHBR0 0xc0040130
+#define PBA_XSHBR1 0xc0040150
 #define PBA_XSHCSN(n) (PBA_XSHCS0 + ((PBA_XSHCS1 - PBA_XSHCS0) * (n)))
-#define PBA_XSHCS0 0x40020138
-#define PBA_XSHCS1 0x40020158
+#define PBA_XSHCS0 0xc0040138
+#define PBA_XSHCS1 0xc0040158
 #define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n)))
-#define PBA_XSHINC0 0x40020140
-#define PBA_XSHINC1 0x40020160
+#define PBA_XSHINC0 0xc0040140
+#define PBA_XSHINC1 0xc0040160
+#define PBA_PIB_BASE 0x68000
+#define PBA_FIR 0x00068000
+#define PBA_FIR_AND 0x00068001
+#define PBA_FIR_OR 0x00068002
+#define PBA_FIRMASK 0x00068003
+#define PBA_FIRMASK_AND 0x00068004
+#define PBA_FIRMASK_OR 0x00068005
+#define PBA_FIRACT0 0x00068006
+#define PBA_FIRACT1 0x00068007
+#define PBA_OCCACT 0x0006800a
+#define PBA_CFG 0x0006800b
+#define PBA_ERRRPT0 0x0006800c
+#define PBA_ERRRPT1 0x0006800d
+#define PBA_ERRRPT2 0x0006800e
+#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
+#define PBA_RBUFVAL0 0x00068010
+#define PBA_RBUFVAL1 0x00068011
+#define PBA_RBUFVAL2 0x00068012
+#define PBA_RBUFVAL3 0x00068013
+#define PBA_RBUFVAL4 0x00068014
+#define PBA_RBUFVAL5 0x00068015
+#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
+#define PBA_WBUFVAL0 0x00068018
+#define PBA_WBUFVAL1 0x00068019
+#define PBA_TRUSTEDPIB_BASE 0x68020
+#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
+#define PBA_BAR0 0x00068020
+#define PBA_BAR1 0x00068021
+#define PBA_BAR2 0x00068022
+#define PBA_BAR3 0x00068023
+#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
+#define PBA_BARMSK0 0x00068024
+#define PBA_BARMSK1 0x00068025
+#define PBA_BARMSK2 0x00068026
+#define PBA_BARMSK3 0x00068027
 
 #endif // __PBA_REGISTER_ADDRESSES_H__
 
diff --git a/src/lib/common/string.h b/src/lib/common/string.h
index 5cfa470..71f54c9 100644
--- a/src/lib/common/string.h
+++ b/src/lib/common/string.h
@@ -45,6 +45,11 @@
 #ifndef __ASSEMBLER__
 
 #include <stddef.h>
+#if !defined(__size_t)
+#include <stdint.h>
+typedef size_t uint32_t;
+#endif
+
 
 // APIs inmplemented by string.c
 
diff --git a/src/occ_405/amec/amec_amester.c b/src/occ_405/amec/amec_amester.c
index cc672cd..4ddf734 100755
--- a/src/occ_405/amec/amec_amester.c
+++ b/src/occ_405/amec/amec_amester.c
@@ -47,6 +47,7 @@
 //*************************************************************************/
 // Externs
 //*************************************************************************/
+extern uint32_t G_present_hw_cores;
 
 //*************************************************************************/
 // Macros
diff --git a/src/occ_405/amec/amec_parm_table.c b/src/occ_405/amec/amec_parm_table.c
index c485484..282a695 100755
--- a/src/occ_405/amec/amec_parm_table.c
+++ b/src/occ_405/amec/amec_parm_table.c
@@ -119,7 +119,8 @@ amec_parm_t g_amec_parm_list[] = {
     AMEC_PARM_UINT16(PARM_SYS_FMIN,"sys_fmin",&g_amec_sys.sys.fmin),
 
     // Global Pstate table
-    AMEC_PARM_RAW(PARM_GPST,"gpst",&G_global_pstate_table,sizeof(GlobalPstateTable)),
+// @TODO - TEMP - global state table changes in P9
+//    AMEC_PARM_RAW(PARM_GPST,"gpst",&G_global_pstate_table,sizeof(GlobalPstateTable)),
     // MHz per pstate
     AMEC_PARM_UINT32(PARM_PSTATE_MHZ,"pstate_mhz",&G_mhz_per_pstate),
     // frequency reason code per-core
diff --git a/src/occ_405/amec/amec_pcap.c b/src/occ_405/amec/amec_pcap.c
index f8ef06f..fcc70aa 100755
--- a/src/occ_405/amec/amec_pcap.c
+++ b/src/occ_405/amec/amec_pcap.c
@@ -93,6 +93,8 @@ uint8_t     G_over_pcap_count=0;
 // End Function Specification
 void amec_pmax_clip_controller(void)
 {
+//  @TODO - TEMP Pstate functions not defined yet
+#if 0
     /*------------------------------------------------------------------------*/
     /*  Local Variables                                                       */
     /*------------------------------------------------------------------------*/
@@ -140,6 +142,7 @@ void amec_pmax_clip_controller(void)
     }
 
     g_amec->proc[0].pwr_votes.pmax_clip_freq = l_pmax_clip_freq;
+#endif // @TODO - TEMP Pstate functions not defined yet
 }
 
 //////////////////////////
diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
index 1778a9e..2815912 100755
--- a/src/occ_405/amec/amec_sensors_power.c
+++ b/src/occ_405/amec/amec_sensors_power.c
@@ -214,8 +214,8 @@ void amec_update_apss_sensors(void)
     // via slave inbox first
     if (G_slv_inbox_received)
     {
-        uint8_t l_proc  = G_pob_id.module_id;
-        uint32_t temp32 = 0;
+        uint8_t l_proc   = G_pbax_id.module_id;
+        uint32_t temp32  = 0;
         uint8_t  l_idx   = 0;
         uint32_t l_bulk_current_sum = 0;
 
diff --git a/src/occ_405/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index c5bbb5f..d9bfdb9 100755
--- a/src/occ_405/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
@@ -436,8 +436,8 @@ errlHndl_t cmdh_fsp_init(void)
             l_mbox_msg.fields.msg_queue_id                    = OCC_MSG_QUEUE_ID;
             l_mbox_msg.fields.msg_payload.fsp_cmd_buffer_addr = CMDH_LINEAR_WINDOW_BASE_ADDRESS;
             l_mbox_msg.fields.msg_payload.fsp_rsp_buffer_addr = CMDH_OCC_RESPONSE_BASE_ADDRESS;
-            // TEMP: This was previously G_pob_id.chip_id (not 0)
-            l_mbox_msg.fields.msg_payload.occ_id              = 0; // TODO: Add OCC ID
+
+            l_mbox_msg.fields.msg_payload.occ_id              = G_pbax_id.chip_id;
 
             do
             {
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c
index c89c230..edd49f3 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c
@@ -1219,14 +1219,16 @@ errlHndl_t cmdh_tmgt_setmodestate(const cmdh_fsp_cmd_t * i_cmd_ptr,
         G_occ_external_req_mode  = l_cmd_ptr->occ_mode;
         G_occ_external_req_state = l_cmd_ptr->occ_state;
 
-        // TODO: Should we have a way to transition state even if
-        // master slave comm isn't working?
-        // TEMP/TODO : This is a temporary hack to allow state and mode transitions
-        //             until DCOM is enabled. Needs to be commented out again once
-        //             that happens. And then perhaps address the above TODO.
+        // In case we need to transition state while
+        // master slave comm isn't working:
+        // This is a temporary hack to allow state and mode transitions
+        //             until DCOM is enabled; commented out again once
+        //             that happens.
+        // This is only valid during early code development. It should
+        // always be commented in p9.
         // if(){
-             G_occ_master_state = l_cmd_ptr->occ_state;
-             G_occ_master_mode  = l_cmd_ptr->occ_mode;
+        //     G_occ_master_state = l_cmd_ptr->occ_state;
+        //     G_occ_master_mode  = l_cmd_ptr->occ_mode;
         // }
         // We need to wait and see if all Slaves correctly make it to state/mode.
         // TODO: Also, if all slaves can't go to this mode (based on their state),
@@ -1460,9 +1462,9 @@ errlHndl_t cmdh_tmgt_get_field_debug_data(const cmdh_fsp_cmd_t * i_cmd_ptr,
         }
 
         // Add occ infomation so that we know where the debug data from
-        l_resp_ptr->occ_node     = G_pob_id.node_id;
-        // TEMP: This was previously G_pob_id.chip_id
-        l_resp_ptr->occ_id       = 0; // TEMP/TODO: add occ id info
+        l_resp_ptr->occ_node     = G_pbax_id.node_id;
+
+        l_resp_ptr->occ_id       =  G_pbax_id.chip_id;
         l_resp_ptr->occ_role     = G_occ_role;
 
         // copy trace data
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
index b2ac116..d9abb17 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
@@ -601,7 +601,7 @@ errlHndl_t apss_store_adc_channel(const eApssAdcChannelAssignments i_func_id, co
 void apss_store_ipmi_sensor_id(const uint16_t i_channel, const apss_cfg_adc_v20_t *i_adc)
 {
     // Get current processor id.
-    uint8_t l_proc  = G_pob_id.module_id;
+    uint8_t l_proc  = G_pbax_id.module_id;
 
     switch (i_adc->assignment)
     {
diff --git a/src/occ_405/dcom/dcom.c b/src/occ_405/dcom/dcom.c
index 4a00f4b..4db4779 100755
--- a/src/occ_405/dcom/dcom.c
+++ b/src/occ_405/dcom/dcom.c
@@ -39,11 +39,7 @@
 #include <amec_data.h>
 #include <amec_sys.h>
 #include "scom.h"
-#include "pss_constants.h"  // @TODO: move with HW registers? 
-
-#define PBAX_CONFIGURE_RCV_GROUP_MASK 0xff
-
-#define PBAX_BROADCAST_GROUP 0xFF
+#include "pss_constants.h"  // @TODO: move with HW registers?
 
 extern uint8_t G_occ_interrupt_type;
 
@@ -78,8 +74,8 @@ uint8_t     G_occ_role = OCC_SLAVE;
 
 uint8_t     G_dcm_occ_role            = OCC_DCM_SLAVE;
 
-// PowerBus ID of this OCC.  Contains ChipId & NodeId.
-pob_id_t    G_pob_id                  = {0};
+// PBAX ID of this OCC is also its PowerBus ID.  Contains ChipId & NodeId.
+pob_id_t    G_pbax_id                  = {0};
 
 // PBAX 'Target' Structure (Register Abstraction) that has the data needed for
 // a multicast operation.
@@ -119,184 +115,61 @@ void dcom_initialize_roles(void)
     G_occ_role = OCC_SLAVE;
 
     // Locals
-    int         l_rc = 0;
-    tpc_gp0_t   l_tp_gp0_read;
+    pba_xcfg_t pbax_cfg_reg;
 
     // Used as a debug tool to correlate time between OCCs & System Time
-    getscom_ffdc( TOD_VALUE_REG, &G_dcomTime.tod, NULL); // Commits errors internally
-    G_dcomTime.base = ssx_timebase_get();
+    // getscom_ffdc(OCB_OTBR, &G_dcomTime.tod, NULL); // Commits errors internally
 
-    // Scom will timeout if it can't be read
-    l_rc = getscom_ffdc( TPC_GP0, (uint64_t *) &l_tp_gp0_read, NULL);  // Commits errors internally
+    G_dcomTime.tod = in64(OCB_OTBR) >> 4;
+    G_dcomTime.base = ssx_timebase_get();
+    pbax_cfg_reg.value = in64(PBA_XCFG);
 
-    if( l_rc == 0 )
+    if(pbax_cfg_reg.fields.rcv_groupid < MAX_NUM_NODES &&
+       pbax_cfg_reg.fields.rcv_chipid < MAX_NUM_OCC)
     {
-        // Added check for Murano ChipId swizzle
-        if(CFAM_CHIP_TYPE_MURANO == cfam_chip_type())
-        {
-            // Murano has a different numbering scheme than you would
-            // expect.  It uses NodeId to denote DCM Id, and ChipId to
-            // denote chip within the DCM.  This is due to they way the
-            // PowerBus works for routing.
-            //
-            // To fix this, we need to manipulate our internal copy of
-            // ChipId/NodeId to match the way OCC FW uses them. We do this by
-            // multiplying the NodeId by 2 then adding chip Id to get a unique
-            // new ChipId (Max Node = 3, Max Chip = 1 by design
-            //
-            // Note that Murano is not multi-drawer capable, so we can
-            // fix our node id at 0
-
-#define MAX_MURANO_CHIP_IDS 2
-#define MAX_MURANO_NODE_IDS 4
-            if( (l_tp_gp0_read.fields.tc_chip_id_dc < MAX_MURANO_CHIP_IDS)
-                    && (l_tp_gp0_read.fields.tc_node_id_dc < MAX_MURANO_NODE_IDS))
-            {
-                // TODO: Check if possible to use node_id read from the chip GPIOs
-
-                // Translate between chip ID & Module Id for Tuleta
-                uint8_t tuleta_chip2module[] = {0,0,2,2,1,1,3,3};
-
-                G_pob_id.chip_id = (l_tp_gp0_read.fields.tc_chip_id_dc
-                        + ( MAX_MURANO_CHIP_IDS * l_tp_gp0_read.fields.tc_node_id_dc));
-                G_pob_id.node_id = 0;
-
-                // The module id is only used by Power Measurements
-                G_pob_id.module_id = tuleta_chip2module[G_pob_id.chip_id];
-            }
-            else
-            {
-                // Chip Ids don't make any sense
-                TRAC_ERR("Proc ChipId (%d) and/or NodeId (%d) don't make sense for Murano",
-                        l_tp_gp0_read.fields.tc_chip_id_dc,
-                        l_tp_gp0_read.fields.tc_node_id_dc);
-                /* @
-                 * @errortype
-                 * @moduleid    DCOM_MID_INIT_ROLES
-                 * @reasoncode  INTERNAL_HW_FAILURE
-                 * @userdata1   TP.GP0 SCOM (upper)
-                 * @userdata2   TP.GP0 SCOM (lower)
-                 * @userdata4   ERC_CHIP_IDS_INVALID
-                 * @devdesc     Failure determining OCC role
-                 */
-                errlHndl_t  l_errl = createErrl(
-                        DCOM_MID_INIT_ROLES,            //ModId
-                        INTERNAL_HW_FAILURE,            //Reasoncode
-                        ERC_CHIP_IDS_INVALID,           //Extended reasoncode
-                        ERRL_SEV_UNRECOVERABLE,         //Severity
-                        NULL,                           //Trace Buf
-                        DEFAULT_TRACE_SIZE,             //Trace Size
-                        l_tp_gp0_read.words.high_order, //Userdata1
-                        l_tp_gp0_read.words.low_order   //Userdata2
-                        );
-
-                // Callout firmware
-                addCalloutToErrl(l_errl,
-                                 ERRL_CALLOUT_TYPE_COMPONENT_ID,
-                                 ERRL_COMPONENT_ID_FIRMWARE,
-                                 ERRL_CALLOUT_PRIORITY_HIGH);
-
-                // Commit log
-                commitErrl( &l_errl );
-            }
-        }
-        else
-        {
-            // Save off chip and node ids directly as read
-            G_pob_id.chip_id = l_tp_gp0_read.fields.tc_chip_id_dc;
-            G_pob_id.node_id = l_tp_gp0_read.fields.tc_node_id_dc;
-
-            // Check if special SMP wrap mode is turned on. In this mode, a
-            // single drawer is configured as two virtual nodes. However, OCC
-            // still needs to treat it as a single node.
-            // As a temporary solution, HWSV is going to set bit 17 of the GP0
-            // register to inform OCC that SMP wrap is on.
-
-#define SMP_WRAP_MASK 0x00004000
-            if(l_tp_gp0_read.words.high_order & SMP_WRAP_MASK)
-            {
-                TRAC_INFO("dcom_initialize_roles: Temporary fix - SMP wrap mode has been detected");
 
-                // This is a single drawer
-                G_pob_id.node_id = 0;
-
-                // Translate the NodeId and ChipId into the correct internal
-                // representation for OCC to work.
-                if(l_tp_gp0_read.fields.tc_node_id_dc == 0)
-                {
-                    G_pob_id.chip_id = 2 * l_tp_gp0_read.fields.tc_chip_id_dc;
-                }
-                else if(l_tp_gp0_read.fields.tc_node_id_dc == 1)
-                {
-                    G_pob_id.chip_id = (l_tp_gp0_read.fields.tc_chip_id_dc) ? 1 : 3;
-                }
-            }
-
-            // If this is a FSP-less system, then use the node ID as the
-            // chip ID. This is because the HW assigns the OCCs as being in
-            // different nodes with the same chip IDs.
-            if (G_occ_interrupt_type != FSP_SUPPORTED_OCC)
-            {
-                G_pob_id.node_id = 0;
-                G_pob_id.chip_id = l_tp_gp0_read.fields.tc_node_id_dc;
-
-                TRAC_IMP("dcom_initialize_roles: Overriding chip_id[%d] with node_id[%d]",
-                         l_tp_gp0_read.fields.tc_chip_id_dc,
-                         l_tp_gp0_read.fields.tc_node_id_dc);
-            }
-
-            // Save off low 2 bits of chip ID as module ID.  Won't be
-            // more than 4 on venice since it is SCMs.
-            G_pob_id.module_id = (G_pob_id.chip_id & 0x03);
-        }
+        TRAC_IMP("Proc ChipId (%d)  NodeId (%d)",
+                 pbax_cfg_reg.fields.rcv_chipid,
+                 pbax_cfg_reg.fields.rcv_groupid);
 
+        G_pbax_id.valid     = 1;
+        G_pbax_id.node_id   = pbax_cfg_reg.fields.rcv_groupid;
+        G_pbax_id.chip_id   = pbax_cfg_reg.fields.rcv_chipid;
+        G_pbax_id.module_id = G_pbax_id.chip_id;
         // Always start as OCC Slave
         G_occ_role = OCC_SLAVE;
         rtl_set_run_mask(RTL_FLAG_NOTMSTR);
 
-// @TODO TEMP - not ready yet for multiple DCMs
-/*
-        // Save off OCC role inside DCM chip
-        if(gpsm_dcm_slave_p())
-        {
-            G_dcm_occ_role = OCC_DCM_SLAVE;
-        }
-        else
-        {
-            G_dcm_occ_role = OCC_DCM_MASTER;
-        }
 
-        TRAC_IMP("Proc ChipId=%d, NodeId=%d, isDcm=%d, isDcmMaster=%d, ChipEC=0x%08x",
-                G_pob_id.chip_id,
-                G_pob_id.node_id,
-                gpsm_dcm_mode_p(),
-                !gpsm_dcm_slave_p(),
-                cfam_id() );
-*/
+        // Set the initial presence mask, and count the number of occ's present
+        G_sysConfigData.is_occ_present |= (0x01 << G_pbax_id.chip_id);
+        G_occ_num_present = __builtin_popcount(G_sysConfigData.is_occ_present);
+
     }
-    else
+    else // Invalid chip/node ID(s)
     {
-        //get scom failure
-        TRAC_ERR("getscom failure rc[0x%08X]", -l_rc );
-
+        TRAC_ERR("Proc ChipId (%d) and/or NodeId (%d) too high: request reset",
+                 pbax_cfg_reg.fields.rcv_chipid,
+                 pbax_cfg_reg.fields.rcv_groupid);
         /* @
          * @errortype
          * @moduleid    DCOM_MID_INIT_ROLES
-         * @reasoncode  INTERNAL_HW_FAILURE
-         * @userdata1   getscom failure rc
-         * @userdata4   ERC_GETSCOM_FAILURE
+         * @reasoncode  INVALID_CONFIGURATION
+         * @userdata1   PBAXCFG (upper)
+         * @userdata2   PBAXCFG (lower)
+         * @userdata4   ERC_CHIP_IDS_INVALID
          * @devdesc     Failure determining OCC role
          */
         errlHndl_t  l_errl = createErrl(
-                    DCOM_MID_INIT_ROLES,            //ModId
-                    INTERNAL_HW_FAILURE,            //Reasoncode
-                    ERC_GETSCOM_FAILURE,            //Extended reasoncode
-                    ERRL_SEV_UNRECOVERABLE,         //Severity
-                    NULL,                           //Trace Buf
-                    DEFAULT_TRACE_SIZE,             //Trace Size
-                    l_rc,                           //Userdata1
-                    0                               //Userdata2
-                    );
+            DCOM_MID_INIT_ROLES,            //ModId
+            INTERNAL_HW_FAILURE,            //Reasoncode
+            ERC_CHIP_IDS_INVALID,           //Extended reasoncode
+            ERRL_SEV_UNRECOVERABLE,         //Severity
+            NULL,                           //Trace Buf
+            DEFAULT_TRACE_SIZE,             //Trace Size
+            pbax_cfg_reg.words.high_order,  //Userdata1
+            pbax_cfg_reg.words.low_order    //Userdata2
+            );
 
         // Callout firmware
         addCalloutToErrl(l_errl,
@@ -304,24 +177,20 @@ void dcom_initialize_roles(void)
                          ERRL_COMPONENT_ID_FIRMWARE,
                          ERRL_CALLOUT_PRIORITY_HIGH);
 
-        // Commit log
-        commitErrl( &l_errl );
+        //Add processor callout
+        addCalloutToErrl(l_errl,
+                         ERRL_CALLOUT_TYPE_HUID,
+                         G_sysConfigData.proc_huid,
+                         ERRL_CALLOUT_PRIORITY_LOW);
 
-        // TODO request a reset of OCC
-        // we are toast without this working correctly
+        G_pbax_id.valid   = 0;  // Invalid Chip/Node ID
     }
 
-    // Set the initial presence mask, and count the number of occ's present
-    G_sysConfigData.is_occ_present |= (0x01 << G_pob_id.chip_id);
-    G_occ_num_present = __builtin_popcount(G_sysConfigData.is_occ_present);
-
-    // Initialize DCOM Thread Sem
-// @TODO - TEMP - Not ready yet in phase 1
-/*
+// Initialize DCOM Thread Sem
     ssx_semaphore_create( &G_dcomThreadWakeupSem, // Semaphore
                           1,                      // Initial Count
                           0);                     // No Max Count
-*/
+
 }
 
 // Function Specification
@@ -333,29 +202,19 @@ void dcom_initialize_roles(void)
 // End Function Specification
 void dcom_initialize_pbax_queues(void)
 {
-    pbax_id_t  l_pbaxid = dcom_pbusid2pbaxid(G_pob_id);
-
-    //SSX return codes
+    // SSX return codes
     int l_rc = 0;
 
     do
     {
-// @TODO - TEMP - PBA_XCFG (Address 0x40020108) is not mapped in simics yet
-//        pbax_send_disable();
-
-        // Check if conversion has valid information
-        if (( l_pbaxid.chip_id > MAX_PBAX_CHIP_ID ) ||
-                ( l_pbaxid.node_id == INVALID_NODE_ID ))
-        {
-            TRAC_ERR("Error converting pbusids to pbaxids. chip_id[0x%08x], node_id[0x%08x]",
-                     l_pbaxid.chip_id, l_pbaxid.node_id);
-            l_rc = -1; // Force error to be logged below.
-            break;
-        }
-
-        l_rc = pbax_configure(G_occ_role,        // master
-                              l_pbaxid.node_id,  // node id
-                              l_pbaxid.chip_id,  // chipd id
+        //disabled pbax send before configuring PBAX
+        pbax_send_disable();
+
+        // TODO: With the new design, PBAX node and chip IDs are set by hostboot
+        //       Remove these ID parameters from the pbax_configure function?
+        l_rc = pbax_configure(G_occ_role,                     // master
+                              G_pbax_id.node_id,              // node id
+                              G_pbax_id.chip_id,              // chipd id
                               PBAX_CONFIGURE_RCV_GROUP_MASK); // group_mask
 
         if(l_rc != 0)
@@ -365,17 +224,16 @@ void dcom_initialize_pbax_queues(void)
         }
 
         //enabled pbax send does not return errors
-// @TODO - TEMP - PBA_XCFG (Address 0x40020108) is not mapped in simics yet
-//        pbax_send_enable();
+        pbax_send_enable();
 
         if(G_occ_role == OCC_SLAVE)
         {
             // create pbax rx queue 1
-            l_rc = pbax_queue_create( &G_pbax_read_queue[1],//queue
-                    ASYNC_ENGINE_PBAX_PUSH1,                //engine
-                    G_pbax_queue_rx1_buffer,                //cq base
-                    NUM_ENTRIES_PBAX_QUEUE1,                //cq entries
-                    PBAX_INTERRUPT_PROTOCOL_AGGRESSIVE      //protocol
+            l_rc = pbax_queue_create( &G_pbax_read_queue[1], //queue
+                    ASYNC_ENGINE_PBAX_PUSH1,                 //engine
+                    G_pbax_queue_rx1_buffer,                 //cq base
+                    NUM_ENTRIES_PBAX_QUEUE1,                 //cq entries
+                    PBAX_INTERRUPT_PROTOCOL_AGGRESSIVE       //protocol
                     );
 
             if(l_rc != 0)
@@ -410,13 +268,12 @@ void dcom_initialize_pbax_queues(void)
 
         if(G_occ_role == OCC_MASTER)
         {
-            // TODO: Change this to PBAX_GROUP for Venice
             l_rc = pbax_target_create( &G_pbax_multicast_target,    // target,
-                    PBAX_BROADCAST,             // type
-                    PBAX_SYSTEM,                // scope TODO
-                    0,                          // queue
-                    l_pbaxid.node_id,           // node
-                    PBAX_BROADCAST_GROUP);      // chip_or_group
+                    PBAX_BROADCAST,                                 // type
+                    PBAX_SYSTEM,                                    // scope TODO
+                    0,                                              // queue
+                    G_pbax_id.node_id,                              // node
+                    PBAX_BROADCAST_GROUP);                          // chip_or_group
 
             if(l_rc != 0)
             {
@@ -456,38 +313,6 @@ void dcom_initialize_pbax_queues(void)
 
 // Function Specification
 //
-// Name: dcom_pbusid2pbaxid
-//
-// Description: Translate between PowerBus ID and pbax ID
-//
-// End Function Specification
-pbax_id_t dcom_pbusid2pbaxid(pob_id_t i_pobid)
-{
-    pbax_id_t l_pbax_id_t = {0};
-
-    // Check if chip id and nod id are valid
-    if((i_pobid.chip_id < MAX_NUM_OCC)
-        && (i_pobid.node_id < MAX_NUM_NODES))
-    {
-        l_pbax_id_t.chip_id = G_sysConfigData.pob2pbax_chip[i_pobid.chip_id];
-        l_pbax_id_t.node_id = G_sysConfigData.pob2pbax_node[i_pobid.node_id];
-    }
-    else
-    {
-        // Invalid data found
-
-        l_pbax_id_t.chip_id = MAX_PBAX_CHIP_ID;
-        l_pbax_id_t.node_id = INVALID_NODE_ID;
-
-        TRAC_ERR("Invalid Powerbus ID, could NOT convert chip id[%x] and node id[%x] to PBAX id",
-                   i_pobid.chip_id,i_pobid.node_id);
-    }
-
-    return l_pbax_id_t;
-}
-
-// Function Specification
-//
 // Name: dcom_error_check
 //
 // Description: keep track of failure counts
@@ -659,7 +484,6 @@ void dcom_build_occfw_msg( const dcom_error_type_t i_which_msg )
 
 }
 
-#if 0 // TODO - TEMP - Phase1 - Not ready yet for multi OCC communications.
 
 // Function Specification
 //
@@ -817,7 +641,5 @@ void task_dcom_parse_occfwmsg(task_t *i_self)
     G_slave_event_flags = (G_slave_event_flags & (~(G_dcom_slv_inbox_rx.occ_fw_mailbox[3])));
 }
 
-#endif // #if 0 -  // TODO - TEMP - Phase1 - Not ready yet for multi OCC communications.
-
 #endif //_DCOM_C
 
diff --git a/src/occ_405/dcom/dcom.h b/src/occ_405/dcom/dcom.h
index 5fcfe17..55f59e3 100755
--- a/src/occ_405/dcom/dcom.h
+++ b/src/occ_405/dcom/dcom.h
@@ -59,8 +59,12 @@
 // Magic Number used to denote the start of Master->Slave Broadcast packets
 #define PBAX_MAGIC_NUMBER2_32B           0x00474A53
 
-#define MAX_PBAX_CHIP_ID 7
-#define INVALID_NODE_ID 7
+#define MAX_PBAX_CHIP_ID (MAX_NUM_OCC - 1)
+
+// PBAX Broadcast Masks, use PBAX_GROUP_MASK_MAX
+#define PBAX_CONFIGURE_RCV_GROUP_MASK PBAX_GROUP_MASK_MAX
+#define PBAX_BROADCAST_GROUP          PBAX_GROUP_MASK_MAX
+
 
 // OCC Slave to Master Messages (inbox ping/pong) - Moved to BAR2
 #define ADDR_SLAVE_OUTBOX_MAIN_MEM_PING 0x20001000
@@ -102,8 +106,10 @@
 typedef struct
 {
     uint8_t module_id  :2;
-    uint8_t node_id    :3;
-    uint8_t chip_id    :3;
+    uint8_t valid      :1;  // Valid chip/node id?
+    uint8_t node_id    :2;
+    uint8_t reserved   :1;
+    uint8_t chip_id    :2;
 } pob_id_t;
 
 // TODO may change in the future
@@ -240,7 +246,7 @@ typedef struct
     {
         struct
         {
-            // PowerBus ID so that the slave knows who the master is
+            // PowerBus ID (= pbax_id) so that the slave knows who the master is
             pob_id_t pob_id;                        //  1 byte
             // Magic Number denoting the start of the packet
             uint32_t magic1                :24;     //  3 bytes
@@ -395,9 +401,9 @@ extern uint8_t G_occ_role;
 // chip. In the case of SCMs, it will always return the Master role.
 extern uint8_t G_dcm_occ_role;
 
-// Holds PowerBus ID of this OCC (Chip & node). From this we can determine OCC ID
-// and PBAX ID.
-extern pob_id_t G_pob_id;
+// Holds PowerBus ID of this OCC (Chip & node). For P9, this is the same
+// for pob_id and PBAX ID.
+extern pob_id_t G_pbax_id;
 
 // PBAX 'Target' Structure (Register Abstraction) that has the data needed for
 // a multicast operation.
@@ -488,9 +494,6 @@ void task_dcom_tx_slv_outbox(task_t *i_self);
 // Initialize the pbax queues
 void dcom_initialize_pbax_queues(void);
 
-// Translate pids to pbax ids
-pbax_id_t dcom_pbusid2pbaxid(pob_id_t i_pobid);
-
 // Receive multicast doorbell
 uint32_t dcom_rx_slv_inbox_doorbell( void );
 
diff --git a/src/occ_405/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index 69f45d4..d166aef 100644
--- a/src/occ_405/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -26,8 +26,7 @@
 #ifndef _DCOMMASTERTX_C
 #define _DCOMMASTERTX_C
 
-#include <pgp_pmc.h>
-#include "pgp_pba.h"
+#include "occhw_pba.h"
 #include <rtls.h>
 #include <apss.h>
 #include <dcom.h>
@@ -174,7 +173,7 @@ uint32_t dcom_build_slv_inbox(void)
     //DOORBELL.................
     //Prepare data for doorbell.  This is sent to all OCCs
 
-    G_dcom_slv_inbox_doorbell_tx.pob_id = G_pob_id;
+    G_dcom_slv_inbox_doorbell_tx.pob_id = G_pbax_id;
     G_dcom_slv_inbox_doorbell_tx.magic1 = PBAX_MAGIC_NUMBER2_32B;
     G_dcom_slv_inbox_doorbell_tx.addr_slv_inbox_buffer0 = l_addr_of_slv_inbox_in_main_mem;
 
diff --git a/src/occ_405/dcom/dcomSlaveRx.c b/src/occ_405/dcom/dcomSlaveRx.c
index d4d8aff..dd9bb82 100644
--- a/src/occ_405/dcom/dcomSlaveRx.c
+++ b/src/occ_405/dcom/dcomSlaveRx.c
@@ -64,7 +64,8 @@ bool     G_apss_lower_pmax_rail = FALSE;
 // End Function Specification
 uint32_t dcom_calc_slv_inbox_addr(void)
 {
-    return (G_dcom_slv_inbox_doorbell_rx.addr_slv_inbox_buffer0 + ( G_pob_id.chip_id * sizeof(dcom_slv_inbox_t) ));
+    return (G_dcom_slv_inbox_doorbell_rx.addr_slv_inbox_buffer0
+            + ( G_pbax_id.chip_id * sizeof(dcom_slv_inbox_t) ) );
 }
 
 // Function Specification
@@ -301,7 +302,7 @@ void task_dcom_rx_slv_inbox( task_t *i_self)
                 // start task waiting for master to talk again.
                 rtl_start_task(TASK_ID_DCOM_WAIT_4_MSTR);
                 rtl_set_run_mask_deferred(RTL_FLAG_MSTR_READY);
-                TRAC_INFO("[%d]: Lost connection to master",(int) G_pob_id.chip_id);
+                TRAC_INFO("[%d]: Lost connection to master",(int) G_pbax_id.chip_id);
                 break;
             }
         }
@@ -599,9 +600,8 @@ void task_dcom_wait_for_master( task_t *i_self)
         // set up a unicast PBAX target to the master.
         if(!L_first_doorbell_rcvd)
         {
-            // Convert powerbus id to pbax id (sets node_id to INVALID_NODE_ID on failure)
-            l_pbaxid = dcom_pbusid2pbaxid(G_dcom_slv_inbox_doorbell_rx.pob_id); // Traces failure internally
-            if(l_pbaxid.node_id == INVALID_NODE_ID)
+            l_pbaxid = G_dcom_slv_inbox_doorbell_rx.pob_id;
+            if(l_pbaxid.node_id >= MAX_NUM_NODES)
             {
                 // We received an invalid power bus id from the master.
                 // This may be a communication failure, so allow some retries.
@@ -679,7 +679,7 @@ void task_dcom_wait_for_master( task_t *i_self)
             }
 
             TRAC_IMP("Slave OCC[%d] Received first doorbell from Master OCC[%d]",
-                     (int) G_pob_id.chip_id,
+                     (int) G_pbax_id.chip_id,
                      G_dcom_slv_inbox_doorbell_rx.pob_id.chip_id);
 
             // First message is dropped, so mark it as counted.
@@ -693,7 +693,7 @@ void task_dcom_wait_for_master( task_t *i_self)
         }
         else
         {
-             TRAC_INFO("[%d] Restablished contact via doorbell from Master",(int) G_pob_id.chip_id);
+             TRAC_INFO("[%d] Restablished contact via doorbell from Master",(int) G_pbax_id.chip_id);
 
              // Inform AMEC that Pmax_rail doesn't need to be lowered and reset
              // the no_master_doorbell counter
diff --git a/src/occ_405/dcom/dcomSlaveTx.c b/src/occ_405/dcom/dcomSlaveTx.c
index 0e16782..b083ff0 100755
--- a/src/occ_405/dcom/dcomSlaveTx.c
+++ b/src/occ_405/dcom/dcomSlaveTx.c
@@ -83,9 +83,9 @@ uint32_t dcom_build_slv_outbox(void)
 
     l_addr_of_slv_outbox_in_main_mem = dcom_which_buffer_slv_outbox();
 
-    l_addr_of_slv_outbox_in_main_mem += G_pob_id.chip_id*sizeof(dcom_slv_outbox_t);
+    l_addr_of_slv_outbox_in_main_mem += G_pbax_id.chip_id*sizeof(dcom_slv_outbox_t);
 
-    G_dcom_slv_outbox_doorbell_tx.pob_id = G_pob_id;
+    G_dcom_slv_outbox_doorbell_tx.pob_id = G_pbax_id;
     G_dcom_slv_outbox_doorbell_tx.pcap_valid = g_amec->pcap_valid;
     G_dcom_slv_outbox_doorbell_tx.active_node_pcap = g_amec->pcap.active_node_pcap;
     G_dcom_slv_outbox_doorbell_tx.addr_slv_outbox_buffer = l_addr_of_slv_outbox_in_main_mem;
diff --git a/src/occ_405/errl/errl.c b/src/occ_405/errl/errl.c
index bd80cd4..45c6c62 100755
--- a/src/occ_405/errl/errl.c
+++ b/src/occ_405/errl/errl.c
@@ -335,7 +335,7 @@ errlHndl_t createErrl(
         //NOTE: Design does not exist for these fields
         //TODO: fix this when design is done!
         l_rc->iv_userDetails.iv_fwLevel = 0;
-        l_rc->iv_userDetails.iv_occId = G_pob_id.chip_id;
+        l_rc->iv_userDetails.iv_occId = G_pbax_id.chip_id;
         l_rc->iv_userDetails.iv_occRole = G_occ_role;
         l_rc->iv_userDetails.iv_occRole = OCC_MASTER;
         l_rc->iv_userDetails.iv_operatingState = CURRENT_STATE();
diff --git a/src/occ_405/homer.c b/src/occ_405/homer.c
index e78a82c..823cbfa 100755
--- a/src/occ_405/homer.c
+++ b/src/occ_405/homer.c
@@ -61,8 +61,10 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
                                    void                    * const o_host_data,
                                    int                     * const o_ssx_rc)
 {
-// TEMP / TODO -- Commented out due to unused var warning
-//    Ppc405MmuMap l_mmuMapHomer = 0;
+#if PPC405_MMU_SUPPORT
+    Ppc405MmuMap l_mmuMapHomer = 0;
+#endif
+
     homer_rc_t l_rc = HOMER_SUCCESS;
     occHostConfigDataArea_t *l_hdcfg_data = 0x00000000;
 
diff --git a/src/occ_405/img_defs.mk b/src/occ_405/img_defs.mk
index a1257a5..da22314 100644
--- a/src/occ_405/img_defs.mk
+++ b/src/occ_405/img_defs.mk
@@ -150,7 +150,7 @@ endif
 # TODO: Enable this once we get MMU support working in simics
 # Currently, turning on MMU support causes an SSX panic (in Simics)
 ifeq "$(PPC405_MMU_SUPPORT)" ""
-PPC405_MMU_SUPPORT = 0
+PPC405_MMU_SUPPORT = 1
 endif
 
 ifeq "$(OCCHW_ASYNC_SUPPORT)" ""
@@ -176,13 +176,9 @@ GCC-O-LEVEL = -Os
 endif
 
 ifdef TRAC_TO_SIMICS
-GCC-DEFS += -DTRAC_TO_SIMICS=1
-endif
-
-ifdef STRAIGHT_TO_OBS_HACK
-GCC-DEFS += -DSTRAIGHT_TO_OBS_HACK=$(STRAIGHT_TO_OBS_HACK)
+GCC-DEFS += -DTRAC_TO_SIMICS=$(TRAC_TO_SIMICS)
 else
-GCC-DEFS += -DSTRAIGHT_TO_OBS_HACK=1
+GCC-DEFS += -DTRAC_TO_SIMICS=0
 endif
 
 GCC-DEFS += -DIMAGE_NAME=$(IMAGE_NAME)
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index 629e88c..3f87870 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -57,6 +57,7 @@
 //#include <fir_data_collect.h>
 #include <pss_service_codes.h>
 #include <dimm.h>
+#include "occhw_shared_data.h"
 
 extern uint32_t __ssx_boot; // Function address is 32 bits
 extern uint32_t G_occ_phantom_critical_count;
@@ -555,8 +556,7 @@ void master_occ_init()
     }
 
     // Reinitialize the PBAX Queues
-    // TEMP -- NO DCOM YET
-    //dcom_initialize_pbax_queues();
+    dcom_initialize_pbax_queues();
 }
 
 /*
@@ -591,8 +591,7 @@ void slave_occ_init()
     }
 */
     //Set up doorbell queues
-    // TEMP -- NO DCOM YET
-    //dcom_initialize_pbax_queues();
+    dcom_initialize_pbax_queues();
 
     // Run AMEC Slave Init Code
     amec_slave_init();
@@ -765,18 +764,8 @@ void Main_thread_routine(void *private)
     // change to use config_data_init at that time.
     // Default role initialization and determine OCC/Chip Id
 
-    // TEMP -- NO DCOM YET, init as OCC Master
-    //dcom_initialize_roles();
+    dcom_initialize_roles();
 
-#if STRAIGHT_TO_OBS_HACK
-    // Remove the next LOC when dcom_initialize_roles() is un-commented
-    G_occ_role = OCC_MASTER;  // TEMP - @TODO
-
-    // Remove the next 2 LOC when dcom_initialize_roles is un-commented
-    // AND cmdh is running to call master_occ_init
-    rtl_set_run_mask(RTL_FLAG_MSTR);
-    master_occ_init();
-#endif
 
     CHECKPOINT(ROLES_INITIALIZED);
 
@@ -829,17 +818,6 @@ void Main_thread_routine(void *private)
     // enable switch to actually start the watchdog function.
 //    ENABLE_WDOG;
 
-// TEMP: Normally these flags are set elsewhere, after the BMC/FSP
-//       send us configuration data. This is a temporary hack until
-//       that communication is enabled. Required for APSS tasks.
-#if STRAIGHT_TO_OBS_HACK
-    rtl_set_run_mask(RTL_FLAG_OBS);
-    rtl_clr_run_mask(RTL_FLAG_STANDBY);
-    rtl_clr_run_mask(RTL_FLAG_APSS_NOT_INITD);
-    rtl_clr_run_mask(RTL_FLAG_RST_REQ);
-#endif
-// END TEMP
-
     while (TRUE)
     {
         // Count each loop so the watchdog can tell the main thread is
@@ -963,6 +941,39 @@ int main(int argc, char **argv)
 
 #if PPC405_MMU_SUPPORT
     l_ssxrc = ppc405_mmu_map(
+            OSD_ADDR,
+            OSD_ADDR,
+//          OSD_ADDR | 0x18000000,
+            OSD_TOTAL_SHARED_DATA_BYTES,
+            0,
+            TLBLO_WR | TLBLO_I,
+            NULL
+            );
+
+    if(l_ssxrc != SSX_OK)
+    {
+        //failure means we can't talk to FSP.
+        SSX_PANIC(0x01000001);
+    }
+
+#if SIMICS_ENVIRONMENT
+    l_ssxrc = ppc405_mmu_map(
+            SIMICS_STDIO_BASE,
+            SIMICS_STDIO_BASE,
+            1024,
+            0,
+            TLBLO_WR | TLBLO_I,
+            NULL
+            );
+
+    if(l_ssxrc != SSX_OK)
+    {
+        //failure means we can't talk to FSP.
+        SSX_PANIC(0x01000001);
+    }
+#endif  /* SIMICS_ENVIRONMENT */
+
+    l_ssxrc = ppc405_mmu_map(
             CMDH_OCC_RESPONSE_BASE_ADDRESS,
             CMDH_OCC_RESPONSE_BASE_ADDRESS,
             CMDH_FSP_RSP_SIZE,
diff --git a/src/occ_405/occLinkInputFile b/src/occ_405/occLinkInputFile
index 0cb4978..eb3f48d 100644
--- a/src/occ_405/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
@@ -2,7 +2,11 @@ INPUT ( amec_data.o
         amec_freq.o
         amec_health.o
         amec_init.o
+        amec_amester.o
         amec_master_smh.o
+        amec_parm.o
+        amec_pcap.o
+        amec_parm_table.o
         amec_part.o
         amec_sensors_fw.o
         amec_sensors_power.o
@@ -22,6 +26,7 @@ INPUT ( amec_data.o
         dcom.o
         dcom_thread.o
         dcomMasterRx.o
+        dcomMasterTx.o
         dcomSlaveRx.o
         dcomSlaveTx.o
         dimm.o
diff --git a/src/occ_405/occ_sys_config.c b/src/occ_405/occ_sys_config.c
index 808fce0..9d7a40f 100755
--- a/src/occ_405/occ_sys_config.c
+++ b/src/occ_405/occ_sys_config.c
@@ -163,12 +163,10 @@ occSysConfigData_t G_sysConfigData =
         .unthrottle    = 0,
     },
 
+
     // -----------------------------------------------------------
     // Master/Slave Section Initializations
     // -----------------------------------------------------------
-    .pob2pbax_chip = {0,1,2,3,4,5,6,7},
-    .pob2pbax_node = {0,1,2,3},
-
     .is_occ_present = SYSCFG_ZERO_OCCS_PRESENT,
 
     .master_config = {
@@ -424,7 +422,7 @@ void sysConfigFspLess(void)
     // ----------------------------------------------------
     // Set OCC Role based on Config Data
     // ----------------------------------------------------
-    if( G_pob_id.chip_id == G_sysConfigData.master_config.default_master )
+    if( G_pbax_id.chip_id == G_sysConfigData.master_config.default_master )
     {
         G_occ_role = OCC_MASTER;
 
diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h
index 4d238ee..796d0bf 100755
--- a/src/occ_405/occ_sys_config.h
+++ b/src/occ_405/occ_sys_config.h
@@ -36,7 +36,7 @@
 #include <apss.h>
 #include <dimm.h>
 
-#define MAX_NUM_OCC              8
+#define MAX_NUM_OCC              4
 #define MAX_NUM_NODES            4
 #define MAX_NUM_CORES           24
 #define MAX_THREADS_PER_CORE     8
diff --git a/src/occ_405/proc/proc_pstate.c b/src/occ_405/proc/proc_pstate.c
index 26704de..a52132a 100755
--- a/src/occ_405/proc/proc_pstate.c
+++ b/src/occ_405/proc/proc_pstate.c
@@ -678,7 +678,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void)
                 TRAC_IMP("MSTR: Initial Pstates: V: %d, F: %d\n",l_voltage_pstate, l_freq_pstate);
 
                 // DCM SYNC (Master2Slave):  Send V & F Pstate to slave
-                G_proc_dcm_sync_state.dcm_pair_id = G_pob_id.chip_id;
+                G_proc_dcm_sync_state.dcm_pair_id = G_pbax_id.chip_id;
                 G_proc_dcm_sync_state.pstate_v = l_voltage_pstate;
                 G_proc_dcm_sync_state.pstate_f = l_freq_pstate;
 
diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h
index 91dd5ac..7ec3c2e 100755
--- a/src/occ_405/rtls/rtls.h
+++ b/src/occ_405/rtls/rtls.h
@@ -45,16 +45,16 @@ typedef enum {
     TASK_ID_APSS_CONT,
     TASK_ID_CORE_DATA_HIGH,
     TASK_ID_APSS_DONE,
-//    TASK_ID_DCOM_RX_INBX,
-//    TASK_ID_DCOM_TX_INBX,
+    TASK_ID_DCOM_RX_INBX,
+    TASK_ID_DCOM_TX_INBX,
     TASK_ID_POKE_WDT,                 // Reset ppc405 watchdog and OCB timer
     TASK_ID_DCOM_WAIT_4_MSTR,
     TASK_ID_DCOM_RX_OUTBX,
     TASK_ID_DCOM_TX_OUTBX,
-//    TASK_ID_DCOM_PARSE_FW_MSG,
     TASK_ID_MISC_405_CHECKS,        // Miscellaneous checks to be done by 405
+    TASK_ID_DCOM_PARSE_FW_MSG,
     TASK_ID_AMEC_SLAVE,             // AMEC SMH tasks
-//    TASK_ID_AMEC_MASTER,            // AMEC SMH tasks
+    TASK_ID_AMEC_MASTER,            // AMEC SMH tasks
 //    TASK_ID_CORE_DATA_CONTROL,
 //    TASK_ID_GPU_SM,                 // GPU State Machine
     TASK_ID_DIMM_SM,                // DIMM State Machine
diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c
index 20b60dd..5f08b17 100755
--- a/src/occ_405/rtls/rtls_tables.c
+++ b/src/occ_405/rtls/rtls_tables.c
@@ -100,24 +100,16 @@ task_t G_task_table[TASK_END] = {
     { FLAGS_APSS_CONT_MEAS,        task_apss_continue_pwr_meas,    NULL },  // TASK_ID_APSS_CONT
     { FLAGS_HIGH_CORES_DATA,       task_core_data,                 (void *) &G_high_cores},
     { FLAGS_APSS_DONE_MEAS,        task_apss_complete_pwr_meas,    NULL },  // TASK_ID_APSS_DONE
-// TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_RX_SLV_INBX,      task_dcom_rx_slv_inbox,         NULL },  // TASK_ID_DCOM_RX_INBX
-// TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_TX_SLV_INBX,      task_dcom_tx_slv_inbox,         NULL },  // TASK_ID_DCOM_TX_INBX
+    { FLAGS_DCOM_RX_SLV_INBX,      task_dcom_rx_slv_inbox,         NULL },  // TASK_ID_DCOM_RX_INBX
+    { FLAGS_DCOM_TX_SLV_INBX,      task_dcom_tx_slv_inbox,         NULL },  // TASK_ID_DCOM_TX_INBX
     { FLAGS_POKE_WDT,              task_poke_watchdogs,            NULL },  // TASK_ID_POKE_WDT
-// TEMP -- NOT SUPPORTED YET IN PHASE1
     { FLAGS_DCOM_WAIT_4_MSTR,      task_dcom_wait_for_master,      NULL },  // TASK_ID_DCOM_WAIT_4_MSTR
-// TEMP -- NOT SUPPORTED YET IN PHASE1
     { FLAGS_DCOM_RX_SLV_OUTBOX,    task_dcom_rx_slv_outboxes,      NULL },  // TASK_ID_DCOM_RX_OUTBX
-// TEMP -- NOT SUPPORTED YET IN PHASE1
     { FLAGS_DCOM_TX_SLV_OUTBOX,    task_dcom_tx_slv_outbox,        NULL },  // TASK_ID_DCOM_TX_OUTBX
-// TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_DCOM_PARSE_OCC_FW_MSG, task_dcom_parse_occfwmsg,       NULL },  // TASK_ID_DCOM_PARSE_FW_MSG
     { FLAGS_MISC_405_CHECKS,       task_misc_405_checks,           NULL },  // TASK_ID_MISC_405_CHECKS
-// TEMP -- NOT SUPPORTED YET IN PHASE1
+    { FLAGS_DCOM_PARSE_OCC_FW_MSG, task_dcom_parse_occfwmsg,       NULL },  // TASK_ID_DCOM_PARSE_FW_MSG
     { FLAGS_AMEC_SLAVE,            task_amec_slave,                NULL },  // TASK_ID_AMEC_SLAVE
-// TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_AMEC_MASTER,           task_amec_master,               NULL },  // TASK_ID_AMEC_MASTER
+    { FLAGS_AMEC_MASTER,           task_amec_master,               NULL },  // TASK_ID_AMEC_MASTER
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_CORE_DATA_CONTROL,     task_core_data_control,         NULL },  // TASK_ID_CORE_DATA_CONTROL
 // TEMP -- NOT YET IMPLEMENTED
@@ -135,15 +127,15 @@ const uint8_t G_tick0_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
                                 TASK_ID_POKE_WDT,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -155,14 +147,14 @@ const uint8_t G_tick1_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -174,14 +166,14 @@ const uint8_t G_tick2_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -193,14 +185,14 @@ const uint8_t G_tick3_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -212,15 +204,15 @@ const uint8_t G_tick4_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
                                 TASK_ID_POKE_WDT,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -232,14 +224,14 @@ const uint8_t G_tick5_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -251,14 +243,14 @@ const uint8_t G_tick6_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -270,14 +262,14 @@ const uint8_t G_tick7_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -289,15 +281,15 @@ const uint8_t G_tick8_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
                                 TASK_ID_POKE_WDT,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -309,14 +301,14 @@ const uint8_t G_tick9_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -328,14 +320,14 @@ const uint8_t G_tick10_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -347,14 +339,14 @@ const uint8_t G_tick11_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -366,15 +358,15 @@ const uint8_t G_tick12_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
                                 TASK_ID_POKE_WDT,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -386,14 +378,14 @@ const uint8_t G_tick13_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -405,14 +397,14 @@ const uint8_t G_tick14_seq[] = {
                                 TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
@@ -424,14 +416,14 @@ const uint8_t G_tick15_seq[] = {
                                 TASK_ID_APSS_DONE,
                                 //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
-                                //TASK_ID_DCOM_WAIT_4_MSTR,
-                                //TASK_ID_DCOM_RX_INBX,
-                                //TASK_ID_DCOM_RX_OUTBX,
-                                //TASK_ID_DCOM_TX_OUTBX,
-                                //TASK_ID_DCOM_TX_INBX,
+                                TASK_ID_DCOM_WAIT_4_MSTR,
+                                TASK_ID_DCOM_RX_INBX,
+                                TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_DCOM_TX_OUTBX,
+                                TASK_ID_DCOM_TX_INBX,
                                 TASK_ID_AMEC_SLAVE,
-                                //TASK_ID_AMEC_MASTER,
-                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                TASK_ID_AMEC_MASTER,
+                                TASK_ID_DCOM_PARSE_FW_MSG,
                                 TASK_ID_MISC_405_CHECKS,
                                 TASK_END };
 
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index 5ba98d5..d8e91fe 100755
--- a/src/occ_405/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -180,10 +180,6 @@ do {                                                                \
 #define USE_EPM_IO 0
 #endif
 
-#if SIMICS_ENVIRONMENT
-#define PPC405_MMU_SUPPORT 0
-#endif
-
 /// The buffer used for 'ssxout' in VBU and lab applications
 ///
 /// The buffer is defined to be quite large in order to accomodate full kernel
diff --git a/src/occ_405/topfiles.mk b/src/occ_405/topfiles.mk
index 93b574f..807e4de 100644
--- a/src/occ_405/topfiles.mk
+++ b/src/occ_405/topfiles.mk
@@ -26,7 +26,11 @@ TOP-C-SOURCES = amec/amec_data.c \
                 amec/amec_freq.c \
                 amec/amec_health.c \
                 amec/amec_init.c \
+                amec/amec_amester.c \
                 amec/amec_master_smh.c \
+                amec/amec_parm.c \
+                amec/amec_pcap.c \
+                amec/amec_parm_table.c \
                 amec/amec_part.c \
                 amec/amec_sensors_fw.c \
                 amec/amec_sensors_power.c \
@@ -45,10 +49,11 @@ TOP-C-SOURCES = amec/amec_data.c \
                 cmdh/cmdh_thread.c \
                 cmdh/cmdh_tunable_parms.c \
                 cmdh/ffdc.c \
-				common.c \
+                common.c \
                 dcom/dcom.c \
                 dcom/dcom_thread.c \
                 dcom/dcomMasterRx.c \
+                dcom/dcomMasterTx.c \
                 dcom/dcomSlaveRx.c \
                 dcom/dcomSlaveTx.c \
                 dimm/dimm.c \
diff --git a/src/occ_405/trac/trac.h b/src/occ_405/trac/trac.h
index 92fd9bf..601d3a8 100755
--- a/src/occ_405/trac/trac.h
+++ b/src/occ_405/trac/trac.h
@@ -63,17 +63,20 @@
 //               TRAC_ERR or TRAC_IMP. Any debug or informational traces.
 //      TRAC_DBG must be used for debug purpose only. This traces will be
 //               turned OFF with product code.
-#ifdef TRAC_TO_SIMICS
+#if TRAC_TO_SIMICS
 
 #define TRAC_ERR(frmt,args...)  \
-        printf(ERR_MRK "%s: "frmt "\n",__FUNCTION__,##args)
+        printf(ERR_MRK "%s: "frmt "\n",__FUNCTION__,##args); \
+        TRACE(&g_des_array[ERR_TRACE_DESCRIPTOR],frmt,##args)
 #define TRAC_INFO(frmt,args...)  \
-        printf(INFO_MRK "%s: "frmt "\n",__FUNCTION__,##args)
+        printf(INFO_MRK "%s: "frmt "\n",__FUNCTION__,##args); \
+        TRACE(&g_des_array[INF_TRACE_DESCRIPTOR],frmt,##args)
 #define TRAC_IMP(frmt,args...)  \
-        printf(IMP_MRK "%s: "frmt "\n",__FUNCTION__,##args)
-
+        printf(IMP_MRK "%s: "frmt "\n",__FUNCTION__,##args); \
+        TRACE(&g_des_array[IMP_TRACE_DESCRIPTOR],frmt,##args)
 #define DBG_PRINT(fmt,args...)  \
-        printf(DBG_MRK "%s: "fmt "\n",__FUNCTION__,##args)
+        printf(DBG_MRK "%s: "fmt "\n",__FUNCTION__,##args); \
+        TRACEBIN(&g_des_array[INF_TRACE_DESCRIPTOR], string, data,len)
 
 extern void dumpHexString(const void *i_data, const unsigned int len, const char *string);
 #define DEBUG_HEXDUMP(data, len, string)  \
diff --git a/src/ssx/occhw/occhw.h b/src/ssx/occhw/occhw.h
index b0ddda8..c0f11df 100644
--- a/src/ssx/occhw/occhw.h
+++ b/src/ssx/occhw/occhw.h
@@ -327,8 +327,18 @@ extern Ppc405MmuMap G_applet1_mmu_map;
 
 #endif  /* __ASSEMBLER__ */
 
-// OCCHW defines a private version of dcache_flush_all() that uses the undefined
-// OCI space at 0x20000000; See dcache_flush_all() in occhw_cache.S.
+// OCCHW defines a private version of dcache_flush_all() that uses undefined
+// OCI space defined by OCCHW_FLUSH_ZERO_ADDRESS.
+// See dcache_flush_all() in occhw_cache.S.
+//
+// DCCR bit | OCCHW_FLUSH_ZERO_ADDRESS ( see 405 spec for full table)
+// ---------|------------------------------------------
+//    0     | 0x00000000 - 0x07ffffff
+//    1     | 0x08000000 - 0x0fffffff
+//    4     | 0x20000000 - 0x27ffffff
+//    8     | 0x40000000 - 0x47ffffff  (undefined range - use for dcache flush)
+//   16     | 0x80000000 - 0x87ffffff  (overlaps PBA defined space)
+//   31     | 0xF8000000 - 0xffffffff  (overlaps SRAM)
 
 #define USE_GENERIC_DCACHE_FLUSH_ALL 0
 #define OCCHW_FLUSH_ZERO_ADDRESS       0x20000000
diff --git a/src/ssx/occhw/occhw_async.c b/src/ssx/occhw/occhw_async.c
index f0fbbca..ae3273b 100644
--- a/src/ssx/occhw/occhw_async.c
+++ b/src/ssx/occhw/occhw_async.c
@@ -999,8 +999,6 @@ async_initialize()
     async_gpe_initialize(&G_async_gpe_queue3, ASYNC_ENGINE_GPE3);
 
 
-    // TODO: add these back in as they are ported to P9
-#if 0
     // BCE
 
     async_bce_initialize(&G_pba_bcde_queue,
@@ -1010,7 +1008,6 @@ async_initialize()
     async_bce_initialize(&G_pba_bcue_queue,
                          ASYNC_ENGINE_BCUE,
                          OCCHW_IRQ_PBA_BCUE_ATTN);
-#endif
 
     // OCB
 
@@ -1062,7 +1059,6 @@ async_initialize()
                          OCB_WRITE3_LENGTH,
                          OCB_WRITE3_PROTOCOL);
 
-#if 0
     // PBAX
 
     async_pbax_initialize(&G_pbax_read_queue[0],
@@ -1078,5 +1074,4 @@ async_initialize()
                           G_pbax_read1_buffer,
                           PBAX_READ1_LENGTH,
                           PBAX_READ1_PROTOCOL);
-#endif
 }
diff --git a/src/ssx/occhw/occhw_async.h b/src/ssx/occhw/occhw_async.h
index e2bbf0a..be2996f 100644
--- a/src/ssx/occhw/occhw_async.h
+++ b/src/ssx/occhw/occhw_async.h
@@ -641,13 +641,13 @@ typedef struct {
     pba_fir_t fir;
 
     /// PBA Error Report 0
-    pba_errpt0_t errpt0;
+    pba_errrpt0_t errrpt0;
 
     /// PBA Error Report 1
-    pba_errpt1_t errpt1;
+    pba_errrpt1_t errrpt1;
 
     /// PBA Error Report 2
-    pba_errpt2_t errpt2;
+    pba_errrpt2_t errrpt2;
 
     /// PBA Read Buffer Valid Status
     pba_rbufvaln_t rbufval[PBA_READ_BUFFERS];
diff --git a/src/ssx/occhw/occhw_async_pba.c b/src/ssx/occhw/occhw_async_pba.c
index 3a03a17..b4bc8fb 100644
--- a/src/ssx/occhw/occhw_async_pba.c
+++ b/src/ssx/occhw/occhw_async_pba.c
@@ -140,9 +140,9 @@ pba_common_ffdc(PbaCommonFfdc* ffdc)
         }
 
         getscom(PBA_FIR, &(ffdc->fir.value));
-        getscom(PBA_ERRPT0, &(ffdc->errpt0.value));
-        getscom(PBA_ERRPT1, &(ffdc->errpt1.value));
-        getscom(PBA_ERRPT2, &(ffdc->errpt2.value));
+        getscom(PBA_ERRRPT0, &(ffdc->errrpt0.value));
+        getscom(PBA_ERRRPT1, &(ffdc->errrpt1.value));
+        getscom(PBA_ERRRPT2, &(ffdc->errrpt2.value));
 
         ffdc->error = 1;
     }
diff --git a/src/ssx/occhw/occhw_init.c b/src/ssx/occhw/occhw_init.c
index f3383b4..bbb67bd 100644
--- a/src/ssx/occhw/occhw_init.c
+++ b/src/ssx/occhw/occhw_init.c
@@ -174,6 +174,7 @@ static const MmuRegion mmu_regions[] = {
      0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_EX | TLBLO_WR,
      &G_ex_free_mmu_map},
 
+/*
     {(SsxAddress)&_APPLET0_SECTION_BASE,
      (size_t)&_APPLET0_SECTION_SIZE,
      0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_WR | TLBLO_EX,
@@ -183,7 +184,7 @@ static const MmuRegion mmu_regions[] = {
      (size_t)&_APPLET1_SECTION_SIZE,
      0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_WR | TLBLO_EX,
      &G_applet1_mmu_map},
-
+*/
     {(SsxAddress)OCI_REGISTER_SPACE_BASE,
      (size_t)OCI_REGISTER_SPACE_SIZE,
      0, TLBLO_WR | TLBLO_I | TLBLO_G, 0} ,
diff --git a/src/ssx/occhw/occhw_pba.c b/src/ssx/occhw/occhw_pba.c
index 4c21bb8..5ba18d5 100644
--- a/src/ssx/occhw/occhw_pba.c
+++ b/src/ssx/occhw/occhw_pba.c
@@ -257,13 +257,13 @@ pba_slave_reset(int id)
 /// not valid for some reason. 
 
 int
-pbax_configure(int master, int node, int chip, int group_mask)
+pbax_configure(int master, int group, int chip, int group_mask)
 {
     pba_xcfg_t pxc;
 
     if (SSX_ERROR_CHECK_API) {
-        SSX_ERROR_IF((node < 0) ||
-                     (node >= PBAX_NODES) ||
+        SSX_ERROR_IF((group < 0) ||
+                     (group >= PBAX_GROUPS) ||
                      (chip < 0) ||
                      (chip >= PBAX_CHIPS) ||
                      (group_mask < 0) ||
@@ -272,7 +272,7 @@ pbax_configure(int master, int node, int chip, int group_mask)
     }
     pxc.value = in64(PBA_XCFG);
     pxc.fields.reservation_en = (master != 0);
-    pxc.fields.rcv_nodeid = node;
+    pxc.fields.rcv_groupid = group;
     pxc.fields.rcv_chipid = chip;
     pxc.fields.rcv_brdcst_group = group_mask;
     out64(PBA_XCFG, pxc.value);
@@ -312,7 +312,7 @@ pbax_configure(int master, int node, int chip, int group_mask)
 int
 pbax_target_create(PbaxTarget* target,
                    int type, int scope, int queue, 
-                   int node, int chip_or_group)
+                   int group, int chip_or_group)
 {
     if (SSX_ERROR_CHECK_API) {
         SSX_ERROR_IF(target == 0, PBAX_INVALID_OBJECT);
@@ -327,7 +327,7 @@ pbax_target_create(PbaxTarget* target,
     target->target.fields.snd_qid = queue;
     target->target.fields.snd_type = type;
     target->target.fields.snd_reservation = (type == PBAX_BROADCAST);
-    target->target.fields.snd_nodeid = node;
+    target->target.fields.snd_groupid = group;
     target->target.fields.snd_chipid = chip_or_group;
 
     return 0;
diff --git a/src/ssx/ssx/ssx_api.h b/src/ssx/ssx/ssx_api.h
index e4f6a10..bcdd0fb 100644
--- a/src/ssx/ssx/ssx_api.h
+++ b/src/ssx/ssx/ssx_api.h
@@ -538,6 +538,24 @@ typedef struct {
 #define SSXTRACE_BIN(str, bufp, buf_size)
 #endif //SSX_TRACE_SUPPORT
 
+//Needed for easy cache flush of trace buffer
+//Note, in order to use this macro you must declare g_ssx_trace_buf[_size]
+//  as extern SsxTraceBuffer [and size_t] variables in the .c file as well
+//  as include ssx_trace.h.
+#if (SSX_TRACE_ENABLE && SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+#define SSX_FLUSH_TRACE_BUF() dcache_flush(&g_ssx_trace_buf, g_ssx_trace_buf_size)
+#else
+#define SSX_FLUSH_TRACE_BUF()
+#endif
+
+//Making sure we can still compile application codes if SSX tracing for some
+//  reason isn't enabled.
+#if (SSX_TRACE_ENABLE && SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT)
+#define SSX_TRACE_INIT(freqhz, time0) ssx_trace_init(freqhz, time0)
+#else
+#define SSX_TRACE_INIT(freqhz, time0)
+#endif
+
 /// A generic doubly-linked list object
 ///
 /// This object functions both as a sentinel mode for a deque as well as a
diff --git a/src/ssx/trace/ssx_trace.h b/src/ssx/trace/ssx_trace.h
index c79452b..3f4505f 100644
--- a/src/ssx/trace/ssx_trace.h
+++ b/src/ssx/trace/ssx_trace.h
@@ -299,5 +299,6 @@ typedef struct
 }SsxTraceBuffer;
 
 extern SsxTraceBuffer g_ssx_trace_buf;
+extern size_t         g_ssx_trace_buf_size;
 
 #endif /* __SSX_TRACE_H__ */
diff --git a/src/ssx/trace/ssx_trace_core.c b/src/ssx/trace/ssx_trace_core.c
index a2db4b8..de9d309 100644
--- a/src/ssx/trace/ssx_trace_core.c
+++ b/src/ssx/trace/ssx_trace_core.c
@@ -162,4 +162,8 @@ void ssx_trace_init(uint32_t    timebase_frequency_hz,
                        0);
 }
 
+////Needed for easy cache flush of trace buffer
+size_t g_ssx_trace_buf_size=sizeof(g_ssx_trace_buf);
+
+
 #endif