setup the GPE0/1 Halt and the System Checkstop interrupts properly

Fix the ownership of these interrupts (assign it to the OCC), and
set the interrupt type to level, and the interrupt polarity to high.

Change-Id: I00c045736f4c3b196a95fdb9aa07f6f4dd66c8c6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38898
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Tested-by: Wael El-Essawy <welessa@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

4 files changed, 32 insertions, 28 deletions

diff --git a/src/occ_405/common.c b/src/occ_405/common.c
index 9ece82b..3304aab 100755
--- a/src/occ_405/common.c
+++ b/src/occ_405/common.c
@@ -42,7 +42,6 @@ uint8_t G_host_notifications_pending = 0;
 //              - checkstops
 //
 // End Function Specification
-
 void task_misc_405_checks(task_t *i_self)
 {
     if (G_host_notifications_pending != 0)
@@ -51,10 +50,10 @@ void task_misc_405_checks(task_t *i_self)
     }
 
     // Check for checkstops
-    ocb_oisr0_t l_oisr0_status;
-    static bool L_checkstop_traced = false;
-    uint8_t     l_reason_code      = 0;
-    bool        gpe_halt_detected  = false;
+    ocb_oisr0_t  l_oisr0_status;       // OCC Interrupt Source 0 Register
+
+    static bool L_checkstop_traced    = false;
+    uint8_t     l_reason_code         = 0;
 
     do
     {
@@ -63,36 +62,40 @@ void task_misc_405_checks(task_t *i_self)
         {
             break;
         }
-
-        // Looked for a frozen GPE, a sign that the chip has stopped working or
-        // check-stopped.  This check also looks for an interrupt status flag that
+        // Look for a frozen GPE, a sign that the chip has stopped working or
+        // halted.  This check also looks for an interrupt status flag that
         // indicates if the system has check-stopped.
         l_oisr0_status.value = in32(OCB_OISR0); // read high order 32 bits of OISR0
 
-        gpe_halt_detected =
-            l_oisr0_status.fields.gpe0_error |   // GPE0 halted
-            l_oisr0_status.fields.gpe1_error;    // GPE1 halted
 
-        if (l_oisr0_status.fields.check_stop_ppc405 || gpe_halt_detected)
+        if (l_oisr0_status.fields.check_stop_ppc405 ||   // System Checkstop
+            l_oisr0_status.fields.gpe0_error        ||   // GPE0 Halt
+            l_oisr0_status.fields.gpe1_error)            // GPE1 Halt
         {
             errlHndl_t l_err = NULL;
 
-            if (gpe_halt_detected)
+            if (l_oisr0_status.fields.gpe0_error)
+            {
+                TRAC_IMP("task_misc_405_checks: Frozen GPE0 detected by RTL: OISR0[0x%08x]",
+                         l_oisr0_status.value);
+                l_reason_code = OCC_GPE_HALTED;
+            }
+
+            if (l_oisr0_status.fields.gpe1_error)
             {
-                TRAC_IMP("Frozen GPE detected by RTL, GPE0|GPE1 HALT:[%d|%d], OISR0[0x%08x]",
-                         l_oisr0_status.fields.gpe0_error, l_oisr0_status.fields.gpe1_error,
+                TRAC_IMP("task_misc_405_checks: Frozen GPE1 detected by RTL: OISR0[0x%08x]",
                          l_oisr0_status.value);
                 l_reason_code = OCC_GPE_HALTED;
             }
 
             if (l_oisr0_status.fields.check_stop_ppc405)
             {
-                TRAC_IMP("System checkstop detected by RTL, OISR0[0x%08x]",
+                TRAC_IMP("task_misc_405_checks: System checkstop detected by RTL: OISR0[0x%08x]",
                          l_oisr0_status.value);
                 l_reason_code = OCC_SYSTEM_HALTED;
             }
 
-            L_checkstop_traced = TRUE;
+            L_checkstop_traced = true;
 
             /*
              * @errortype
diff --git a/src/occ_405/common.h b/src/occ_405/common.h
index 6501783..ac4a9fd 100644
--- a/src/occ_405/common.h
+++ b/src/occ_405/common.h
@@ -27,7 +27,6 @@
 
 #include <rtls.h>
 
-
 // Reasons why the OCCMISC external interrupt was triggered
 typedef enum
 {
diff --git a/src/occ_405/errl/errl.c b/src/occ_405/errl/errl.c
index 07b5e6e..8076163 100755
--- a/src/occ_405/errl/errl.c
+++ b/src/occ_405/errl/errl.c
@@ -372,18 +372,20 @@ void addTraceToErrl(
     void * l_traceAddr = io_err;
     uint16_t l_actualSizeOfUsrDtls = 0;
 
-    ocb_oisr0_t l_oisr0_status;
-    static bool L_sys_checkstop_traced = FALSE;
+    ocb_oisr0_t  l_oisr0_status;       // OCC Interrupt Source 0 Register
 
+    static bool L_sys_checkstop_traced = FALSE;
 
     // Check if there is any system checkstop
-    l_oisr0_status.value = in32(OCB_OISR0);
+    l_oisr0_status.value    = in32(OCB_OISR0);
 
-    if (l_oisr0_status.fields.check_stop_ppc405 && !L_sys_checkstop_traced)
+    // Level triggered interrupts?
+    if (l_oisr0_status.fields.check_stop_ppc405 &&
+        !L_sys_checkstop_traced)
     {
-        L_sys_checkstop_traced = TRUE;
-        TRAC_IMP("addTraceToErrl: System checkstop detected: ppc405, OISR0[0x%08x]",
-                 l_oisr0_status.value);
+            L_sys_checkstop_traced = TRUE;
+            TRAC_IMP("addTraceToErrl: System checkstop detected: ppc405, OISR0[0x%08x]",
+                     l_oisr0_status.value);
     }
 
     // 1. Check if error log is not null
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index 1418d0b..7764ccc 100755
--- a/src/occ_405/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -72,10 +72,10 @@ do {                                                                \
 /// IRQ#, TYPE, POLARITY, ENABLE
 ///
 #define APPCFG_EXT_IRQS_CONFIG \
-    OCCHW_IRQ_GPE0_HALT                 OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
-    OCCHW_IRQ_GPE1_HALT                 OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
+    OCCHW_IRQ_GPE0_HALT                 OCCHW_IRQ_TYPE_LEVEL    OCCHW_IRQ_POLARITY_HI       OCCHW_IRQ_MASKED \
+    OCCHW_IRQ_GPE1_HALT                 OCCHW_IRQ_TYPE_LEVEL    OCCHW_IRQ_POLARITY_HI       OCCHW_IRQ_MASKED \
     OCCHW_IRQ_PPC405_HALT               OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
-    OCCHW_IRQ_CHECK_STOP_PPC405         OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
+    OCCHW_IRQ_CHECK_STOP_PPC405         OCCHW_IRQ_TYPE_LEVEL    OCCHW_IRQ_POLARITY_HI       OCCHW_IRQ_MASKED \
     OCCHW_IRQ_OCB_ERROR                 OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
     OCCHW_IRQ_SPIPSS_ERROR              OCCHW_IRQ_TYPE_EDGE     OCCHW_IRQ_POLARITY_RISING   OCCHW_IRQ_MASKED \
     OCCHW_IRQ_EXTERNAL_TRAP             OCCHW_IRQ_TYPE_LEVEL    OCCHW_IRQ_POLARITY_HI       OCCHW_IRQ_MASKED \