Sync HW SSX with OCC FW SSX

Change-Id: I2d416da654566747f40df3bed0e122919fc514e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29592
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

4 files changed, 26 insertions, 134 deletions

diff --git a/src/ssx/occhw/occhw_ocb.c b/src/ssx/occhw/occhw_ocb.c
index 813517e..7ecb713 100644
--- a/src/ssx/occhw/occhw_ocb.c
+++ b/src/ssx/occhw/occhw_ocb.c
@@ -144,43 +144,25 @@ ocb_timer_setup(int timer,
                 int priority)
 {
     int rc;
-    tpc_hpr2_t l_hpr2;
 
-    do
-    {
-        //Read Hang Pulse Register 2 to get the log base 2 of the ocb clock divider -- grm
-// TEMP/TODO: Cannot do getscom from 405
-// TODO: Need to discuss this getscom and whether it is necessary.
-//        rc = getscom(TPC_HPR2, &l_hpr2.value);
-
-        if(rc)
-        {
-            break;
-        }
-//TEMP/TODO: l_hpr2.fields.hang_pulse_reg is typically 9
-//        g_ocb_timer_divider = 1 << l_hpr2.fields.hang_pulse_reg;
-        g_ocb_timer_divider = 1 << 9;
+    //printk("ocb_timer_setup(%d, %d, %d, %p, %p, %d)\n",
+    //       timer, auto_reload, timeout_ns,
+    //       handler, arg, priority);
 
-        //printk("ocb_timer_setup(%d, %d, %d, %p, %p, %d)\n",
-        //       timer, auto_reload, timeout_ns,
-        //       handler, arg, priority);
+    ssx_irq_disable(OCCHW_IRQ_OCC_TIMER0 + timer);
 
-        ssx_irq_disable(OCCHW_IRQ_OCC_TIMER0 + timer);
+    ssx_irq_setup(OCCHW_IRQ_OCC_TIMER0 + timer,
+                  SSX_IRQ_POLARITY_ACTIVE_HIGH,
+                  SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
 
-        ssx_irq_setup(OCCHW_IRQ_OCC_TIMER0 + timer,
-                      SSX_IRQ_POLARITY_ACTIVE_HIGH,
-                      SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
+    ssx_irq_handler_set(OCCHW_IRQ_OCC_TIMER0 + timer,
+                        handler,
+                        arg,
+                        priority);
 
-        ssx_irq_handler_set(OCCHW_IRQ_OCC_TIMER0 + timer,
-                            handler,
-                            arg,
-                            priority);
+    rc = ocb_timer_reset(timer, auto_reload, timeout_ns);
 
-        rc = ocb_timer_reset(timer, auto_reload, timeout_ns);
-
-        ssx_irq_enable(OCCHW_IRQ_OCC_TIMER0 + timer);
-    }
-    while(0);
+    ssx_irq_enable(OCCHW_IRQ_OCC_TIMER0 + timer);
 
     return rc;
 }
diff --git a/src/ssx/occhw/occhw_pba.c b/src/ssx/occhw/occhw_pba.c
index 55d7a6c..15b4c35 100644
--- a/src/ssx/occhw/occhw_pba.c
+++ b/src/ssx/occhw/occhw_pba.c
@@ -318,7 +318,7 @@ pbax_configure(int master, int group, int chip, int group_mask)
 int
 pbax_target_create(PbaxTarget* target,
                    int type, int scope, int queue,
-                   int group, int chip_or_group)
+                   int group, int chip_or_group, int cnt)
 {
     if (SSX_ERROR_CHECK_API)
     {
@@ -336,6 +336,7 @@ pbax_target_create(PbaxTarget* target,
     target->target.fields.snd_reservation = (type == PBAX_BROADCAST);
     target->target.fields.snd_groupid = group;
     target->target.fields.snd_chipid = chip_or_group;
+    target->target.fields.snd_cnt = cnt;
 
     return 0;
 }
@@ -441,7 +442,7 @@ _pbax_send(PbaxTarget* target, uint64_t data, SsxInterval timeout)
 
     if (!rc)
     {
-        out32(PBA_XSNDTX, target->target.words.high_order);
+        out64(PBA_XSNDTX, target->target.value);
         out32(PBA_XSNDDAT + 4, data >> 32);
         out32(PBA_XSNDDAT, data & 0xffffffff);
     }
@@ -449,7 +450,6 @@ _pbax_send(PbaxTarget* target, uint64_t data, SsxInterval timeout)
     return rc;
 }
 
-
 /// Use PBAX to send 64 bits to a target with a default timeout
 ///
 /// \param target An abstract PBAX target object
@@ -496,13 +496,3 @@ pbax_send(PbaxTarget* target, uint64_t data)
 }
 
 
-
-
-
-
-
-
-
-
-
-
diff --git a/src/ssx/occhw/occhw_pba.h b/src/ssx/occhw/occhw_pba.h
index b5ee30b..9346d0d 100644
--- a/src/ssx/occhw/occhw_pba.h
+++ b/src/ssx/occhw/occhw_pba.h
@@ -33,6 +33,8 @@
 #include "pba_register_addresses.h"
 #include "pba_firmware_registers.h"
 
+#include "occhw_pba_common.h"
+
 #define POWERBUS_CACHE_LINE_SIZE 128
 #define LOG_POWERBUS_CACHE_LINE_SIZE 7
 
@@ -85,76 +87,7 @@
 /// The number of PBA write buffers
 #define PBA_WRITE_BUFFERS 2
 
-
-////////////////////////////////////
-// Macros for fields of PBA_SLVCTLn
-////////////////////////////////////
-
-// PBA write Ttypes
-
-#define PBA_WRITE_TTYPE_DMA_PR_WR    0x0 /// DMA Partial Write
-#define PBA_WRITE_TTYPE_LCO_M        0x1 /// L3 LCO for IPL, Tsize denotes chiplet.
-#define PBA_WRITE_TTYPE_ATOMIC_RMW   0x2 /// Atomic operations
-#define PBA_WRITE_TTYPE_CACHE_INJECT 0x3 /// Cache inject after IPL
-#define PBA_WRITE_TTYPE_CI_PR_W      0x4 /// Cache-inhibited partial write for Centaur putscom().
-
-#define PBA_WRITE_TTYPE_DC PBA_WRITE_TTYPE_DMA_PR_WR // Don't care
-
-
-// PBA write Tsize is only required for PBA_WRITE_TTYPE_LCO_M (where it
-// actually specifies a core chiplet id) and PBA_WRITE_TTYPE_ATOMIC_RMW.
-
-#define PBA_WRITE_TSIZE_CHIPLET(chiplet) (chiplet)
-
-#define PBA_WRITE_TSIZE_ARMW_ADD 0x02
-#define PBA_WRITE_TSIZE_ARMW_AND 0x22
-#define PBA_WRITE_TSIZE_ARMW_OR  0x42
-#define PBA_WRITE_TSIZE_ARMW_XOR 0x62
-
-#define PBA_WRITE_TSIZE_DC 0x0
-
-
-// PBA write gather timeouts are defined in terms of the number of 'pulses'. A
-// pulse occurs every 64 OCI cycles. The timing of the last write of a
-// sequence is variable, so the timeout will occur somewhere between (N - 1) *
-// 64 and N * 64 OCI cycles.  If write gather timeouts are disabled, the PBA
-// holds the data until some condition occurs that causes it to disgorge the
-// data. Slaves using cache-inhibited partial write never gather write
-// data. Note from spec. : "Write gather timeouts must NOT be disabled if
-// multiple masters are enabled to write through the PBA".  The only case
-// where write gather timeouts will be disabled is for the IPL-time injection
-// of data into the L3 caches. Note that disabling write-gathering timeouts is
-// different from disabling write-gathering altogether with the
-// SLVCTL.dis_write_gather setting.
-
-#define PBA_WRITE_GATHER_TIMEOUT_DISABLE   0x0
-#define PBA_WRITE_GATHER_TIMEOUT_2_PULSES  0x4
-#define PBA_WRITE_GATHER_TIMEOUT_4_PULSES  0x5
-#define PBA_WRITE_GATHER_TIMEOUT_8_PULSES  0x6
-#define PBA_WRITE_GATHER_TIMEOUT_16_PULSES 0x7
-
-/// PBA write gather timeout don't care assignment - see gpe_pba_parms_create()
-#define PBA_WRITE_GATHER_TIMEOUT_DC -1
-
-
-// PBA read Ttype
-
-#define PBA_READ_TTYPE_CL_RD_NC      0x0 /// Cache line read
-#define PBA_READ_TTYPE_CI_PR_RD      0x1 /// Cache-inhibited partial read for Centaur getscom().
-
-/// PBA read TTYPE don't care assignment
-#define PBA_READ_TTYPE_DC PBA_READ_TTYPE_CL_RD_NC
-
-
-// PBA read prefetch options
-
-#define PBA_READ_PREFETCH_AUTO_EARLY  0x0 /// Aggressive prefetch
-#define PBA_READ_PREFETCH_NONE        0x1 /// No prefetch
-#define PBA_READ_PREFETCH_AUTO_LATE   0x2 /// Non-aggressive prefetch
-
-/// PBA read prefetch don't care assignment - see gpe_pba_parms_create()
-#define PBA_READ_PREFETCH_DC -1
-
+// PBASLVCTLn and PBASLVRST macros defined in occhw_pba_common.h
 
 // PBA PowerBus command scope and priority, and PBA defaults
 
@@ -182,24 +115,6 @@
 /// Default command scope for BCDE/BCUE transfers
 #define PBA_POWERBUS_COMMAND_SCOPE_DEFAULT POWERBUS_COMMAND_SCOPE_NODAL
 
-
-
-// Abstract fields of the PBA Slave Reset register used in pba_slave_reset(),
-// which checks 'n' for validity.p
-
-#define PBA_SLVRST_SET(n) (4 + (n))
-#define PBA_SLVRST_IN_PROG(n) (0x8 >> (n))
-
-/// The default timeout for pba_slave_reset().
-///
-/// Currently the procedure pba_slave_reset() is thought to be an
-/// initialization-only and/or lab-only procedure, so this long polling
-/// timeout is not a problem.
-#ifndef PBA_SLAVE_RESET_TIMEOUT
-    #define PBA_SLAVE_RESET_TIMEOUT SSX_MICROSECONDS(100)
-#endif
-
-
 // PBA Error/Panic codes
 
 #define PBA_SCOM_ERROR1                    0x00722001
@@ -306,7 +221,7 @@ typedef struct
 int
 pbax_target_create(PbaxTarget* target,
                    int type, int scope, int queue,
-                   int node, int chip_or_group);
+                   int node, int chip_or_group, int cnt);
 
 int
 pbax_configure(int master, int node, int chip, int group_mask);
@@ -317,7 +232,6 @@ _pbax_send(PbaxTarget* target, uint64_t data, SsxInterval timeout);
 int
 pbax_send(PbaxTarget* target, uint64_t data);
 
-
 /// Enable the PBAX send mechanism
 
 static inline void
diff --git a/src/ssx/ppc405/ppc405_exceptions.S b/src/ssx/ppc405/ppc405_exceptions.S
index c8080de..01038a3 100644
--- a/src/ssx/ppc405/ppc405_exceptions.S
+++ b/src/ssx/ppc405/ppc405_exceptions.S
@@ -80,6 +80,12 @@
 __vectors:
 __vectors_0000:
 
+#ifndef SSX_NO_BOOT_VECTOR0
+        // FIXME: This is just a quick hack to get SSX running on simics -- grm
+        .global __ssx_boot
+        b __ssx_boot
+#endif
+
 ### ****************************************************************************
 ### .vectors_0100
 ### ****************************************************************************