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| author | William Bryan <wilbryan@us.ibm.com> | 2015-08-03 12:38:58 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2015-08-03 15:32:27 -0500 |
| commit | 420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3 (patch) | |
| tree | c9f6691eddba39193e39aa769367e1267fb9fc86 /src/ssx | |
| parent | adade8c8ef30ed519322674c762d95663009c5d4 (diff) | |
| download | talos-occ-420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3.tar.gz talos-occ-420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3.zip | |
new ssx and lib files
Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/ssx')
131 files changed, 4065 insertions, 24310 deletions
diff --git a/src/ssx/occhw/Makefile b/src/ssx/occhw/Makefile new file mode 100644 index 0000000..c16da5b --- /dev/null +++ b/src/ssx/occhw/Makefile @@ -0,0 +1,77 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/occhw/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# This Makefile compiles all of the SSX code required for the OCC port +# of SSX. See the "img_defs.mk" file in the top directory. + +#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/ssx +export SUB_OBJDIR = /ssx + +include img_defs.mk +include ssxocchwfiles.mk + +ifeq "$(SSX_TIMER_SUPPORT)" "1" +OCCHW_OBJECTS += ${OCCHW-TIMER-C-SOURCES:.c=.o} ${OCCHW-TIMER-S-SOURCES:.S=.o} +endif + +ifeq "$(SSX_THREAD_SUPPORT)" "1" +OCCHW_OBJECTS += ${OCCHW-THREAD-C-SOURCES:.c=.o} ${OCCHW-THREAD-S-SOURCES:.S=.o} +endif + +ifeq "$(OCCHW_ASYNC_SUPPORT)" "1" +OCCHW_OBJECTS += ${OCCHW-ASYNC-C-SOURCES:.c=.o} ${OCCHW-ASYNC-S-SOURCES:.S=.o} +endif + +OBJS := $(addprefix $(OBJDIR)/, $(OCCHW_OBJECTS)) + +libssx.a: ssx ppc405 ppc32 trace occhw + $(AR) crs $(OBJDIR)/libssx.a $(OBJDIR)/*.o + +.PHONY: clean occhw ssx ppc405 ppc32 trace + +occhw: $(OBJS) + +trace: + $(MAKE) -I $(IMAGE_SRCDIR) -C ../trace + +ssx: + $(MAKE) -I $(IMAGE_SRCDIR) -C ../ssx + +ppc405: + $(MAKE) -I $(IMAGE_SRCDIR) -C ../ppc405 + +ppc32: + $(MAKE) -I $(IMAGE_SRCDIR) -C ../ppc32 + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ssx/pgp/pgp.h b/src/ssx/occhw/occhw.h index fb99e4f..b0ddda8 100755..100644 --- a/src/ssx/pgp/pgp.h +++ b/src/ssx/occhw/occhw.h @@ -1,70 +1,79 @@ -#ifndef __PGP_H__ -#define __PGP_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_H__ +#define __OCCHW_H__ -// $Id: pgp.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp.h -/// \brief The PgP environment for SSX. +/// \file occhw.h +/// \brief The OCCHW environment for SSX. // This is a 'circular' reference in SSX, but included here to simplify PGAS // programming. -#ifndef CHIP_PGP -#define CHIP_PGP +#ifndef HWMACRO_OCC +#define HWMACRO_OCC #include "ppc405.h" #endif // Can't include this here due to ordering issues. It's included in // ppc405_irq.h. -// #include "pgp_irq.h" +// #include "occhw_irq.h" // Required for MMU Map declarations #include "ppc405_mmu.h" -#include "pgp_common.h" -#include "pgp_core.h" -#include "pgp_trace.h" -#include "pgp_ocb.h" -#include "pgp_pba.h" -#include "pgp_pore.h" -#include "pgp_pmc.h" -#include "pgp_sramctl.h" -#include "pgp_vrm.h" -#include "pgp_id.h" -#include "pgp_centaur.h" +#include "occhw_common.h" +#include "occhw_core.h" +#include "occhw_ocb.h" +#include "occhw_pba.h" +#include "occhw_scom.h" +#include "occhw_sramctl.h" +//#include "occhw_vrm.h" +#include "occhw_id.h" +//#include "occhw_centaur.h" -#include "pcbs_register_addresses.h" -#include "pcbs_firmware_registers.h" +//#include "pcbs_register_addresses.h" +//#include "pcbs_firmware_registers.h" -#include "tod_register_addresses.h" -#include "tod_firmware_registers.h" +//#include "tod_register_addresses.h" +//#include "tod_firmware_registers.h" -#include "plb_arbiter_register_addresses.h" -#include "plb_arbiter_firmware_registers.h" +//#include "mcs_register_addresses.h" +//#include "mcs_firmware_registers.h" -#include "mcs_register_addresses.h" -#include "mcs_firmware_registers.h" - -#include "centaur_firmware_registers.h" -#include "centaur_register_addresses.h" +//#include "centaur_firmware_registers.h" +//#include "centaur_register_addresses.h" #include "tpc_register_addresses.h" #include "tpc_firmware_registers.h" -#include "oha_register_addresses.h" -#include "oha_firmware_registers.h" - - -// Include other driver headers - -#include "pgp_async.h" - /// \defgroup memory_map Real-mode memory map setup for SRAM-resident applications /// /// Below are the interpretations of the default settings of the real-mode @@ -112,11 +121,11 @@ /// @} -/// PgP always runs from a memory image +/// OCCHW always runs from a memory image #define SSX_RUN_FROM_MEMORY 1 -/// This is the initial value of Cache Control Register 0 (CCR0) for PgP. +/// This is the initial value of Cache Control Register 0 (CCR0) for OCCHW. /// This definition can be overridden by the application. /// /// The default setting: @@ -128,7 +137,7 @@ /// performance evaluation). Non-cacheable regions are not prefetched. /// /// - Gives highest PLB priority to ICU fetches. This setting can be -/// overriden by scan-only dials in the PgP design which force a fixed +/// overriden by scan-only dials in the OCCHW design which force a fixed /// priority on the ICU. /// /// - Sets priority bit 1 to '1' for DCU operations. The DCU sets priority @@ -148,7 +157,7 @@ #ifndef __ASSEMBLER__ -/// \page noncacheable_support Non-cacheable modes for PgP +/// \page noncacheable_support Non-cacheable modes for OCCHW /// /// In order to support evaluation of cache management strategies on /// performance, DMA buffers read/written by DMA devices can be declared as @@ -164,7 +173,7 @@ /// sections are enforced only if PPC405_MMU_SUPPORT is also configured. /// Writethrogh sections are assumed to be read-write. /// -/// PGP_HIGH_MEMORY_LOAD +/// OCCHW_HIGH_MEMORY_LOAD /// /// cacheable : 0xfff8000 - 0xffffffff /// noncacheable : 0xf7f8000 - 0xf7ffffff [cacheable - 128MB] @@ -318,11 +327,11 @@ extern Ppc405MmuMap G_applet1_mmu_map; #endif /* __ASSEMBLER__ */ -// PgP defines a private version of dcache_flush_all() that uses the undefined -// OCI space at 0x80000000; See dcache_flush_all() in pgp_cache.S. +// OCCHW defines a private version of dcache_flush_all() that uses the undefined +// OCI space at 0x20000000; See dcache_flush_all() in occhw_cache.S. #define USE_GENERIC_DCACHE_FLUSH_ALL 0 -#define PGP_FLUSH_ZERO_ADDRESS 0x80000000 -#define PGP_FLUSH_ZERO_DCCR 0x00008000 +#define OCCHW_FLUSH_ZERO_ADDRESS 0x20000000 +#define OCCHW_FLUSH_ZERO_DCCR 0x08000000 -#endif /* __PGP_H__ */ +#endif /* __OCCHW_H__ */ diff --git a/src/ssx/pgp/pgp_async.c b/src/ssx/occhw/occhw_async.c index f9c446f..f0fbbca 100755..100644 --- a/src/ssx/pgp/pgp_async.c +++ b/src/ssx/occhw/occhw_async.c @@ -1,12 +1,34 @@ -// $Id: pgp_async.c,v 1.4 2014/02/14 12:18:05 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_async.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_async.c +/// \file occhw_async.c /// \brief Support for asynchronous request queuing and callback mechanisms /// /// This file implements device drivers for asynchronous requests. The model @@ -74,9 +96,9 @@ /// request using the API async_request_timestamps_get(). /// /// This is largely a generic implementation, designed to reduce code space by -/// allowing the PORE, PBA and OCB drivers to use the same generic data +/// allowing the GPE, PBA and OCB drivers to use the same generic data /// structures and code. This is supported by the 'single-inheritence class -/// hierarchy' described in the comments for pgp_async.h. +/// hierarchy' described in the comments for occhw_async.h. /// /// <b> Request Completion and Callback States </b> /// @@ -126,16 +148,19 @@ /// handling to fast-mode assembler routines. #include "ssx.h" - +#include "occhw_async.h" //////////////////////////////////////////////////////////////////////////// // Global Data //////////////////////////////////////////////////////////////////////////// -/// Queue of deferred callbacks +/// Queue of deferred async callbacks static SsxDeque G_async_callback_queue; +/// Queue of deferred IPC callbacks + +SsxDeque G_ipc_deferred_queue; //////////////////////////////////////////////////////////////////////////// // FFDC @@ -155,18 +180,19 @@ static SsxDeque G_async_callback_queue; void oci_ffdc(OciFfdc* ffdc, int master_id) { - uint32_t pesr_lock_mask; - - ffdc->pearl.value = mfdcr(PLB_PEARL); - ffdc->pesr.value = mfdcr(PLB_PESR); - - pesr_lock_mask = 0x30000000 >> (4 * master_id); - if (ffdc->pesr.value & pesr_lock_mask) { - ffdc->mine = 1; - mtdcr(PLB_PESR, pesr_lock_mask); - } else { - ffdc->mine = 0; - } +// \todo, fix new pib access to dcr registers +// uint32_t oesr_lock_mask; + +// ffdc->oear.value = mfdcr(OCB_OEAR); +// ffdc->oesr.value = mfdcr(OCB_OESR); + +// oesr_lock_mask = 0x30000000 >> (4 * master_id); +// if (ffdc->oesr.value & oesr_lock_mask) { +// ffdc->mine = 1; +// mtdcr(OCB_OESR, oesr_lock_mask); +// } else { +// ffdc->mine = 0; +// } } @@ -294,7 +320,7 @@ async_request_complete(AsyncRequest *request) } ssx_critical_section_exit(&ctx); - ssx_irq_status_set(PGP_IRQ_ASYNC_IPI, 1); + ssx_irq_status_set(OCCHW_IRQ_ASYNC_IPI, 1); } } @@ -757,12 +783,12 @@ async_request_latency(AsyncRequest* request, SsxTimebase* latency) // Dump an AsyncRequest - +#if 0 void async_request_printk(AsyncRequest *request) { printk("----------------------------------------\n"); - printk("-- AsyncRequest @@ %p\n", request); + printk("-- AsyncRequest @ %p\n", request); printk("-- deque = %p\n", &(request->deque)); printk("-- start_time = 0x%016llx\n", request->start_time); printk("-- end_time = 0x%016llx\n", request->end_time); @@ -777,7 +803,7 @@ async_request_printk(AsyncRequest *request) printk("-- options = 0x%04x\n", request->options); printk("----------------------------------------\n"); } - +#endif //////////////////////////////////////////////////////////////////////////// // Callback Queue @@ -855,18 +881,17 @@ void async_callback_handler_full(void *arg, SsxIrqId irq, int priority) { SsxMachineContext ctx; - SsxDeque *queue = (SsxDeque *)arg; AsyncRequest *request; + ipc_msg_t *msg; ssx_irq_disable(irq); + //Check for any async callbacks first do { ssx_critical_section_enter(SSX_CRITICAL, &ctx); - - request = (AsyncRequest *)ssx_deque_pop_front(queue); + request = (AsyncRequest *)ssx_deque_pop_front(&G_async_callback_queue); if (!request) { - ssx_irq_status_clear(irq); break; } @@ -877,6 +902,28 @@ async_callback_handler_full(void *arg, SsxIrqId irq, int priority) } while (1); ssx_critical_section_exit(&ctx); + + //Next, check for any deferred IPC messages + do { + + ssx_critical_section_enter(SSX_CRITICAL, &ctx); + + msg = (ipc_msg_t *)ssx_deque_pop_front(&G_ipc_deferred_queue); + if (!msg) { + ssx_irq_status_clear(irq); + break; + } + + ssx_critical_section_exit(&ctx); + +void ipc_process_msg(ipc_msg_t* msg); + + //handle the command or response message in a noncritical context + ipc_process_msg(msg); + + } while (1); + + ssx_critical_section_exit(&ctx); ssx_irq_enable(irq); } @@ -924,17 +971,18 @@ async_level_handler_setup(SsxIrqHandler handler, void -async_callbacks_initialize(SsxDeque *queue, SsxIrqId irq) +async_callbacks_initialize(SsxIrqId irq) { - ssx_deque_sentinel_create(queue); + ssx_deque_sentinel_create(&G_async_callback_queue); + ssx_deque_sentinel_create(&G_ipc_deferred_queue); async_edge_handler_setup(async_callback_handler, - (void *)queue, + 0, irq, SSX_NONCRITICAL); ssx_irq_enable(irq); } -/// Create all of the PgP asynchronous request structures and install and +/// Create all of the asynchronous request structures and install and /// activate the interrupt handlers. void @@ -943,30 +991,26 @@ async_initialize() // This is the callback queue used e.g. when critical interrupts need to // run non-critical callbacks. - async_callbacks_initialize(&G_async_callback_queue, PGP_IRQ_ASYNC_IPI); + async_callbacks_initialize(OCCHW_IRQ_ASYNC_IPI); - // PORE + async_gpe_initialize(&G_async_gpe_queue0, ASYNC_ENGINE_GPE0); + async_gpe_initialize(&G_async_gpe_queue1, ASYNC_ENGINE_GPE1); + async_gpe_initialize(&G_async_gpe_queue2, ASYNC_ENGINE_GPE2); + async_gpe_initialize(&G_async_gpe_queue3, ASYNC_ENGINE_GPE3); - async_pore_initialize(&G_pore_gpe0_queue, ASYNC_ENGINE_PORE_GPE0); - async_pore_initialize(&G_pore_gpe1_queue, ASYNC_ENGINE_PORE_GPE1); - - -#if CONFIGURE_PTS - // PTS - - async_pts_initialize(&G_pts_gpe0_queue, ASYNC_ENGINE_PORE_GPE0); - async_pts_initialize(&G_pts_gpe1_queue, ASYNC_ENGINE_PORE_GPE1); -#endif + // TODO: add these back in as they are ported to P9 +#if 0 // BCE async_bce_initialize(&G_pba_bcde_queue, ASYNC_ENGINE_BCDE, - PGP_IRQ_PBA_BCDE_ATTN); + OCCHW_IRQ_PBA_BCDE_ATTN); async_bce_initialize(&G_pba_bcue_queue, ASYNC_ENGINE_BCUE, - PGP_IRQ_PBA_BCUE_ATTN); + OCCHW_IRQ_PBA_BCUE_ATTN); +#endif // OCB @@ -988,6 +1032,12 @@ async_initialize() OCB_READ2_LENGTH, OCB_READ2_PROTOCOL); + async_ocb_initialize(&(G_ocb_read_queue[3]), + ASYNC_ENGINE_OCB_PUSH3, + G_ocb_read3_buffer, + OCB_READ3_LENGTH, + OCB_READ3_PROTOCOL); + async_ocb_initialize(&(G_ocb_write_queue[0]), ASYNC_ENGINE_OCB_PULL0, G_ocb_write0_buffer, @@ -1006,19 +1056,27 @@ async_initialize() OCB_WRITE2_LENGTH, OCB_WRITE2_PROTOCOL); + async_ocb_initialize(&(G_ocb_write_queue[3]), + ASYNC_ENGINE_OCB_PULL3, + G_ocb_write3_buffer, + OCB_WRITE3_LENGTH, + OCB_WRITE3_PROTOCOL); + +#if 0 // PBAX async_pbax_initialize(&G_pbax_read_queue[0], ASYNC_ENGINE_PBAX_PUSH0, - PGP_IRQ_PBA_OCC_PUSH0, + OCCHW_IRQ_PBAX_OCC_PUSH0, G_pbax_read0_buffer, PBAX_READ0_LENGTH, PBAX_READ0_PROTOCOL); async_pbax_initialize(&G_pbax_read_queue[1], ASYNC_ENGINE_PBAX_PUSH1, - PGP_IRQ_PBA_OCC_PUSH1, + OCCHW_IRQ_PBAX_OCC_PUSH1, G_pbax_read1_buffer, PBAX_READ1_LENGTH, PBAX_READ1_PROTOCOL); +#endif } diff --git a/src/ssx/pgp/pgp_async.h b/src/ssx/occhw/occhw_async.h index ecd3ae2..e2bbf0a 100755..100644 --- a/src/ssx/pgp/pgp_async.h +++ b/src/ssx/occhw/occhw_async.h @@ -1,15 +1,37 @@ -#ifndef __PGP_ASYNC_H__ -#define __PGP_ASYNC_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_async.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_ASYNC_H__ +#define __OCCHW_ASYNC_H__ -// $Id: pgp_async.h,v 1.2 2014/02/03 01:30:34 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_async.h +/// \file occhw_async.h /// \brief Support for asynchronous request/callback mechanisms /// /// The data structures defined here provide a 'C' implementation of multiple @@ -17,53 +39,52 @@ /// 'superclass' as the initial element of the structure, allowing subclass /// pointers to be safely cast to the superclass, and vice-versa (assuming /// that the subclass is known). One benefit of this approach is that it -/// allows code sharing between requests targeting PORE-GPE, PORE-SW, +/// allows code sharing between requests targeting GPE, /// PBA-BCDE, PBA-BCUE and the deferred callback queue. /// /// The 'class hierarchy' : /// /// SsxDeque /// AsyncRequest -/// PoreRequest -/// PoreFixed -/// PoreFlex +/// GpeRequest /// BceRequest /// OcbRequest /// Pbaxrequest /// /// AsyncQueue -/// PoreQueue +/// GpeQueue /// BceQueue /// OcbQueue /// PbaxQueue /// -/// \bug We may need to redo how we start jobs since writing the EXE-TRIGGER -/// does not guarantee a restart from a good state, although if we get our CCB -/// request through it will. +#include "ipc_async_cmd.h" +#include "occhw_xir_dump.h" -// PgP Execution engines for the purposes of the generic request mechanism. +// OCCHW Execution engines for the purposes of the generic request mechanism. #define ASYNC_ENGINE_ANONYMOUS 0x00 -#define ASYNC_ENGINE_PORE 0x10 -#define ASYNC_ENGINE_PORE_GPE0 0x10 -#define ASYNC_ENGINE_PORE_GPE1 0x11 -#define ASYNC_ENGINE_PORE_SLW 0x12 +#define ASYNC_ENGINE_GPE 0x10 +#define ASYNC_ENGINE_GPE0 0x10 +#define ASYNC_ENGINE_GPE1 0x11 +#define ASYNC_ENGINE_GPE2 0x12 +#define ASYNC_ENGINE_GPE3 0x13 #define ASYNC_ENGINE_BCE 0x20 #define ASYNC_ENGINE_BCDE 0x20 #define ASYNC_ENGINE_BCUE 0x21 -// Indirect channel 3 no longer supports push/pull queues and they have been -// removed. +// Indirect channel 3 is now back online to support push/pull queues in P9. #define ASYNC_ENGINE_OCB 0x40 #define ASYNC_ENGINE_OCB_PUSH0 0x41 #define ASYNC_ENGINE_OCB_PUSH1 0x42 #define ASYNC_ENGINE_OCB_PUSH2 0x43 +#define ASYNC_ENGINE_OCB_PUSH3 0x44 #define ASYNC_ENGINE_OCB_PULL0 0x45 #define ASYNC_ENGINE_OCB_PULL1 0x46 #define ASYNC_ENGINE_OCB_PULL2 0x47 +#define ASYNC_ENGINE_OCB_PULL3 0x48 #define ASYNC_ENGINE_PBAX 0x80 #define ASYNC_ENGINE_PBAX_PUSH0 0x81 @@ -94,17 +115,17 @@ typedef uint8_t AsyncEngine; typedef struct { - /// PLB arbiter Error Address Register Low + /// PLB arbiter Error Address Register /// /// This is the address of the last PLB timeout or other error recorded in - /// the PEARL. This is an error for the unit in question only if the + /// the PEAR. This is an error for the unit in question only if the /// \a mine data member is non-zero. - plb_pearl_t pearl; + ocb_oear_t oear; /// PLB arbiter Error Status Register /// /// The PESR at the time of the error. - plb_pesr_t pesr; + ocb_oesr_t oesr; /// Is the unit in question responsible for the error address recorded in /// the PEARL? @@ -493,160 +514,66 @@ async_level_handler_setup(SsxIrqHandler handler, int polarity); void -async_callbacks_initialize(SsxDeque *queue, SsxIrqId irq); +async_callbacks_initialize(SsxIrqId irq); #endif // __ASSEMBLER__ - //////////////////////////////////////////////////////////////////////////// -// PoreRequest +// GpeRequest //////////////////////////////////////////////////////////////////////////// #ifndef __ASSEMBLER__ -struct PoreQueue; - -/// PORE FFDC -/// -/// The PORE engine has 208 bytes of programmer-visible state - too much to -/// allocate in every PoreRequest on the off-chance that a request may fail. -/// This PoreFfdc structure is designed to capture a reasonble amount of data -/// in the case of failure of a PoreFlex request, which does not include any -/// PORE error handlers. This structure is currently 48 bytes. -/// -/// The most common recoverable errors are expected to be erroneous PIB -/// responses from deconfigured (garded) cores. These will show up as Error -/// event 0 and can be debugged from the debug registers. We also include the -/// instruction buffer registers to help debug error 2 - instruction -/// fetch/decode errors. -/// -/// To get a full picture in the event of OCI execution phase errors (error -/// 1), the PORE memory-space address registers are captured. We also capture -/// FFDC from the PLB arbiter, which can be used to debug illegal address-type -/// problems. - -typedef struct { - - /// FFDC from the PLB (OCI) arbiter - OciFfdc oci_ffdc; - - /// PORE Debug Registers - /// - /// - [0] Contains PIB address and PIB return code - /// - [1] Contains failing PC and error status bits - uint64_t debug[2]; - - /// PORE Memory-space address registers. - /// - /// We only save the low-order 32 bits of each - the high-order bits are - /// implied/ignored for OCI-attached engines. If OCC managed the SBE then - /// we would require the high-order bits in an FFDC dump. - uint32_t address[2]; - - /// PORE Instruction buffer 0-2 - /// - /// - [0] Contains the opcode and register/short operands - /// - [1:2] Contain the 64-bit immediate - uint32_t ibuf[3]; - -} PoreFfdc; - +struct GpeQueue; -/// A PORE branch immediate address instruction, used in PORE jump tables. +/// GPE FFDC typedef struct { - uint32_t word[3]; -} PoreBraia; - - -void -pore_braia_create(PoreBraia* instr, uint32_t address); + uint32_t func_id; + int32_t ipc_rc; + int xir_dump_rc; + occhw_xir_dump_t xir_dump; +} GpeFfdc; - -/// A request to run a PORE program +/// A request to run a GPE command /// -/// A PORE request extends the generic AsyncRequest request by the addition of -/// several fields required to be set up in the engine before the job is run, -/// including the program parameter for the routine. The PoreRequest is an -/// internal class that is re-typed to create the PoreFixed and PoreFlex -/// request classes, which differ only slightly in their behavior. +/// A GPE request extends the generic AsyncRequest request by the addition of +/// several fields required for running a job on a GPE +/// including the program parameter for the routine. /// /// As long as the request is known to be idle the application is free to -/// change the \a parameter value between executions of the PORE program, +/// change the \a parameter value between executions of the GPE command, /// e.g., to do ping-pong buffer management. None of the other fields should /// be directly modified by the application. typedef struct { /// The generic request - AsyncRequest request; - - /// Error information - PoreFfdc ffdc; - - /// The PORE Jump Table - PoreBraia* table; - - /// The initial value of the high-order 32 bits of the ERROR_MASK register - uint32_t error_mask; - - /// The entry point address of the routine. - /// - /// For PoreFlex this entry point will be non-0 and will be inserted into - /// D0, as PoreFlex jobs are kicked off by BRAD. For PoreFixed this - /// parameter will be zero and ignored. - uint32_t entry_point; - - /// The single parameter of the PORE program - EXE-Trigger[32:63] - uint32_t parameter; - - /// The high-order 32 bits of EXE-Trigger used to kick off the program. - /// - /// For PoreFlex this field is always 0, as PoreFlex only uses table entry - /// 0 which contains a BRAD. For PoreFixed this encodes the address of - /// the table entry to kick off. - uint32_t exe_trigger; + AsyncRequest request; -} PoreRequest; + /// Error information collected by the 405 + GpeFfdc ffdc; + /// The targeted IPC function ID for this request + ipc_func_enum_t targeted_func_id; -typedef PoreRequest PoreFlex; + /// A pointer to any command data that is used by the GPE or + /// returned by the GPE. + void* cmd_data; -typedef PoreRequest PoreFixed; +} GpeRequest; int -pore_run_method(AsyncRequest* request); +gpe_run_method(AsyncRequest* request); int -pore_error_method(AsyncRequest* request); - -#endif /* __ASSEMBLER__ */ - -/// The (fixed) number of PORE jump table error handler slots -#define PORE_ERROR_SLOTS 5 - -/// The maximum number of PORE jump table EXE_TRIGGER slots -#define PORE_TRIGGER_SLOTS 16 - -/// Compute the address of error handler BRAIA entry n of a PORE branch table -#define PORE_ERROR_BRANCH(table, n) ((table) + ((n) * 12)) - -/// Compute the address of entry point BRAIA entry n of a PORE branch table -#define PORE_ENTRY_BRANCH(table, n) \ - ((table) + (((PORE_ERROR_SLOTS) + (n)) * 12)) - - -//////////////////////////////////////////////////////////////////////////// -// PoreFlex -//////////////////////////////////////////////////////////////////////////// - -#ifndef __ASSEMBLER__ +gpe_error_method(AsyncRequest* request); int -pore_flex_create(PoreFlex* request, - struct PoreQueue* queue, - PoreEntryPoint entry_point, - uint32_t parameter, +gpe_request_create(GpeRequest* request, + struct GpeQueue* queue, + ipc_func_enum_t func_id, + void* cmd_data, SsxInterval timeout, AsyncRequestCallback callback, void *arg, @@ -655,85 +582,41 @@ pore_flex_create(PoreFlex* request, /// See async_request_schedule() for documentation. static inline int -pore_flex_schedule(PoreFlex* request) -{ - return async_request_schedule((AsyncRequest *)request); -} - -#endif /* __ASSEMBLER__ */ - - -//////////////////////////////////////////////////////////////////////////// -// PoreFixed -//////////////////////////////////////////////////////////////////////////// - -#ifndef __ASSEMBLER__ - -int -pore_fixed_create(PoreFixed *request, - struct PoreQueue *queue, - PoreBraia* table, - uint32_t error_mask, - int start_vector, - uint32_t parameter, - SsxInterval timeout, - AsyncRequestCallback callback, - void *arg, - int options); - -/// See async_request_schedule() for documentation. -static inline int -pore_fixed_schedule(PoreFixed *request) +gpe_request_schedule(GpeRequest* request) { return async_request_schedule((AsyncRequest *)request); } -#endif /* __ASSEMBLER__ */ - - //////////////////////////////////////////////////////////////////////////// -// PoreQueue +// GpeQueue //////////////////////////////////////////////////////////////////////////// -#ifndef __ASSEMBLER__ -/// A PORE engine queue +/// A GPE engine queue /// -/// A PORE queue consists of a generic AsyncQueue to manage jobs on the -/// engine, the OCI base address of the PORE control register space of the -/// engine, and interrupt information. +/// A GPE queue consists of a generic AsyncQueue to manage jobs on the +/// engine. -typedef struct PoreQueue { +typedef struct GpeQueue { /// The generic request queue - the "base class" AsyncQueue queue; - /// The base address of the OCI control register space for this engine. - uint32_t oci_base; + /// The IPC target_id + uint8_t ipc_target_id; - /// The IRQ associated with normal completion on the engine - /// - /// \todo Due to header reference ordering we can't define this as SsxIrqId - uint8_t irq; + /// Pointer to an IPC command message + ipc_async_cmd_t *ipc_cmd; - /// The IRQ associated with error completion on the engine - /// - /// \todo Due to header reference ordering we can't define this as SsxIrqId - uint8_t error_irq; - - /// The OCI master number of this engine; See pore_error_method() - uint8_t oci_master; - -} PoreQueue; +} GpeQueue; int -pore_queue_create(PoreQueue *queue, +gpe_queue_create(GpeQueue *queue, int engine); #endif /* ASSEMBLER */ - //////////////////////////////////////////////////////////////////////////// // PBA FFDC Structures //////////////////////////////////////////////////////////////////////////// @@ -1102,7 +985,7 @@ pbax_request_schedule(PbaxRequest *request); //////////////////////////////////////////////////////////////////////////// // NB: This assignment ordering is assumed by static initialization code in -// pgp_async.c - these constants are used as array indices. +// occhw_async.c - these constants are used as array indices. #define PBAX_ENGINE_PUSH0 0 #define PBAX_ENGINE_PUSH1 1 @@ -1339,7 +1222,7 @@ ocb_request_schedule(OcbRequest *request); //////////////////////////////////////////////////////////////////////////// // NB: This assignment ordering is assumed by static initialization code in -// pgp_async.c - these constants are used as array indices. The code also +// occhw_async.c - these constants are used as array indices. The code also // assumes this ordering for the access of G_ocb_ocbsesn[], and for // determining whether the engine is a PUSH or PULL queue. // Note: push/pull queues for channel 3 have been deleted @@ -1350,8 +1233,10 @@ ocb_request_schedule(OcbRequest *request); #define OCB_ENGINE_PULL1 3 #define OCB_ENGINE_PUSH2 4 #define OCB_ENGINE_PULL2 5 +#define OCB_ENGINE_PUSH3 6 +#define OCB_ENGINE_PULL3 7 -#define OCB_ENGINES 6 +#define OCB_ENGINES 8 #ifndef __ASSEMBLER__ @@ -1411,13 +1296,8 @@ ocb_queue_create(OcbQueue *queue, #define ASYNC_INVALID_OBJECT_PBAX_QUEUE 0x00279606 #define ASYNC_INVALID_OBJECT_BCE_REQUEST 0x00279607 #define ASYNC_INVALID_OBJECT_BCE_QUEUE 0x00279608 -#define ASYNC_INVALID_OBJECT_PORE_REQUEST 0x00279609 -#define ASYNC_INVALID_OBJECT_PORE_QUEUE 0x0027960a -#define ASYNC_INVALID_OBJECT_PTS_REQUEST 0x0027960b -#define ASYNC_INVALID_OBJECT_PTS_THREAD 0x0027960c -#define ASYNC_INVALID_OBJECT_PTS_QUEUE 0x0027960d -#define ASYNC_INVALID_OBJECT_PTS_START 0x0027960e -#define ASYNC_INVALID_OBJECT_PTS_SCHEDULE 0x0027960f +#define ASYNC_INVALID_OBJECT_GPE_REQUEST 0x00279609 +#define ASYNC_INVALID_OBJECT_GPE_QUEUE 0x0027960a #define ASYNC_INVALID_ARGUMENT 0x00279610 #define ASYNC_INVALID_ARGUMENT_OCB_READ 0x00279611 #define ASYNC_INVALID_ARGUMENT_OCB_WRITE 0x00279612 @@ -1430,19 +1310,15 @@ ocb_queue_create(OcbQueue *queue, #define ASYNC_INVALID_ARGUMENT_PBAX_REQUEST 0x00279619 #define ASYNC_INVALID_ARGUMENT_PBAX_SCHEDULE 0x0027961a #define ASYNC_INVALID_ARGUMENT_PBAX_QUEUE 0x0027961b -#define ASYNC_INVALID_ARGUMENT_PORE_REQUEST 0x0027961c -#define ASYNC_INVALID_ARGUMENT_PTS_THREAD 0x0027961d -#define ASYNC_INVALID_ARGUMENT_PTS_REQUEST 0x0027961e +#define ASYNC_INVALID_ARGUMENT_GPE_REQUEST 0x0027961c #define ASYNC_INVALID_ENGINE_OCB 0x0027961f #define ASYNC_INVALID_ENGINE_PBAX 0x00279620 #define ASYNC_INVALID_ENGINE_BCE 0x00279621 -#define ASYNC_INVALID_ENGINE_PORE 0x00279622 -#define ASYNC_INVALID_ENGINE_PTS 0x00279623 +#define ASYNC_INVALID_ENGINE_GPE 0x00279622 #define ASYNC_INVALID_OPTIONS 0x00279624 #define ASYNC_INVALID_ASSIGNMENT 0x00279625 #define ASYNC_CALLBACK_PROTOCOL_UNSPECIFIED 0x00279626 #define ASYNC_REQUEST_NOT_IDLE 0x00279627 -#define ASYNC_REQUEST_NOT_IDLE_PTS 0x00279628 #define ASYNC_REQUEST_COMPLETE 0x00279629 #define ASYNC_INVALID_TIMESTAMPS 0x0027962a #define ASYNC_OCB_ERROR_READ_OLD 0x0027962b @@ -1452,11 +1328,10 @@ ocb_queue_create(OcbQueue *queue, #define ASYNC_PBAX_ERROR_OLD 0x0027962f #define ASYNC_PBAX_ERROR_NEW 0x00279630 #define ASYNC_REQUEST_NOT_COMPLETE 0x00279631 -#define ASYNC_REQUEST_NOT_COMPLETE_PTS 0x00279632 // Panic codes -#define ASYNC_PORE_FIXED_INVARIANT 0x00279633 +#define ASYNC_GPE_FIXED_INVARIANT 0x00279633 #define ASYNC_PHANTOM_INTERRUPT 0x00279634 #define ASYNC_PHANTOM_INTERRUPT_OCB 0x00279635 #define ASYNC_PHANTOM_INTERRUPT_BCE 0x00279636 @@ -1465,9 +1340,7 @@ ocb_queue_create(OcbQueue *queue, #define ASYNC_TIMEOUT_BUG 0x00279639 #define ASYNC_INVALID_STATE 0x0027963a #define ASYNC_PHANTOM_ERROR 0x0027963b -#define ASYNC_BUG_PORE_AT_CREATE 0x0027963c -#define ASYNC_BUG_PTS_AT_CREATE 0x0027963d -#define ASYNC_BUG_PTS_AT_RUN 0x0027963e +#define ASYNC_BUG_GPE_AT_CREATE 0x0027963c //////////////////////////////////////////////////////////////////////////// // Global Data and Constants @@ -1475,31 +1348,12 @@ ocb_queue_create(OcbQueue *queue, #ifndef __ASSEMBLER__ -// PORE Queues - -extern PoreQueue G_pore_gpe0_queue; -extern PoreQueue G_pore_gpe1_queue; -extern PoreQueue G_pore_slw_queue; - -/// Define a PORE branch table. All error slots are always defined, but space -/// can be saved if not all of the entry points are required. -#define PORE_TABLE(var, slots) PoreBraia var[PORE_ERROR_SLOTS + (slots)] - - -// PTS Queues -// -// These queues are only defined if CONFIGURE_PTS is non-zero. CONFIGURE_PTS -// is 0 by default. - -#ifndef CONFIGURE_PTS -#define CONFIGURE_PTS 0 -#endif +// GPE Queues -#if CONFIGURE_PTS -#include "pgp_async_pts.h" -extern PtsQueue G_pts_gpe0_queue; -extern PtsQueue G_pts_gpe1_queue; -#endif +extern GpeQueue G_async_gpe_queue0; +extern GpeQueue G_async_gpe_queue1; +extern GpeQueue G_async_gpe_queue2; +extern GpeQueue G_async_gpe_queue3; // OCB Queues and FFDC @@ -1533,18 +1387,22 @@ extern PtsQueue G_pts_gpe1_queue; #define OCB_READ0_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_READ1_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_READ2_LENGTH OCB_PUSH_PULL_LENGTH_MAX +#define OCB_READ3_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_WRITE0_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_WRITE1_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_WRITE2_LENGTH OCB_PUSH_PULL_LENGTH_MAX +#define OCB_WRITE3_LENGTH OCB_PUSH_PULL_LENGTH_MAX #define OCB_READ0_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE #define OCB_READ1_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE #define OCB_READ2_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE +#define OCB_READ3_PROTOCOL OCB_INTERRUPT_PROTOCOL_AGGRESSIVE #define OCB_WRITE0_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY #define OCB_WRITE1_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY #define OCB_WRITE2_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY +#define OCB_WRITE3_PROTOCOL OCB_INTERRUPT_PROTOCOL_LAZY extern OcbUnitFfdc G_ocb_ffdc; @@ -1554,10 +1412,12 @@ extern OcbQueue G_ocb_write_queue[]; extern uint64_t G_ocb_read0_buffer[]; extern uint64_t G_ocb_read1_buffer[]; extern uint64_t G_ocb_read2_buffer[]; +extern uint64_t G_ocb_read3_buffer[]; extern uint64_t G_ocb_write0_buffer[]; extern uint64_t G_ocb_write1_buffer[]; extern uint64_t G_ocb_write2_buffer[]; +extern uint64_t G_ocb_write3_buffer[]; // PBA Queues @@ -1630,7 +1490,7 @@ extern uint64_t G_pbax_read1_buffer[]; // Initialization APIs void -async_pore_initialize(PoreQueue *queue, int engine); +async_gpe_initialize(GpeQueue *queue, int engine); void async_bce_initialize(BceQueue *queue, int engine, SsxIrqId irq); @@ -1651,4 +1511,4 @@ async_initialize(); #endif /* __ASSEMBLER__ */ -#endif /* __PGP_ASYNC_H__ */ +#endif /* __OCCHW_ASYNC_H__ */ diff --git a/src/ssx/occhw/occhw_async_gpe.c b/src/ssx/occhw/occhw_async_gpe.c new file mode 100644 index 0000000..524411d --- /dev/null +++ b/src/ssx/occhw/occhw_async_gpe.c @@ -0,0 +1,309 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_async_gpe.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2015 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file occhw_async_gpe.c +/// \brief Async driver code for GPE + +#include "ssx.h" +#include "occhw_async.h" + +/////////////////////////////////////////////////////////////////////////////// +/// Global Data +/////////////////////////////////////////////////////////////////////////////// +#define ASYNC_NUM_GPE_QUEUES 4 +#define ASYNC_ENG2GPE(eng) ((eng) & 0x0000000f) + +// The GPE queue objects. +GpeQueue G_async_gpe_queue0; +GpeQueue G_async_gpe_queue1; +GpeQueue G_async_gpe_queue2; +GpeQueue G_async_gpe_queue3; + +// Each GPE queue gets one IPC command. These are allocated separately so that +// they can be allocated in a non-cacheable section. +ipc_async_cmd_t G_async_ipc_cmd[ASYNC_NUM_GPE_QUEUES] SECTION_ATTRIBUTE(".noncacheable"); + +/////////////////////////////////////////////////////////////////////////////// +/// GpeQueue +/////////////////////////////////////////////////////////////////////////////// + +/// Create (initialize) a GpeQueue +/// +/// \param queue An uninitialized or otherwise idle GpeeQueue +/// +/// \param engine The identifier of a GPE engine associated with this queue. +/// +/// This API initializes the GpeQueue structure. +/// +/// \retval 0 Success +/// +/// \retval -ASYNC_INVALID_OBJECT_PORE_QUEUE The \a queue was NULL (0). +/// +/// \retval -ASYNC_INVALID_ENGINE_GPE The \a engine is not a (valid) +/// GPE engine. + +int +gpe_queue_create(GpeQueue *queue, int engine) +{ + if (SSX_ERROR_CHECK_API) { + SSX_ERROR_IF(queue == 0, ASYNC_INVALID_OBJECT_GPE_QUEUE); + SSX_ERROR_IF(!(engine & ASYNC_ENGINE_GPE), ASYNC_INVALID_ENGINE_GPE); + SSX_ERROR_IF((ASYNC_ENG2GPE(engine) >= ASYNC_NUM_GPE_QUEUES), ASYNC_INVALID_ENGINE_GPE); + } + + //initialize the base async queue + async_queue_create(&queue->queue, engine); + + //assign an IPC message to be used with the queue + //This is kept as a pointer so that the message can kept in a + //cache-inhibited section of SRAM. + queue->ipc_cmd = &G_async_ipc_cmd[ASYNC_ENG2GPE(engine)]; + + //The IPC target ID that all messages on this queue will be sent to + queue->ipc_target_id = ASYNC_ENG2GPE(engine); + + return 0; +} + +//////////////////////////////////////////////////////////////////////////// +// async_ipc_callback +//////////////////////////////////////////////////////////////////////////// + +/// Internal function that handles aysnc IPC command responses + +void +gpe_async_handler(ipc_msg_t* rsp, void* arg) +{ + // check for errors detected by the GPE code + if(rsp->ipc_rc != IPC_RC_SUCCESS) + { + //calls gpe_error_method before calling async_handler + async_error_handler((AsyncQueue *)arg, ASYNC_REQUEST_STATE_FAILED); + } + else + { + + //handle async callbacks and process the next gpe request in the queue + //(if any) + async_handler((AsyncQueue *) arg); + } +} + +//////////////////////////////////////////////////////////////////////////// +// GpeRequest +//////////////////////////////////////////////////////////////////////////// + +/// Create (initialize) the GpeRequest base class +/// +/// \param request An uninitialized or otherwise idle GpeRequest. +/// +/// \param queue An initialized GpeQueue. +/// +/// \param func_id The IPC function ID of the GPE command. +/// +/// \param cmd_data A pointer to command-specific input and output data. +/// +/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request +/// will be governed by a private watchdog timer that will cancel a queued job +/// or kill a running job if the hardware operation does not complete before +/// it times out. +/// +/// \param callback The callback to execute when the GPE command completes, +/// or NULL (0) to indicate no callback. +/// +/// \param arg The parameter to the callback routine; ignored if the \a +/// callback is NULL. +/// +/// \param options Options to control request priority and callback context. +/// +/// This routine has no way to know if the GpeRequest structure is currently +/// in use, so this API should only be called on uninitialized or otherwise +/// idle GpeRequest structures. +/// +/// \retval 0 Success +/// +/// \retval -ASYNC_INVALID_OBJECT_GPE_REQUEST The \a request was NULL (0) +/// or the \a queue was NULL (0) or not a GpeQueue. +/// +/// \retval IPC_RC_INVALID_FUNC_ID The func_id has an invalid target id +/// for the specified GPE queue. +/// +/// See async_request_create() for other errors that may be returned by this +/// call. + +int +gpe_request_create(GpeRequest *request, + GpeQueue *queue, + ipc_func_enum_t func_id, + void* cmd_data, + SsxInterval timeout, + AsyncRequestCallback callback, + void *arg, + int options) +{ + AsyncQueue *async_queue = (AsyncQueue *)queue; + uint32_t targeted_func_id; + int rc; + + if (SSX_ERROR_CHECK_API) { + SSX_ERROR_IF(!(async_queue->engine & ASYNC_ENGINE_GPE), + ASYNC_INVALID_OBJECT_GPE_REQUEST); + } + + //initialize the base async request + rc = async_request_create(&(request->request), + async_queue, + gpe_run_method, + gpe_error_method, + timeout, + callback, + arg, + options); + if(!rc) + { + + //If this is a multi-target function ID we need to set the target id. + if(IPC_FUNCID_IS_MT(func_id)) + { + //This macro will set the target to an invalid target id if this + //function id is not a multi-target function ID and this condition + //will be caught when we check that the target id for the request + //matches the target id for the queue. + targeted_func_id = IPC_SET_MT_TARGET(func_id, queue->ipc_target_id); + } + else + { + //single target function IDs already have a target + targeted_func_id = func_id; + } + + //check that target id of the command matches the target id + //of the queue. + if (IPC_GET_TARGET_ID(targeted_func_id) != queue->ipc_target_id) + { + rc = IPC_RC_INVALID_FUNC_ID; + } + else + { + //initialize data that will be used when sending the command + request->cmd_data = cmd_data; + request->targeted_func_id = targeted_func_id; + } + } + + return rc; +} + + +// Start a GpeRequest on a GPE +// +// \param async_request A GpeRequest upcast to an AsyncRequest. +// +// This is an internal API. +// +// This routine sends an async_request to a GPE. +// + +int +gpe_run_method(AsyncRequest *async_request) +{ + GpeQueue *queue = (GpeQueue*)(async_request->queue); + GpeRequest *request = (GpeRequest*)async_request; + ipc_async_cmd_t *ipc_cmd = queue->ipc_cmd; + int rc; + + //Initialize the IPC command message + ipc_init_msg(&ipc_cmd->cmd, + request->targeted_func_id, + gpe_async_handler, + queue); + ipc_cmd->cmd_data = request->cmd_data; + + //Send the IPC command + rc = ipc_send_cmd(&ipc_cmd->cmd); + + //If there's an error in the send, collect ffdc and mark it as + //having failed. + if(rc) + { + gpe_error_method(async_request); + async_request->completion_state = ASYNC_REQUEST_STATE_FAILED; + rc = -ASYNC_REQUEST_COMPLETE; + } + + return rc; +} + + +// GPE FFDC collection +// +// \param async_request A GpeRequest upcast to an AsyncRequest +// +// This is an internal API, called from the async base code when an async +// request times out. +// +// GPE async error handling procedure: +// +// - Collect FFDC from the failing engine +// +// Currently all GPE errors are treated as recoverable + + +int +gpe_error_method(AsyncRequest *async_request) +{ + GpeQueue *queue = (GpeQueue*)(async_request->queue); + GpeRequest *request = (GpeRequest*)async_request; + + // Collect data that could explain why a GPE command + // couldn't be sent or timed out on the response and save it + // in the ffdc fields + + //retrieve IPC data + request->ffdc.func_id = queue->ipc_cmd->cmd.func_id.word32; + request->ffdc.ipc_rc = queue->ipc_cmd->cmd.ipc_rc; + + //retrieve XIR data + request->ffdc.xir_dump_rc = + occhw_xir_dump(queue->ipc_target_id, &request->ffdc.xir_dump); + + return 0; +} + + +//////////////////////////////////////////////////////////////////////////// +// Initialization +//////////////////////////////////////////////////////////////////////////// + +void +async_gpe_initialize(GpeQueue *queue,int engine) +{ + gpe_queue_create(queue, engine); +} diff --git a/src/ssx/pgp/pgp_async_ocb.c b/src/ssx/occhw/occhw_async_ocb.c index b9ef4b8..1a0abef 100755..100644 --- a/src/ssx/pgp/pgp_async_ocb.c +++ b/src/ssx/occhw/occhw_async_ocb.c @@ -1,16 +1,38 @@ -// $Id: pgp_async_ocb.c,v 1.2 2014/02/03 01:30:34 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_ocb.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_async_ocb.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_async_ocb.c +/// \file occhw_async_ocb.c /// \brief Async driver code for OCB #include "ssx.h" - +#include "occhw_async.h" //////////////////////////////////////////////////////////////////////////// // Global Data @@ -54,10 +76,12 @@ OcbQueue G_ocb_write_queue[OCB_INDIRECT_CHANNELS]; OCB_CQ_READ_BUFFER(G_ocb_read0_buffer, OCB_READ0_LENGTH); OCB_CQ_READ_BUFFER(G_ocb_read1_buffer, OCB_READ1_LENGTH); OCB_CQ_READ_BUFFER(G_ocb_read2_buffer, OCB_READ2_LENGTH); +OCB_CQ_READ_BUFFER(G_ocb_read3_buffer, OCB_READ3_LENGTH); OCB_CQ_WRITE_BUFFER(G_ocb_write0_buffer, OCB_WRITE0_LENGTH); OCB_CQ_WRITE_BUFFER(G_ocb_write1_buffer, OCB_WRITE1_LENGTH); OCB_CQ_WRITE_BUFFER(G_ocb_write2_buffer, OCB_WRITE2_LENGTH); +OCB_CQ_WRITE_BUFFER(G_ocb_write3_buffer, OCB_WRITE3_LENGTH); //////////////////////////////////////////////////////////////////////////// @@ -72,14 +96,16 @@ OCB_CQ_WRITE_BUFFER(G_ocb_write2_buffer, OCB_WRITE2_LENGTH); static const SsxAddress G_ocb_ocbsxcsn[OCB_ENGINES] = {OCB_OCBSHCS0, OCB_OCBSLCS0, OCB_OCBSHCS1, OCB_OCBSLCS1, - OCB_OCBSHCS2, OCB_OCBSLCS2}; + OCB_OCBSHCS2, OCB_OCBSLCS2, + OCB_OCBSHCS3, OCB_OCBSLCS3}; /// OCB Stream Push/Pull Base Register addresses static const SsxAddress G_ocb_ocbsxbrn[OCB_ENGINES] = {OCB_OCBSHBR0, OCB_OCBSLBR0, OCB_OCBSHBR1, OCB_OCBSLBR1, - OCB_OCBSHBR2, OCB_OCBSLBR2}; + OCB_OCBSHBR2, OCB_OCBSLBR2, + OCB_OCBSHBR3, OCB_OCBSLBR3}; /// OCB Stream Push/Pull Increment Register addresses @@ -87,13 +113,14 @@ static const SsxAddress G_ocb_ocbsxbrn[OCB_ENGINES] = static const SsxAddress G_ocb_ocbsxin[OCB_ENGINES] = {OCB_OCBSHI0, OCB_OCBSLI0, OCB_OCBSHI1, OCB_OCBSLI1, - OCB_OCBSHI2, OCB_OCBSLI2}; + OCB_OCBSHI2, OCB_OCBSLI2, + OCB_OCBSHI3, OCB_OCBSLI3}; /// OCB Stream Error Status; There is only one register per OCB channel const SsxAddress G_ocb_ocbsesn[OCB_ENGINES / 2] = - {OCB_OCBSES0, OCB_OCBSES1, OCB_OCBSES2}; + {OCB_OCBSES0, OCB_OCBSES1, OCB_OCBSES2, OCB_OCBSES3}; //////////////////////////////////////////////////////////////////////////// @@ -123,6 +150,8 @@ static void ocb_ffdc(int channel) { OcbFfdc* ffdc; + ocb_ocbshcsn_t ocbshcsn; + ocb_ocbslcsn_t ocbslcsn; if (channel < 0) { ffdc = &(G_ocb_ffdc.bridge); @@ -145,10 +174,12 @@ ocb_ffdc(int channel) ffdc->slbr.value = in32(OCB_OCBSLBRN(channel)); ffdc->slcs.value = in32(OCB_OCBSLCSN(channel)); - out32(OCB_OCBSHCSN(channel), - ffdc->shcs.value & ~OCB_OCBSHCSN_PUSH_ENABLE); - out32(OCB_OCBSLCSN(channel), - ffdc->slcs.value & ~OCB_OCBSLCSN_PULL_ENABLE); + ocbshcsn.value = ffdc->shcs.value; + ocbshcsn.fields.push_enable = 0; + out32(OCB_OCBSHCSN(channel), ocbshcsn.value); + ocbslcsn.value = ffdc->slcs.value; + ocbslcsn.fields.pull_enable = 0; + out32(OCB_OCBSLCSN(channel), ocbslcsn.value); } @@ -540,12 +571,14 @@ ocb_request_create(OcbRequest *request, case ASYNC_ENGINE_OCB_PULL0: case ASYNC_ENGINE_OCB_PULL1: case ASYNC_ENGINE_OCB_PULL2: + case ASYNC_ENGINE_OCB_PULL3: run_method = ocb_write_method; break; case ASYNC_ENGINE_OCB_PUSH0: case ASYNC_ENGINE_OCB_PUSH1: case ASYNC_ENGINE_OCB_PUSH2: + case ASYNC_ENGINE_OCB_PUSH3: run_method = ocb_read_method; break; } @@ -766,20 +799,25 @@ ocb_queue_create(OcbQueue *queue, // These are the read engines from OCC's perspective. case ASYNC_ENGINE_OCB_PUSH0: - queue->irq = PGP_IRQ_STRM0_PUSH; + queue->irq = OCCHW_IRQ_STRM0_PUSH; queue->engine = OCB_ENGINE_PUSH0; goto read_engine; case ASYNC_ENGINE_OCB_PUSH1: - queue->irq = PGP_IRQ_STRM1_PUSH; + queue->irq = OCCHW_IRQ_STRM1_PUSH; queue->engine = OCB_ENGINE_PUSH1; goto read_engine; case ASYNC_ENGINE_OCB_PUSH2: - queue->irq = PGP_IRQ_STRM2_PUSH; + queue->irq = OCCHW_IRQ_STRM2_PUSH; queue->engine = OCB_ENGINE_PUSH2; goto read_engine; + case ASYNC_ENGINE_OCB_PUSH3: + queue->irq = OCCHW_IRQ_STRM3_PUSH; + queue->engine = OCB_ENGINE_PUSH3; + goto read_engine; + read_engine: align_mask = CACHE_LINE_SIZE - 1; async_queue_create(async_queue, engine); @@ -789,20 +827,25 @@ ocb_queue_create(OcbQueue *queue, // These are the write engines from OCC's perspective. case ASYNC_ENGINE_OCB_PULL0: - queue->irq = PGP_IRQ_STRM0_PULL; + queue->irq = OCCHW_IRQ_STRM0_PULL; queue->engine = OCB_ENGINE_PULL0; goto write_engine; case ASYNC_ENGINE_OCB_PULL1: - queue->irq = PGP_IRQ_STRM1_PULL; + queue->irq = OCCHW_IRQ_STRM1_PULL; queue->engine = OCB_ENGINE_PULL1; goto write_engine; case ASYNC_ENGINE_OCB_PULL2: - queue->irq = PGP_IRQ_STRM2_PULL; + queue->irq = OCCHW_IRQ_STRM2_PULL; queue->engine = OCB_ENGINE_PULL2; goto write_engine; + case ASYNC_ENGINE_OCB_PULL3: + queue->irq = OCCHW_IRQ_STRM3_PULL; + queue->engine = OCB_ENGINE_PULL3; + goto write_engine; + write_engine: align_mask = 8 - 1; async_queue_create(async_queue, engine); @@ -898,15 +941,18 @@ void ocb_error_handler_full(void *arg, SsxIrqId irq, int priority) { ocb_occlfir_t fir; + ocb_occlfir_t fir_temp; int channel; AsyncQueue* queue; ssx_irq_status_clear(irq); getscom(OCB_OCCLFIR, &(fir.value)); - + + fir_temp.value = 0; + fir_temp.fields.ocb_idc0_error = 1; for (channel = 0; channel < OCB_INDIRECT_CHANNELS; channel++) { - if (fir.value & (OCB_OCCLFIR_OCB_IDC0_ERROR >> channel)) { + if (fir.value & (fir_temp.value >> channel)) { queue = (AsyncQueue*)(&(G_ocb_read_queue[channel])); if (queue->state == ASYNC_QUEUE_STATE_RUNNING) { diff --git a/src/ssx/pgp/pgp_async_pba.c b/src/ssx/occhw/occhw_async_pba.c index 14b5619..3a03a17 100755..100644 --- a/src/ssx/pgp/pgp_async_pba.c +++ b/src/ssx/occhw/occhw_async_pba.c @@ -1,15 +1,38 @@ -// $Id: pgp_async_pba.c,v 1.2 2014/02/03 01:30:34 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_pba.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_async_pba.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_async_pba.c +/// \file occhw_async_pba.c /// \brief Async device drivers for the PBA block copy engines and PBAX #include "ssx.h" +#include "occhw_async.h" //////////////////////////////////////////////////////////////////////////// // Global Data @@ -958,12 +981,12 @@ pbax_queue_create(PbaxQueue *queue, switch (engine) { case ASYNC_ENGINE_PBAX_PUSH0: - queue->irq = PGP_IRQ_PBA_OCC_PUSH0; + queue->irq = OCCHW_IRQ_PBAX_OCC_PUSH0; queue->engine = PBAX_ENGINE_PUSH0; break; case ASYNC_ENGINE_PBAX_PUSH1: - queue->irq = PGP_IRQ_PBA_OCC_PUSH1; + queue->irq = OCCHW_IRQ_PBAX_OCC_PUSH1; queue->engine = PBAX_ENGINE_PUSH1; break; diff --git a/src/ssx/pgp/pgp_cache.S b/src/ssx/occhw/occhw_cache.S index 4208f59..052021b 100755..100644 --- a/src/ssx/pgp/pgp_cache.S +++ b/src/ssx/occhw/occhw_cache.S @@ -1,13 +1,35 @@ -// $Id: pgp_cache.S,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_cache.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_cache.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_cache.S -/// \brief Cache-management specific to PGP +/// \file occhw_cache.S +/// \brief Cache-management specific to OCCHW #include "ssx.h" @@ -23,12 +45,12 @@ /// valid before flushing the entry. /// /// This algorithm works by filling the cache with 0s to displace any dirty -/// lines. Then the cache is invalidated. In PgP the first 16 KB of the +/// lines. Then the cache is invalidated. In OCCHW the first 16 KB of the /// 0x80000000 address range are used as the zero-fill range. This memory is /// not mapped on the OCI so these lines must never escape the D-cache. /// /// Note: Our Simics model includes this 16K memory area since Simics does not -/// default to having a cache. Since we run PgP with the MMU enabled and we +/// default to having a cache. Since we run OCCHW with the MMU enabled and we /// don't MMU-map this area, memory addressing bugs should not be able to slip /// through. #ifdef DOXYGEN_ONLY @@ -57,7 +79,7 @@ dcache_flush_all: ## DCBZ to work. mfdccr %r11 - _liwa %r3, PGP_FLUSH_ZERO_DCCR + _liwa %r3, OCCHW_FLUSH_ZERO_DCCR or %r3, %r3, %r11 mtdccr %r3 isync @@ -66,7 +88,7 @@ dcache_flush_all: li %r3, DCACHE_LINES mtctr %r3 - _liwa %r3, PGP_FLUSH_ZERO_ADDRESS + _liwa %r3, OCCHW_FLUSH_ZERO_ADDRESS 1: dcbz %r0, %r3 addi %r3, %r3, CACHE_LINE_SIZE @@ -78,7 +100,7 @@ dcache_flush_all: li %r3, DCACHE_LINES mtctr %r3 - _liwa %r3, PGP_FLUSH_ZERO_ADDRESS + _liwa %r3, OCCHW_FLUSH_ZERO_ADDRESS 1: dcbi %r0, %r3 addi %r3, %r3, CACHE_LINE_SIZE diff --git a/src/ssx/occhw/occhw_core.h b/src/ssx/occhw/occhw_core.h new file mode 100644 index 0000000..b576e40 --- /dev/null +++ b/src/ssx/occhw/occhw_core.h @@ -0,0 +1,42 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_core.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_CORE_H__ +#define __OCCHW_CORE_H__ + +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file occhw_core.h +/// \brief processor core units header. Local and mechanically generated macros. + +//#include "pc_register_addresses.h" +//#include "pc_firmware_registers.h" +//#include "sensors_register_addresses.h" +//#include "sensors_firmware_registers.h" + +#endif /* __OCCHW_CORE_H__ */ diff --git a/src/ssx/pgp/pgp_id.c b/src/ssx/occhw/occhw_id.c index 0b4d4d7..ab6f5bc 100644 --- a/src/ssx/pgp/pgp_id.c +++ b/src/ssx/occhw/occhw_id.c @@ -1,16 +1,38 @@ -// $Id: pgp_id.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_id.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_id.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_id.h -/// \brief PgP chip and EC-level identification + chip configuration +/// \file occhw_id.h +/// \brief processor chip and EC-level identification + chip configuration #include "ssx.h" -#include "pgp_config.h" +#include "chip_config.h" // Note: These cached variables are all declared as 64 bits, noncacheable so @@ -23,7 +45,7 @@ uint64_t G_cfam_chip_type SECTION_ATTRIBUTE(".noncacheable") = 0; uint64_t G_cfam_ec_level SECTION_ATTRIBUTE(".noncacheable") = 0; void -_pgp_get_ids(void) +_occhw_get_ids(void) { tpc_gp0_t gp0; tpc_device_id_t deviceId; @@ -91,7 +113,7 @@ uint64_t G_core_configuration SECTION_ATTRIBUTE(".noncacheable") = 0; /// pending Simics support for the base pervasive functionality void -_pgp_get_chip_configuration(void) +_occhw_get_chip_configuration(void) { if (SIMICS_ENVIRONMENT) { @@ -107,14 +129,14 @@ _pgp_get_chip_configuration(void) int rc; rc = getscom(0x000f0008, &select); /* TP CHIPLET SELECT */ - if (rc) SSX_PANIC(PGP_ID_SCOM_ERROR_SELECT); - if (select != 0) SSX_PANIC(PGP_ID_SELECT_ERROR); + if (rc) SSX_PANIC(OCCHW_ID_SCOM_ERROR_SELECT); + if (select != 0) SSX_PANIC(OCCHW_ID_SELECT_ERROR); rc = getscom(MC_ADDRESS(0x000f0012, MC_GROUP_EX_CORE, PCB_MULTICAST_SELECT), &configuration); - if (rc) SSX_PANIC(PGP_ID_SCOM_ERROR_CONFIG); + if (rc) SSX_PANIC(OCCHW_ID_SCOM_ERROR_CONFIG); G_chip_configuration = (configuration << 16) & 0xffff000000000000ull; } diff --git a/src/ssx/pgp/pgp_id.h b/src/ssx/occhw/occhw_id.h index 2b0ecab..d591f6a 100644 --- a/src/ssx/pgp/pgp_id.h +++ b/src/ssx/occhw/occhw_id.h @@ -1,16 +1,38 @@ -#ifndef __PGP_ID_H__ -#define __PGP_ID_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_id.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_ID_H__ +#define __OCCHW_ID_H__ -// $Id: pgp_id.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_id.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_id.h -/// \brief PgP chip and EC-level identification + chip configuration +/// \file occhw_id.h +/// \brief chip and EC-level identification + chip configuration /// /// During initialization the device identification SCOM registers are read /// and cached. @@ -43,21 +65,20 @@ // Error/Panic Codes -#define PGP_ID_SCOM_ERROR_SELECT 0x00747401 -#define PGP_ID_SCOM_ERROR_CONFIG 0x00747402 -#define PGP_ID_SELECT_ERROR 0x00747403 +#define OCCHW_ID_SCOM_ERROR_SELECT 0x00747401 +#define OCCHW_ID_SCOM_ERROR_CONFIG 0x00747402 +#define OCCHW_ID_SELECT_ERROR 0x00747403 #ifndef __ASSEMBLER__ #include <stdint.h> #include "tpc_firmware_registers.h" -#include "pgp_config.h" -/// Get TPC device identification (internal API, called once from __pgp_setup(). +/// Get TPC device identification (internal API, called once from __occhw_setup(). void -_pgp_get_ids(void); +_occhw_get_ids(void); /// Get the TPC Node Id uint8_t node_id(void); @@ -68,13 +89,13 @@ uint8_t chip_id(void); /// Get the CFAM Chip Id /// /// \returns A 32-bit value to be compared against the enumeration of known -/// CFAM ids. See \ref pgp_cfam_chip_ids. +/// CFAM ids. See \ref cfam_chip_ids. uint32_t cfam_id(void); /// Get the CFAM Chip Type /// /// \returns An 8-bit value to be compared against the enumeration of known -/// CFAM chip types. See \ref pgp_cfam_chip_types. +/// CFAM chip types. See \ref cfam_chip_types. uint8_t cfam_chip_type(void); /// Get the CFAM Chip EC Level @@ -85,9 +106,9 @@ uint8_t cfam_chip_type(void); uint8_t cfam_ec_level(void); -/// Compute the chip configuration (internal API, called once from __pgp_setup(). +/// Compute the chip configuration (internal API, called once from __occhw_setup(). void -_pgp_get_chip_configuration(void); +_occhw_get_chip_configuration(void); /// Get the core configuration /// @@ -100,7 +121,7 @@ core_configuration(void); #endif // __ASSEMBLER__ -/// \defgroup pgp_cfam_chip_types PGP CFAM Chip Types (Including Centaur) +/// \defgroup cfam_chip_types CFAM Chip Types (Including Centaur) /// /// The CFAM Chip Type is an 8-bit value that uniquely identfies a chip /// architecture. @@ -114,7 +135,7 @@ core_configuration(void); /// @} -/// \defgroup pgp_cfam_chip_ids PGP CFAM Chip Ids (Including Centaur) +/// \defgroup cfam_chip_ids CFAM Chip Ids (Including Centaur) /// /// The CFAM Chip ID is a 32-bit value that uniquely identfies a chip and its /// EC level. @@ -180,4 +201,4 @@ typedef union { /// @} -#endif // __PGP_ID_H__ +#endif // __OCCHW_ID_H__ diff --git a/src/ssx/pgp/pgp_init.c b/src/ssx/occhw/occhw_init.c index 4e28014..f3383b4 100755..100644 --- a/src/ssx/pgp/pgp_init.c +++ b/src/ssx/occhw/occhw_init.c @@ -1,20 +1,44 @@ -// $Id: pgp_init.c,v 1.2 2014/03/14 16:34:34 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_init.c -/// \brief SSX initialization for PgP +/// \file occhw_init.c +/// \brief SSX initialization for OCCHW /// /// The entry points in this routine are used during initialization. This /// code space can be deallocated and reassigned after application /// initialization if required. #include "ssx.h" -#include "pgp_vrm.h" +#include "occhw_async.h" + +//#include "occhw_vrm.h" #include "simics_stdio.h" #include "string_stream.h" @@ -24,7 +48,7 @@ #endif // We need to make sure that the PLB arbiter is set up correctly to obtain -// highest performance in the PgP environment, and that PLB error reporting is +// highest performance in the OCCHW environment, and that PLB error reporting is // appropriate. // The PLB arbiter is configured to support fair arbitration of equal-priority @@ -37,19 +61,22 @@ static void plb_arbiter_setup() { - plb_pacr_t pacr; + //TODO: enable this once OCB support is present in simics +#if 0 + ocb_oacr_t oacr; ocb_ocichsw_t oo; - pacr.value = 0; - pacr.fields.ppm = 1; /* Fair arbitration */ - pacr.fields.hbu = 1; /* High bus utilization */ - pacr.fields.rdp = 1; /* 2-deep read pipelining */ - pacr.fields.wrp = 1; /* 2-deep write pipelining */ - mtdcr(PLB_PACR, pacr.value); + oacr.value = 0; + oacr.fields.oci_priority_mode = 1; /* Fair arbitration */ + oacr.fields.oci_hi_bus_mode = 1; /* High bus utilization */ + oacr.fields.oci_read_pipeline_control = 1; /* 2-deep read pipelining */ + oacr.fields.oci_write_pipeline_control = 1; /* 2-deep write pipelining */ + mtdcr(OCB_OACR, oacr.value); oo.value = in32(OCB_OCICHSW); oo.fields.plbarb_lockerr = 1; out32(OCB_OCICHSW, oo.value); +#endif } @@ -162,7 +189,7 @@ static const MmuRegion mmu_regions[] = { 0, TLBLO_WR | TLBLO_I | TLBLO_G, 0} , }; -/// PgP MMU setup +/// OCCHW MMU setup /// /// Run down the mmu_regions[] array and map all regions with non-0 sizes. /// These are direct maps, setting the effective address to the physical @@ -173,7 +200,7 @@ static const MmuRegion mmu_regions[] = { /// to access main memory from the OCC. static void -pgp_mmu_setup() +occhw_mmu_setup() { int i, regions; @@ -272,39 +299,93 @@ io_setup() stderr = (FILE *)(&simics_stderr); ssxout = (FILE *)(&simics_stdout); + printf("Initialize the Simics stdio.\n"); + #endif // I/O Configuration } - -/// PgP environment initial setup. +/// OCCHW environment initial setup. /// -/// This is setup common to all PgP applications. This setup takes place +/// This is setup common to all OCCHW applications. This setup takes place /// during boot, before main() is called. void -__pgp_setup() +__occhw_setup() { - // All OCB interrupts are masked. The SSX/PPC405 Boot code masks PPC405 - // PIT, FIT, and Watchdog interrupts. All interrupts are also initially - // set up as noncritical, non-debugged, edge-triggered, active-high, and - // their status is cleared. This clarifies IPL debugging as it eliminates - // spurious "asserted" interrupts until the firmware comes in and actually - // sets up the interrupt. - - out32(OCB_OIMR0, 0xffffffff); /* Masked */ - out32(OCB_OIMR1, 0xffffffff); - out32(OCB_OITR0, 0xffffffff); /* Edge */ - out32(OCB_OITR1, 0xffffffff); - out32(OCB_OIEPR0, 0xffffffff); /* Active High */ - out32(OCB_OIEPR1, 0xffffffff); - out32(OCB_OCIR0, 0); /* Noncritical */ - out32(OCB_OCIR1, 0); - out32(OCB_OISR0_AND, 0); /* Clear Status */ - out32(OCB_OISR1_AND, 0); - out32(OCB_OUDER0, 0); /* No Unconditional Debug Event */ - out32(OCB_OUDER1, 0); - out32(OCB_ODHER0, 0); /* No Debug Halt Event */ - out32(OCB_ODHER1, 0); + uint64_t oirrA; + uint64_t oirrB; + uint64_t oirrC; + uint64_t owned_actual; + uint64_t reverse_polarity; + +#if (APPCFG_OCC_INSTANCE_ID == OCCHW_IRQ_ROUTE_OWNER) + //If this instance is the owner of the interrupt routting registers + //then write the routing registers for all OCC interrupts. + //This instance must be the first instance to run within the OCC + //This will be done while all external interrupts are masked. + out32(OCB_OIMR0_OR, 0xffffffff); + out32(OCB_OIMR1_OR, 0xffffffff); + out32(OCB_OIRR0A, (uint32_t)(g_ext_irqs_routeA >> 32)); + out32(OCB_OIRR1A, (uint32_t)g_ext_irqs_routeA); + out32(OCB_OIRR0B, (uint32_t)(g_ext_irqs_routeB >> 32)); + out32(OCB_OIRR1B, (uint32_t)g_ext_irqs_routeB); + out32(OCB_OIRR0C, (uint32_t)(g_ext_irqs_routeC >> 32)); + out32(OCB_OIRR1C, (uint32_t)g_ext_irqs_routeC); + + //Note: all interrupts are left in the masked state at this point +#endif + + //Determine from the routing registers which irqs are owned by this instance + //NOTE: If a bit is not set in the routeA register, it is not owned by a GPE + + oirrA = ((uint64_t)in32(OCB_OIRR0A)) << 32; + oirrA |= in32(OCB_OIRR1A); + oirrB = ((uint64_t)in32(OCB_OIRR0B)) << 32; + oirrB |= in32(OCB_OIRR1B); + oirrC = ((uint64_t)in32(OCB_OIRR0C)) << 32; + oirrC |= in32(OCB_OIRR1C); + + //All interrupts owned by the 405 will not have a bit set in routeA + owned_actual = ~oirrA; + + //Panic if we don't own the irqs we were expecting + //NOTE: we don't panic if we are given more IRQ's than expected + if((owned_actual & g_ext_irqs_owned) != g_ext_irqs_owned) + { + //IRQ's were not routed to us correctly. + SSX_PANIC(OCCHW_IRQ_ROUTING_ERROR); + } + + //Mask all external interrupts owned by this instance + //(even the ones given to us that we weren't expecting) + out32(OCB_OIMR0_OR, (uint32_t)(owned_actual >> 32)); + out32(OCB_OIMR1_OR, (uint32_t)owned_actual); + + //Set the interrupt type for all interrupts owned by this instance + out32(OCB_OITR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32)); + out32(OCB_OITR1_CLR, (uint32_t)g_ext_irqs_owned); + out32(OCB_OITR0_OR, (uint32_t)(g_ext_irqs_type >> 32)); + out32(OCB_OITR1_OR, (uint32_t)g_ext_irqs_type); + + //Set the interrupt polarity for all interrupts owned by this instance + out32(OCB_OIEPR0_CLR, (uint32_t)(g_ext_irqs_owned >> 32)); + out32(OCB_OIEPR1_CLR, (uint32_t)g_ext_irqs_owned); + out32(OCB_OIEPR0_OR, (uint32_t)(g_ext_irqs_polarity >> 32)); + out32(OCB_OIEPR1_OR, (uint32_t)g_ext_irqs_polarity); + + //clear the status of all external interrupts owned by this instance + out32(OCB_OISR0_CLR, ((uint32_t)(g_ext_irqs_owned >> 32))); + out32(OCB_OISR1_CLR, ((uint32_t)g_ext_irqs_owned)); + + //set the status for interrupts that have reverse polarity + reverse_polarity = ~g_ext_irqs_polarity & g_ext_irqs_owned; + out32(OCB_OISR0_OR, ((uint32_t)(reverse_polarity >> 32))); + out32(OCB_OISR1_OR, ((uint32_t)reverse_polarity)); + + //Unmask the interrupts owned by this instance that are to be enabled by default + out32(OCB_OIMR0_CLR, (uint32_t)(g_ext_irqs_enable >> 32)); + out32(OCB_OIMR1_CLR, (uint32_t)g_ext_irqs_enable); + // Setup requires SCOM, which requires a timeout. Therefore we need to set // up a default timebase frequency, which may be overridden during @@ -319,9 +400,12 @@ __pgp_setup() io_setup(); + // TODO: enable once chip id support is present +#if 0 // Cache the device identification and chip configuration - _pgp_get_ids(); - _pgp_get_chip_configuration(); + _occhw_get_ids(); + _occhw_get_chip_configuration(); +#endif // Set up the PLB arbiter @@ -331,10 +415,9 @@ __pgp_setup() // MMU is activated. #if PPC405_MMU_SUPPORT - pgp_mmu_setup(); + occhw_mmu_setup(); #endif - // The PgP Async drivers are initialized. - + // The Async drivers are initialized. async_initialize(); } diff --git a/src/ssx/pgp/pgp_irq.h b/src/ssx/occhw/occhw_irq.h index f45ed52..b5c25c0 100755..100644 --- a/src/ssx/pgp/pgp_irq.h +++ b/src/ssx/occhw/occhw_irq.h @@ -1,31 +1,53 @@ -#ifndef __PGP_IRQ_H__ -#define __PGP_IRQ_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_irq.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_IRQ_H__ +#define __OCCHW_IRQ_H__ -// $Id: pgp_irq.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_irq.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_irq.h -/// \brief PPC405-PgP Interrupt handling for SSX +/// \file occhw_irq.h +/// \brief PPC405-OCCHW Interrupt handling for SSX /// -/// The PgP interrupt controller supports a maximum of 64 interrupts, split +/// The OCCHW interrupt controller supports a maximum of 64 interrupts, split /// into 2 x 32-bit non-cascaded interrupt controllers with simple OR /// combining of the interrupt signals. /// -/// The PGP interrupt controller allows interrupt status to be set directly by +/// The OCB interrupt controller allows interrupt status to be set directly by /// software, as well as providing a mode that causes an enabled pending -/// interrupt to trigger an Unconditional Debug Event. The PGP interrupt +/// interrupt to trigger an Unconditional Debug Event. The OCB interrupt /// controller contains a 'mask' register, unlike other 405 interrupt -/// controllers that have an 'enable' register. The PgP mask and status -/// registers also have atomic AND/OR function so that it is never necessary +/// controllers that have an 'enable' register. The OCCHW mask and status +/// registers also have atomic CLR/OR function so that it is never necessary /// to enter a critical section to enable/disable/clear interrupts and /// interrupt status. -#include "pgp_common.h" +#include "occhw_common.h" #include "ocb_register_addresses.h" #ifndef __ASSEMBLER__ @@ -36,7 +58,7 @@ UNLESS__PPC405_IRQ_CORE_C__(extern) inline void ssx_irq_enable(SsxIrqId irq) { - out32(OCB_OIMR_AND(irq), ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIMR_CLR(irq), OCCHW_IRQ_MASK32(irq)); } @@ -46,18 +68,18 @@ UNLESS__PPC405_IRQ_CORE_C__(extern) inline void ssx_irq_disable(SsxIrqId irq) { - out32(OCB_OIMR_OR(irq), PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIMR_OR(irq), OCCHW_IRQ_MASK32(irq)); } -/// Clear interrupt status with an AND mask. Only meaningful for +/// Clear interrupt status with an CLR mask. Only meaningful for /// edge-triggered interrupts. UNLESS__PPC405_IRQ_CORE_C__(extern) inline void ssx_irq_status_clear(SsxIrqId irq) { - out32(OCB_OISR_AND(irq), ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq)); } @@ -67,7 +89,7 @@ UNLESS__PPC405_IRQ_CORE_C__(extern) inline int ssx_irq_status_get(SsxIrqId irq) { - return (in32(OCB_OISR(irq)) & PGP_IRQ_MASK32(irq)) != 0; + return (in32(OCCHW_OISR(irq)) & OCCHW_IRQ_MASK32(irq)) != 0; } @@ -78,9 +100,9 @@ inline void ssx_irq_status_set(SsxIrqId irq, int value) { if (value) { - out32(OCB_OISR_OR(irq), PGP_IRQ_MASK32(irq)); + out32(OCCHW_OISR_OR(irq), OCCHW_IRQ_MASK32(irq)); } else { - out32(OCB_OISR_AND(irq), ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OISR_CLR(irq), OCCHW_IRQ_MASK32(irq)); } } @@ -90,9 +112,9 @@ ssx_irq_debug_set(SsxIrqId irq, int value); #endif /* __ASSEMBLER__ */ -/// \page pgp_irq_macros PgP IRQ API Assembler Macros +/// \page occhw_irq_macros OCCHW IRQ API Assembler Macros /// -/// These macros encapsulate the SSX API for the PgP interrupt +/// These macros encapsulate the SSX API for the OCCHW interrupt /// controller. These macros require 2 scratch registers in addition to the \c /// irq parameter register passed into the handler from SSX interrupt /// dispatch. These macros also modift CR0. @@ -156,16 +178,15 @@ ssx_irq_debug_set(SsxIrqId irq, int value); .endm - .macro _pgp_irq_or_mask, rirq:req, rmask:req + .macro _occhw_irq_or_mask, rirq:req, rmask:req .two_unique \rirq, \rmask lis \rmask, 0x8000 srw \rmask, \rmask, \rirq .endm - .macro _pgp_irq_and_mask, rirq:req, rmask:req + .macro _occhw_irq_clr_mask, rirq:req, rmask:req .two_unique \rirq, \rmask - _pgp_irq_or_mask \rirq, \rmask - not \rmask, \rmask + _occhw_irq_or_mask \rirq, \rmask .endm @@ -174,12 +195,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value); andi. \raddr, \rirq, 0x20 clrlwi \raddr, \rirq, 27 - _pgp_irq_and_mask \raddr, \rmask + _occhw_irq_clr_mask \raddr, \rmask bne- 888f - _stwi \rmask, \raddr, OCB_OIMR0_AND + _stwi \rmask, \raddr, OCB_OIMR0_CLR b 999f 888: - _stwi \rmask, \raddr, OCB_OIMR1_AND + _stwi \rmask, \raddr, OCB_OIMR1_CLR 999: eieio .endm @@ -190,7 +211,7 @@ ssx_irq_debug_set(SsxIrqId irq, int value); andi. \raddr, \rirq, 0x20 clrlwi \raddr, \rirq, 27 - _pgp_irq_or_mask \raddr, \rmask + _occhw_irq_or_mask \raddr, \rmask bne- 888f _stwi \rmask, \raddr, OCB_OIMR0_OR b 999f @@ -206,12 +227,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value); andi. \raddr, \rirq, 0x20 clrlwi \raddr, \rirq, 27 - _pgp_irq_and_mask \raddr, \rmask + _occhw_irq_clr_mask \raddr, \rmask bne- 888f - _stwi \rmask, \raddr, OCB_OISR0_AND + _stwi \rmask, \raddr, OCB_OISR0_CLR b 999f 888: - _stwi \rmask, \raddr, OCB_OISR1_AND + _stwi \rmask, \raddr, OCB_OISR1_CLR 999: eieio .endm @@ -224,7 +245,7 @@ ssx_irq_debug_set(SsxIrqId irq, int value); clrlwi \raddr, \rirq, 27 .if \imm - _pgp_irq_or_mask \raddr, \rmask + _occhw_irq_or_mask \raddr, \rmask bne- 888f _stwi \rmask, \raddr, OCB_OISR0_OR b 999f @@ -233,12 +254,12 @@ ssx_irq_debug_set(SsxIrqId irq, int value); .else - _pgp_irq_and_mask \raddr, \rmask + _occhw_irq_clr_mask \raddr, \rmask bne- 888f - _stwi \rmask, \raddr, OCB_OISR0_AND + _stwi \rmask, \raddr, OCB_OISR0_CLR b 999f 888: - _stwi \rmask, \raddr, OCB_OISR1_AND + _stwi \rmask, \raddr, OCB_OISR1_CLR .endif 999: @@ -249,4 +270,4 @@ ssx_irq_debug_set(SsxIrqId irq, int value); /// \endcond -#endif /* __PGP_IRQ_H__ */ +#endif /* __OCCHW_IRQ_H__ */ diff --git a/src/ssx/pgp/pgp_irq_init.c b/src/ssx/occhw/occhw_irq_init.c index 6719766..da10cda 100755..100644 --- a/src/ssx/pgp/pgp_irq_init.c +++ b/src/ssx/occhw/occhw_irq_init.c @@ -1,13 +1,35 @@ -// $Id: pgp_irq_init.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_irq_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_irq_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_irq_init.c -/// \brief PGP IRQ initialization code for SSX +/// \file occhw_irq_init.c +/// \brief OCCHW IRQ initialization code for SSX /// /// The entry points in this file are initialization rotines that could be /// eliminated/deallocated by the application to free up storage if they are @@ -39,10 +61,10 @@ ssx_irq_setup(SsxIrqId irq, int trigger) { SsxMachineContext ctx; - uint32_t oitr, oeipr; if (SSX_ERROR_CHECK_API) { - SSX_ERROR_IF(!PGP_IRQ_VALID(irq) || + SSX_ERROR_IF(!OCCHW_IRQ_VALID(irq) || + !OCCHW_IRQ_OWNED(irq) || !((polarity == SSX_IRQ_POLARITY_ACTIVE_HIGH) || (polarity == SSX_IRQ_POLARITY_ACTIVE_LOW)) || !((trigger == SSX_IRQ_TRIGGER_LEVEL_SENSITIVE) || @@ -52,18 +74,16 @@ ssx_irq_setup(SsxIrqId irq, ssx_critical_section_enter(SSX_CRITICAL, &ctx); - oeipr = in32(OCB_OIEPR(irq)); if (polarity == SSX_IRQ_POLARITY_ACTIVE_HIGH) { - out32(OCB_OIEPR(irq), oeipr | PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIEPR_OR(irq), OCCHW_IRQ_MASK32(irq)); } else { - out32(OCB_OIEPR(irq), oeipr & ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIEPR_CLR(irq), OCCHW_IRQ_MASK32(irq)); } - oitr = in32(OCB_OITR(irq)); if (trigger == SSX_IRQ_TRIGGER_EDGE_SENSITIVE) { - out32(OCB_OITR(irq), oitr | PGP_IRQ_MASK32(irq)); + out32(OCCHW_OITR_OR(irq), OCCHW_IRQ_MASK32(irq)); } else { - out32(OCB_OITR(irq), oitr & ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OITR_CLR(irq), OCCHW_IRQ_MASK32(irq)); } ssx_critical_section_exit(&ctx); @@ -92,10 +112,10 @@ ssx_irq_handler_set(SsxIrqId irq, int priority) { SsxMachineContext ctx; - uint32_t ocir; if (SSX_ERROR_CHECK_API) { - SSX_ERROR_IF(!PGP_IRQ_VALID(irq) || + SSX_ERROR_IF(!OCCHW_IRQ_VALID(irq) || + !OCCHW_IRQ_OWNED(irq) || (handler == 0) || !((priority == SSX_NONCRITICAL) || (priority == SSX_CRITICAL)), @@ -104,11 +124,15 @@ ssx_irq_handler_set(SsxIrqId irq, ssx_critical_section_enter(SSX_CRITICAL, &ctx); - ocir = in32(OCB_OCIR(irq)); + //Regardless of priority, OIRRA & OIRRB will be cleared + out32(OCCHW_OIRRA_CLR(irq), OCCHW_IRQ_MASK32(irq)); + out32(OCCHW_OIRRB_CLR(irq), OCCHW_IRQ_MASK32(irq)); + + //Critical priority needs a 1 in OIRRC if (priority == SSX_CRITICAL) { - out32(OCB_OCIR(irq), ocir | PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIRRC_OR(irq), OCCHW_IRQ_MASK32(irq)); } else { - out32(OCB_OCIR(irq), ocir & ~PGP_IRQ_MASK32(irq)); + out32(OCCHW_OIRRC_CLR(irq), OCCHW_IRQ_MASK32(irq)); } __ppc405_irq_handlers[irq].handler = handler; @@ -126,15 +150,16 @@ void ssx_irq_debug_set(SsxIrqId irq, int value) { SsxMachineContext ctx; - uint32_t ouder; + //uint32_t ouder; ssx_critical_section_enter(SSX_CRITICAL, &ctx); - ouder = in32(OCB_OUDER(irq)); + //TODO: port this over to using the OIRR instead of the OUDER + //ouder = in32(OCCHW_OUDER(irq)); if (value) { - out32(OCB_OUDER(irq), ouder | PGP_IRQ_MASK32(irq)); + //out32(OCCHW_OUDER(irq), ouder | OCCHW_IRQ_MASK32(irq)); } else { - out32(OCB_OUDER(irq), ouder & ~PGP_IRQ_MASK32(irq)); + //out32(OCCHW_OUDER(irq), ouder & ~OCCHW_IRQ_MASK32(irq)); } ssx_critical_section_exit(&ctx); diff --git a/src/ssx/pgp/pgp_ocb.c b/src/ssx/occhw/occhw_ocb.c index e39475e..237c333 100755..100644 --- a/src/ssx/pgp/pgp_ocb.c +++ b/src/ssx/occhw/occhw_ocb.c @@ -1,13 +1,35 @@ -// $Id: pgp_ocb.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_ocb.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_ocb.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_ocb.c -/// \brief OCB-related drivers for PgP +/// \file occhw_ocb.c +/// \brief OCB-related drivers for OCCHW #include "ssx.h" @@ -140,20 +162,20 @@ ocb_timer_setup(int timer, // timer, auto_reload, timeout_ns, // handler, arg, priority); - ssx_irq_disable(PGP_IRQ_OCC_TIMER0 + timer); + ssx_irq_disable(OCCHW_IRQ_OCC_TIMER0 + timer); - ssx_irq_setup(PGP_IRQ_OCC_TIMER0 + timer, + ssx_irq_setup(OCCHW_IRQ_OCC_TIMER0 + timer, SSX_IRQ_POLARITY_ACTIVE_HIGH, SSX_IRQ_TRIGGER_LEVEL_SENSITIVE); - ssx_irq_handler_set(PGP_IRQ_OCC_TIMER0 + timer, + ssx_irq_handler_set(OCCHW_IRQ_OCC_TIMER0 + timer, handler, arg, priority); rc = ocb_timer_reset(timer, auto_reload, timeout_ns); - ssx_irq_enable(PGP_IRQ_OCC_TIMER0 + timer); + ssx_irq_enable(OCCHW_IRQ_OCC_TIMER0 + timer); }while(0); return rc; @@ -181,7 +203,7 @@ ocb_core_interrupt() oo.value = 0; oo.fields.core_ext_intr = 1; - out32(OCB_OCCMISC_AND, ~oo.value); + out32(OCB_OCCMISC_CLR, oo.value); out32(OCB_OCCMISC_OR, oo.value); return 0; @@ -227,7 +249,7 @@ ocb_linear_window_initialize(int channel, uint32_t base, int log_size) if (SSX_ERROR_CHECK_API) { SSX_ERROR_IF((channel < 0) || - (channel > 2) || + (channel > 3) || (log_size < OCB_LW_LOG_SIZE_MIN) || (log_size > OCB_LW_LOG_SIZE_MAX) || ((base & mask) != 0), @@ -238,19 +260,17 @@ ocb_linear_window_initialize(int channel, uint32_t base, int log_size) mask = ~mask; - // Configure OCB Linear Write Control Register + // Enable LW mode ocblwcrn.fields.linear_window_enable = 1; - // base 13:28 (16 bits) - ocblwcrn.fields.linear_window_bar = (base >> 3) & 0xFFFF; - // mask 17:28 (12 bits) + // Select bits(12:28) of OCI addr for the LW bar + ocblwcrn.fields.linear_window_bar = (base >> 3) & 0x1FFFF; ocblwcrn.fields.linear_window_mask = (mask >> 3) & 0xFFF; out32(OCB_OCBLWCRN(channel), ocblwcrn.value); - // Configure OCB Linear Window Write Base Register - ocblwsbrn.fields.linear_window_region = 3; // SRAM only - // \todo: Are there constants for the OCI regions? - // base 2:9 (8 bits) - ocblwsbrn.fields.linear_window_base = (base >> 19) & 0xFF; + // Configure LW region for SRAM access + ocblwsbrn.fields.linear_window_region = 7; + // Select bits(5:11) of OCI addr for the LW base + ocblwsbrn.fields.linear_window_base = (base >> 20) & 0x7F; out32(OCB_OCBLWSBRN(channel), ocblwsbrn.value); return 0 ; @@ -276,12 +296,12 @@ ocb_linear_window_disable(int channel) if (SSX_ERROR_CHECK_API) { SSX_ERROR_IF((channel < 0) || - (channel > 2), + (channel > 3), OCB_INVALID_ARGUMENT_LW_DISABLE); } ocblwcrn.value = in32(OCB_OCBLWCRN(channel)); - // Configure OCB Linear Write Control Register + // Disable LW mode ocblwcrn.fields.linear_window_enable = 0; out32(OCB_OCBLWCRN(channel), ocblwcrn.value); @@ -314,6 +334,9 @@ ocb_linear_window_disable(int channel) /// +//NOTE: The OCBICR register seems to have gone away in P9 and we didn't ever +// call this function in P8 so I'm removing this function for now. (grm) +#if 0 int ocb_allow_untrusted_initialize(int channel, int allow_untrusted) { @@ -333,3 +356,4 @@ ocb_allow_untrusted_initialize(int channel, int allow_untrusted) return 0 ; } +#endif diff --git a/src/ssx/occhw/occhw_ocb.h b/src/ssx/occhw/occhw_ocb.h new file mode 100644 index 0000000..9a780b4 --- /dev/null +++ b/src/ssx/occhw/occhw_ocb.h @@ -0,0 +1,113 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_ocb.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_OCB_H__ +#define __OCCHW_OCB_H__ + +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file occhw_ocb.h +/// \brief OCB unit header. Local and mechanically generated macros and APIs. + +#include "ssx.h" +#include "ppc32.h" + +#include "occhw_common.h" +#include "ocb_register_addresses.h" +#include "ocb_firmware_registers.h" + +#include "ppc405_irq.h" + +#define OCB_TIMER0 0 +#define OCB_TIMER1 1 + +#define OCB_TIMERS 2 + +#define OCB_TIMER_ONE_SHOT 0 +#define OCB_TIMER_AUTO_RELOAD 1 + +#define OCB_LW_LOG_SIZE_MIN 3 +#define OCB_LW_LOG_SIZE_MAX 15 + +#define OCB_INVALID_ARGUMENT_TIMER 0x00622001 +#define OCB_INVALID_ARGUMENT_LW_INIT 0x00622002 +#define OCB_INVALID_ARGUMENT_LW_DISABLE 0x00622003 +#define OCB_INVALID_ARGUMENT_UNTRUST 0x00622004 + +#ifndef __ASSEMBLER__ + +int +ocb_timer_reset(int timer, + int auto_reload, + int timeout_ns); + +#ifdef OCC +int +ocb_timer_setup(int timer, + int auto_reload, + int timeout_ns, + SsxIrqHandler handler, + void *arg, + int priority) INIT_SECTION; +#else +int +ocb_timer_setup(int timer, + int auto_reload, + int timeout_ns, + SsxIrqHandler handler, + void *arg, + int priority); +#endif + +/// Clear OCB timer status based on the IRQ +/// +/// This API can be called from OCB timer interrupt handlers, using the IRQ +/// provided to the handler. No error checks are provided. + +static inline void +ocb_timer_status_clear(SsxIrqId irq) +{ + ocb_otrn_t otrn_reg; + otrn_reg.value = 0; + otrn_reg.fields.timeout = 1; + out32(OCB_OTRN(irq - OCCHW_IRQ_OCC_TIMER0), otrn_reg.value); +} + +int +ocb_linear_window_initialize(int channel, uint32_t base, int log_size); + +int +ocb_linear_window_disable(int channel); + +int +ocb_allow_untrusted_initialize(int channel, int allow_untrusted); + + +#endif /* __ASSEMBLER__ */ + +#endif /* __OCCHW_OCB_H__ */ diff --git a/src/ssx/pgp/pgp_pba.c b/src/ssx/occhw/occhw_pba.c index 0f5d2d9..4c21bb8 100755..100644 --- a/src/ssx/pgp/pgp_pba.c +++ b/src/ssx/occhw/occhw_pba.c @@ -1,18 +1,40 @@ -// $Id: pgp_pba.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pba.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_pba.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_pba.c +/// \file occhw_pba.c /// \brief procedures for pba setup and operation. #include "ssx.h" -#include "pgp_pba.h" -#include "pgp_pmc.h" -#include "pgp_common.h" +#include "occhw_pba.h" +#include "occhw_scom.h" +#include "occhw_common.h" #include "polling.h" diff --git a/src/ssx/pgp/pgp_pba.h b/src/ssx/occhw/occhw_pba.h index 647c334..c962936 100755..100644 --- a/src/ssx/pgp/pgp_pba.h +++ b/src/ssx/occhw/occhw_pba.h @@ -1,15 +1,37 @@ -#ifndef __PGP_PBA_H__ -#define __PGP_PBA_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_pba.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_PBA_H__ +#define __OCCHW_PBA_H__ -// $Id: pgp_pba.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pba.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_pba.h +/// \file occhw_pba.h /// \brief PBA unit header. Local and mechanically generated macros. /// \todo Add Doxygen grouping to constant groups @@ -355,4 +377,4 @@ pbax_clear_receive_error(void) #endif /* __ASSEMBLER__ */ -#endif /* __PGP_PBA_H__ */ +#endif /* __OCCHW_PBA_H__ */ diff --git a/src/ssx/pgp/pgp_pmc.c b/src/ssx/occhw/occhw_scom.c index bf3673b..743d0dc 100755..100644 --- a/src/ssx/pgp/pgp_pmc.c +++ b/src/ssx/occhw/occhw_scom.c @@ -1,21 +1,39 @@ -// $Id: pgp_pmc.c,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pmc.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_scom.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_pmc.c -/// \brief PgP procedures and support for PMC operations +/// \file occhw_scom.c +/// \brief procedures and support for scom operations /// /// <b> SCOM Operations </b> /// -/// The PMC provides an indirect bridge from the OCI to the PIB/PCB. OCC -/// firmware therefore has the ability to do immediate putscom()/getscom() -/// operations in addition to the capabilities provided by the PORE-GPE -/// engines. In PgP, SCOM latency from OCC is expected to be in the range of -/// 150 - 1000 ns. The maximum latency of a PIB operation has a hard upper +/// The maximum latency of a PIB operation has a hard upper /// bound derived from the hardware implementation. The putscom()/getscom() /// drivers here take advantage of this upper bound and implement tight /// timeouts, enforced by polling the timebase while waiting for the SCOM @@ -62,8 +80,8 @@ /// \bug Implement and use a generic poll_with_timeout(f, arg, t) #include "ssx.h" -#include "pgp_pmc.h" - +#include "occhw_scom.h" +#include "occhw_shared_data.h" //////////////////////////////////////////////////////////////////////////// // SCOM @@ -73,27 +91,28 @@ // at least twice to guarantee that we always poll once after a timeout. static int -poll_scom(SsxInterval timeout, pmc_o2p_ctrl_status_reg_t *cs) +poll_scom(SsxInterval timeout) { SsxTimebase start; int timed_out; + int rc; start = ssx_timebase_get(); timed_out = 0; do { - cs->value = in32(PMC_O2P_CTRL_STATUS_REG); - if (!(cs->fields.o2p_ongoing)) { + rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); + if (!rc) { break; } if (timed_out) { - return -SCOM_TIMEOUT_ERROR; + rc = -SCOM_TIMEOUT_ERROR; + break; } timed_out = ((timeout != SSX_WAIT_FOREVER) && ((ssx_timebase_get() - start) > timeout)); } while (1); - - return 0; + return rc; } @@ -132,44 +151,65 @@ poll_scom(SsxInterval timeout, pmc_o2p_ctrl_status_reg_t *cs) int _getscom(uint32_t address, uint64_t *data, SsxInterval timeout) { - pmc_o2p_addr_reg_t addr; - pmc_o2p_ctrl_status_reg_t cs; - SsxMachineContext ctx; - Uint64 data64; - int rc; - - ssx_critical_section_enter(SSX_CRITICAL, &ctx); + SsxMachineContext ctx; + int rc; + occhw_scom_cmd_t *scom_cmd = &OSD_PTR->scom_cmd; + occhw_scom_status_t scom_status; + + do + { + if(address & OCCHW_SCOM_READ_MASK) + { + rc = -SCOM_INVALID_ADDRESS; + break; + } - // Check for a transaction already ongoing + ssx_critical_section_enter(SSX_CRITICAL, &ctx); - cs.value = in32(PMC_O2P_CTRL_STATUS_REG); - if (cs.fields.o2p_ongoing) { - ssx_critical_section_exit(&ctx); - return -SCOM_PROTOCOL_ERROR_GETSCOM_BUSY; - } + // Check for a transaction already ongoing + rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); + if (rc) { + ssx_critical_section_exit(&ctx); + rc = -SCOM_PROTOCOL_ERROR_GETSCOM_BUSY; + break; + } - // Start the read. The 'read' bit is forced into the address. Writing - // the PMC_O2P_ADDR_REG starts the read. + // Setup the write. The 'read' bit is set in the address. + scom_cmd->scom_status.status32 = OCCHW_SCOM_PENDING; + scom_cmd->scom_addr = address | OCCHW_SCOM_READ_MASK; - addr.value = address; - addr.fields.o2p_read_not_write = 1; - out32(PMC_O2P_ADDR_REG, addr.value); + // Notify the GPE (by raising an interrupt) that a request is pending + ssx_irq_status_set(OCCHW_IRQ_IPI_SCOM, 1); - // Polling and return. + // Poll until completed or timed out + rc = poll_scom(timeout); - rc = poll_scom(timeout, &cs); + // Extract the data and status out of the scom command block + *data = scom_cmd->scom_data; + scom_status.status32 = scom_cmd->scom_status.status32; - data64.word[0] = in32(PMC_O2P_RECV_DATA_HI_REG); - data64.word[1] = in32(PMC_O2P_RECV_DATA_LO_REG); - *data = data64.value; + ssx_critical_section_exit(&ctx); - ssx_critical_section_exit(&ctx); + if(!rc) + { + //check that the GPE updated the scom status. Normally, + //the gpe won't clear the interrupt until it has updated + //the status field. The exception is if the GPE gets + //reset. + if(scom_status.status32 == OCCHW_SCOM_PENDING) + { + rc = -SCOM_PROTOCOL_ERROR_GETSCOM_RST; + } + else + { + //The SIBRC field of the MSR is where we get the status for + //the last scom operation. + rc = scom_status.sibrc; + } + } - if (rc) { - return rc; - } else { - return cs.fields.o2p_scresp; - } + }while(0); + return rc; } @@ -211,8 +251,8 @@ getscom(uint32_t address, uint64_t *data) *data = 0; } else { - printk("getscom(0x%08x, %p) : Failed with error %d\n", - address, data, rc); + //printk("getscom(0x%08x, %p) : Failed with error %d\n", + // address, data, rc); if (rc > 0) { switch (rc) { @@ -268,44 +308,62 @@ getscom(uint32_t address, uint64_t *data) int _putscom(uint32_t address, uint64_t data, SsxInterval timeout) { - pmc_o2p_addr_reg_t addr; - pmc_o2p_ctrl_status_reg_t cs; - SsxMachineContext ctx; - Uint64 data64; - int rc; - - ssx_critical_section_enter(SSX_CRITICAL, &ctx); - - // Check for a transaction already ongoing - - cs.value = in32(PMC_O2P_CTRL_STATUS_REG); - if (cs.fields.o2p_ongoing) { - ssx_critical_section_exit(&ctx); - return -SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY; - } + SsxMachineContext ctx; + int rc; + occhw_scom_cmd_t *scom_cmd = &OSD_PTR->scom_cmd; + occhw_scom_status_t scom_status; + + do + { + if(address & OCCHW_SCOM_READ_MASK) + { + rc = -SCOM_INVALID_ADDRESS; + break; + } - // Start the write. The 'write' bit is cleared in the address. Here the - // PIB write starts when the PMC_O2P_SEND_DATA_LO_REG is written. + ssx_critical_section_enter(SSX_CRITICAL, &ctx); - addr.value = address; - addr.fields.o2p_read_not_write = 0; - out32(PMC_O2P_ADDR_REG, addr.value); + // Check for a transaction already ongoing + rc = ssx_irq_status_get(OCCHW_IRQ_IPI_SCOM); + if (rc) { + ssx_critical_section_exit(&ctx); + rc = -SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY; + break; + } - data64.value = data; - out32(PMC_O2P_SEND_DATA_HI_REG, data64.word[0]); - out32(PMC_O2P_SEND_DATA_LO_REG, data64.word[1]); - - // Poll and return. + // Setup the write. The 'read' bit is cleared in the address. + scom_cmd->scom_status.status32 = OCCHW_SCOM_PENDING; + scom_cmd->scom_addr = address; + scom_cmd->scom_data = data; - rc = poll_scom(timeout, &cs); + // Notify the GPE (by raising an interrupt) that a request is pending + ssx_irq_status_set(OCCHW_IRQ_IPI_SCOM, 1); - ssx_critical_section_exit(&ctx); + // Poll until completed or timed out + rc = poll_scom(timeout); + scom_status.status32 = scom_cmd->scom_status.status32; - if (rc) { - return rc; - } else { - return cs.fields.o2p_scresp; - } + ssx_critical_section_exit(&ctx); + + if(!rc) + { + //check that the GPE updated the scom status. Normally, + //the gpe won't clear the interrupt until it has updated + //the status field. The exception is if the GPE gets + //reset. + if(scom_status.status32 == OCCHW_SCOM_PENDING) + { + rc = -SCOM_PROTOCOL_ERROR_PUTSCOM_RST; + } + else + { + //The SIBRC field of the MSR is where we get the status for + //the last scom operation. + rc = scom_status.sibrc; + } + } + }while(0); + return rc; } @@ -343,8 +401,8 @@ putscom(uint32_t address, uint64_t data) return rc; } - printk("putscom(0x%08x, 0x%016llx) : Failed with error %d\n", - address, data, rc); + //printk("putscom(0x%08x, 0x%016llx) : Failed with error %d\n", + // address, data, rc); if (rc > 0) { switch (rc) { diff --git a/src/ssx/pgp/pgp_pmc.h b/src/ssx/occhw/occhw_scom.h index 1b372db..847fa90 100755..100644 --- a/src/ssx/pgp/pgp_pmc.h +++ b/src/ssx/occhw/occhw_scom.h @@ -1,20 +1,42 @@ -#ifndef __PGP_PMC_H__ -#define __PGP_PMC_H__ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_scom.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_SCOM_H__ +#define __OCCHW_SCOM_H__ -// $Id: pgp_pmc.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pmc.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file pgp_pmc.h -/// \brief PgP procedures and support for PMC operations +/// \file occhw_scom.h +/// \brief procedures and support for SCOM operations #include "ssx.h" -#include "pgp_common.h" +#include "occhw_common.h" #include "pmc_register_addresses.h" #include "pmc_firmware_registers.h" @@ -62,6 +84,9 @@ putscom(uint32_t address, uint64_t data); #define SCOM_PROTOCOL_ERROR_PUTSCOM 0x00726614 #define SCOM_PROTOCOL_ERROR_GETSCOM_BUSY 0x00726615 #define SCOM_PROTOCOL_ERROR_PUTSCOM_BUSY 0x00726616 +#define SCOM_PROTOCOL_ERROR_PUTSCOM_RST 0x00726617 +#define SCOM_PROTOCOL_ERROR_GETSCOM_RST 0x00726618 +#define SCOM_INVALID_ADDRESS 0x00726619 /// The default timeout for getscom()/putscom() @@ -69,7 +94,7 @@ putscom(uint32_t address, uint64_t data); /// This timeout is enforced by the firmware to guarantee a timeout regardless /// of the hardware setup. /// -/// The expectation is that the PgP hardware will be set up to enforce a PCB +/// The expectation is that the hardware will be set up to enforce a PCB /// timeout of 8K cycles, or 16.384us @ 500 MHz. A timeout only occurs if /// someone erroneously issues a SCOM for a chiplet that does not exist. If /// this happens, then all other SCOMS waiting for the timed-out SCOM to @@ -102,4 +127,4 @@ putscom(uint32_t address, uint64_t data); #define SCOM_ERROR_LIMIT PCB_ERROR_CHIPLET_OFFLINE #endif -#endif // __PGP_PMC_H__ +#endif // __OCCHW_SCOM_H__ diff --git a/src/ssx/occhw/occhw_sramctl.h b/src/ssx/occhw/occhw_sramctl.h new file mode 100644 index 0000000..7f1b1e5 --- /dev/null +++ b/src/ssx/occhw/occhw_sramctl.h @@ -0,0 +1,40 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/occhw_sramctl.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __OCCHW_SRAMCTL_H__ +#define __OCCHW_SRAMCTL_H__ + +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file occhw_sramctl.h +/// \brief SRAMCTL unit header. Local and mechanically generated macros. + +#include "sramctl_register_addresses.h" +#include "sramctl_firmware_registers.h" + +#endif /* __OCCHW_SRAMCTL_H__ */ diff --git a/src/ssx/occhw/ssx_port.h b/src/ssx/occhw/ssx_port.h new file mode 100644 index 0000000..81a52aa --- /dev/null +++ b/src/ssx/occhw/ssx_port.h @@ -0,0 +1,40 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/occhw/ssx_port.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __SSX_PORT_H__ +#define __SSX_PORT_H__ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_port.h +/// \brief The top-level OCCHW environment header for SSX. + +#define HWMACRO_OCC + +#include "ppc405.h" + +#endif /* __SSX_PORT_H__ */ diff --git a/src/ssx/occhw/ssxocchwfiles.mk b/src/ssx/occhw/ssxocchwfiles.mk new file mode 100644 index 0000000..3559ae7 --- /dev/null +++ b/src/ssx/occhw/ssxocchwfiles.mk @@ -0,0 +1,58 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/occhw/ssxocchwfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file ssxoccwhfiles.mk +# +# @brief mk for including occwh object files +# +# @page ChangeLogs Change Logs +# @section ssxoccwhfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## +OCCHW-C-SOURCES = occhw_init.c occhw_irq_init.c occhw_scom.c occhw_ocb.c occhw_pba.c \ + occhw_id.c occhw_centaur.c +OCCHW-S-SOURCES = occhw_cache.S + +OCCHW-TIMER-C-SOURCES = +OCCHW-TIMER-S-SOURCES = + +OCCHW-THREAD-C-SOURCES = +OCCHW-THREAD-S-SOURCES = + +OCCHW-ASYNC-C-SOURCES = occhw_async.c occhw_async_ocb.c \ + occhw_async_pba.c occhw_async_gpe.c +OCCHW-ASYNC-S-SOURCES = + +OCCHW_OBJECTS += $(OCCHW-C-SOURCES:.c=.o) $(OCCHW-S-SOURCES:.S=.o) + diff --git a/src/ssx/pgp/Makefile b/src/ssx/pgp/Makefile deleted file mode 100755 index 417a452..0000000 --- a/src/ssx/pgp/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# $Id: Makefile,v 1.2 2013/12/12 16:12:28 bcbrock Exp $ - -# This Makefile compiles all of the SSX code required for the PgP port -# of SSX. See the "ssx.mk" file in this directory. - -include ssx.mk -include ssxpgpfiles.mk - - -ifeq "$(SSX_TIMER_SUPPORT)" "1" -PGP_OBJECTS += ${PGP-TIMER-C-SOURCES:.c=.o} ${PGP-TIMER-S-SOURCES:.S=.o} -endif - -ifeq "$(SSX_THREAD_SUPPORT)" "1" -PGP_OBJECTS += ${PGP-THREAD-C-SOURCES:.c=.o} ${PGP-THREAD-S-SOURCES:.S=.o} -endif - -ifeq "$(PGP_ASYNC_SUPPORT)" "1" -PGP_OBJECTS += ${PGP-ASYNC-C-SOURCES:.c=.o} ${PGP-ASYNC-S-SOURCES:.S=.o} -endif - - -all: local - $(MAKE) -I ../pgp -C ../ssx - $(MAKE) -I ../pgp -C ../ppc405 - -local: $(PGP_OBJECTS) - - -.PHONY : clean -clean: - rm -f *.o *.d *.d.* *.ps *.pdf - $(MAKE) -I ../pgp -C ../ssx clean - $(MAKE) -I ../pgp -C ../ppc405 clean - -ifneq ($(MAKECMDGOALS),clean) -include $(PGP_OBJECTS:.o=.d) -endif diff --git a/src/ssx/pgp/linkssx.cmd b/src/ssx/pgp/linkssx.cmd deleted file mode 100755 index 0556a03..0000000 --- a/src/ssx/pgp/linkssx.cmd +++ /dev/null @@ -1,499 +0,0 @@ -// $Id: linkssx.cmd,v 1.2 2014/03/14 16:33:45 bcbrock Exp $ - -// This linker script creates SRAM images of SSX applications for PgP. This -// script is processed through the C proprocessor to create -// configuration-dependent images. -// -// All sections with different MMU protection properties are 1KB-aligned, even -// when linked in real-addressing mode. -// -// NB: According to *info* manual for ld, it should not be necessary to specify -// the '.' in the section commands, e.g., -// -// .data.startup . : { *(.data.startup) } > sram -// -// However without these the sections are not aligned properly, as the linker -// seems to ignore the LC and move the section 'backwards' until it abuts -// (aligned) with the previous one. -// -// Info on PPC binaries: -// http://devpit.org/wiki/Debugging_PowerPC_ELF_Binaries - -// Need to do this so that elf32-powerpc is not modified! -#undef powerpc - -#ifndef INITIAL_STACK_SIZE -#define INITIAL_STACK_SIZE 2000 -#endif - -OUTPUT_FORMAT(elf32-powerpc); - -// Define the beginning of SRAM, the location of the PowerPC exception -// vectors (must be 64K-aligned) and the location of the boot branch. - -// 512 KB SRAM at the top of the 32-bit address space - -#define origin 0xfff80000 -#define vectors 0xfff80000 -#define reset 0xffffffec -#define sram_available (reset - origin) -#define sram_size 0x00080000 - -// The SRAM controller aliases the SRAM at 8 x 128MB boundaries to support -// real-mode memory attributes using DCCR, ICCR etc. Noncacheable access is -// the next-to-last 128MB PPC405 region. Write-though access is the -// next-to-next-to-last 128MB PPC405 region - -#define noncacheable_offset 0x08000000 -#define noncacheable_origin (origin - 0x08000000) - -#define writethrough_offset 0x10000000 -#define writethrough_origin (origin - 0x10000000) - -// Define SSX kernel text sections to be packed into nooks and crannies of -// the exception vector area. An option is provided _not_ to pack, to help -// better judge the best way to pack. Note that any code eligible for packing -// is considered 'core' code that will be needed by the application at -// runtime. Any header data is _always_ packed into .vectors_0000 however. -// -// Note that in order to support MMU protection, we can't pack data along -// with the text. All of the packed data sections are thus left empty. - - -// .vectors_0000 - -#define text_0000 \ -*(.vectors_0000) - -#define data_0000 - - -// .vectors_0100 - -#define text_0100 \ -ppc405_core.o(.text) \ -ppc405_irq_core.o(.text) - -#define data_0100 - - -// .vectors_0c00 - -#if SSX_TIMER_SUPPORT -#define text_0c00_conditional -#else -#define text_0c00_conditional -#endif - - -#define text_0c00 \ -text_0c00_conditional \ -ppc405_cache_core.o(.text) - -#define data_0c00 - - -// .vectors_0f00 - -#if SSX_TIMER_SUPPORT - -#if SSX_THREAD_SUPPORT -#define text_0f00_conditional \ -ssx_timer_init.o(.text) \ -ssx_timer_core.o(.text) \ -ssx_semaphore_core.o(.text) -#endif /* SSX_THREAD_SUPPORT */ - -#if !SSX_THREAD_SUPPORT -#define text_0f00_conditional \ -ssx_timer_init.o(.text) \ -ssx_timer_core.o(.text) -#endif /* !SSX_THREAD_SUPPORT */ - -#else /* SSX_TIMER_SUPPORT */ - -#define text_0f00_conditional -#endif /* SSX_TIMER_SUPPORT */ - -#define text_0f00 \ -text_0f00_conditional - -#define data_0f00 - -// .vectors_2000 - -#if SSX_THREAD_SUPPORT -#define thread_text \ -ssx_thread_init.o(.text) \ -ssx_thread_core.o(.text) \ -ppc405_irq_init.o(.text) \ -ppc405_thread_init.o(.text) \ -ssx_semaphore_init.o(.text) -#else -#define thread_text -#endif - -#if PPC405_MMU_SUPPORT -#define mmu_text \ -ppc405_mmu.o(.text)\ -ppc405_mmu_asm.o(.text) -#else -#define mmu_text -#endif - -#define text_2000 \ -pgp_irq_init.o(.text) \ -ppc405_cache_init.o(.text) \ -ppc405_breakpoint.o(.text) \ -pgp_cache.o(.text) \ -ssx_stack_init.o(.text) \ -thread_text \ -mmu_text \ -pgp_async.o(.text) \ -pgp_async_pore.o(.text) \ -pgp_async_ocb.o(.text) \ -pgp_async_pba.o(.text) \ -pgp_pmc.o(.text) \ -pgp_ocb.o(.text) \ -pgp_pba.o(.text) \ -pgp_id.o(.text) \ -pgp_centaur.o(.text) \ -ppc405_lib_core.o(.text) \ -ssx_core.o(.text) \ - -#define data_2000 - -// .vectors_0000 is always packed with header information - -#define pack_0000 text_0000 data_0000 -#define nopack_0000 - -#ifndef NO_PACK_SSX - -#define pack_0100 text_0100 data_0100 -#define nopack_0100 - -#define pack_0c00 text_0c00 data_0c00 -#define nopack_0c00 - -#define pack_0f00 text_0f00 data_0f00 -#define nopack_0f00 - -#define pack_2000 text_2000 data_2000 -#define nopack_2000 - -#else - -#define pack_0100 -#define nopack_0100 text_0100 data_0100 - -#define pack_0c00 -#define nopack_0c00 text_0c00 data_0c00 - -#define pack_0f00 -#define nopack_0f00 text_0f00 data_0f00 - -#define pack_2000 -#define nopack_2000 text_2000 data_2000 - -#endif - -#define init_text \ -ssx_init.o(.text) \ -ppc405_boot.o(.text) \ -ppc405_init.o(.text) \ -pgp_init.o(.text) - -// Define memory areas. - -MEMORY -{ - sram : ORIGIN = origin, LENGTH = sram_available - noncacheable : ORIGIN = noncacheable_origin, LENGTH = sram_available - writethrough : ORIGIN = writethrough_origin, LENGTH = sram_available - boot : ORIGIN = reset, LENGTH = 20 -} - -// NB: The code that sets up the MMU assumes that the linker script provides a -// standard set of symbols that define the base address and size of each -// expected section. Any section with a non-0 size will be mapped in the MMU -// using protection attributes appropriate for the section. All sections -// requiring different MMU attributes must be 1KB-aligned. - -SECTIONS -{ - . = origin; - . = vectors; - - _MEMORY_ORIGIN = .; - _MEMORY_SIZE = sram_size; - - //////////////////////////////// - // Text0 - //////////////////////////////// - - // Low-memory kernel code and any other code that would benefit from being - // resident in lower-latency SRAM - - _TEXT0_SECTION_BASE = .; - _PPC405_VECTORS_BASE = .; - - .exceptions . : { - ___vectors = .; - ppc405_exceptions.o(.vectors_0000) - pack_0000 - . = ___vectors + 0x0100; - ppc405_exceptions.o(.vectors_0100) - pack_0100 - . = ___vectors + 0x0c00; - ppc405_exceptions.o(.vectors_0c00) - pack_0c00 - . = ___vectors + 0x0f00; - ppc405_exceptions.o(.vectors_0f00) - pack_0f00 - . = ___vectors + 0x2000; - ppc405_exceptions.o(.vectors_2000) - pack_2000 - } > sram - - // If we're not packing, then place 'core' code immediately after the - // exception vectors. - - .nopack . : { nopack_0000 nopack_0100 nopack_0c00 nopack_0f00 nopack_2000 } > sram - - . = ALIGN(1024); - _TEXT0_SECTION_SIZE = . - _TEXT0_SECTION_BASE; - - //////////////////////////////// - // Noncacheable and Write-through Data - //////////////////////////////// - - // Non-cacheable and write-through data is placed in low memory to - // improve latency. PORE-private text and data is also placed here. PORE - // text and data are segregated to enable relocated PORE disassembly of - //.text.pore. PORE text is read-only to OCC, however PORE data is writable - // by OCC to allow shared data structures (e.g., PTS). - - // When running without the MMU we need to carefully arrange things such - // that the noncacheable and writethrough data is linked at the correct - // aliased VMA while remaining loaded in contiguous LMA addresses. - -#if PPC405_MMU_SUPPORT - -#define ALIASED_SECTION(s) s . : {*(s)} > sram - -#else - -#define ALIASED_SECTION(s) \ - _LMA = . + _lma_offset; \ - s . : AT (_LMA) {*(s)} - -#endif - -#if !PPC405_MMU_SUPPORT - . = . - noncacheable_offset; - _lma_offset = noncacheable_offset; -#endif - - _NONCACHEABLE_RO_SECTION_BASE = .; - - ALIASED_SECTION(.noncacheable_ro) - ALIASED_SECTION(.text.pore) - - . = ALIGN(1024); - _NONCACHEABLE_RO_SECTION_SIZE = . - _NONCACHEABLE_RO_SECTION_BASE; - - - _NONCACHEABLE_SECTION_BASE = .; - - ALIASED_SECTION(.noncacheable) - ALIASED_SECTION(.data.pore) - - . = ALIGN(1024); - _NONCACHEABLE_SECTION_SIZE = . - _NONCACHEABLE_SECTION_BASE; - - -#if !PPC405_MMU_SUPPORT - . = . + noncacheable_offset - writethrough_offset; - _lma_offset = writethrough_offset; -#endif - - - _WRITETHROUGH_SECTION_BASE = .; - - ALIASED_SECTION(.writethrough) - - . = ALIGN(1024); - _WRITETHROUGH_SECTION_SIZE = . - _WRITETHROUGH_SECTION_BASE; - -#if !PPC405_MMU_SUPPORT - . = . + writethrough_offset; -#endif - - - //////////////////////////////// - // Read-only Data - //////////////////////////////// - - // Accesses of read-only data may or may not benefit from being in fast - // SRAM - we'll give it the benefit of the doubt. - - _RODATA_SECTION_BASE = .; - - // SDA2 constant sections .sdata2 and .sbss2 must be adjacent to each - // other. Our SDATA sections are small so we'll use strictly positive - // offsets. - - _SDA2_BASE_ = .; - .sdata2 . : { *(.sdata2) } > sram - .sbss2 . : { *(.sbss2) } > sram - - // The .rodata.vclcommand section contains read-only VclCommandRecord for - // the benefit of the vcl_console() command interpreter. - - _VCL_COMMAND_SECTION_BASE = .; - .rodata.vclcommand . : { *(.rodata.vclcommand) } > sram - _VCL_COMMAND_SECTION_SIZE = . - _VCL_COMMAND_SECTION_BASE; - - // The .rodata.vclthread section contains read-only VclThreadRecord for the - // benefit of the thread command. - - _VCL_THREAD_SECTION_BASE = .; - .rodata.vclthread . : { *(.rodata.vclthread) } > sram - _VCL_THREAD_SECTION_SIZE = . - _VCL_THREAD_SECTION_BASE; - - // The .rodata.vclpackage section contains read-only char* pointers for the - // benefit of the package command. - - _VCL_PACKAGE_SECTION_BASE = .; - .rodata.vclpackage . : { *(.rodata.vclpackage) } > sram - _VCL_PACKAGE_SECTION_SIZE = . - _VCL_PACKAGE_SECTION_BASE; - - // Other read-only data. - - .rodata . : { *(.rodata*) *(.got2) } > sram - - . = ALIGN(1024); - _RODATA_SECTION_SIZE = . - _RODATA_SECTION_BASE; - - //////////////////////////////// - // Text1 - //////////////////////////////// - - // The default text section - - _TEXT1_SECTION_BASE = .; - - // Initialization text. If we ever do a scheme to get rid of - // initialization text then this will have to be moved if we're also doing - // MMU protection. - - .itext . : { init_text } > sram - - // Other text - // It's not clear why boot.S is generating empty .glink,.iplt - - .otext . : { *(.text) *(.text.startup)} > sram - .glink . : { *(.glink) } > sram - - . = ALIGN(1024); - _TEXT1_SECTION_SIZE = . - _TEXT1_SECTION_BASE; - - //////////////////////////////// - // Read-write Data - //////////////////////////////// - - _DATA_SECTION_BASE = .; - - // SDA sections .sdata and .sbss must be adjacent to each - // other. Our SDATA sections are small so we'll use strictly positive - // offsets. - - _SDA_BASE_ = .; - .sdata . : { *(.sdata) } > sram - .sbss . : { *(.sbss) } > sram - - // Other read-write data - // It's not clear why boot.S is generating empty .glink,.iplt - - .rela . : { *(.rela*) } > sram - .rwdata . : { *(.data) *(.bss) } > sram - .iplt . : { *(.iplt) } > sram - - - // Initialization-only data. This includes the stack of main, the data - // structures declared by INITCALL, and any other data areas that can be - // reclaimed to the heap after initialization. - // - // NB: If we ever do reclaim this space, we need to modify the concept of - // executable free space. - - _INIT_ONLY_DATA_BASE = .; - - _SSX_INITIAL_STACK_LIMIT = .; - . = . + INITIAL_STACK_SIZE; - _SSX_INITIAL_STACK = . - 1; - - _INITCALL_SECTION_BASE = .; - .data.initcall . : { *(.data.initcall) } > sram - _INITCALL_SECTION_SIZE = . - _INITCALL_SECTION_BASE; - - .data.startup . : { *(.data.startup) } > sram - - _INIT_ONLY_DATA_SIZE = . - _INIT_ONLY_DATA_BASE; - - //////////////////////////////// - // Free Space - //////////////////////////////// - - // If the configuration allows executing from free space - i.e., - // malloc()-ing a buffer and loading and executing code from it - then the - // free space is separated and aligned so that it can be marked executable. - // Otherwise it is simply read/write like the normal data sections. - -#ifndef EXECUTABLE_FREE_SPACE -#define EXECUTABLE_FREE_SPACE 0 -#endif - -#if PPC405_MMU_SUPPORT && EXECUTABLE_FREE_SPACE - . = ALIGN(1024); -#endif - - // The free space available to the program starts here. This space does - // not include the initial stack used by the boot loader and main(). The - // initial stack space is considered part of the free 'section' for MMU - // purposes. Free space is always 8-byte aligned. - // - // Note that there is no data after _SSX_FREE_START. When binary images - // are created they can be padded to _SSX_FREE_START to guarantee - // that .bss and COMMON data are zeroed, and that the images contain an - // even multiple of 8 bytes (required for HW loaders). - - . = ALIGN(8); - _EX_FREE_SECTION_BASE = .; - _SSX_FREE_START = .; - -#if EXECUTABLE_FREE_SPACE - _DATA_SECTION_SIZE = . - _DATA_SECTION_BASE; - _EX_FREE_SECTION_SIZE = 0 - _EX_FREE_SECTION_BASE; -#else - _DATA_SECTION_SIZE = 0 - _DATA_SECTION_BASE; - _EX_FREE_SECTION_SIZE = 0; -#endif - - //////////////////////////////// - // Applet areas - //////////////////////////////// - - // These symbols are currently unused, but required to be defined. - - _APPLET0_SECTION_BASE = 0; - _APPLET0_SECTION_SIZE = 0; - _APPLET1_SECTION_BASE = 0; - _APPLET1_SECTION_SIZE = 0; - - // The final 16 bytes of memory are reserved for the hardware boot branch - - _SSX_FREE_END = reset - 1; -} - diff --git a/src/ssx/pgp/pgp_async_pore.c b/src/ssx/pgp/pgp_async_pore.c deleted file mode 100755 index 5f9b425..0000000 --- a/src/ssx/pgp/pgp_async_pore.c +++ /dev/null @@ -1,644 +0,0 @@ -// $Id: pgp_async_pore.c,v 1.5 2014/05/14 13:35:43 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_async_pore.c,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_async_pore.c -/// \brief PgP "async" drivers for PORE engines - -#include "ssx.h" - -//////////////////////////////////////////////////////////////////////////// -// Global Data -//////////////////////////////////////////////////////////////////////////// - -// The PORE queue objects. - -PoreQueue G_pore_gpe0_queue; -PoreQueue G_pore_gpe1_queue; -PoreQueue G_pore_slw_queue; - - -//////////////////////////////////////////////////////////////////////////// -// Local Data -//////////////////////////////////////////////////////////////////////////// - -/// PoreFlex entry point - See G_pore_flex_table. - -static uint32_t G_pore_flex_entry0 = PORE_BRAD_D0; - - -/// Entry 0 of the PoreFlex branch table -/// -/// This variable is the only thing we represent of the branch table for PORE -/// flex requests. PoreFlex requests are forbidden from using PORE error -/// handlers. Therefore they don't require the 60 redundant bytes of error -/// handler entry points. They also only run trigger slot 0, and begin -/// execution with a BRAD D0, so the only thing we represent is a single BRAD -/// D0 instruction. - -static uint32_t* G_pore_flex_table = &G_pore_flex_entry0 - (PORE_ERROR_SLOTS * 3); - - -//////////////////////////////////////////////////////////////////////////// -// PoreQueue -//////////////////////////////////////////////////////////////////////////// - -/// Create (initialize) a PoreQueue -/// -/// \param queue An uninitialized of otherwise idle PoreQueue -/// -/// \param engine The identifier of a PORE engine associated with this queue. -/// -/// This API initializes the PoreQueue structure and also initializes the -/// underlying PORE hardware to run in the OCC environment. Neither the -/// branch table nor the error modes are specified here - those are considered -/// application-specific functions that are set up each time a job is run on -/// the engine. -/// -/// \retval 0 Success -/// -/// \retval -ASYNC_INVALID_OBJECT_PORE_QUEUE The \a queue was NULL (0). -/// -/// \retval -ASYNC_INVALID_ENGINE_PORE The \a engine is not a (valid) -/// PORE engine. - -int -pore_queue_create(PoreQueue *queue, int engine) -{ - pore_control_t control; - - if (SSX_ERROR_CHECK_API) { - SSX_ERROR_IF(queue == 0, ASYNC_INVALID_OBJECT_PORE_QUEUE); - SSX_ERROR_IF(!(engine & ASYNC_ENGINE_PORE), ASYNC_INVALID_ENGINE_PORE); - } - - async_queue_create(&(queue->queue), engine); - - switch (engine) { - - case ASYNC_ENGINE_PORE_GPE0: - queue->oci_base = PORE_GPE0_OCI_BASE; - queue->irq = PGP_IRQ_PORE_GPE0_COMPLETE; - queue->error_irq = PGP_IRQ_PORE_GPE0_ERROR; - queue->oci_master = OCI_MASTER_ID_PORE_GPE; - break; - - case ASYNC_ENGINE_PORE_GPE1: - queue->oci_base = PORE_GPE1_OCI_BASE; - queue->irq = PGP_IRQ_PORE_GPE1_COMPLETE; - queue->error_irq = PGP_IRQ_PORE_GPE1_ERROR; - queue->oci_master = OCI_MASTER_ID_PORE_GPE; - break; - - case ASYNC_ENGINE_PORE_SLW: - queue->oci_base = PORE_SLW_OCI_BASE; - queue->irq = PGP_IRQ_PORE_SW_COMPLETE; - queue->error_irq = PGP_IRQ_PORE_SW_ERROR; - queue->oci_master = OCI_MASTER_ID_PORE_SLW; - break; - - default: - SSX_PANIC(ASYNC_BUG_PORE_AT_CREATE); - } - - // PORE engine setup - // - // Force the PORE to stop and set it up for OCC control. Neither the - // breakpoint address nor the trap enable setting are modified in case - // they are being controlled from Simics or a hardware debugger ab initio. - // - // Register field settings: - // - // The scanclk ratio is not modified. - // The EXE-Trigger register is unlocked - // The freeze action is not modified - // Instruction parity is ignored - // The PIB parity checking setting is not modified - // The TRAP enable is not modified - // The breakpoint address is not modified - - control.value = in64(queue->oci_base + PORE_CONTROL_OFFSET); - - control.fields.start_stop = 1; - control.fields.lock_exe_trig= 0; - control.fields.check_parity = 0; - - out64(queue->oci_base + PORE_CONTROL_OFFSET, control.value); - - return 0; -} - - -// The interrupt handler for asynchronous PORE errors -// -// The PORE interrupts are disabled here, then cleared and re-enabled when the -// next job runs. This is to protect against "phantom" interrupts caused by -// PORE freeze-on-checkstop behavior. - -SSX_IRQ_FAST2FULL(pore_async_error_handler, pore_async_error_handler_full); - -void -pore_async_error_handler_full(void *arg, SsxIrqId irq, int priority) -{ - PoreQueue* queue = (PoreQueue*)arg; - - ssx_irq_disable(queue->irq); - ssx_irq_disable(queue->error_irq); - - async_error_handler((AsyncQueue *)arg, ASYNC_REQUEST_STATE_FAILED); -} - - -// The interrupt handler for asynchronous PORE requests -// -// The PORE interrupts are disabled here, then cleared and re-enabled when the -// next job runs. This is to protect against "phantom" interrupts caused by -// PORE freeze-on-checkstop behavior. -// -// Note that if the system checkstops and freezes the PORE we will get a -// normal completion interrupt. Therefore we have to check to see if the -// completion is associated with a freeze, and if so, fail the job. - -SSX_IRQ_FAST2FULL(pore_async_handler, pore_async_handler_full); - -void -pore_async_handler_full(void *arg, SsxIrqId irq, int priority) -{ - PoreQueue* queue = (PoreQueue*)arg; - pore_status_t status; - - status.value = in64(queue->oci_base + PORE_STATUS_OFFSET); - if (status.fields.freeze_action) { - - pore_async_error_handler_full(arg, irq, priority); - - } else { - - ssx_irq_disable(queue->irq); - ssx_irq_disable(queue->error_irq); - - async_handler((AsyncQueue *)arg); - } -} - - -//////////////////////////////////////////////////////////////////////////// -// PoreRequest -//////////////////////////////////////////////////////////////////////////// - -/// Create (initialize) the PoreRequest base class -/// -/// \param request An uninitialized or otherwise idle PoreRequest. -/// -/// \param queue An initialized PoreQueue -/// -/// \param table The PORE branch table to install prior to kicking off the -/// engine. All PoreFlex jobs use a common (stubbed) table. PoreFixed jobs -/// must supply a fully-formed table. -/// -/// \param error_mask The initial value of the PORE ERROR_MASK register to be -/// installed before kicking off the engine. -/// -/// \param entry_point The entry point address of the routine. For PoreFlex -/// this entry point will be non-0 and will be inserted into D0, as PoreFlex -/// jobs are kicked off by BRAD D0. For PoreFixed this parameter will be zero -/// and ignored. -/// -/// \param start_vector The TBAR start vector to execute. This will always be -/// 0 for PoreFlex. -/// -/// \param parameter The single 32-bit parameter to the PORE program. This -/// value is stored in the low-order part of the \c EXE_TRIGGER register -/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER -/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as -/// this is the hardware usage for hardware-initiated PORE-SLW routines.) -/// -/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request -/// will be governed by a private watchdog timer that will cancel a queued job -/// or kill a running job if the hardware operation does not complete before -/// it times out. -/// -/// \param callback The callback to execute when the PORE program completes, -/// or NULL (0) to indicate no callback. -/// -/// \param arg The parameter to the callback routine; ignored if the \a -/// callback is NULL. -/// -/// \param options Options to control request priority and callback context. -/// -/// This routine has no way to know if the PoreRequest structure is currently -/// in use, so this API should only be called on uninitialized or otherwise -/// idle PoreRequest structures. -/// -/// \retval 0 Success -/// -/// \retval -ASYNC_INVALID_OBJECT_PORE_REQUEST The \a request was NULL (0) -/// or the \a queue was NULL (0) or not a PoreQueue. -/// -/// \retval -ASYNC_INVALID_ARGUMENT_PORE_REQUEST The \a start_vector is invalid or any of -/// the parameters that represent OCI addresses are not 4-byte aligned, , or -/// the \a table was null. -/// -/// See async_request_create() for other errors that may be returned by this -/// call. - -int -pore_request_create(PoreRequest *request, - PoreQueue *queue, - PoreBraia* table, - uint32_t error_mask, - uint32_t entry_point, - int start_vector, - uint32_t parameter, - SsxInterval timeout, - AsyncRequestCallback callback, - void *arg, - int options) -{ - AsyncQueue *async_queue = (AsyncQueue *)queue; - int rc; - pore_exe_trigger_t etr; - - if (SSX_ERROR_CHECK_API) { - SSX_ERROR_IF(!(async_queue->engine & ASYNC_ENGINE_PORE), - ASYNC_INVALID_OBJECT_PORE_REQUEST); - SSX_ERROR_IF((start_vector < 0) || - (start_vector >= PORE_TRIGGER_SLOTS) || - ((uint32_t) table % 4) || - (entry_point % 4) || - (table == 0), - ASYNC_INVALID_ARGUMENT_PORE_REQUEST); - } - - rc = async_request_create(&(request->request), - async_queue, - pore_run_method, - pore_error_method, - timeout, - callback, - arg, - options); - - if (!rc) { - request->table = table; - request->error_mask = error_mask; - request->entry_point = entry_point; - request->parameter = parameter; - etr.value = 0; - etr.fields.start_vector = start_vector; - request->exe_trigger = etr.words.high_order; - } - - return rc; -} - - -// Start a PoreRequest on a PORE -// -// \param async_request A PoreRequest upcast to an AsyncRequest. -// -// This is an internal API. At entry both the completion and error interrupts -// are disabled and may show status that needs to be cleared before they are -// re-enabled. -// -// This routine implements a simple procedure: -// -// - Check to make sure the PORE is not frozen due to a checkstop, and if so, -// collect FFDC and immediately fail the job. -// -// Otherwise: -// -// - Reset the PORE engine to clear up any error status that may remain from -// the last job . -// - Install the TBAR (Table Base Address Register) from the request as an OCI -// address -// - Set the EMR (Error Mask Register) from the request -// - Install the parameter (ETR[32:63]) -// - If the entry point is non-0 then this is a PoreFlex job that is kicked -// off by a BRAD D0, and the entry point is installed in D0 as a full OCI -// address. -// - Clear pending interrupt status -// - Hit ETR[0:31] to start the job. -// - Enable interrupts. -// -// If the PORE is frozen due to a system checkstop we fail the job immediately -// right here. Note that there is still a small window where the system may -// checkstop and the PORE may freeze after this check. Unfortunately the PORE -// design locks out register writes while frozen, and instead of reporting -// write access attempts as bus errors, silently ignores them and simply sets -// a FIR bit. Originally the "frozen" check was done last to shrink the -// window, however this practically guarantees these FIRs in a checkstopped -// system (which the FW team finds problematic), so the check was moved to the -// front of the procedure. (SW256621). -// -// Note that PORE interrupts remain masked unless the job starts successfully. - -int -pore_run_method(AsyncRequest *async_request) -{ - PoreQueue *queue = (PoreQueue*)(async_request->queue); - PoreRequest *request = (PoreRequest*)async_request; - pore_status_t status; - pore_reset_t reset; - uint32_t oci_base; - int rc; - - oci_base = queue->oci_base; - - status.value = in64(oci_base + PORE_STATUS_OFFSET); - if (status.fields.freeze_action) { - - pore_error_method(async_request); - async_request->completion_state = ASYNC_REQUEST_STATE_FAILED; - rc = -ASYNC_REQUEST_COMPLETE; - - } else { - - reset.value = 0; - reset.fields.fn_reset = 1; - out32(oci_base + PORE_RESET_OFFSET, reset.value); - - out32(oci_base + PORE_TABLE_BASE_ADDR_OFFSET, PORE_ADDRESS_SPACE_OCI); - out32(oci_base + PORE_TABLE_BASE_ADDR_OFFSET + 4, - (uint32_t)(request->table)); - out32(oci_base + PORE_ERROR_MASK_OFFSET, request->error_mask); - out32(oci_base + PORE_EXE_TRIGGER_OFFSET + 4, request->parameter); - - if (request->entry_point != 0) { - out32(oci_base + PORE_SCRATCH1_OFFSET, PORE_ADDRESS_SPACE_OCI); - out32(oci_base + PORE_SCRATCH1_OFFSET + 4, request->entry_point); - } - - ssx_irq_status_clear(queue->irq); - ssx_irq_status_clear(queue->error_irq); - - out32(oci_base + PORE_EXE_TRIGGER_OFFSET, request->exe_trigger); - - ssx_irq_enable(queue->irq); - ssx_irq_enable(queue->error_irq); - rc = 0; - } - - return rc; -} - - -// PORE FFDC collection -// -// \param async_request A PoreRequest upcast to an AsyncRequest -// -// This is an internal API, called from an interrupt context when a PORE -// engine signals an error interrupt. See the comments for PoreFfdc for a -// description of why this particular set of data is collected. -// -// PORE error handling procedure: -// -// - Collect FFDC from the PLB arbiter -// -// - Collect FFDC from the failing engine -// -// Currently all PORE errors are treated as recoverable - -/// \todo Consider analyzing the errors to determine if the error should be -/// considered fatal. - -int -pore_error_method(AsyncRequest *async_request) -{ - PoreQueue *queue = (PoreQueue*)(async_request->queue); - PoreRequest *request = (PoreRequest*)async_request; - uint32_t oci_base; - PoreFfdc* ffdc; - - oci_base = queue->oci_base; - ffdc = &(request->ffdc); - - oci_ffdc(&(ffdc->oci_ffdc), queue->oci_master); - - ffdc->debug[0] = in64(oci_base + PORE_DBG0_OFFSET); - ffdc->debug[1] = in64(oci_base + PORE_DBG1_OFFSET); - ffdc->address[0] = in32(oci_base + PORE_OCI_BASE_ADDRESS0_OFFSET + 4); - ffdc->address[1] = in32(oci_base + PORE_OCI_BASE_ADDRESS1_OFFSET + 4); - ffdc->ibuf[0] = in32(oci_base + PORE_IBUF_01_OFFSET); - ffdc->ibuf[1] = in32(oci_base + PORE_IBUF_01_OFFSET + 4); - ffdc->ibuf[2] = in32(oci_base + PORE_IBUF_2_OFFSET); - - return 0; -} - - -/// Create (initialize) a PoreBraia branch table entry -/// -/// \param instr A pointer to the BRAIA instruction to initialize. Use the -/// macros PORE_ERROR_BRANCH(table, n) and PORE_ENTRY_BRANCH(table, n) to -/// select one of 5 error branches or one of 16 entry point branches in a PORE -/// branch table. -/// -/// \param address The 32-bit OCI address of the error routine or entry point. -/// -/// This routine initializes the given entry of a PORE branch table with an -/// OCI-based BRAIA instruction, them flushes the entry from the D-Cache. - -// Note that we don't know the alignment of the jump table, so we need to -// flush both the first and last jump address to ensure that the BRAI is -// completely flushed. This assumes (correctly) that uint32_t are at least -// 4-byte aligned. - -void -pore_braia_create(PoreBraia* instr, uint32_t address) { - instr->word[0] = PORE_BRAI; - instr->word[1] = PORE_ADDRESS_SPACE_OCI; - instr->word[2] = address; - dcache_flush_line(&(instr->word[0])); - dcache_flush_line(&(instr->word[2])); -} - - -//////////////////////////////////////////////////////////////////////////// -// PoreFlex -//////////////////////////////////////////////////////////////////////////// - -/// Create (initialize) a flex-mode PORE request -/// -/// \param request An uninitialized or otherwise idle PoreFlex. -/// -/// \param queue A pointer to a PoreQueue -/// -/// \param entry_point The entry point of the PORE program. This must be a -/// 32-bit, 4-byte aligned byte address in OCI space. The PoreEntryPoint -/// typedef is provided to declare external PORE entry points. Note that an \a -/// entry_point of 0 is considered an error - although it \e is conceivably a -/// legal OCI address in mainstore via the PBA. -/// -/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request -/// will be governed by a private watchdog timer that will cancel a queued job -/// or kill a running job if the hardware operation does not complete before -/// it times out. -/// -/// \param parameter The single 32-bit parameter to the PORE program. This -/// value is stored in the high-order part of the \c EXE_TRIGGER register -/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER -/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as -/// this is the hardware usage for hardware-initiated PORE-SLW routines.) -/// -/// \param callback The callback to execute when the PORE program completes, -/// or NULL (0) to indicate no callback. -/// -/// \param arg The parameter to the callback routine; ignored if the \a -/// callback is NULL. -/// -/// \param options Options to control request priority and callback context. -/// -/// This routine has no way to know if the PoreFlex structure is currently -/// in use, so this API should only be called on uninitialized or -/// otherwise idle PoreFlex structures. -/// -/// \retval 0 Success -/// -/// See pore_request_create() for error return codes that may be returned by -/// this call. - -int -pore_flex_create(PoreFlex *request, - PoreQueue *queue, - PoreEntryPoint entry_point, - uint32_t parameter, - SsxInterval timeout, - AsyncRequestCallback callback, - void *arg, - int options) -{ - uint32_t emr; - - // PoreFlex jobs run w/o error handlers, and ignore sleeping cores. All - // errors are signalled on both error outputs of all PORE engines. - - emr = (PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 | - PORE_ERROR_MASK_ENABLE_ERR_OUTPUT1 | - PORE_ERROR_MASK_ENABLE_ERR_OUTPUT2 | - PORE_ERROR_MASK_ENABLE_ERR_OUTPUT3 | - PORE_ERROR_MASK_ENABLE_ERR_OUTPUT4 | - PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 | - PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 | - PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 | - PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 | - PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 | - PORE_ERROR_MASK_STOP_EXE_ON_ERROR0 | - PORE_ERROR_MASK_STOP_EXE_ON_ERROR1 | - PORE_ERROR_MASK_STOP_EXE_ON_ERROR2 | - PORE_ERROR_MASK_STOP_EXE_ON_ERROR3 | - PORE_ERROR_MASK_STOP_EXE_ON_ERROR4) >> 32; - - return pore_request_create((PoreRequest*)request, - queue, - (PoreBraia*)G_pore_flex_table, - emr, - (uint32_t)entry_point, - 0, - parameter, - timeout, - callback, - arg, - options); -} - - -//////////////////////////////////////////////////////////////////////////// -// PoreFixed -//////////////////////////////////////////////////////////////////////////// - -/// Create (initialize) a fixed-mode PORE request -/// -/// \param request An uninitialized or otherwise idle PoreFixed request. -/// -/// \param queue A PoreQueue capable of running fixed requests. -/// -/// \param table A PORE branch table containing all of the error handler and -/// entry point assignments required for the request. -/// -/// \param error_mask A value that will be loaded into the high-order 32-bits -/// of the PORE Error Mask Register to control error behavior. -/// -/// \param start_vector The branch table slot reserved for this request. -/// -/// \param parameter The single 32-bit parameter to the PORE program. This -/// value is stored in the high-order part of the \c EXE_TRIGGER register -/// prior to initiating the PORE program. (This part of the \c EXE_TRIGGER -/// register is referred to as the 'Chiplet Select Mask' in PORE docs., as -/// this is the hardware usage for hardware-initiated PORE-SLW routines.) -/// -/// \param timeout If not specified as SSX_WAIT_FOREVER, then this request -/// will be governed by a private watchdog timer that will cancel a queued job -/// or kill a running job if the hardware operation does not complete before -/// it times out. -/// -/// \param callback The callback to execute when the PORE program completes, -/// or NULL (0) to indicate no callback. -/// -/// \param arg The parameter to the callback routine; ignored if the \a -/// callback is NULL. -/// -/// \param options Options to control request priority and callback context. -/// -/// This routine has no way to know if the PoreFixed structure is currently -/// in use, so this API should only be called on uninitialized or -/// otherwise idle PoreFlex structures. -/// -/// \retval 0 Success -/// -/// See pore_request_create() for error return codes that may be returned by -/// this call. - -int -pore_fixed_create(PoreFixed *request, - PoreQueue *queue, - PoreBraia* table, - uint32_t error_mask, - int start_vector, - uint32_t parameter, - SsxInterval timeout, - AsyncRequestCallback callback, - void *arg, - int options) -{ - return pore_request_create((PoreRequest*)request, - queue, - table, - error_mask, - 0, - start_vector, - parameter, - timeout, - callback, - arg, - options); -} - - -//////////////////////////////////////////////////////////////////////////// -// Initialization -//////////////////////////////////////////////////////////////////////////// - -// Due to the fact that PORE signals a "complete" interrupt on a freeze event -// (i.e., a checkstop, even if PORE is not running), we can not enable PORE -// interrupts globally. They need to be carefully managed to avoid "phantom -// interrupt" panics from async_handler(). - -void -async_pore_initialize(PoreQueue *queue,int engine) -{ - pore_queue_create(queue, engine); - async_edge_handler_setup(pore_async_handler, - (void *)queue, - queue->irq, SSX_CRITICAL); - async_edge_handler_setup(pore_async_error_handler, - (void *)queue, - queue->error_irq, SSX_CRITICAL); -} - - - diff --git a/src/ssx/pgp/pgp_centaur.c b/src/ssx/pgp/pgp_centaur.c deleted file mode 100644 index 85a0dd3..0000000 --- a/src/ssx/pgp/pgp_centaur.c +++ /dev/null @@ -1,644 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/ssx/pgp/pgp_centaur.c $ */ -/* */ -/* OpenPOWER OnChipController Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: pgp_centaur.c,v 1.6 2015/01/27 17:56:26 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_centaur.c,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_centaur.c -/// \brief Support for Centaur access and configuration from OCC. -/// -/// Generic PBA generated PowerBus Address in pictures and words: -/// -/// \code -/// -/// 1 2 3 4 5 6 -/// 0123456789012345678901234567890123456789012345678901234567890123 -/// | | | | | | | | | | | | | | | -/// -/// ..............B-------BX------------XO-----OA------------------A -/// -/// .: Unused -/// B: Direct from PBA BAR, bits 14:22 -/// X: If PBA BAR MASK 23:36 == 0, then PBA BAR 23:36 -/// Else Extended Address 0:13 -/// O: If PBA BAR MASK 37:43 == 0, then PBA BAR 37:43 -/// Else OCI Address 5:11 -/// A: OCI Address 12:31 -/// -/// \endcode -/// -/// The OCI address always selects the low-order 20 bits of the PowerBus -/// address, i.e., the window size is always a multiple of 1MB. The PBA BAR -/// mask allows up to a 128MB window into main memory without using the -/// extended address. The extended address allows OCC to address up to 2^41 -/// bytes by manipulating the extended address, assuming PHYP sets up the mask -/// correctly. -/// -/// -/// Centaur in-band SCOM, sensor cache and SYNC addressing in pictures and words: -/// -/// \code -/// -/// 1 2 3 4 5 6 -/// 0123456789012345678901234567890123456789012345678901234567890123 -/// | | | | | | | | | | | | | | | -/// -/// ..............B-------BX------------XO-----OA------------------A - See Above -/// ..............M-----------M10S------------------------------S000 - SCOM -/// ..............M-----------M1100000000000000000000000000000000000 - Sensor cache -/// ..............M-----------M1110000000000000000000000000000000000 - Sync -/// -/// .: Unused -/// M: The base address of the Centaur, taken from the MCS MCFGPR. -/// O: 1 Signifies that this access comes from the OCC. -/// S: The 32-bit SCOM address -/// 0: Zero -/// -/// \endcode -/// -/// In order to access the Centaur for in-band SCOM, the PBA BAR MASK must -/// extend at least from bit 29 down to bit 43, in order to allow the OCC to -/// generate these addresses. In practice the mask must allow all configured -/// Centaur to be accessed. This means that all Centaur in-band address bits -/// not controllable by OCC through the mask must be equal. -/// -/// Note that the SCOM address must be split between the extended address and -/// the OCI address. -/// -/// We assume (and verify) that MCMODE0(36) will always be set which means -/// that bit 27 is a flag indicating whether an access comes from FSP or -/// OCC. All OCC (GPE) accesses set this flag to 1. - -#include "ssx.h" -#include "gpe_scom.h" - -#if defined(VERIFICATION) || defined(LAB_VALIDATION) -#define PRINTD(...) printk(__VA_ARGS__) -#else -#define PRINTD(...) -#endif - -CentaurConfiguration G_centaurConfiguration -SECTION_ATTRIBUTE(".noncacheable_ro") = {.configRc = CENTAUR_NOT_CONFIGURED}; - -const uint16_t _pgp_mcs_offset[PGP_NMCS] = { - 0x0800, 0x0880, 0x0900, 0x0980, 0x0c00, 0x0c80, 0x0d00, 0x0d80 -}; - - -// All GpeScomParms structures are required to be noncacheable, so we have to -// allocate a static instance rather than using the stack. For simplicity the -// single-entry scomList_t required to collect the Centaur device IDs is -// allocated statically as well. - -static GpeScomParms S_parms SECTION_ATTRIBUTE(".noncacheable") = {0}; -static scomList_t S_scomList SECTION_ATTRIBUTE(".noncacheable") = {{{0}}}; - -int -_centaur_configuration_create(int i_bar, int i_slave, int i_setup) -{ - CentaurConfiguration config; - int i, designatedSync, diffInit; - int64_t rc; /* Must be copied to global struct. */ - mcfgpr_t mcfgpr; - mcifir_t mcifir; - mcsmode0_t mcsmode0; - pba_slvctln_t slvctl; - uint64_t diffMask, addrAccum, bar, mask, base; - PoreFlex request; - - // Start by clearing the local structure and setting the error flag. - memset(&config, 0, sizeof(config)); - config.configRc = CENTAUR_NOT_CONFIGURED; - - designatedSync = -1; - - do { - // Basic consistency checks - - if ((i_bar < 0) || (i_bar >= PBA_BARS) || - (i_slave < 0) || (i_slave >= PBA_SLAVES)) { - - rc = CENTAUR_INVALID_ARGUMENT; - break; - } - - - // Create the setups for the GPE procedures. The 'dataParms' are the - // setup for accessing the Centaur sensor cache. The 'scomParms' are - // the setup for accessing Centaur SCOMs. - - rc = gpe_pba_parms_create(&(config.dataParms), - PBA_SLAVE_PORE_GPE, - PBA_WRITE_TTYPE_CI_PR_W, - PBA_WRITE_TTYPE_DC, - PBA_READ_TTYPE_CL_RD_NC); - if (rc) { - rc = CENTAUR_DATA_SETUP_ERROR; - break; - } - - rc = gpe_pba_parms_create(&(config.scomParms), - PBA_SLAVE_PORE_GPE, - PBA_WRITE_TTYPE_CI_PR_W, - PBA_WRITE_TTYPE_DC, - PBA_READ_TTYPE_CI_PR_RD); - if (rc) { - rc = CENTAUR_SCOM_SETUP_ERROR; - break; - } - - - // Go into each MCS on the chip, and for all enabled MCS get a couple - // of SCOMs and check configuration items for correctness. If any of - // the Centaur are configured, exactly one of the MCS must be - // designated to receive the SYNC commands. - - // Note that the code uniformly treats SCOM failures of the MCFGPR - // registers as an unconfigured Centaur. This works both for Murano, - // which only defines the final 4 MCS, as well as for our VBU models - // where some of the "valid" MCS are not in the simulation models. - - for (i = 0; i < PGP_NCENTAUR; i++) { - - // SW273928: New function added for FW820, when centaur has channel - // checkstop, we consider centaur is not usable so treat it as - // deconfigured. Note that the current implementation assumes when - // centaur is dead, its mcs is also dead, which is wrong. However, - // it only concerns when MCS happens to be the SYNC master because - // the gpe procedure only tries to talk to centaurs regardless what - // MCS status it knows about. In this particular case, - // the procedure will turn on SYNC on a different MCS with - // valid centaur. According to Eric Retter, it would be ok for - // HW to have more MCS turned on as SYNC master as long as FW - // only send SYNC command to one of them. - - rc = _getscom(MCS_ADDRESS(MCIFIR, i), &(mcifir.value), - SCOM_TIMEOUT); - if (rc) { - rc = 0; - config.baseAddress[i] = 0; - continue; - } - - if (mcifir.fields.channel_fail_signal_active) continue; - - rc = _getscom(MCS_ADDRESS(MCFGPR, i), &(mcfgpr.value), - SCOM_TIMEOUT); - if (rc) { - rc = 0; - config.baseAddress[i] = 0; - continue; - } - - if (!mcfgpr.fields.mcfgprq_valid) continue; - - rc = _getscom(MCS_ADDRESS(MCSMODE0, i), &(mcsmode0.value), - SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n", - (uint32_t)rc, i); - rc = CENTAUR_MCSMODE0_SCOM_FAILURE; - break; - } - - - // We require that the MCFGRP_19_IS_HO_BIT be set in the mode - // register. We do not support the option of this bit not being - // set, and all of our procedures will set bit 19 of the PowerBus - // address to indicate that OCC is making the access. - - if (!mcsmode0.fields.mcfgrp_19_is_ho_bit) { - - PRINTD("MCSMODE0(%d).mcfgrp_19_is_ho_bit == 0\n", i); - rc = CENTAUR_MCSMODE0_19_FAILURE; - break; - } - - - // The 14-bit base-address is moved to begin at bit 14 in the - // 64-bit PowerBus address. The low-order bit of this address (bit - // 19 mentioned above which is bit 27 as an address bit) must be 0 - // - otherwise there is confusion over who's controlling this - // bit. - - config.baseAddress[i] = - ((uint64_t)(mcfgpr.fields.mcfgprq_base_address)) << - (64 - 14 - 14); - - if (config.baseAddress[i] & 0x0000001000000000ull) { - - PRINTD("Centaur base address %d has bit 27 set\n", i); - rc = CENTAUR_ADDRESS_27_FAILURE; - break; - } - - - // If this MCS is configured to be the designated SYNC unit, it - // must be the only one. - - if (mcsmode0.fields.enable_centaur_sync) { - - if (designatedSync > 0) { - - PRINTD("Both MCS %d and %d are designated " - "for Centaur Sync\n", - designatedSync, i); - rc = CENTAUR_MULTIPLE_DESIGNATED_SYNC; - break; - - } else { - - designatedSync = i; - } - } - - - // Add the Centaur to the configuration - - config.config |= (CHIP_CONFIG_MCS(i) | CHIP_CONFIG_CENTAUR(i)); - } - - if (rc) break; - - - // If Centaur are configured, make sure at least one of the MCS will - // handle the SYNC. If so, convert its base address into an address - // for issuing SYNC commands by setting bits 27 (OCC) 28 and 29 - // (Sync), then insert this address into the extended address field of - // a PBA slave control register image. gsc_scom_centaur() then merges - // this extended address into the PBA slave control register (which - // has been set up for Centaur SCOM) to do the SYNC. - - // In the override mode (i_setup > 1) we tag the first valid MCS - // to recieve the sync if the firmware has not set it up correctly. - - if (config.config) { - - if (designatedSync < 0) { - - if (i_setup <= 1) { - - PRINTD("No MCS is designated for Centaur SYNC\n"); - rc = CENTAUR_NO_DESIGNATED_SYNC; - break; - - } else { - - designatedSync = - cntlz32(left_justify_mcs_config(config.config)); - - rc = _getscom(MCS_ADDRESS(MCSMODE0, designatedSync), - &(mcsmode0.value), - SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n", - (uint32_t)rc, designatedSync); - rc = CENTAUR_MCSMODE0_SCOM_FAILURE; - break; - } - - mcsmode0.fields.enable_centaur_sync = 1; - - rc = _putscom(MCS_ADDRESS(MCSMODE0, designatedSync), - mcsmode0.value, - SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing MCSMODE0(%d)\n", - (uint32_t)rc, designatedSync); - rc = CENTAUR_MCSMODE0_SCOM_FAILURE; - break; - } - } - } - - base = config.baseAddress[designatedSync] | 0x0000001c00000000ull; - - slvctl.value = 0; - slvctl.fields.extaddr = (base & 0x000001fff8000000ull) >> 27; - - config.syncSlaveControl = slvctl.value; - } - - - // At this point we have one or more enabled MCS and they pass the - // initial configuration sniff test. We can now implement the option - // to configure the PBA BAR and BAR MASK correctly to allow access to - // these Centaur. We do this by computing the minimum BAR mask that - // covers all of the Centaur base addresses. This is done by - // accumulating a difference mask of the base addresses and finding - // the first set bit in the mask. - // - // Note that we do the configuration here on demand, but always do the - // correctness checking as the next step. - - if (i_setup && (config.config != 0)) { - - diffInit = 0; - diffMask = 0; /* GCC happiness */ - addrAccum = 0; /* GCC happiness */ - - for (i = 0; i < PGP_NCENTAUR; i++) { - - if (config.baseAddress[i] != 0) { - - if (!diffInit) { - - diffInit = 1; - diffMask = 0; - addrAccum = config.baseAddress[i]; - - } else { - - diffMask |= - (config.baseAddress[i] ^ addrAccum); - addrAccum |= config.baseAddress[i]; - } - - if (0) { - - // Debug - - printk("i:%d baseAddress: 0x%016llx " - "diffMask: 0x%016llx, addrAccum: 0x%016llx\n", - i, config.baseAddress[i], diffMask, addrAccum); - } - } - } - - // The mask must cover all differences - and must also have at - // least bit 27 set. The mask register contains only the mask. The - // BAR is set to the accumulated address outside of the mask. The - // BAR also contains a scope field which defaults to 0 (Nodal - // Scope) for Centaur inband access. - - diffMask |= 0x0000001000000000ull; - mask = - ((1ull << (64 - cntlz64(diffMask))) - 1) & - PBA_BARMSKN_MASK_MASK; - - rc = _putscom(PBA_BARMSKN(i_bar), mask, SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n", - (uint32_t)rc, i_bar); - rc = CENTAUR_BARMSKN_PUTSCOM_FAILURE; - break; - } - - rc = _putscom(PBA_BARN(i_bar), addrAccum & ~mask, SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n", - (uint32_t)rc, i_bar); - rc = CENTAUR_BARN_PUTSCOM_FAILURE; - break; - } - } - - - // Do an independent check that every Centaur base address - // can be generated by the combination of the current BAR and - // BAR Mask, along with the initial requirement that the mask must - // include at least bits 27:43. - - if (config.config != 0) { - - rc = _getscom(PBA_BARN(i_bar), &bar, SCOM_TIMEOUT); - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n", - (uint32_t)rc, i_bar); - rc = CENTAUR_BARN_GETSCOM_FAILURE; - break; - } - - rc = _getscom(PBA_BARMSKN(i_bar), &mask, SCOM_TIMEOUT); - - if (rc) { - PRINTD("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n", - (uint32_t)rc, i_bar); - rc = CENTAUR_BARMSKN_GETSCOM_FAILURE; - break; - } - - bar = bar & PBA_BARN_ADDR_MASK; - mask = mask & PBA_BARMSKN_MASK_MASK; - - if ((mask & 0x0000001ffff00000ull) != 0x0000001ffff00000ull) { - - PRINTD("PBA BAR mask (%d) does not cover bits 27:43\n", i_bar); - rc = CENTAUR_MASK_ERROR; - break; - } - - for (i = 0; i < PGP_NCENTAUR; i++) { - - if (config.baseAddress[i] != 0) { - - if ((config.baseAddress[i] & ~mask) != - (bar & ~mask)) { - - PRINTD("BAR/Mask (%d) error for MCS/Centaur %d\n" - " base = 0x%016llx\n" - " bar = 0x%016llx\n" - " mask = 0x%016llx\n", - - i_bar, i, config.baseAddress[i], bar, mask); - rc = CENTAUR_BAR_MASK_ERROR; - break; - } - } - } - - if (rc) break; - } - - - // At this point the structure is initialized well-enough that it can - // be used by gpe_scom_centaur(). We run gpe_scom_centaur() to collect - // the CFAM ids of the chips. Prior to this we copy our local copy - // into the global read-only data structure. (Note that GPE can DMA - // under the OCC TLB memory protection.) In order for - // gpe_scom_centaur() to run the global configuration must be valid - // (configRc == 0) - so we provisionally mark it valid (and will - // invalidate it later if errors occur here). - - // Note however that if no Centaur are present then we're already - // done. - - // It's assumed that this procedure is being run before threads have - // started, therefore we must poll for completion of the GPE program. - // Assuming no contention for GPE1 this procedure should take a few - // microseconds at most to complete. - - if (0) { - - // Debug for Simics - only enable MCS 5 - - config.baseAddress[0] = - config.baseAddress[1] = - config.baseAddress[2] = - config.baseAddress[3] = - config.baseAddress[4] = - config.baseAddress[6] = - config.baseAddress[7] = 0; - } - - - config.configRc = 0; - memcpy_real(&G_centaurConfiguration, &config, sizeof(config)); - - if (config.config == 0) break; - - S_scomList.scom = CENTAUR_DEVICE_ID; - S_scomList.commandType = GPE_SCOM_READ_VECTOR; - S_scomList.pData = G_centaurConfiguration.deviceId; - - S_parms.scomList = CAST_POINTER(uint64_t, &S_scomList); - S_parms.entries = 1; - S_parms.options = 0; - - pore_flex_create(&request, - &G_pore_gpe1_queue, - gpe_scom_centaur, - (uint32_t)(&S_parms), - SSX_MILLISECONDS(10), /* Timeout */ - 0, 0, 0); - - rc = pore_flex_schedule(&request); - - if (rc) break; - - while (!async_request_is_idle((AsyncRequest*)(&request))); - - if (!async_request_completed((AsyncRequest*)(&request)) || - (S_parms.rc != 0)) { - - PRINTD("gpe_scom_centaur() for CENTAUR_DEVICE_ID failed:\n" - " Async state = 0x%02x\n" - " gpe_scom_centaur() rc = %u\n" - " gpe_scom_centaur() errorIndex = %d\n", - ((AsyncRequest*)(&request))->state, - S_parms.rc, S_parms.errorIndex); - - rc = CENTAUR_READ_TPC_ID_FAILURE; - } - - if (0) { - - // Debug - - slvctl.value = G_gsc_lastSlaveControl; - - PRINTD("centaur_configuration_create:Debug\n" - " Last SCOM (PowerBus) address = 0x%016llx\n" - " Last Slave Control = 0x%016llx\n" - " Extended Address (positioned) = 0x%016llx\n" - " Last OCI Address = 0x%016llx\n", - G_gsc_lastScomAddress, - G_gsc_lastSlaveControl, - (unsigned long long)(slvctl.fields.extaddr) << - (64 - 23 - 14), - G_gsc_lastOciAddress); - } - - } while (0); - - // Copy the final RC into the global structure and done. - - memcpy_real(&(G_centaurConfiguration.configRc), &rc, sizeof(rc)); - - return rc; -} - - -// For now we have to handle configuring the PBA BAR and mask, and designating -// a SYNC if the firmware forgot to. - -int -centaur_configuration_create(void) -{ - return _centaur_configuration_create(PBA_BAR_CENTAUR, - PBA_SLAVE_PORE_GPE, - 2); -} - - -uint32_t mb_id(int i_mb) -{ - uint32_t rv; - centaur_device_id_t id; - - if ((i_mb < 0) || (i_mb >= PGP_NCENTAUR) || - (G_centaurConfiguration.configRc != 0)) { - - rv = (uint32_t)-1; - - } else { - - id.value = G_centaurConfiguration.deviceId[i_mb]; - rv = id.fields.cfam_id; - } - - return rv; -} - - -uint8_t mb_chip_type(int i_mb) -{ - uint8_t rv; - cfam_id_t id; - - if ((id.value = mb_id(i_mb)) == -1) { - - rv = (uint8_t)-1; - - } else { - - rv = id.chipType; - } - - return rv; -} - - -uint8_t mb_ec_level(int i_mb) -{ - uint8_t rv; - cfam_id_t id; - - if ((id.value = mb_id(i_mb)) == -1) { - - rv = (uint8_t)-1; - - } else { - - rv = (id.majorEc << 4) | id.minorEc; - } - - return rv; -} diff --git a/src/ssx/pgp/pgp_centaur.h b/src/ssx/pgp/pgp_centaur.h deleted file mode 100644 index 8c2ccee..0000000 --- a/src/ssx/pgp/pgp_centaur.h +++ /dev/null @@ -1,254 +0,0 @@ -#ifndef __PGP_CENTAUR_H__ -#define __PGP_CENTAUR_H__ - -// $Id: pgp_centaur.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_centaur.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_centaur.h -/// \brief Support for Centaur access and configuration from OCC. - -#include "gpe_pba.h" - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - -/// Compute the address of an MCS unit register from an index -/// -/// The MCS units have a bizarre PIB addressing scheme. This macro generates -/// MCS unit PIB addresses from a register name (w/o unit/index prefix), -/// assuming a valid index in the range 0:7. In the big sceheme of things it -/// probably saves space and time to do this with a table lookup rather than -/// generating the code to compute the address modification. (If we ever need -/// these in assembler code we'll have to implement a macro). - -#define MCS_ADDRESS(reg, index) (MCS0_##reg | _pgp_mcs_offset[index]) - -extern const uint16_t _pgp_mcs_offset[PGP_NMCS]; - - -/// A description of the current Centaur configuration -/// -/// \note Because this structure is read by the GPE engine it is strongly -/// recommended to allocate instances of this structure in non-cacheable data -/// sections, with the caveat that data structures assigned to non-default -/// data sections must always be initialized. For example: -/// -/// \code -/// -/// CentaurConfiguration G_centaurConfiguration -/// SECTION_ATTRIBUTE(".noncacheable_ro") = -/// {.configRc = CENTAUR_NOT_CONFIGURED}; -/// -/// \endcode - -typedef struct { - - /// Centaur base addresses for in-band operations - /// - /// These base addresses are used by GPE programs so it is most convenient - /// to store the entire 64 bits, even though only bits 23:26 of the base - /// address can be manipulated through the PBA BARs and BAR masks. A 0 - /// value indicates an unconfigured Centaur (MCS). - uint64_t baseAddress[PGP_NCENTAUR]; - - /// Contents of Centaur device id registers - /// - /// These are the device ID SCOMs (0x000f000f) read from configured - /// Centaur during initialization. A 0 value indicates an unconfigured - /// Centaur. These values are deconstructed by the memory buffer (mb) - /// APIs mb_id(), mb_chip_type() and mb_ec_level(). - uint64_t deviceId[PGP_NCENTAUR]; - - /// A "chip configuration" bit mask denoting valid Centaur - /// - /// It shoud always be true that a bit denoting a configured Centaur is - /// associated with a non-0 \a baseAddress and vice-versa. - ChipConfig config; - - /// The image of the PBA slave control register to use for the SYNC command - /// - /// The PowerBus address used to accomplish a Centaur SYNC is - /// constant. To simplify the procedures the PBA slave control register - /// (containing the extended address portion of the address) is - /// pre-computed and stored here. - /// - /// \note One and Only one of the MCS units can be targeted with SYNC - /// commands. The design includes a private bus connecting all MCS on the - /// chip that allows this "SYNC master" to broadcast the SYNC to all other - /// MCS on the chip. - uint64_t syncSlaveControl; - - /// A GpePbaParms parameter block for gpe_mem_data() - /// - /// This parameter block is set up in advance and used by the GPE - /// procedure gpe_mem_data(). Given the complexity of accessing Centaur - /// sensors and SCOM through the PBA it is simpler to set these up ahead - /// of time and simply have the GPE procedures access preconfigured global - /// data. The \a dataParms and \a scomParms members are distinguished by - /// the different way the PBA slave needs to be configured to access - /// either the Centaur sensor cache or Centaur SCOMs. - GpePbaParms dataParms; - - /// A GpePbaParms parameter block for gpe_scom_centaur(). - GpePbaParms scomParms; - - /// The final return code from centaur_configuration_create(). - /// - /// If initialization fails then this value can be used to diagnose what - /// happend. This field should be statically initialized to a non-0 value - /// (CENTAUR_NOT_CONFIGURED) and can then be checked against 0 to - /// determine if the structure has been correctly initialized. - int64_t configRc; - -} CentaurConfiguration; - -/// The global CentaurConfiguration created during initialization -extern CentaurConfiguration G_centaurConfiguration; - -#else // __ASSEMBLER__ - - .set CENTAUR_CONFIGURATION_BASE_ADDRESS, 0x0 - - .set CENTAUR_CONFIGURATION_DEVICE_ID, \ - (CENTAUR_CONFIGURATION_BASE_ADDRESS + (8 * PGP_NCENTAUR)) - - .set CENTAUR_CONFIGURATION_CONFIG, \ - (CENTAUR_CONFIGURATION_DEVICE_ID + (8 * PGP_NCENTAUR)) - - .set CENTAUR_CONFIGURATION_SYNC_SLAVE_CONTROL, \ - (CENTAUR_CONFIGURATION_CONFIG + 8) - - .set CENTAUR_CONFIGURATION_DATA_PARMS, \ - (CENTAUR_CONFIGURATION_SYNC_SLAVE_CONTROL + 8) - - .set CENTAUR_CONFIGURATION_SCOM_PARMS, \ - (CENTAUR_CONFIGURATION_DATA_PARMS + SIZEOF_GPEPBAPARMS) - - .set CENTAUR_CONFIGURATION_CONFIG_RC, \ - (CENTAUR_CONFIGURATION_SCOM_PARMS + SIZEOF_GPEPBAPARMS) - - .set SIZEOF_CENTAUR_CONFIGURATION, \ - (CENTAUR_CONFIGURATION_CONFIG_RC + 8) - -#endif // __ASSEMBLER__ - - -#ifndef __ASSEMBLER__ - -/// Error return codes set/returned by centaur_configuration_create() - -enum CentaurConfigurationCreateRc{ - - CENTAUR_INVALID_ARGUMENT = 0x007ccc01, - CENTAUR_MCSMODE0_SCOM_FAILURE = 0x007ccc02, - CENTAUR_MCSMODE0_19_FAILURE = 0x007ccc03, - CENTAUR_ADDRESS_27_FAILURE = 0x007ccc04, - CENTAUR_MULTIPLE_DESIGNATED_SYNC = 0x007ccc05, - CENTAUR_NO_DESIGNATED_SYNC = 0x007ccc06, - CENTAUR_BAR_MASK_ERROR = 0x007ccc07, - CENTAUR_CONFIGURATION_FAILED = 0x007ccc08, - CENTAUR_DATA_SETUP_ERROR = 0x007ccc09, - CENTAUR_SCOM_SETUP_ERROR = 0x007ccc0a, - CENTAUR_NOT_CONFIGURED = 0x007ccc0b, - CENTAUR_MASK_ERROR = 0x007ccc0c, - CENTAUR_READ_TPC_ID_FAILURE = 0x007ccc0d, - CENTAUR_BARMSKN_PUTSCOM_FAILURE = 0x007ccc0e, - CENTAUR_BARN_PUTSCOM_FAILURE = 0x007ccc0f, - CENTAUR_BARMSKN_GETSCOM_FAILURE = 0x007ccc10, - CENTAUR_BARN_GETSCOM_FAILURE = 0x007ccc11, -}; - - -/// Create (initialize) G_centaurConfiguration -/// -/// G_centaurConfiguration is a global structure used by GPE procedures to -/// access Centaur, and the mb_*() APIs to return CFAM-id type information -/// about the Centaurs. -/// -/// To complete Centaur configuration requires running the GPE program -/// gpe_scom_centaur() on PORE-GPE1 to collect the TPC device Ids of the -/// Centaur chips. This means that the "async" drivers must be set up prior to -/// the call. We assume this API will be called before threads have started, -/// thus it will poll the async request for completion. Assuming no other GPE -/// programs are scheduled this should take a few microseconds at most. -/// -/// \returns Either 0 for success or an element of the -/// CentaurConfigurationCreateRc enumeration. -int -centaur_configuration_create(void); - - -/// Create (initialize) G_centaurConfiguration (Internal API) -/// -/// \param[in] i_bar The index of the PBA BAR reserved for access to -/// Centaur. This will normally be passed as the constant PBA_BAR_CENTAUR but -/// is allowed to be variable for special cases. -/// -/// \param[in] i_slave The index of the PBA slave reserved for access from the -/// GPE complex. This will normally be passed as the constant -/// PBA_SLAVE_PORE_GPE but is allowed to be variable for special cases. -/// -/// \param[in] i_setup If non-0, then this procedure will set up the PBA BAR -/// correctly for access to Centaur. If > 1, then the procedure will also -/// designate an MCS to recieve the Centaur SYNC if the firmware failed to do -/// so. -/// -/// This API must be run early in the initialization flow, likely before the -/// real-time loop is activated. The API first scans the MBS configuration for -/// correctness and (optionally) sets up the PBA BAR and mask for access to -/// Centaur. The API then runs the gpe_scom_centaur() procedure to get the -/// CFAM Id from each configured Centaur. -/// -/// \note Normally we would implement test/bringup workarounds like the \a -/// i_setup parameter separately, however the setup of Centaur is at a level -/// of complexity where it makes sense to implement this override in a -/// mainline procedure. -int -_centaur_configuration_create(int i_bar, int i_slave, int i_setup); - - -/// Get a Centaur (MB) CFAM Chip Id -/// -/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being -/// queried. -/// -/// \returns A 32-bit value to be compared against the enumeration of known -/// CFAM ids. See \ref pgp_cfam_chip_ids. If the \a i_mb is invalid or the -/// Centaur is not configured or the G_centaurConfiguration is not valid then -/// (uint32_t)-1 is returned. -uint32_t mb_id(int i_mb); - - -/// Get a Centaur (MB) Chip Type -/// -/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being -/// queried. -/// -/// \returns An 8-bit value to be compared against the enumeration of known -/// CFAM chip types. See \ref pgp_cfam_chip_types. If the \a i_mb is invalid -/// or the Centaur is not configured or the G_centaurConfiguration is not -/// valid then (uint8_t)-1 is returned. -uint8_t mb_chip_type(int i_mb); - - -/// Get a Centaur (MB) CFAM Chip EC Level -/// -/// \param[in] i_mb The index (0..PGP_NCENTAUR - 1) of the memory buffer being -/// queried. -/// -/// \returns An 8-bit value; The high-order nibble is the major EC level and -/// the low-order nibble is the minor EC level. For example a value of 0x21 -/// indicates DD 2.1. If the \a i_mb is invalid or the Centaur is not -/// configured or the G_centaurConfiguration is not valid then (uint8_t)-1 is -/// returned. -uint8_t mb_ec_level(int i_mb); - -#endif // __ASSEMBLER - -#endif // __PGP_CENTAUR_H__ diff --git a/src/ssx/pgp/pgp_common.h b/src/ssx/pgp/pgp_common.h deleted file mode 100755 index 305f7c2..0000000 --- a/src/ssx/pgp/pgp_common.h +++ /dev/null @@ -1,717 +0,0 @@ -#ifndef __PGP_COMMON_H__ -#define __PGP_COMMON_H__ - -// $Id: pgp_common.h,v 1.4 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_common.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_common.h -/// \brief Common header for SSX and PMX versions of PgP -/// -/// This header is maintained as part of the SSX port for PgP, but needs to be -/// physically present in the PMX area to allow dropping PMX code as a whole -/// to other teams. - -// -*- WARNING: This file is maintained as part of SSX. Do not edit in -*- -// -*- the PMX area as your edits will be lost. -*- - -#ifndef __ASSEMBLER__ -#include <stdint.h> -extern unsigned int g_ocb_timer_divider; //grm -#endif - -//////////////////////////////////////////////////////////////////////////// -// Configuration -//////////////////////////////////////////////////////////////////////////// - -#define PGP_NCORES 16 -#define PGP_NCORE_PARTITIONS 4 -#define PGP_NMCS 8 -#define PGP_NCENTAUR 8 -#define PGP_NTHREADS 8 -#define PGP_NDTSCPM 4 - -#ifndef PROCESSOR_EC_LEVEL -#define MURANO_DD10 1 -#else -#define MURANO_DD10 0 -#endif - - -//////////////////////////////////////////////////////////////////////////// -// Clocking -//////////////////////////////////////////////////////////////////////////// -// -// The SSX timebase is driven by the pervasive clock, which is nest / 4. This -// will typically be 600MHz, but may be 500MHz for power-constrained system -// designs. - -/// The pervasive hang timer divider used for the OCB timer -/// -/// This is supposed to yield an approximately 1us timer, however for MURANO -/// DD10 we need to use an approximate 64us timer - -#if MURANO_DD10 -#define OCB_TIMER_DIVIDER_DEFAULT (64 * 512) -#else -#define OCB_TIMER_DIVIDER_DEFAULT 512 -#endif - -/// This is set to the above default at compile time but may be updated -/// at run time. grm -#define OCB_TIMER_DIVIDER g_ocb_timer_divider - -/// The OCB timer frequency -#define OCB_TIMER_FREQUENCY_HZ (SSX_TIMEBASE_FREQUENCY_HZ / OCB_TIMER_DIVIDER) - -/// The pervasive hang timer divider used for the PMC (same as OCB timer) -#define PMC_TIMER_DIVIDER OCB_TIMER_DIVIDER - -/// The PMC hang pulse frequency -#define PMC_HANG_PULSE_FREQUENCY_HZ \ - (SSX_TIMEBASE_FREQUENCY_HZ / PMC_TIMER_DIVIDER) - -/// The pervasive hang timer divider for PCBS 'fast' timers -/// -/// This timer yeilds an approximate 100ns pulse with a 2.4 GHz pervasive clock -#define PCBS_FAST_TIMER_DIVIDER 64 - -/// The pervasive hang timer divider for PCBS 'slow' timers -/// -/// This timer yeilds an approximate 1us pulse with a 2.4 GHz pervasive clock -#define PCBS_SLOW_TIMER_DIVIDER 512 - -/// The PCBS slow divider frequency -#define PCBS_SLOW_HANG_PULSE_FREQUENCY_HZ \ - (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_SLOW_TIMER_DIVIDER) - -/// The PCBS occ heartbeat pulse is predivided in hardware by 64 -#define PCBS_HEARTBEAT_DIVIDER \ - (PCBS_SLOW_TIMER_DIVIDER * 64) - -/// The PCBS heartbeat pulse frequency -#define PCBS_HEARTBEAT_PULSE_FREQUENCY_HZ \ - (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_HEARTBEAT_DIVIDER) - - - -//////////////////////////////////////////////////////////////////////////// -// OCI -//////////////////////////////////////////////////////////////////////////// - -// OCI Master Id assigments - required for PBA slave programming. These Ids -// also appear as bits 12:15 of the OCI register space addresses of the OCI -// registers for each device that contains OCI-addressable registers (GPE, -// PMC, PBA, SLW and OCB). - -#define OCI_MASTER_ID_PORE_GPE 0 -#define OCI_MASTER_ID_PMC 1 -#define OCI_MASTER_ID_PBA 2 -#define OCI_MASTER_ID_UNUSED 3 -#define OCI_MASTER_ID_PORE_SLW 4 -#define OCI_MASTER_ID_OCB 5 -#define OCI_MASTER_ID_OCC_ICU 6 -#define OCI_MASTER_ID_OCC_DCU 7 - - -//////////////////////////////////////////////////////////////////////////// -// IRQ -//////////////////////////////////////////////////////////////////////////// - -// The OCB interrupt controller consists of 2 x 32-bit controllers. Unlike -// PPC ASICs, the OCB controllers are _not_ cascaded. The combined -// controllers are presented to the application as if there were a single -// 64-bit interrupt controller, while the code underlying the abstraction -// manipulates the 2 x 32-bit controllers independently. -// -// Note that the bits named *RESERVED* are actually implemented in the -// controller, but the interrupt input is tied low. That means they can also -// be used as IPI targets. Logical bits 32..63 are not implemented. - -#define PGP_IRQ_DEBUGGER 0 /* 0x00 */ -#define PGP_IRQ_TRACE_TRIGGER 1 /* 0x01 */ -#define PGP_IRQ_OCC_ERROR 2 /* 0x02 */ -#define PGP_IRQ_PBA_ERROR 3 /* 0x03 */ -#define PGP_IRQ_SRT_ERROR 4 /* 0x04 */ -#define PGP_IRQ_PORE_SW_ERROR 5 /* 0x05 */ -#define PGP_IRQ_PORE_GPE0_FATAL_ERROR 6 /* 0x06 */ -#define PGP_IRQ_PORE_GPE1_FATAL_ERROR 7 /* 0x07 */ -#define PGP_IRQ_PORE_SBE_FATAL_ERROR 8 /* 0x08 */ -#define PGP_IRQ_PMC_ERROR 9 /* 0x09 */ -#define PGP_IRQ_OCB_ERROR 10 /* 0x0a */ -#define PGP_IRQ_SPIPSS_ERROR 11 /* 0x0b */ -#define PGP_IRQ_CHECK_STOP 12 /* 0x0c */ -#define PGP_IRQ_PMC_MALF_ALERT 13 /* 0x0d */ -#define PGP_IRQ_ADU_MALF_ALERT 14 /* 0x0e */ -#define PGP_IRQ_EXTERNAL_TRAP 15 /* 0x0f */ -#define PGP_IRQ_OCC_TIMER0 16 /* 0x10 */ -#define PGP_IRQ_OCC_TIMER1 17 /* 0x11 */ -#define PGP_IRQ_PORE_GPE0_ERROR 18 /* 0x12 */ -#define PGP_IRQ_PORE_GPE1_ERROR 19 /* 0x13 */ -#define PGP_IRQ_PORE_SBE_ERROR 20 /* 0x14 */ -#define PGP_IRQ_PMC_INTERCHIP_MSG_RECV 21 /* 0x15 */ -#define PGP_IRQ_RESERVED_22 22 /* 0x16 */ -#define PGP_IRQ_PORE_GPE0_COMPLETE 23 /* 0x17 */ -#define PGP_IRQ_PORE_GPE1_COMPLETE 24 /* 0x18 */ -#define PGP_IRQ_ADCFSM_ONGOING 25 /* 0x19 */ -#define PGP_IRQ_RESERVED_26 26 /* 0x1a */ -#define PGP_IRQ_PBA_OCC_PUSH0 27 /* 0x1b */ -#define PGP_IRQ_PBA_OCC_PUSH1 28 /* 0x1c */ -#define PGP_IRQ_PBA_BCDE_ATTN 29 /* 0x1d */ -#define PGP_IRQ_PBA_BCUE_ATTN 30 /* 0x1e */ -#define PGP_IRQ_RESERVED_31 31 /* 0x1f */ - -#define PGP_IRQ_RESERVED_32 32 /* 0x20 */ -#define PGP_IRQ_RESERVED_33 33 /* 0x21 */ -#define PGP_IRQ_STRM0_PULL 34 /* 0x22 */ -#define PGP_IRQ_STRM0_PUSH 35 /* 0x23 */ -#define PGP_IRQ_STRM1_PULL 36 /* 0x24 */ -#define PGP_IRQ_STRM1_PUSH 37 /* 0x25 */ -#define PGP_IRQ_STRM2_PULL 38 /* 0x26 */ -#define PGP_IRQ_STRM2_PUSH 39 /* 0x27 */ -#define PGP_IRQ_STRM3_PULL 40 /* 0x28 */ -#define PGP_IRQ_STRM3_PUSH 41 /* 0x29 */ -#define PGP_IRQ_RESERVED_42 42 /* 0x2a */ -#define PGP_IRQ_RESERVED_43 43 /* 0x2b */ -#define PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING 44 /* 0x2c */ -#define PGP_IRQ_PMC_PROTOCOL_ONGOING 45 /* 0x2d */ -#define PGP_IRQ_PMC_SYNC 46 /* 0x2e */ -#define PGP_IRQ_PMC_PSTATE_REQUEST 47 /* 0x2f */ -#define PGP_IRQ_RESERVED_48 48 /* 0x30 */ -#define PGP_IRQ_RESERVED_49 49 /* 0x31 */ -#define PGP_IRQ_PMC_IDLE_EXIT 50 /* 0x32 */ -#define PGP_IRQ_PORE_SW_COMPLETE 51 /* 0x33 */ -#define PGP_IRQ_PMC_IDLE_ENTER 52 /* 0x34 */ -#define PGP_IRQ_RESERVED_53 53 /* 0x35 */ -#define PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING 54 /* 0x36 */ -#define PGP_IRQ_OCI2SPIVID_ONGOING 55 /* 0x37 */ -#define PGP_IRQ_PMC_OCB_O2P_ONGOING 56 /* 0x38 */ -#define PGP_IRQ_PSSBRIDGE_ONGOING 57 /* 0x39 */ -#define PGP_IRQ_PORE_SBE_COMPLETE 58 /* 0x3a */ -#define PGP_IRQ_IPI0 59 /* 0x3b */ -#define PGP_IRQ_IPI1 60 /* 0x3c */ -#define PGP_IRQ_IPI2 61 /* 0x3d */ -#define PGP_IRQ_IPI3 62 /* 0x3e */ -#define PGP_IRQ_RESERVED_63 63 /* 0x3f */ - - -// Please keep the string definitions up-to-date as they are used for -// reporting in the Simics simulation. - -#define PGP_IRQ_STRINGS(var) \ - const char* var[64] = { \ - "PGP_IRQ_DEBUGGER", \ - "PGP_IRQ_TRACE_TRIGGER", \ - "PGP_IRQ_OCC_ERROR", \ - "PGP_IRQ_PBA_ERROR", \ - "PGP_IRQ_SRT_ERROR", \ - "PGP_IRQ_PORE_SW_ERROR", \ - "PGP_IRQ_PORE_GPE0_FATAL_ERROR", \ - "PGP_IRQ_PORE_GPE1_FATAL_ERROR", \ - "PGP_IRQ_PORE_SBE_FATAL_ERROR", \ - "PGP_IRQ_PMC_ERROR", \ - "PGP_IRQ_OCB_ERROR", \ - "PGP_IRQ_SPIPSS_ERROR", \ - "PGP_IRQ_CHECK_STOP", \ - "PGP_IRQ_PMC_MALF_ALERT", \ - "PGP_IRQ_ADU_MALF_ALERT", \ - "PGP_IRQ_EXTERNAL_TRAP", \ - "PGP_IRQ_OCC_TIMER0", \ - "PGP_IRQ_OCC_TIMER1", \ - "PGP_IRQ_PORE_GPE0_ERROR", \ - "PGP_IRQ_PORE_GPE1_ERROR", \ - "PGP_IRQ_PORE_SBE_ERROR", \ - "PGP_IRQ_PMC_INTERCHIP_MSG_RECV", \ - "PGP_IRQ_RESERVED_22", \ - "PGP_IRQ_PORE_GPE0_COMPLETE", \ - "PGP_IRQ_PORE_GPE1_COMPLETE", \ - "PGP_IRQ_ADCFSM_ONGOING", \ - "PGP_IRQ_RESERVED_26", \ - "PGP_IRQ_PBA_OCC_PUSH0", \ - "PGP_IRQ_PBA_OCC_PUSH1", \ - "PGP_IRQ_PBA_BCDE_ATTN", \ - "PGP_IRQ_PBA_BCUE_ATTN", \ - "PGP_IRQ_RESERVED_31", \ - "PGP_IRQ_RESERVED_32", \ - "PGP_IRQ_RESERVED_33", \ - "PGP_IRQ_STRM0_PULL", \ - "PGP_IRQ_STRM0_PUSH", \ - "PGP_IRQ_STRM1_PULL", \ - "PGP_IRQ_STRM1_PUSH", \ - "PGP_IRQ_STRM2_PULL", \ - "PGP_IRQ_STRM2_PUSH", \ - "PGP_IRQ_STRM3_PULL", \ - "PGP_IRQ_STRM3_PUSH", \ - "PGP_IRQ_RESERVED_42", \ - "PGP_IRQ_RESERVED_43", \ - "PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING", \ - "PGP_IRQ_PMC_PROTOCOL_ONGOING", \ - "PGP_IRQ_PMC_SYNC", \ - "PGP_IRQ_PMC_PSTATE_REQUEST", \ - "PGP_IRQ_RESERVED_48", \ - "PGP_IRQ_RESERVED_49", \ - "PGP_IRQ_PMC_IDLE_EXIT", \ - "PGP_IRQ_PORE_SW_COMPLETE", \ - "PGP_IRQ_PMC_IDLE_ENTER", \ - "PGP_IRQ_RESERVED_53", \ - "PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING", \ - "PGP_IRQ_OCI2SPIVID_ONGOING", \ - "PGP_IRQ_PMC_OCB_O2P_ONGOING", \ - "PGP_IRQ_PSSBRIDGE_ONGOING", \ - "PGP_IRQ_PORE_SBE_COMPLETE", \ - "PGP_IRQ_IPI0", \ - "PGP_IRQ_IPI1", \ - "PGP_IRQ_IPI2", \ - "PGP_IRQ_IPI3 (ASYNC-IPI)", \ - "PGP_IRQ_RESERVED_63" \ - }; - - -/// This constant is used to define the size of the table of interrupt handler -/// structures as well as a limit for error checking. The entire 64-bit -/// vector is now in use. - -#define PPC405_IRQS 64 - - -// Note: All standard-product IPI uses are declared here to avoid conflicts -// Validation- and lab-only IPI uses are documented in validation.h - -/// The deferred callback queue interrupt -/// -/// This IPI is reserved for use of the async deferred callback mechanism. -/// This IPI is used by both critical and noncritical async handlers to -/// activate the deferred callback mechanism. -#define PGP_IRQ_ASYNC_IPI PGP_IRQ_IPI3 - - -/// The PTS completion queue intererupt -/// -/// This IPI is reserved for use of the PTS completion queues. A single -/// interrupt serves PTS for both GPE0 and GPE1. Note that as defined here, -/// PTS completion takes precedence over other ASYNC processing, however in -/// reality they both run callbacks preemptible so they will tend to be more -/// or less at the same priority. If this is a problem then they could be -/// combined onto a single interrupt and handled with the appropriate priority -/// in the async_callback_handler_full(). - -#define PGP_IRQ_PTS_IPI PGP_IRQ_IPI2 - - -#ifndef __ASSEMBLER__ - -/// This expression recognizes only those IRQ numbers that have named -/// (non-reserved) interrupts in the OCB interrupt controller. - -// There are so many invalid interrupts now that it's a slight improvement in -// code size to let the compiler optimize the invalid IRQs to a bit mask for -// the comparison. - -#define PGP_IRQ_VALID(irq) \ - ({unsigned __irq = (unsigned)(irq); \ - ((__irq < PPC405_IRQS) && \ - ((PGP_IRQ_MASK64(__irq) & \ - (PGP_IRQ_MASK64(PGP_IRQ_RESERVED_22) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_26) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_31) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_32) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_33) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_42) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_43) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_48) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_49) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_53) | \ - PGP_IRQ_MASK64(PGP_IRQ_RESERVED_63))) == 0));}) - -/// This is a 32-bit mask, with big-endian bit (irq % 32) set. -#define PGP_IRQ_MASK32(irq) (((uint32_t)0x80000000) >> ((irq) % 32)) - -/// This is a 64-bit mask, with big-endian bit 'irq' set. -#define PGP_IRQ_MASK64(irq) (0x8000000000000000ull >> (irq)) - -#endif /* __ASSEMBLER__ */ - - -//////////////////////////////////////////////////////////////////////////// -// OCB -//////////////////////////////////////////////////////////////////////////// - -/// The base address of the OCI control register space -#define OCI_REGISTER_SPACE_BASE 0x40000000 - -/// The base address of the entire PIB port mapped by the OCB. The -/// OCB-contained PIB registers are based at OCB_PIB_BASE. -#define OCB_PIB_SLAVE_BASE 0x00060000 - -/// The size of the OCI control register address space -/// -/// There are at most 8 slaves, each of which maps 2**16 bytes of register -/// address space. -#define OCI_REGISTER_SPACE_SIZE POW2_32(19) - -/// This macro converts an OCI register space address into a PIB address as -/// seen through the OCB direct bridge. -#define OCI2PIB(addr) ((((addr) & 0x0007ffff) >> 3) + OCB_PIB_SLAVE_BASE) - - -// OCB communication channel constants - -#define OCB_INDIRECT_CHANNELS 4 - -#define OCB_RW_READ 0 -#define OCB_RW_WRITE 1 - -#define OCB_STREAM_MODE_DISABLED 0 -#define OCB_STREAM_MODE_ENABLED 1 - -#define OCB_STREAM_TYPE_LINEAR 0 -#define OCB_STREAM_TYPE_CIRCULAR 1 - -#define OCB_INTR_ACTION_FULL 0 -#define OCB_INTR_ACTION_NOT_FULL 1 -#define OCB_INTR_ACTION_EMPTY 2 -#define OCB_INTR_ACTION_NOT_EMPTY 3 - -#ifndef __ASSEMBLER__ - -// These macros select OCB interrupt controller registers based on the IRQ -// number. - -#define OCB_OIMR_AND(irq) (((irq) & 0x20) ? OCB_OIMR1_AND : OCB_OIMR0_AND) -#define OCB_OIMR_OR(irq) (((irq) & 0x20) ? OCB_OIMR1_OR : OCB_OIMR0_OR) - -#define OCB_OISR(irq) (((irq) & 0x20) ? OCB_OISR1 : OCB_OISR0) -#define OCB_OISR_AND(irq) (((irq) & 0x20) ? OCB_OISR1_AND : OCB_OISR0_AND) -#define OCB_OISR_OR(irq) (((irq) & 0x20) ? OCB_OISR1_OR : OCB_OISR0_OR) - -#define OCB_OIEPR(irq) (((irq) & 0x20) ? OCB_OIEPR1 : OCB_OIEPR0) -#define OCB_OITR(irq) (((irq) & 0x20) ? OCB_OITR1 : OCB_OITR0) -#define OCB_OCIR(irq) (((irq) & 0x20) ? OCB_OCIR1 : OCB_OCIR0) -#define OCB_OUDER(irq) (((irq) & 0x20) ? OCB_OUDER1 : OCB_OUDER0) - -#endif /* __ASSEMBLER__ */ - - -//////////////////////////////////////////////////////////////////////////// -// PMC -//////////////////////////////////////////////////////////////////////////// - -#ifndef __ASSEMBLER__ - -/// A Pstate type -/// -/// Pstates are signed, but our register access macros operate on unsigned -/// values. To avoid bugs, Pstate register fields should always be extracted -/// to a variable of type Pstate. If the size of Pstate variables ever -/// changes we will have to revisit this convention. -typedef int8_t Pstate; - -/// A DPLL frequency code -/// -/// DPLL frequency codes moved from 8 to 9 bits going from P7 to P8 -typedef uint16_t DpllCode; - -/// A VRM11 VID code -typedef uint8_t Vid11; - -#endif /* __ASSEMBLER__ */ - -/// The minimum Pstate -#define PSTATE_MIN -128 - -/// The maximum Pstate -#define PSTATE_MAX 127 - -/// The minimum \e legal DPLL frequency code -/// -/// This is ~1GHz with a 33.3MHz tick frequency. -#define DPLL_MIN 0x01e - -/// The maximum DPLL frequency code -#define DPLL_MAX 0x1ff - -/// The minimum \a legal (non-power-off) VRM11 VID code -#define VID11_MIN 0x02 - -/// The maximum \a legal (non-power-off) VRM11 VID code -#define VID11_MAX 0xfd - - -//////////////////////////////////////////////////////////////////////////// -// PCB -//////////////////////////////////////////////////////////////////////////// - -/// Convert a core chiplet 0 SCOM address to the equivalent address for any -/// other core chiplet. -/// -/// Note that it is unusual to address core chiplet SCOMs directly. Normally -/// this is done as part of a GPE program where the program iterates over core -/// chiplets, using the chiplet-0 address + a programmable offset held in a -/// chiplet address register. Therefore the only address macro defined is the -/// chiplet-0 address. This macro is used for the rare cases of explicit -/// getscom()/ putscom() to a particular chiplet. - -#define CORE_CHIPLET_ADDRESS(addr, core) ((addr) + ((core) << 24)) - - -// PCB Error codes - -#define PCB_ERROR_NONE 0 -#define PCB_ERROR_RESOURCE_OCCUPIED 1 -#define PCB_ERROR_CHIPLET_OFFLINE 2 -#define PCB_ERROR_PARTIAL_GOOD 3 -#define PCB_ERROR_ADDRESS_ERROR 4 -#define PCB_ERROR_CLOCK_ERROR 5 -#define PCB_ERROR_PACKET_ERROR 6 -#define PCB_ERROR_TIMEOUT 7 - -// PCB Multicast modes - -#define PCB_MULTICAST_OR 0 -#define PCB_MULTICAST_AND 1 -#define PCB_MULTICAST_SELECT 2 -#define PCB_MULTICAST_COMPARE 4 -#define PCB_MULTICAST_WRITE 5 - -/// \defgroup pcb_multicast_groups PCB Multicast Groups -/// -/// Technically the multicast groups are programmable; This is the multicast -/// grouping established by proc_sbe_chiplet_init(). -/// -/// - Group 0 : All functional chiplets (PRV PB XBUS ABUS PCIE TPCEX) -/// - Group 1 : All functional EX chiplets (no cores) -/// - Group 2 : All functional EX chiplets (core only) -/// - Group 3 : All functional chiplets except pervasive (PRV) -/// -/// @{ - -#define MC_GROUP_ALL 0 -#define MC_GROUP_EX 1 -#define MC_GROUP_EX_CORE 2 -#define MC_GROUP_ALL_BUT_PRV 3 - -/// @} - - -/// Convert any SCOM address to a multicast address -#define MC_ADDRESS(address, group, mode) \ - (((address) & 0x00ffffff) | ((0x40 | ((mode) << 3) | (group)) << 24)) - - - -//////////////////////////////////////////////////////////////////////////// -// PBA -//////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////// -// Macros for fields of PBA_MODECTL -//////////////////////////////////// - -/// The 64KB OCI HTM marker space is enabled by default at 0x40070000 -/// -/// See the comments for pgp_trace.h - -#define PBA_OCI_MARKER_BASE 0x40070000 - - -// SSX Kernel reserved trace addresses, see pgp_trace.h. - -#define SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE 0xf000 -#define SSX_TRACE_CRITICAL_IRQ_EXIT_BASE 0xf100 -#define SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE 0xf200 -#define SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE 0xf300 -#define SSX_TRACE_THREAD_SWITCH_BASE 0xf400 -#define SSX_TRACE_THREAD_SLEEP_BASE 0xf500 -#define SSX_TRACE_THREAD_WAKEUP_BASE 0xf600 -#define SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE 0xf700 -#define SSX_TRACE_THREAD_SEMAPHORE_POST_BASE 0xf800 -#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE 0xf900 -#define SSX_TRACE_THREAD_SUSPENDED_BASE 0xfa00 -#define SSX_TRACE_THREAD_DELETED_BASE 0xfb00 -#define SSX_TRACE_THREAD_COMPLETED_BASE 0xfc00 -#define SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE 0xfd00 -#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE 0xfe00 -#define SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE 0xff00 - - -// Please keep the string definitions up to date as they are used for -// reporting in the Simics simulation. - -#define SSX_TRACE_STRINGS(var) \ - const char* var[16] = { \ - "Critical IRQ Entry ", \ - "Critical IRQ Exit ", \ - "Noncritical IRQ Entry ", \ - "Noncritical IRQ Exit ", \ - "Thread Switch ", \ - "Thread Blocked : Sleep ", \ - "Thread Unblocked : Wakeup ", \ - "Thread Blocked : Semaphore ", \ - "Thread Unblocked : Semaphore ", \ - "Thread Unblocked : Sem. Timeout", \ - "Thread Suspended ", \ - "Thread Deleted ", \ - "Thread Completed ", \ - "Thread Mapped Runnable ", \ - "Thread Mapped Semaphore Pend. ", \ - "Thread Mapped Sleeping ", \ - }; - - -// PBA transaction sizes for the block copy engines - -#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0 -#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1 -#define PBA_BCE_OCI_TRANSACTION_8_BYTES 2 - - -// PBAX communication channel constants - -#define PBAX_CHANNELS 2 - -#define PBAX_INTR_ACTION_FULL 0 -#define PBAX_INTR_ACTION_NOT_FULL 1 -#define PBAX_INTR_ACTION_EMPTY 2 -#define PBAX_INTR_ACTION_NOT_EMPTY 3 - - -// PBA Write Buffer fields - -#define PBA_WBUFVALN_STATUS_EMPTY 0x01 -#define PBA_WBUFVALN_STATUS_GATHERING 0x02 -#define PBA_WBUFVALN_STATUS_WAIT 0x04 -#define PBA_WBUFVALN_STATUS_WRITING 0x08 -#define PBA_WBUFVALN_STATUS_CRESPERR 0x10 - - -//////////////////////////////////////////////////////////////////////////// -// VRM -//////////////////////////////////////////////////////////////////////////// - -// These are the command types recognized by the VRMs - -#define VRM_WRITE_VOLTAGE 0x0 -#define VRM_READ_STATE 0xc -#define VRM_READ_VOLTAGE 0x3 - -// Voltage rail designations for the read voltage command -#define VRM_RD_VDD_RAIL 0x0 -#define VRM_RD_VCS_RAIL 0x1 - - -//////////////////////////////////////////////////////////////////////////// -// OHA -//////////////////////////////////////////////////////////////////////////// - -// Power proxy trace record idle state encodings. These encodings are unique -// to the Power proxy trace record. - -#define PPT_IDLE_NON_IDLE 0x0 -#define PPT_IDLE_NAP 0x1 -#define PPT_IDLE_LIGHT_SLEEP 0x2 -#define PPT_IDLE_FAST_SLEEP 0x3 -#define PPT_IDLE_DEEP_SLEEP 0x4 -#define PPT_IDLE_LIGHT_WINKLE 0x5 -#define PPT_IDLE_FAST_WINKLE 0x6 -#define PPT_IDLE_DEEP_WINKLE 0x7 - - -//////////////////////////////////////////////////////////////////////////// -// PC -//////////////////////////////////////////////////////////////////////////// - -// SPRC numbers for PC counters. The low-order 3 bits are always defined as -// 0. The address can also be modified by OR-ing in 0x400 to indicate -// auto-increment addressing. Note that the frequency-sensitivity counters -// are called "workrate" counters in the hardware documentation. -// -// Notes on the throttle counters: -// -// SPRN_IFU_THROTTLE_COUNTER -// Cycles the IFU throttle was actually blocking fetch -// -// <= if_pc_didt_throttle_blocked -// -// SPRN_ISU_THROTTLE_COUNTER -// Cycles that ISU throttle was active and modeably IFU throttle request -// was not -// -// <= sd_pc_uthrottle_active AND -// (NOT scom_isuonly_count_mode OR NOT trigger_didt_throttle) -// -// SPRN_IFU_ACTIVE_COUNTER -// Cycles that IFU throttle active input is asserted -// -// <= if_pc_didt_throttle_active - - -/// \note The OCC SPRC/SPRD hardware has a bug that makes it such that the OCC -/// SPRC increments whenever the OCC SPRD is accessed, regardless of the -/// setting of the SPRN_PC_AUTOINCREMENT bit. This bug won't be fixed. - -#define SPRN_CORE_INSTRUCTION_DISPATCH 0x200 -#define SPRN_CORE_INSTRUCTION_COMPLETE 0x208 -#define SPRN_CORE_FREQUENCY_SENSITIVITY_BUSY 0x210 -#define SPRN_CORE_FREQUENCY_SENSITIVITY_FINISH 0x218 -#define SPRN_CORE_RUN_CYCLE 0x220 -#define SPRN_CORE_RAW_CYCLE 0x228 -#define SPRN_CORE_MEM_HIER_A 0x230 -#define SPRN_CORE_MEM_HIER_B 0x238 -#define SPRN_CORE_MEM_C_LPAR(p) (0x240 + (8 * (p))) -#define SPRN_WEIGHTED_INSTRUCTION_PROCESSING 0x260 -#define SPRN_WEIGHTED_GPR_REGFILE_ACCESS 0x268 -#define SPRN_WEIGHTED_VRF_REGFILE_ACCESS 0x270 -#define SPRN_WEIGHTED_FLOATING_POINT_ISSUE 0x278 -#define SPRN_WEIGHTED_CACHE_READ 0x280 -#define SPRN_WEIGHTED_CACHE_WRITE 0x288 -#define SPRN_WEIGHTED_ISSUE 0x290 -#define SPRN_WEIGHTED_CACHE_ACCESS 0x298 -#define SPRN_WEIGHTED_VSU_ISSUE 0x2a0 -#define SPRN_WEIGHTED_FXU_ISSUE 0x2a8 - -#define SPRN_THREAD_RUN_CYCLES(t) (0x2b0 + (0x20 * (t))) -#define SPRN_THREAD_INSTRUCTION_COMPLETE(t) (0x2b8 + (0x20 * (t))) -#define SPRN_THREAD_MEM_HIER_A(t) (0x2c0 + (0x20 * (t))) -#define SPRN_THREAD_MEM_HIER_B(t) (0x2c8 + (0x20 * (t))) - -#define SPRN_IFU_THROTTLE_COUNTER 0x3b0 -#define SPRN_ISU_THROTTLE_COUNTER 0x3b8 -#define SPRN_IFU_ACTIVE_COUNTER 0x3c0 - -#define SPRN_PC_AUTOINCREMENT 0x400 - - -//////////////////////////////////////////////////////////////////////////// -// Centaur -//////////////////////////////////////////////////////////////////////////// - -// DIMM sensor status codes - -/// The next sampling period began before this sensor was read or the master -/// enable is off, or the individual sensor is disabled. If the subsequent -/// read completes on time, this will return to valid reading. Sensor data may -/// be accurate, but stale. If due to a stall, the StallError FIR will be -/// set. -#define DIMM_SENSOR_STATUS_STALLED 0 - -/// The sensor data was not returned correctly either due to parity -/// error or PIB bus error code. Will return to valid if the next PIB -/// access to this sensor is valid, but a FIR will be set; Refer to FIR -/// for exact error. Sensor data should not be considered valid while -/// this code is present. -#define DIMM_SENSOR_STATUS_ERROR 1 - -/// Sensor data is valid, and has been valid since the last time this -/// register was read. -#define DIMM_SENSOR_STATUS_VALID_OLD 2 - -/// Sensor data is valid and has not yet been read by a SCOM. The status code -/// return to DIMM_SENSOR_STATUS_VALID_OLD after this register is read. -#define DIMM_SENSOR_STATUS_VALID_NEW 3 - - -#endif /* __PGP_COMMON_H__ */ diff --git a/src/ssx/pgp/pgp_core.h b/src/ssx/pgp/pgp_core.h deleted file mode 100755 index 59edb26..0000000 --- a/src/ssx/pgp/pgp_core.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __PGP_CORE_H__ -#define __PGP_CORE_H__ - -// $Id: pgp_core.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_core.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_core.h -/// \brief PgP core units header. Local and mechanically generated macros. - -#include "pc_register_addresses.h" -#include "pc_firmware_registers.h" -#include "sensors_register_addresses.h" -#include "sensors_firmware_registers.h" - -#endif /* __PGP_CORE_H__ */ diff --git a/src/ssx/pgp/pgp_ocb.h b/src/ssx/pgp/pgp_ocb.h deleted file mode 100755 index fd36c9a..0000000 --- a/src/ssx/pgp/pgp_ocb.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __PGP_OCB_H__ -#define __PGP_OCB_H__ - -// $Id: pgp_ocb.h,v 1.2 2014/02/03 01:30:35 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_ocb.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_ocb.h -/// \brief OCB unit header. Local and mechanically generated macros and APIs. - -#include "ssx.h" -#include "ppc32.h" - -#include "pgp_common.h" -#include "ocb_register_addresses.h" -#include "ocb_firmware_registers.h" - -#include "ppc405_irq.h" - -#define OCB_TIMER0 0 -#define OCB_TIMER1 1 - -#define OCB_TIMERS 2 - -#define OCB_TIMER_ONE_SHOT 0 -#define OCB_TIMER_AUTO_RELOAD 1 - -#define OCB_LW_LOG_SIZE_MIN 3 -#define OCB_LW_LOG_SIZE_MAX 15 - -#define OCB_INVALID_ARGUMENT_TIMER 0x00622001 -#define OCB_INVALID_ARGUMENT_LW_INIT 0x00622002 -#define OCB_INVALID_ARGUMENT_LW_DISABLE 0x00622003 -#define OCB_INVALID_ARGUMENT_UNTRUST 0x00622004 - -#ifndef __ASSEMBLER__ - -int -ocb_timer_reset(int timer, - int auto_reload, - int timeout_ns); - -#ifdef OCC -int -ocb_timer_setup(int timer, - int auto_reload, - int timeout_ns, - SsxIrqHandler handler, - void *arg, - int priority) INIT_SECTION; -#else -int -ocb_timer_setup(int timer, - int auto_reload, - int timeout_ns, - SsxIrqHandler handler, - void *arg, - int priority); -#endif - -/// Clear OCB timer status based on the IRQ -/// -/// This API can be called from OCB timer interrupt handlers, using the IRQ -/// provided to the handler. No error checks are provided. - -static inline void -ocb_timer_status_clear(SsxIrqId irq) -{ - out32(OCB_OTRN(irq - PGP_IRQ_OCC_TIMER0), OCB_OTRN_TIMEOUT); -} - -int -ocb_linear_window_initialize(int channel, uint32_t base, int log_size); - -int -ocb_linear_window_disable(int channel); - -int -ocb_allow_untrusted_initialize(int channel, int allow_untrusted); - - -#endif /* __ASSEMBLER__ */ - -#endif /* __PGP_OCB_H__ */ diff --git a/src/ssx/pgp/pgp_pore.h b/src/ssx/pgp/pgp_pore.h deleted file mode 100755 index e40ccac..0000000 --- a/src/ssx/pgp/pgp_pore.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __PGP_PORE_H__ -#define __PGP_PORE_H__ - -// $Id: pgp_pore.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_pore.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_pore.h -/// \brief PORE unit header. Local and mechanically generated macros. - -#include "pore_register_addresses.h" -#include "pore_firmware_registers.h" - -/// The parameter for GPE-protocol triggering is the low-order word of the -/// EXE_TRIGGER register -#define PORE_EXE_PARAMETER_OFFSET (PORE_EXE_TRIGGER_OFFSET + 4) - -/// The PORE OCI address space descriptor -#define PORE_ADDRESS_SPACE_OCI 0x8000 - -/// The PORE BRAI opcode -#define PORE_BRAI 0xa2000000 - -/// The PORE BRAD D0 opcode -#define PORE_BRAD_D0 0x38500000 - - -#ifndef __ASSEMBLER__ - -/// The putative type of PORE program entry points - to make GCC happy -typedef void *(PoreEntryPoint)(void); - -#endif /* __ASSEMBLER__ */ - -#endif /* __PGP_PORE_H__ */ diff --git a/src/ssx/pgp/pgp_sramctl.h b/src/ssx/pgp/pgp_sramctl.h deleted file mode 100755 index fe2ed69..0000000 --- a/src/ssx/pgp/pgp_sramctl.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __PGP_SRAMCTL_H__ -#define __PGP_SRAMCTL_H__ - -// $Id: pgp_sramctl.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_sramctl.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_sramctl.h -/// \brief SRAMCTL unit header. Local and mechanically generated macros. - -#include "sramctl_register_addresses.h" -#include "sramctl_firmware_registers.h" - -#endif /* __PGP_SRAMCTL_H__ */ diff --git a/src/ssx/pgp/pgp_trace.h b/src/ssx/pgp/pgp_trace.h deleted file mode 100755 index 3544ce0..0000000 --- a/src/ssx/pgp/pgp_trace.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __PGP_TRACE_H__ -#define __PGP_TRACE_H__ - -// $Id: pgp_trace.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_trace.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_trace.h -/// \brief Implementation of SSX_TRACE macros for PgP -/// -/// Kernel and application tracing uses the PBA "OCI Marker Space", a 64KB OCI -/// register space implemented by PBA. When enabled in the PBA, any OCI write -/// transactions of any size are ACK'ed by the PBA and the data is ignored. -/// This creates an OCI transaction record that can be captured by the NHTM -/// for later analysis. -/// -/// SSX provides a generic SSX_TRACE() macro that accepts a single -/// parameter. On PgP, valid parameters are integers in the range -/// 0x0,...,0xffff. The PgP SSX kernel reserves trace addresses -/// 0xe000,...,0xffff for kernel event traces. Applications are free to use -/// the other trace addresses in the range 0x0000,...,0xdfff as they see fit. -/// -/// Application tracing is globally disabled by default, and is enabled by -/// defining the switch SSX_TRACE_ENABLE=1. Kernel event tracing is also -/// globally disabled by default, and is enabled by defining the switch -/// SSX_KERNEL_TRACE_ENABLE=1. Kernel event tracing adds overhead to every -/// interrupt handler and kernel API so should probably remain disabled unless -/// required. -/// -/// The Simics PBA model supports trace reporting, either to stdout or to a -/// file. To enable trace reporting set pba->trace_report = 1. To capture -/// traces to a file other than stdout, set pba->trace_file = \<filename\>. The -/// Simics model understands SSX kernel trace events and produces a readable -/// commentary of kernel traces events - user events will be reported simply -/// as the integer tag. - -#include "pgp_common.h" - -/// Output an OCI Trace Marker -/// -/// See the comments for the file pgp_trace.h - -#if SSX_TRACE_ENABLE -#define SSX_TRACE(event) out8(PBA_OCI_MARKER_BASE + (event), 0) -#endif - -#if SSX_KERNEL_TRACE_ENABLE - -// Note: The *BASE constants are defined in pgp_common.h - -#define SSX_KERNEL_TRACE(event) out8(PBA_OCI_MARKER_BASE + (event), 0) - -#define SSX_TRACE_THREAD_SLEEP(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SLEEP_BASE + priority) - -#define SSX_TRACE_THREAD_WAKEUP(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_WAKEUP_BASE + priority) - -#define SSX_TRACE_THREAD_SEMAPHORE_PEND(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE + priority) - -#define SSX_TRACE_THREAD_SEMAPHORE_POST(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_POST_BASE + priority) - -#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE + priority) - -#define SSX_TRACE_THREAD_SUSPENDED(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_SUSPENDED_BASE + priority) - -#define SSX_TRACE_THREAD_DELETED(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_DELETED_BASE + priority) - -#define SSX_TRACE_THREAD_COMPLETED(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_COMPLETED_BASE + priority) - -#define SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE + priority) - -#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE + priority) - -#define SSX_TRACE_THREAD_MAPPED_SLEEPING(priority) \ - SSX_KERNEL_TRACE(SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE + priority) - -#endif /* SSX_KERNEL_TRACE_ENABLE */ - - -#ifdef __ASSEMBLER__ - -// NB: CPP macros are not expanded as arguments to .if in GAS macro -// definitions. That's why e.g. we have to use _liw instead of _liwa. - -#if SSX_KERNEL_TRACE_ENABLE - - .macro SSX_TRACE_CRITICAL_IRQ_ENTRY, irqreg, scratch - _liw \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE) - stbx \irqreg, \irqreg, \scratch - eieio - .endm - - .macro SSX_TRACE_CRITICAL_IRQ_EXIT, scratch0, scratch1 - _liw \scratch0, (PBA_OCI_MARKER_BASE + SSX_TRACE_CRITICAL_IRQ_EXIT_BASE) - mfusprg0 \scratch1 - extrwi \scratch1, \scratch1, 8, 16 - stbx \scratch1, \scratch0, \scratch1 - eieio - .endm - - .macro SSX_TRACE_NONCRITICAL_IRQ_ENTRY, irqreg, scratch - _liw \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE) - stbx \irqreg, \irqreg, \scratch - eieio - .endm - - .macro SSX_TRACE_NONCRITICAL_IRQ_EXIT, scratch0, scratch1 - _liw \scratch0, (PBA_OCI_MARKER_BASE + SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE) - mfusprg0 \scratch1 - extrwi \scratch1, \scratch1, 8, 16 - stbx \scratch1, \scratch0, \scratch1 - eieio - .endm - - .macro SSX_TRACE_THREAD_SWITCH, priority, scratch - _liw \scratch, (PBA_OCI_MARKER_BASE + SSX_TRACE_THREAD_SWITCH_BASE) - stbx \priority, \priority, \scratch - eieio - .endm - -#else /* SSX_KERNEL_TRACE_ENABLE */ - - .macro SSX_TRACE_CRITICAL_IRQ_ENTRY, irq, scratch - .endm - - .macro SSX_TRACE_CRITICAL_IRQ_EXIT, scratch0, scratch1 - .endm - - .macro SSX_TRACE_NONCRITICAL_IRQ_ENTRY, irq, scratch - .endm - - .macro SSX_TRACE_NONCRITICAL_IRQ_EXIT, scratch0, scratch1 - .endm - - .macro SSX_TRACE_THREAD_SWITCH, priority, scratch - .endm - -#endif /* SSX_KERNEL_TRACE_ENABLE */ - -#endif /* __ASSEMBLER__ */ - -#endif /* __PGP_TRACE_H__ */ diff --git a/src/ssx/pgp/pgp_vrm.h b/src/ssx/pgp/pgp_vrm.h deleted file mode 100755 index aaa6760..0000000 --- a/src/ssx/pgp/pgp_vrm.h +++ /dev/null @@ -1,223 +0,0 @@ -#ifndef __PGP_VRM_H__ -#define __PGP_VRM_H__ - -// $Id: pgp_vrm.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/pgp_vrm.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pgp_vrm.h -/// \brief Header for PgP VRM device drivers. Some constants are also held in -/// pgp_common.h. - -#include "pgp_common.h" - - -#ifndef __ASSEMBLER__ - -/// VRM Command Header -/// -/// This structure defines the values written on the SPI interface for -/// 'read' commands. - -//typedef union { -// uint64_t value; -// uint32_t word[2]; -// struct { -// uint64_t address : 4; -// uint64_t command : 4; -// } fields; -//} vrm_command_t; - - -/// VRM Write Transaction Command -/// -/// The 8-bit \a phase_enable is an 8-bit VRM-11 VID code -/// -/// The 8-bit \a vcs_offset is an 8-bit signed offset - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t command : 4; - uint64_t phase_enable : 4; - uint64_t vdd_vid : 8; - uint64_t vcs_offset : 8; - uint64_t master_crc : 8; - } fields; -} vrm_write_transaction_t; - - -/// VRM Write Transaction Response -/// writes status is duplicated 3x for the minority detect feature. - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t write_status0 : 8; - uint64_t write_status1 : 8; - uint64_t write_status2 : 8; - uint64_t optional_crc : 8; - } fields; -} vrm_write_resp_t; - - - -/// VRM Read State Command -/// reserved field should be sent as 0s - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t command : 4; - uint64_t reserved : 20; - uint64_t master_crc : 8; - } fields; -} vrm_read_state_t; - - -/// VRM Read State Response -/// Results are duplicated 3x for the minority detecte feature. - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t read_ready0 : 1; - uint64_t minus_nplus1_0 : 1; - uint64_t minus_n0 : 1; - uint64_t reserved1_0 : 1; - uint64_t vrm_fan0 : 1; - uint64_t vrm_overtemp0 : 1; - uint64_t reserved2_0 : 2; - uint64_t read_ready1 : 1; - uint64_t minus_nplus1_1 : 1; - uint64_t minus_n1 : 1; - uint64_t reserved1_1 : 1; - uint64_t vrm_fan1 : 1; - uint64_t vrm_overtemp1 : 1; - uint64_t reserved2_1 : 2; - uint64_t read_ready2 : 1; - uint64_t minus_nplus1_2 : 1; - uint64_t minus_n2 : 1; - uint64_t reserved1_2 : 1; - uint64_t vrm_fan2 : 1; - uint64_t vrm_overtemp2 : 1; - uint64_t reserved2_2 : 2; - uint64_t slave_crc : 8; - } fields; -} vrm_read_state_resp_t; - -/// VRM Read Voltage Command -/// reserved field should be sent as 0s - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t command : 4; - uint64_t rail : 4; - uint64_t reserved : 1; - uint64_t master_crc : 8; - } fields; -} vrm_read_voltage_t; - - -/// VRM Read Voltage Response -/// Results are duplicated 3x for the minority detect feature. - -typedef union { - uint64_t value; - uint32_t word[2]; - struct { - uint64_t vid0 : 8; - uint64_t vid1 : 8; - uint64_t vid2 : 8; - uint64_t slave_crc : 8; - } fields; -} vrm_read_voltage_resp_t; - - -/// VRM Read Current 1 Response -/// -/// The 16-bit current readings come from 12-bit DACS; the DAC output is -/// right-padded with 0b0000. The current units are 0.025 Ampere. - -//typedef union { -// uint64_t value; -// uint32_t word[2]; -// struct { -// uint64_t header : 8; -// uint64_t read_not_ready : 1; -// uint64_t minus_nplus1 : 1; -// uint64_t minus_n : 1; -// uint64_t reserved0 : 1; -// uint64_t vrm_fan : 1; -// uint64_t vrm_overtemp : 1; -// uint64_t reserved1 : 2; -// uint64_t vdd_current : 16; -// uint64_t vcs_current : 16; -// uint64_t vio_current : 16; -// } fields; -//} vrm_read_current_1_t; - - -/// VRM Read Current 2 Response -/// -/// The 16-bit current readings come from 12-bit DACS; the DAC output is -/// right-padded with 0b0000. The current units are 0.025 Ampere. - -//typedef union { -// uint64_t value; -// uint32_t word[2]; -// struct { -// uint64_t header : 8; -// uint64_t read_not_ready : 1; -// uint64_t minus_nplus1 : 1; -// uint64_t minus_n : 1; -// uint64_t reserved0 : 1; -// uint64_t vrm_fan : 1; -// uint64_t vrm_overtemp : 1; -// uint64_t reserved1 : 2; -// uint64_t spare1_current : 16; -// uint64_t spare2_current : 16; -// uint64_t spare3_current : 16; -// } fields; -//} vrm_read_current_2_t; - -#endif /* __ASSEMBLER__ */ - -// These are the default values for the SPIVRM/O2S interface - -#define SPIVRM_BITS 71 /* Actual # of bits minus 1 */ -#define SPIVRM_CPOL 0 /* Clock polarity */ -#define SPIVRM_CPHA 0 /* Clock phase */ -#define SPIVRM_FREQUENCY_HZ 16000000 /* 16 MHz */ -#define SPIVRM_ENABLE_ECC 1 -#define SPIVRM_NPORTS 3 /* Maximum # of ports supported by HW */ -#define SPIVRM_NRAILS 2 /* Maximum # of rails supported by read voltage cmd*/ -#define SPIVRM_ENABLED_PORTS 0x4 /* 3 bit mask, left justified */ -#define SPIVRM_PHASES 15 /* System dependent */ - -/// Convert an integer index into a VRM designator (mask) -#define SPIVRM_PORT(i) (1 << (SPIVRM_NPORTS - (i) - 1)) - -// SPIVRM specific setup defaults - -#define SPIVRM_READ_STATUS_DELAY 48 /* Cycles, system dependent */ -#define SPIVRM_ADDRESS 0 /* First 4 bits of SPIVRM packet */ - -// Default values for the O2S bridge - -#define O2S_BRIDGE_ENABLE 1 -#define O2S_READ_DELAY 48 /* Cycles, system dependent */ -#define O2S_ADDRESS 0 /* First 4 bits of O2S packet */ - - -#endif /* __PGP_VRM_H__ */ diff --git a/src/ssx/pgp/registers/centaur_firmware_registers.h b/src/ssx/pgp/registers/centaur_firmware_registers.h deleted file mode 100755 index 39f168f..0000000 --- a/src/ssx/pgp/registers/centaur_firmware_registers.h +++ /dev/null @@ -1,1496 +0,0 @@ -#ifndef __CENTAUR_FIRMWARE_REGISTERS_H__ -#define __CENTAUR_FIRMWARE_REGISTERS_H__ - -// $Id: centaur_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file centaur_firmware_registers.h -/// \brief C register structs for the CENTAUR unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union centaur_device_id { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cfam_id : 32; - uint64_t module_id : 2; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t module_id : 2; - uint64_t cfam_id : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_device_id_t; - - - -typedef union centaur_mbs_fir_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_reg_t; - - - -typedef union centaur_mbs_fir_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_reg_and_t; - - - -typedef union centaur_mbs_fir_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_reg_or_t; - - - -typedef union centaur_mbs_fir_mask_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_mask_reg_t; - - - -typedef union centaur_mbs_fir_mask_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_mask_reg_and_t; - - - -typedef union centaur_mbs_fir_mask_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_mask_reg_or_t; - - - -typedef union centaur_mbs_fir_action0_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_fir_action0_reg_t; - - - -typedef union centaur_mbs_firact1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t host_protocol_error : 1; - uint64_t int_protocol_error : 1; - uint64_t invalid_address_error : 1; - uint64_t external_timeout : 1; - uint64_t internal_timeout : 1; - uint64_t int_buffer_ce : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_parity_error : 1; - uint64_t cache_srw_ce : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_sue : 1; - uint64_t dir_ce : 1; - uint64_t dir_ue : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t lru_error : 1; - uint64_t edram_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t host_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t occ_inband_write_error : 1; - uint64_t srb_buffer_ce : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_sue : 1; - uint64_t dir_purge_ce : 1; - uint64_t spare_fir30 : 1; - uint64_t spare_fir31 : 1; - uint64_t internal_scom_error : 1; - uint64_t internal_scom_error_copy : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t internal_scom_error_copy : 1; - uint64_t internal_scom_error : 1; - uint64_t spare_fir31 : 1; - uint64_t spare_fir30 : 1; - uint64_t dir_purge_ce : 1; - uint64_t srb_buffer_sue : 1; - uint64_t srb_buffer_ue : 1; - uint64_t srb_buffer_ce : 1; - uint64_t occ_inband_write_error : 1; - uint64_t occ_inband_read_error : 1; - uint64_t host_inband_write_error : 1; - uint64_t host_inband_read_error : 1; - uint64_t emergency_throttle_set : 1; - uint64_t edram_error : 1; - uint64_t lru_error : 1; - uint64_t dir_all_members_deleted : 1; - uint64_t dir_member_deleted : 1; - uint64_t dir_ue : 1; - uint64_t dir_ce : 1; - uint64_t cache_co_sue : 1; - uint64_t cache_co_ue : 1; - uint64_t cache_co_ce : 1; - uint64_t cache_srw_sue : 1; - uint64_t cache_srw_ue : 1; - uint64_t cache_srw_ce : 1; - uint64_t int_parity_error : 1; - uint64_t int_buffer_sue : 1; - uint64_t int_buffer_ue : 1; - uint64_t int_buffer_ce : 1; - uint64_t internal_timeout : 1; - uint64_t external_timeout : 1; - uint64_t invalid_address_error : 1; - uint64_t int_protocol_error : 1; - uint64_t host_protocol_error : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbs_firact1_t; - - - -typedef union centaur_mbscfgq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t eccbp_exit_sel : 1; - uint64_t dram_ecc_bypass_dis : 1; - uint64_t mbs_scom_wat_trigger : 1; - uint64_t mbs_prq_ref_avoidance_en : 1; - uint64_t reserved4_6 : 3; - uint64_t occ_deadman_timer_sel : 4; - uint64_t sync_fsync_mba_strobe_en : 1; - uint64_t hca_timebase_op_mode : 1; - uint64_t hca_local_timer_inc_select : 3; - uint64_t mbs_01_rdtag_delay : 4; - uint64_t mbs_01_rdtag_force_dead_cycle : 1; - uint64_t sync_lat_pol_01 : 1; - uint64_t sync_lat_adj_01 : 2; - uint64_t mbs_23_rdtag_delay : 4; - uint64_t mbs_23_rdtag_force_dead_cycle : 1; - uint64_t sync_lat_pol_23 : 1; - uint64_t sync_lat_adj_23 : 2; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t sync_lat_adj_23 : 2; - uint64_t sync_lat_pol_23 : 1; - uint64_t mbs_23_rdtag_force_dead_cycle : 1; - uint64_t mbs_23_rdtag_delay : 4; - uint64_t sync_lat_adj_01 : 2; - uint64_t sync_lat_pol_01 : 1; - uint64_t mbs_01_rdtag_force_dead_cycle : 1; - uint64_t mbs_01_rdtag_delay : 4; - uint64_t hca_local_timer_inc_select : 3; - uint64_t hca_timebase_op_mode : 1; - uint64_t sync_fsync_mba_strobe_en : 1; - uint64_t occ_deadman_timer_sel : 4; - uint64_t reserved4_6 : 3; - uint64_t mbs_prq_ref_avoidance_en : 1; - uint64_t mbs_scom_wat_trigger : 1; - uint64_t dram_ecc_bypass_dis : 1; - uint64_t eccbp_exit_sel : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbscfgq_t; - - - -typedef union centaur_mbsemerthroq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t emergency_throttle_ip : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t emergency_throttle_ip : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbsemerthroq_t; - - - -typedef union centaur_mbsocc01hq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_01_rd_hit : 32; - uint64_t occ_01_wr_hit : 32; -#else - uint64_t occ_01_wr_hit : 32; - uint64_t occ_01_rd_hit : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbsocc01hq_t; - - - -typedef union centaur_mbsocc23hq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_23_rd_hit : 32; - uint64_t occ_23_wr_hit : 32; -#else - uint64_t occ_23_wr_hit : 32; - uint64_t occ_23_rd_hit : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbsocc23hq_t; - - - -typedef union centaur_mbsoccitcq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_cent_idle_th_cnt : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t occ_cent_idle_th_cnt : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbsoccitcq_t; - - - -typedef union centaur_mbsoccscanq { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_01_spec_can : 32; - uint64_t occ_23_spec_can : 32; -#else - uint64_t occ_23_spec_can : 32; - uint64_t occ_01_spec_can : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbsoccscanq_t; - - - -typedef union centaur_mbarpc0qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cfg_lp2_entry_req : 1; - uint64_t cfg_lp2_state : 1; - uint64_t cfg_min_max_domains_enable : 1; - uint64_t cfg_min_max_domains : 3; - uint64_t cfg_pup_avail : 5; - uint64_t cfg_pdn_pup : 5; - uint64_t cfg_pup_pdn : 5; - uint64_t reserved0 : 1; - uint64_t cfg_min_domain_reduction_enable : 1; - uint64_t cfg_min_domain_reduction_on_time : 10; - uint64_t cfg_pup_after_activate_wait_enable : 1; - uint64_t cfg_pup_after_activate_wait_time : 8; - uint64_t cfg_force_spare_pup : 1; - uint64_t _reserved0 : 21; -#else - uint64_t _reserved0 : 21; - uint64_t cfg_force_spare_pup : 1; - uint64_t cfg_pup_after_activate_wait_time : 8; - uint64_t cfg_pup_after_activate_wait_enable : 1; - uint64_t cfg_min_domain_reduction_on_time : 10; - uint64_t cfg_min_domain_reduction_enable : 1; - uint64_t reserved0 : 1; - uint64_t cfg_pup_pdn : 5; - uint64_t cfg_pdn_pup : 5; - uint64_t cfg_pup_avail : 5; - uint64_t cfg_min_max_domains : 3; - uint64_t cfg_min_max_domains_enable : 1; - uint64_t cfg_lp2_state : 1; - uint64_t cfg_lp2_entry_req : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbarpc0qn_t; - - - -typedef union centaur_mba_farb3qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cfg_nm_n_per_mba : 15; - uint64_t cfg_nm_n_per_chip : 16; - uint64_t cfg_nm_m : 14; - uint64_t cfg_nm_ras_weight : 3; - uint64_t cfg_nm_cas_weight : 3; - uint64_t cfg_nm_per_slot_enabled : 1; - uint64_t cfg_nm_count_other_mba_dis : 1; - uint64_t _reserved0 : 11; -#else - uint64_t _reserved0 : 11; - uint64_t cfg_nm_count_other_mba_dis : 1; - uint64_t cfg_nm_per_slot_enabled : 1; - uint64_t cfg_nm_cas_weight : 3; - uint64_t cfg_nm_ras_weight : 3; - uint64_t cfg_nm_m : 14; - uint64_t cfg_nm_n_per_chip : 16; - uint64_t cfg_nm_n_per_mba : 15; -#endif // _BIG_ENDIAN - } fields; -} centaur_mba_farb3qn_t; - - - -typedef union centaur_mbapcn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t mode_hp_sub_cnt : 1; - uint64_t mode_lp_sub_cnt : 1; - uint64_t mode_static_idle_dly : 5; - uint64_t mode_emer_min_max_domain : 3; - uint64_t mode_pup_all_wr_pending : 2; - uint64_t mode_lp_ref_sim_enq : 1; - uint64_t _reserved0 : 51; -#else - uint64_t _reserved0 : 51; - uint64_t mode_lp_ref_sim_enq : 1; - uint64_t mode_pup_all_wr_pending : 2; - uint64_t mode_emer_min_max_domain : 3; - uint64_t mode_static_idle_dly : 5; - uint64_t mode_lp_sub_cnt : 1; - uint64_t mode_hp_sub_cnt : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbapcn_t; - - - -typedef union centaur_mbasrqn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t emergency_m : 14; - uint64_t emergency_n : 15; - uint64_t _reserved0 : 35; -#else - uint64_t _reserved0 : 35; - uint64_t emergency_n : 15; - uint64_t emergency_m : 14; -#endif // _BIG_ENDIAN - } fields; -} centaur_mbasrqn_t; - - - -typedef union centaur_pmu0qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t read_count : 32; - uint64_t write_count : 32; -#else - uint64_t write_count : 32; - uint64_t read_count : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu0qn_t; - - - -typedef union centaur_pmu1qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t activate_count : 32; - uint64_t pu_counts : 32; -#else - uint64_t pu_counts : 32; - uint64_t activate_count : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu1qn_t; - - - -typedef union centaur_pmu2qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t frame_count : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t frame_count : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu2qn_t; - - - -typedef union centaur_pmu3qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t low_idle_threshold : 16; - uint64_t med_idle_threshold : 16; - uint64_t high_idle_threshold : 32; -#else - uint64_t high_idle_threshold : 32; - uint64_t med_idle_threshold : 16; - uint64_t low_idle_threshold : 16; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu3qn_t; - - - -typedef union centaur_pmu4qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t base_idle_count : 32; - uint64_t low_idle_count : 32; -#else - uint64_t low_idle_count : 32; - uint64_t base_idle_count : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu4qn_t; - - - -typedef union centaur_pmu5qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t med_idle_count : 32; - uint64_t high_idle_count : 32; -#else - uint64_t high_idle_count : 32; - uint64_t med_idle_count : 32; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu5qn_t; - - - -typedef union centaur_pmu6qn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t total_gap_counts : 18; - uint64_t specific_gap_counts : 18; - uint64_t gap_length_adder : 3; - uint64_t specific_gap_condition : 4; - uint64_t cmd_to_cmd_count : 18; - uint64_t command_pattern_to_count : 3; -#else - uint64_t command_pattern_to_count : 3; - uint64_t cmd_to_cmd_count : 18; - uint64_t specific_gap_condition : 4; - uint64_t gap_length_adder : 3; - uint64_t specific_gap_counts : 18; - uint64_t total_gap_counts : 18; -#endif // _BIG_ENDIAN - } fields; -} centaur_pmu6qn_t; - - - -typedef union centaur_sensor_cache_data0_3 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t crittrip0 : 1; - uint64_t abovetrip0 : 1; - uint64_t belowtrip0 : 1; - uint64_t signbit0 : 1; - uint64_t temperature0 : 8; - uint64_t temp_frac0 : 2; - uint64_t status0 : 2; - uint64_t crittrip1 : 1; - uint64_t abovetrip1 : 1; - uint64_t belowtrip1 : 1; - uint64_t signbit1 : 1; - uint64_t temperature1 : 8; - uint64_t temp_frac1 : 2; - uint64_t status1 : 2; - uint64_t crittrip2 : 1; - uint64_t abovetrip2 : 1; - uint64_t belowtrip2 : 1; - uint64_t signbit2 : 1; - uint64_t temperature2 : 8; - uint64_t temp_frac2 : 2; - uint64_t status2 : 2; - uint64_t crittrip3 : 1; - uint64_t abovetrip3 : 1; - uint64_t belowtrip3 : 1; - uint64_t signbit3 : 1; - uint64_t temperature3 : 8; - uint64_t temp_frac3 : 2; - uint64_t status3 : 2; -#else - uint64_t status3 : 2; - uint64_t temp_frac3 : 2; - uint64_t temperature3 : 8; - uint64_t signbit3 : 1; - uint64_t belowtrip3 : 1; - uint64_t abovetrip3 : 1; - uint64_t crittrip3 : 1; - uint64_t status2 : 2; - uint64_t temp_frac2 : 2; - uint64_t temperature2 : 8; - uint64_t signbit2 : 1; - uint64_t belowtrip2 : 1; - uint64_t abovetrip2 : 1; - uint64_t crittrip2 : 1; - uint64_t status1 : 2; - uint64_t temp_frac1 : 2; - uint64_t temperature1 : 8; - uint64_t signbit1 : 1; - uint64_t belowtrip1 : 1; - uint64_t abovetrip1 : 1; - uint64_t crittrip1 : 1; - uint64_t status0 : 2; - uint64_t temp_frac0 : 2; - uint64_t temperature0 : 8; - uint64_t signbit0 : 1; - uint64_t belowtrip0 : 1; - uint64_t abovetrip0 : 1; - uint64_t crittrip0 : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_sensor_cache_data0_3_t; - - - -typedef union centaur_sensor_cache_data4_7 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t crittrip4 : 1; - uint64_t abovetrip4 : 1; - uint64_t belowtrip4 : 1; - uint64_t signbit4 : 1; - uint64_t temperature4 : 8; - uint64_t temp_frac4 : 2; - uint64_t status4 : 2; - uint64_t crittrip5 : 1; - uint64_t abovetrip5 : 1; - uint64_t belowtrip5 : 1; - uint64_t signbit5 : 1; - uint64_t temperature5 : 8; - uint64_t temp_frac5 : 2; - uint64_t status5 : 2; - uint64_t crittrip6 : 1; - uint64_t abovetrip6 : 1; - uint64_t belowtrip6 : 1; - uint64_t signbit6 : 1; - uint64_t temperature6 : 8; - uint64_t temp_frac6 : 2; - uint64_t status6 : 2; - uint64_t crittrip7 : 1; - uint64_t abovetrip7 : 1; - uint64_t belowtrip7 : 1; - uint64_t signbit7 : 1; - uint64_t temperature7 : 8; - uint64_t temp_frac7 : 2; - uint64_t status7 : 2; -#else - uint64_t status7 : 2; - uint64_t temp_frac7 : 2; - uint64_t temperature7 : 8; - uint64_t signbit7 : 1; - uint64_t belowtrip7 : 1; - uint64_t abovetrip7 : 1; - uint64_t crittrip7 : 1; - uint64_t status6 : 2; - uint64_t temp_frac6 : 2; - uint64_t temperature6 : 8; - uint64_t signbit6 : 1; - uint64_t belowtrip6 : 1; - uint64_t abovetrip6 : 1; - uint64_t crittrip6 : 1; - uint64_t status5 : 2; - uint64_t temp_frac5 : 2; - uint64_t temperature5 : 8; - uint64_t signbit5 : 1; - uint64_t belowtrip5 : 1; - uint64_t abovetrip5 : 1; - uint64_t crittrip5 : 1; - uint64_t status4 : 2; - uint64_t temp_frac4 : 2; - uint64_t temperature4 : 8; - uint64_t signbit4 : 1; - uint64_t belowtrip4 : 1; - uint64_t abovetrip4 : 1; - uint64_t crittrip4 : 1; -#endif // _BIG_ENDIAN - } fields; -} centaur_sensor_cache_data4_7_t; - - - -typedef union centaur_dts_thermal_sensor_results { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts0 : 12; - uint64_t thermal_trip0 : 2; - uint64_t spare0 : 1; - uint64_t valid0 : 1; - uint64_t dts1 : 12; - uint64_t thermal_trip1 : 2; - uint64_t spare1 : 1; - uint64_t valid1 : 1; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t valid1 : 1; - uint64_t spare1 : 1; - uint64_t thermal_trip1 : 2; - uint64_t dts1 : 12; - uint64_t valid0 : 1; - uint64_t spare0 : 1; - uint64_t thermal_trip0 : 2; - uint64_t dts0 : 12; -#endif // _BIG_ENDIAN - } fields; -} centaur_dts_thermal_sensor_results_t; - - -#endif // __ASSEMBLER__ -#endif // __CENTAUR_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/centaur_register_addresses.h b/src/ssx/pgp/registers/centaur_register_addresses.h deleted file mode 100755 index 7c9c095..0000000 --- a/src/ssx/pgp/registers/centaur_register_addresses.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef __CENTAUR_REGISTER_ADDRESSES_H__ -#define __CENTAUR_REGISTER_ADDRESSES_H__ - -// $Id: centaur_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file centaur_register_addresses.h -/// \brief Symbolic addresses for the CENTAUR unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define CENTAUR_PIB_BASE 0 -#define CENTAUR_DEVICE_ID 0x000f000f -#define CENTAUR_MBS_FIR_REG 0x02011400 -#define CENTAUR_MBS_FIR_REG_AND 0x02011401 -#define CENTAUR_MBS_FIR_REG_OR 0x02011402 -#define CENTAUR_MBS_FIR_MASK_REG 0x02011403 -#define CENTAUR_MBS_FIR_MASK_REG_AND 0x02011404 -#define CENTAUR_MBS_FIR_MASK_REG_OR 0x02011405 -#define CENTAUR_MBS_FIR_ACTION0_REG 0x02011406 -#define CENTAUR_MBS_FIRACT1 0x02011407 -#define CENTAUR_MBSCFGQ 0x02011411 -#define CENTAUR_MBSEMERTHROQ 0x0201142d -#define CENTAUR_MBSOCC01HQ 0x02011429 -#define CENTAUR_MBSOCC23HQ 0x0201142a -#define CENTAUR_MBSOCCITCQ 0x02011428 -#define CENTAUR_MBSOCCSCANQ 0x0201142b -#define CENTAUR_MBARPC0QN(n) (CENTAUR_MBARPC0Q0 + ((CENTAUR_MBARPC0Q1 - CENTAUR_MBARPC0Q0) * (n))) -#define CENTAUR_MBARPC0Q0 0x03010434 -#define CENTAUR_MBARPC0Q1 0x03010c34 -#define CENTAUR_MBA_FARB3QN(n) (CENTAUR_MBA_FARB3Q0 + ((CENTAUR_MBA_FARB3Q1 - CENTAUR_MBA_FARB3Q0) * (n))) -#define CENTAUR_MBA_FARB3Q0 0x03010416 -#define CENTAUR_MBA_FARB3Q1 0x03010c16 -#define CENTAUR_PMU0QN(n) (CENTAUR_PMU0Q0 + ((CENTAUR_PMU0Q1 - CENTAUR_PMU0Q0) * (n))) -#define CENTAUR_PMU0Q0 0x03010437 -#define CENTAUR_PMU0Q1 0x03010c37 -#define CENTAUR_PMU1QN(n) (CENTAUR_PMU1Q0 + ((CENTAUR_PMU1Q1 - CENTAUR_PMU1Q0) * (n))) -#define CENTAUR_PMU1Q0 0x03010438 -#define CENTAUR_PMU1Q1 0x03010c38 -#define CENTAUR_PMU2QN(n) (CENTAUR_PMU2Q0 + ((CENTAUR_PMU2Q1 - CENTAUR_PMU2Q0) * (n))) -#define CENTAUR_PMU2Q0 0x03010439 -#define CENTAUR_PMU2Q1 0x03010c39 -#define CENTAUR_PMU3QN(n) (CENTAUR_PMU3Q0 + ((CENTAUR_PMU3Q1 - CENTAUR_PMU3Q0) * (n))) -#define CENTAUR_PMU3Q0 0x0301043a -#define CENTAUR_PMU3Q1 0x03010c3a -#define CENTAUR_PMU4QN(n) (CENTAUR_PMU4Q0 + ((CENTAUR_PMU4Q1 - CENTAUR_PMU4Q0) * (n))) -#define CENTAUR_PMU4Q0 0x0301043b -#define CENTAUR_PMU4Q1 0x03010c3b -#define CENTAUR_PMU5QN(n) (CENTAUR_PMU5Q0 + ((CENTAUR_PMU5Q1 - CENTAUR_PMU5Q0) * (n))) -#define CENTAUR_PMU5Q0 0x0301043c -#define CENTAUR_PMU5Q1 0x03010c3c -#define CENTAUR_PMU6QN(n) (CENTAUR_PMU6Q0 + ((CENTAUR_PMU6Q1 - CENTAUR_PMU6Q0) * (n))) -#define CENTAUR_PMU6Q0 0x0301043d -#define CENTAUR_PMU6Q1 0x03010c3d -#define CENTAUR_SENSOR_CACHE_DATA0_3 0x020115ca -#define CENTAUR_SENSOR_CACHE_DATA4_7 0x020115cb -#define CENTAUR_DTS_THERMAL_SENSOR_RESULTS 0x02050000 - -#endif // __CENTAUR_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/fasti2c_firmware_registers.h b/src/ssx/pgp/registers/fasti2c_firmware_registers.h deleted file mode 100644 index 4390508..0000000 --- a/src/ssx/pgp/registers/fasti2c_firmware_registers.h +++ /dev/null @@ -1,232 +0,0 @@ -#ifndef __FASTI2C_FIRMWARE_REGISTERS_H__ -#define __FASTI2C_FIRMWARE_REGISTERS_H__ - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -// $Id: fasti2c_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ - -/// \file fasti2c_firmware_registers.h -/// \brief C register structs for the FASTI2C unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#include <stdint.h> - - - -typedef union fasti2c_control { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t with_start : 1; - uint64_t with_address : 1; - uint64_t read_continue : 1; - uint64_t with_stop : 1; - uint64_t data_length : 4; - uint64_t device_address : 7; - uint64_t read_not_write : 1; - uint64_t speed : 2; - uint64_t port_number : 5; - uint64_t address_range : 3; - uint64_t _reserved0 : 6; - uint64_t data0 : 8; - uint64_t data1 : 8; - uint64_t data2 : 8; - uint64_t data3 : 8; -#else - uint64_t data3 : 8; - uint64_t data2 : 8; - uint64_t data1 : 8; - uint64_t data0 : 8; - uint64_t _reserved0 : 6; - uint64_t address_range : 3; - uint64_t port_number : 5; - uint64_t speed : 2; - uint64_t read_not_write : 1; - uint64_t device_address : 7; - uint64_t data_length : 4; - uint64_t with_stop : 1; - uint64_t read_continue : 1; - uint64_t with_address : 1; - uint64_t with_start : 1; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_control_t; - - - -typedef union fasti2c_reset { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_reset_t; - - - -typedef union fasti2c_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pib_address_invalid : 1; - uint64_t pib_write_invalid : 1; - uint64_t pib_read_invalid : 1; - uint64_t pib_address_parity_error : 1; - uint64_t pib_parity_error : 1; - uint64_t lb_parity_error : 1; - uint64_t read_data : 32; - uint64_t _reserved0 : 6; - uint64_t i2c_macro_busy : 1; - uint64_t i2c_invalid_command : 1; - uint64_t i2c_parity_error : 1; - uint64_t i2c_back_end_overrun_error : 1; - uint64_t i2c_back_end_access_error : 1; - uint64_t i2c_arbitration_lost : 1; - uint64_t i2c_nack_received : 1; - uint64_t i2c_data_request : 1; - uint64_t i2c_command_complete : 1; - uint64_t i2c_stop_error : 1; - uint64_t i2c_port_busy : 1; - uint64_t i2c_interface_busy : 1; - uint64_t i2c_fifo_entry_count : 8; -#else - uint64_t i2c_fifo_entry_count : 8; - uint64_t i2c_interface_busy : 1; - uint64_t i2c_port_busy : 1; - uint64_t i2c_stop_error : 1; - uint64_t i2c_command_complete : 1; - uint64_t i2c_data_request : 1; - uint64_t i2c_nack_received : 1; - uint64_t i2c_arbitration_lost : 1; - uint64_t i2c_back_end_access_error : 1; - uint64_t i2c_back_end_overrun_error : 1; - uint64_t i2c_parity_error : 1; - uint64_t i2c_invalid_command : 1; - uint64_t i2c_macro_busy : 1; - uint64_t _reserved0 : 6; - uint64_t read_data : 32; - uint64_t lb_parity_error : 1; - uint64_t pib_parity_error : 1; - uint64_t pib_address_parity_error : 1; - uint64_t pib_read_invalid : 1; - uint64_t pib_write_invalid : 1; - uint64_t pib_address_invalid : 1; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_status_t; - - - -typedef union fasti2c_data { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_data_t; - - - -typedef union fasti2c_ecc_start { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_ecc_start_t; - - - -typedef union fasti2c_ecc_stop { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} fasti2c_ecc_stop_t; - - -#endif // __ASSEMBLER__ -#endif // __FASTI2C_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/fasti2c_register_addresses.h b/src/ssx/pgp/registers/fasti2c_register_addresses.h deleted file mode 100644 index b034831..0000000 --- a/src/ssx/pgp/registers/fasti2c_register_addresses.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __FASTI2C_REGISTER_ADDRESSES_H__ -#define __FASTI2C_REGISTER_ADDRESSES_H__ - -// $Id: fasti2c_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ - -/// \file fasti2c_register_addresses.h -/// \brief Symbolic addresses for the FASTI2C unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define FASTI2C_LPCM_PIB_BASE 0x0000000b -#define FASTI2C_CONTROL_OFFSET 0x00000000 -#define FASTI2C_LPCM_CONTROL 0x0000000b -#define FASTI2C_RESET_OFFSET 0x00000001 -#define FASTI2C_LPCM_RESET 0x0000000c -#define FASTI2C_STATUS_OFFSET 0x00000002 -#define FASTI2C_LPCM_STATUS 0x0000000d -#define FASTI2C_DATA_OFFSET 0x00000003 -#define FASTI2C_LPCM_DATA 0x0000000e -#define FASTI2C_ECC_START_OFFSET 0x00000004 -#define FASTI2C_LPCM_ECC_START 0x0000000f -#define FASTI2C_ECC_STOP_OFFSET 0x00000005 -#define FASTI2C_LPCM_ECC_STOP 0x00000010 - -#endif // __FASTI2C_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/i2cengine_firmware_registers.h b/src/ssx/pgp/registers/i2cengine_firmware_registers.h deleted file mode 100644 index ed02574..0000000 --- a/src/ssx/pgp/registers/i2cengine_firmware_registers.h +++ /dev/null @@ -1,710 +0,0 @@ -#ifndef __I2CENGINE_FIRMWARE_REGISTERS_H__ -#define __I2CENGINE_FIRMWARE_REGISTERS_H__ - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -// $Id: i2cengine_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ - -/// \file i2cengine_firmware_registers.h -/// \brief C register structs for the I2CENGINE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#include <stdint.h> - - - -typedef union i2cengine_fast_control { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t with_start : 1; - uint64_t with_address : 1; - uint64_t read_continue : 1; - uint64_t with_stop : 1; - uint64_t data_length : 4; - uint64_t device_address : 7; - uint64_t read_not_write : 1; - uint64_t speed : 2; - uint64_t port_number : 5; - uint64_t address_range : 3; - uint64_t _reserved0 : 6; - uint64_t data0 : 8; - uint64_t data1 : 8; - uint64_t data2 : 8; - uint64_t data3 : 8; -#else - uint64_t data3 : 8; - uint64_t data2 : 8; - uint64_t data1 : 8; - uint64_t data0 : 8; - uint64_t _reserved0 : 6; - uint64_t address_range : 3; - uint64_t port_number : 5; - uint64_t speed : 2; - uint64_t read_not_write : 1; - uint64_t device_address : 7; - uint64_t data_length : 4; - uint64_t with_stop : 1; - uint64_t read_continue : 1; - uint64_t with_address : 1; - uint64_t with_start : 1; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fast_control_t; - - - -typedef union i2cengine_fast_reset { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fast_reset_t; - - - -typedef union i2cengine_fast_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pib_address_invalid : 1; - uint64_t pib_write_invalid : 1; - uint64_t pib_read_invalid : 1; - uint64_t pib_address_parity_error : 1; - uint64_t pib_parity_error : 1; - uint64_t lb_parity_error : 1; - uint64_t read_data : 32; - uint64_t _reserved0 : 6; - uint64_t i2c_macro_busy : 1; - uint64_t i2c_invalid_command : 1; - uint64_t i2c_parity_error : 1; - uint64_t i2c_back_end_overrun_error : 1; - uint64_t i2c_back_end_access_error : 1; - uint64_t i2c_arbitration_lost : 1; - uint64_t i2c_nack_received : 1; - uint64_t i2c_data_request : 1; - uint64_t i2c_command_complete : 1; - uint64_t i2c_stop_error : 1; - uint64_t i2c_port_busy : 1; - uint64_t i2c_interface_busy : 1; - uint64_t i2c_fifo_entry_count : 8; -#else - uint64_t i2c_fifo_entry_count : 8; - uint64_t i2c_interface_busy : 1; - uint64_t i2c_port_busy : 1; - uint64_t i2c_stop_error : 1; - uint64_t i2c_command_complete : 1; - uint64_t i2c_data_request : 1; - uint64_t i2c_nack_received : 1; - uint64_t i2c_arbitration_lost : 1; - uint64_t i2c_back_end_access_error : 1; - uint64_t i2c_back_end_overrun_error : 1; - uint64_t i2c_parity_error : 1; - uint64_t i2c_invalid_command : 1; - uint64_t i2c_macro_busy : 1; - uint64_t _reserved0 : 6; - uint64_t read_data : 32; - uint64_t lb_parity_error : 1; - uint64_t pib_parity_error : 1; - uint64_t pib_address_parity_error : 1; - uint64_t pib_read_invalid : 1; - uint64_t pib_write_invalid : 1; - uint64_t pib_address_invalid : 1; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fast_status_t; - - - -typedef union i2cengine_fast_data { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fast_data_t; - - - -typedef union i2cengine_fifo_byte { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t data : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t data : 32; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fifo_byte_t; - - - -typedef union i2cengine_command { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t with_start : 1; - uint64_t with_address : 1; - uint64_t read_continue : 1; - uint64_t not_used : 1; - uint64_t reserved : 4; - uint64_t device_address : 7; - uint64_t read_not_write : 1; - uint64_t length_bytes : 16; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t length_bytes : 16; - uint64_t read_not_write : 1; - uint64_t device_address : 7; - uint64_t reserved : 4; - uint64_t not_used : 1; - uint64_t read_continue : 1; - uint64_t with_address : 1; - uint64_t with_start : 1; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_command_t; - - - -typedef union i2cengine_mode { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t bit_rate_divisor : 15; - uint64_t _reserved0 : 1; - uint64_t port_number : 6; - uint64_t reserved : 6; - uint64_t enhanced_mode : 1; - uint64_t diagnostic_mode : 1; - uint64_t pacing_allow_mode : 1; - uint64_t wrap_mode : 1; - uint64_t _reserved1 : 32; -#else - uint64_t _reserved1 : 32; - uint64_t wrap_mode : 1; - uint64_t pacing_allow_mode : 1; - uint64_t diagnostic_mode : 1; - uint64_t enhanced_mode : 1; - uint64_t reserved : 6; - uint64_t port_number : 6; - uint64_t _reserved0 : 1; - uint64_t bit_rate_divisor : 15; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_mode_t; - - - -typedef union i2cengine_watermark { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 15; - uint64_t _reserved0 : 1; - uint64_t high_water_mark : 4; - uint64_t reserved1 : 4; - uint64_t low_water_mark : 4; - uint64_t reserved2 : 4; - uint64_t _reserved1 : 32; -#else - uint64_t _reserved1 : 32; - uint64_t reserved2 : 4; - uint64_t low_water_mark : 4; - uint64_t reserved1 : 4; - uint64_t high_water_mark : 4; - uint64_t _reserved0 : 1; - uint64_t reserved : 15; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_watermark_t; - - - -typedef union i2cengine_interrupt_mask { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 16; - uint64_t invalid_command : 1; - uint64_t lbus_parity_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t back_end_access_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t nack_received_error : 1; - uint64_t data_request : 1; - uint64_t command_complete : 1; - uint64_t stop_error : 1; - uint64_t i2c_busy : 1; - uint64_t not_i2c_busy : 1; - uint64_t reserved1 : 1; - uint64_t scl_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t sda_eq_0 : 1; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t sda_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t scl_eq_1 : 1; - uint64_t reserved1 : 1; - uint64_t not_i2c_busy : 1; - uint64_t i2c_busy : 1; - uint64_t stop_error : 1; - uint64_t command_complete : 1; - uint64_t data_request : 1; - uint64_t nack_received_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t back_end_access_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t lbus_parity_error : 1; - uint64_t invalid_command : 1; - uint64_t reserved : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_interrupt_mask_t; - - - -typedef union i2cengine_interrupt_condition { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 16; - uint64_t invalid_command : 1; - uint64_t lbus_parity_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t back_end_access_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t nack_received_error : 1; - uint64_t data_request : 1; - uint64_t command_complete : 1; - uint64_t stop_error : 1; - uint64_t i2c_busy : 1; - uint64_t not_i2c_busy : 1; - uint64_t reserved1 : 1; - uint64_t scl_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t sda_eq_0 : 1; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t sda_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t scl_eq_1 : 1; - uint64_t reserved1 : 1; - uint64_t not_i2c_busy : 1; - uint64_t i2c_busy : 1; - uint64_t stop_error : 1; - uint64_t command_complete : 1; - uint64_t data_request : 1; - uint64_t nack_received_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t back_end_access_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t lbus_parity_error : 1; - uint64_t invalid_command : 1; - uint64_t reserved : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_interrupt_condition_t; - - - -typedef union i2cengine_interrupts { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 16; - uint64_t invalid_command : 1; - uint64_t lbus_parity_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t back_end_access_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t nack_received_error : 1; - uint64_t data_request : 1; - uint64_t command_complete : 1; - uint64_t stop_error : 1; - uint64_t i2c_busy : 1; - uint64_t not_i2c_busy : 1; - uint64_t reserved1 : 1; - uint64_t scl_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t sda_eq_0 : 1; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t sda_eq_0 : 1; - uint64_t sda_eq_1 : 1; - uint64_t scl_eq_0 : 1; - uint64_t scl_eq_1 : 1; - uint64_t reserved1 : 1; - uint64_t not_i2c_busy : 1; - uint64_t i2c_busy : 1; - uint64_t stop_error : 1; - uint64_t command_complete : 1; - uint64_t data_request : 1; - uint64_t nack_received_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t back_end_access_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t lbus_parity_error : 1; - uint64_t invalid_command : 1; - uint64_t reserved : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_interrupts_t; - - - -typedef union i2cengine_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t invalid_command : 1; - uint64_t lbus_parity_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t back_end_access_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t nack_received_error : 1; - uint64_t data_request : 1; - uint64_t command_complete : 1; - uint64_t stop_error : 1; - uint64_t upper_threshold : 6; - uint64_t _reserved0 : 1; - uint64_t any_i2c_interrupt : 1; - uint64_t reserved1 : 3; - uint64_t scl_input_lvl : 1; - uint64_t sda_input_lvl : 1; - uint64_t i2c_port_busy : 1; - uint64_t i2c_interface_busy : 1; - uint64_t fifo_entry_count : 8; - uint64_t _reserved1 : 32; -#else - uint64_t _reserved1 : 32; - uint64_t fifo_entry_count : 8; - uint64_t i2c_interface_busy : 1; - uint64_t i2c_port_busy : 1; - uint64_t sda_input_lvl : 1; - uint64_t scl_input_lvl : 1; - uint64_t reserved1 : 3; - uint64_t any_i2c_interrupt : 1; - uint64_t _reserved0 : 1; - uint64_t upper_threshold : 6; - uint64_t stop_error : 1; - uint64_t command_complete : 1; - uint64_t data_request : 1; - uint64_t nack_received_error : 1; - uint64_t arbitration_lost_error : 1; - uint64_t back_end_access_error : 1; - uint64_t back_end_overrun_error : 1; - uint64_t lbus_parity_error : 1; - uint64_t invalid_command : 1; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_status_t; - - - -typedef union i2cengine_extended_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t table_base_addr : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t table_base_addr : 32; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_extended_status_t; - - - -typedef union i2cengine_residual_front_end_back_end_length { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t residual_front_end_length : 16; - uint64_t residual_back_end_length : 16; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t residual_back_end_length : 16; - uint64_t residual_front_end_length : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_residual_front_end_back_end_length_t; - - - -typedef union i2cengine_immediate_reset_s_scl { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t residual_front_end_length : 16; - uint64_t residual_back_end_length : 16; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t residual_back_end_length : 16; - uint64_t residual_front_end_length : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_immediate_reset_s_scl_t; - - - -typedef union i2cengine_immediate_set_s_sda { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t residual_front_end_length : 16; - uint64_t residual_back_end_length : 16; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t residual_back_end_length : 16; - uint64_t residual_front_end_length : 16; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_immediate_set_s_sda_t; - - - -typedef union i2cengine_immediate_reset_s_sda { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t field : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t field : 1; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_immediate_reset_s_sda_t; - - - -typedef union i2cengine_fifo_word { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t data : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t data : 32; -#endif // _BIG_ENDIAN - } fields; -} i2cengine_fifo_word_t; - - -#endif // __ASSEMBLER__ -#endif // __I2CENGINE_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/i2cengine_register_addresses.h b/src/ssx/pgp/registers/i2cengine_register_addresses.h deleted file mode 100644 index bbe9104..0000000 --- a/src/ssx/pgp/registers/i2cengine_register_addresses.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __I2CENGINE_REGISTER_ADDRESSES_H__ -#define __I2CENGINE_REGISTER_ADDRESSES_H__ - -// $Id: i2cengine_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ - -/// \file i2cengine_register_addresses.h -/// \brief Symbolic addresses for the I2CENGINE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define I2CENGINE_PIB_BASE 0x00000000 -#define I2CENGINE_FAST_CONTROL 0x00000000 -#define I2CENGINE_FAST_RESET 0x00000001 -#define I2CENGINE_FAST_STATUS 0x00000002 -#define I2CENGINE_FAST_DATA 0x00000003 -#define I2CENGINE_FIFO_BYTE 0x00000004 -#define I2CENGINE_COMMAND 0x00000005 -#define I2CENGINE_MODE 0x00000006 -#define I2CENGINE_WATERMARK 0x00000007 -#define I2CENGINE_INTERRUPT_MASK 0x00000008 -#define I2CENGINE_INTERRUPT_CONDITION 0x00000009 -#define I2CENGINE_INTERRUPTS 0x0000000a -#define I2CENGINE_STATUS 0x0000000b -#define I2CENGINE_EXTENDED_STATUS 0x0000000c -#define I2CENGINE_RESIDUAL_FRONT_END_BACK_END_LENGTH 0x0000000d -#define I2CENGINE_IMMEDIATE_RESET_S_SCL 0x0000000f -#define I2CENGINE_IMMEDIATE_SET_S_SDA 0x00000010 -#define I2CENGINE_IMMEDIATE_RESET_S_SDA 0x00000011 -#define I2CENGINE_FIFO_WORD 0x00000012 - -#endif // __I2CENGINE_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/icp_firmware_registers.h b/src/ssx/pgp/registers/icp_firmware_registers.h deleted file mode 100755 index 4e17a68..0000000 --- a/src/ssx/pgp/registers/icp_firmware_registers.h +++ /dev/null @@ -1,189 +0,0 @@ -#ifndef __ICP_FIRMWARE_REGISTERS_H__ -#define __ICP_FIRMWARE_REGISTERS_H__ - -// $Id: icp_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file icp_firmware_registers.h -/// \brief C register structs for the ICP unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union icp_bar { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t icp_bar : 30; - uint64_t icp_bar_en : 1; - uint64_t _reserved0 : 33; -#else - uint64_t _reserved0 : 33; - uint64_t icp_bar_en : 1; - uint64_t icp_bar : 30; -#endif // _BIG_ENDIAN - } fields; -} icp_bar_t; - -#endif // __ASSEMBLER__ -#define ICP_BAR_ICP_BAR_MASK SIXTYFOUR_BIT_CONSTANT(0xfffffffc00000000) -#define ICP_BAR_ICP_BAR_EN SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) -#ifndef __ASSEMBLER__ - - -typedef union icp_mode0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t priority : 8; - uint64_t reserved0 : 1; - uint64_t scope_initial : 3; - uint64_t reserved1 : 1; - uint64_t no_hang2status : 1; - uint64_t oper_disable_hang : 1; - uint64_t oper_hang_div : 5; - uint64_t reserved2 : 2; - uint64_t data_disable_hang : 1; - uint64_t data_hang_div : 5; - uint64_t backoff_disable : 1; - uint64_t fwd_que_fwd_conv_disable : 1; - uint64_t disa_wait4cresp_mode4ris : 1; - uint64_t disa_auto_no_retry4ris : 1; - uint64_t disa_retry_mode4ris : 1; - uint64_t hang_on_addr_error : 1; - uint64_t eoi_correction : 2; - uint64_t max_load_count : 4; - uint64_t max_store_count : 4; - uint64_t reserved3 : 3; - uint64_t enable_inject : 1; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t enable_inject : 1; - uint64_t reserved3 : 3; - uint64_t max_store_count : 4; - uint64_t max_load_count : 4; - uint64_t eoi_correction : 2; - uint64_t hang_on_addr_error : 1; - uint64_t disa_retry_mode4ris : 1; - uint64_t disa_auto_no_retry4ris : 1; - uint64_t disa_wait4cresp_mode4ris : 1; - uint64_t fwd_que_fwd_conv_disable : 1; - uint64_t backoff_disable : 1; - uint64_t data_hang_div : 5; - uint64_t data_disable_hang : 1; - uint64_t reserved2 : 2; - uint64_t oper_hang_div : 5; - uint64_t oper_disable_hang : 1; - uint64_t no_hang2status : 1; - uint64_t reserved1 : 1; - uint64_t scope_initial : 3; - uint64_t reserved0 : 1; - uint64_t priority : 8; -#endif // _BIG_ENDIAN - } fields; -} icp_mode0_t; - -#endif // __ASSEMBLER__ -#define ICP_MODE0_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) -#define ICP_MODE0_SCOPE_INITIAL_MASK SIXTYFOUR_BIT_CONSTANT(0x0070000000000000) -#define ICP_MODE0_NO_HANG2STATUS SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define ICP_MODE0_OPER_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define ICP_MODE0_OPER_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x0001f00000000000) -#define ICP_MODE0_DATA_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) -#define ICP_MODE0_DATA_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x000001f000000000) -#define ICP_MODE0_BACKOFF_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) -#define ICP_MODE0_FWD_QUE_FWD_CONV_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) -#define ICP_MODE0_DISA_WAIT4CRESP_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) -#define ICP_MODE0_DISA_AUTO_NO_RETRY4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) -#define ICP_MODE0_DISA_RETRY_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) -#define ICP_MODE0_HANG_ON_ADDR_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) -#define ICP_MODE0_EOI_CORRECTION_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000030000000) -#define ICP_MODE0_MAX_LOAD_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x000000000f000000) -#define ICP_MODE0_MAX_STORE_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000f00000) -#define ICP_MODE0_ENABLE_INJECT SIXTYFOUR_BIT_CONSTANT(0x0000000000010000) -#ifndef __ASSEMBLER__ - - -typedef union icp_iir { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t inject_target_core : 16; - uint64_t inject_target_thread : 8; - uint64_t reserved0 : 8; - uint64_t inject_level : 4; - uint64_t reserved1 : 4; - uint64_t inject_priority : 8; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t inject_priority : 8; - uint64_t reserved1 : 4; - uint64_t inject_level : 4; - uint64_t reserved0 : 8; - uint64_t inject_target_thread : 8; - uint64_t inject_target_core : 16; -#endif // _BIG_ENDIAN - } fields; -} icp_iir_t; - -#endif // __ASSEMBLER__ -#define ICP_IIR_INJECT_TARGET_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0xffff000000000000) -#define ICP_IIR_INJECT_TARGET_THREAD_MASK SIXTYFOUR_BIT_CONSTANT(0x0000ff0000000000) -#define ICP_IIR_INJECT_LEVEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000f0000000) -#define ICP_IIR_INJECT_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000ff0000) -#ifndef __ASSEMBLER__ - -#endif // __ASSEMBLER__ -#endif // __ICP_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/icp_register_addresses.h b/src/ssx/pgp/registers/icp_register_addresses.h deleted file mode 100755 index 7cb8350..0000000 --- a/src/ssx/pgp/registers/icp_register_addresses.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __ICP_REGISTER_ADDRESSES_H__ -#define __ICP_REGISTER_ADDRESSES_H__ - -// $Id: icp_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file icp_register_addresses.h -/// \brief Symbolic addresses for the ICP unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define ICP_PIB_BASE 0x020109c0 -#define ICP_BAR 0x020109ca -#define ICP_MODE0 0x020109cb -#define ICP_IIR 0x020109cc - -#endif // __ICP_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/mcs_firmware_registers.h b/src/ssx/pgp/registers/mcs_firmware_registers.h deleted file mode 100755 index 23e04b8..0000000 --- a/src/ssx/pgp/registers/mcs_firmware_registers.h +++ /dev/null @@ -1,210 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/ssx/pgp/registers/mcs_firmware_registers.h $ */ -/* */ -/* OpenPOWER OnChipController Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -#ifndef __MCS_FIRMWARE_REGISTERS_H__ -#define __MCS_FIRMWARE_REGISTERS_H__ - -// $Id: mcs_firmware_registers.h,v 1.4 2015/01/27 17:56:30 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file mcs_firmware_registers.h -/// \brief C register structs for the MCS unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union mcfgpr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t mcfgprq_valid : 1; - uint64_t reserved0 : 5; - uint64_t mcfgprq_base_address : 14; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t mcfgprq_base_address : 14; - uint64_t reserved0 : 5; - uint64_t mcfgprq_valid : 1; -#endif // _BIG_ENDIAN - } fields; -} mcfgpr_t; - -#endif // __ASSEMBLER__ -#define MCFGPR_MCFGPRQ_VALID SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define MCFGPR_MCFGPRQ_BASE_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x03fff00000000000) -#ifndef __ASSEMBLER__ - - -typedef union mcsmode0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_cmd_byp_stutter : 1; - uint64_t reserved1 : 1; - uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1; - uint64_t enable_centaur_local_checkstop_command : 1; - uint64_t l3_prefetch_retry_threshold : 4; - uint64_t number_of_cl_entries_reserved_for_read : 4; - uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4; - uint64_t number_of_cl_entries_reserved_for_writes : 4; - uint64_t number_of_cl_entries_reserved_for_cp_writes : 4; - uint64_t number_of_cl_entries_reserved_for_cp_ig : 4; - uint64_t number_of_cl_entries_reserved_for_htm_ops : 4; - uint64_t number_of_cl_entries_reserved_for_ha_assist : 4; - uint64_t mcfgrp_19_is_ho_bit : 1; - uint64_t cl_channel_timeout_forces_channel_fail : 1; - uint64_t enable_fault_line_for_global_checkstop : 1; - uint64_t reserved39 : 5; - uint64_t address_collision_modes : 9; - uint64_t include_cp_ig_in_cp_write_fullness_group : 1; - uint64_t enable_dmawr_cmd_bit : 1; - uint64_t enable_read_lsfr_data : 1; - uint64_t force_channel_fail : 1; - uint64_t disable_read_crc_ecc_bypass_taken : 1; - uint64_t disable_cl_ao_queueus : 1; - uint64_t address_select_lfsr_value : 2; - uint64_t enable_centaur_sync : 1; - uint64_t write_data_buffer_ecc_check_disable : 1; - uint64_t write_data_buffer_ecc_correct_disable : 1; -#else - uint64_t write_data_buffer_ecc_correct_disable : 1; - uint64_t write_data_buffer_ecc_check_disable : 1; - uint64_t enable_centaur_sync : 1; - uint64_t address_select_lfsr_value : 2; - uint64_t disable_cl_ao_queueus : 1; - uint64_t disable_read_crc_ecc_bypass_taken : 1; - uint64_t force_channel_fail : 1; - uint64_t enable_read_lsfr_data : 1; - uint64_t enable_dmawr_cmd_bit : 1; - uint64_t include_cp_ig_in_cp_write_fullness_group : 1; - uint64_t address_collision_modes : 9; - uint64_t reserved39 : 5; - uint64_t enable_fault_line_for_global_checkstop : 1; - uint64_t cl_channel_timeout_forces_channel_fail : 1; - uint64_t mcfgrp_19_is_ho_bit : 1; - uint64_t number_of_cl_entries_reserved_for_ha_assist : 4; - uint64_t number_of_cl_entries_reserved_for_htm_ops : 4; - uint64_t number_of_cl_entries_reserved_for_cp_ig : 4; - uint64_t number_of_cl_entries_reserved_for_cp_writes : 4; - uint64_t number_of_cl_entries_reserved_for_writes : 4; - uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4; - uint64_t number_of_cl_entries_reserved_for_read : 4; - uint64_t l3_prefetch_retry_threshold : 4; - uint64_t enable_centaur_local_checkstop_command : 1; - uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1; - uint64_t reserved1 : 1; - uint64_t enable_cmd_byp_stutter : 1; -#endif // _BIG_ENDIAN - } fields; -} mcsmode0_t; - -#endif // __ASSEMBLER__ -#define MCSMODE0_ENABLE_CMD_BYP_STUTTER SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define MCSMODE0_ENABLE_NS_RD_AO_SFU_FOR_DCBZ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define MCSMODE0_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define MCSMODE0_L3_PREFETCH_RETRY_THRESHOLD_MASK SIXTYFOUR_BIT_CONSTANT(0x0f00000000000000) -#define MCSMODE0_MCFGRP_19_IS_HO_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) -#define MCSMODE0_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) -#define MCSMODE0_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) -#define MCSMODE0_ADDRESS_COLLISION_MODES_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000ff800) -#define MCSMODE0_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000400) -#define MCSMODE0_ENABLE_DMAWR_CMD_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000000000200) -#define MCSMODE0_ENABLE_READ_LSFR_DATA SIXTYFOUR_BIT_CONSTANT(0x0000000000000100) -#define MCSMODE0_FORCE_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000000000080) -#define MCSMODE0_DISABLE_READ_CRC_ECC_BYPASS_TAKEN SIXTYFOUR_BIT_CONSTANT(0x0000000000000040) -#define MCSMODE0_DISABLE_CL_AO_QUEUEUS SIXTYFOUR_BIT_CONSTANT(0x0000000000000020) -#define MCSMODE0_ADDRESS_SELECT_LFSR_VALUE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000000018) -#define MCSMODE0_ENABLE_CENTAUR_SYNC SIXTYFOUR_BIT_CONSTANT(0x0000000000000004) -#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000002) -#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000001) -#ifndef __ASSEMBLER__ - -typedef union mcifir { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 30; - uint64_t channel_fail_signal_active : 1; - uint64_t _reserved1 : 33; -#else - uint64_t _reserved1 : 33; - uint64_t channel_fail_signal_active : 1; - uint64_t _reserved0 : 30; -#endif // _BIG_ENDIAN - } fields; -} mcifir_t; - -#endif // __ASSEMBLER__ -#endif // __MCS_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/ocb_firmware_registers.h b/src/ssx/pgp/registers/ocb_firmware_registers.h deleted file mode 100755 index 34037ff..0000000 --- a/src/ssx/pgp/registers/ocb_firmware_registers.h +++ /dev/null @@ -1,2698 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/ssx/pgp/registers/ocb_firmware_registers.h $ */ -/* */ -/* OpenPOWER OnChipController Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -#ifndef __OCB_FIRMWARE_REGISTERS_H__ -#define __OCB_FIRMWARE_REGISTERS_H__ - -// $Id: ocb_firmware_registers.h,v 1.3 2015/02/18 20:35:27 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file ocb_firmware_registers.h -/// \brief C register structs for the OCB unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union ocb_oitr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_oitr0_t; - - - -typedef union ocb_oiepr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_oiepr0_t; - - - -typedef union ocb_ocir0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocir0_t; - - - -typedef union ocb_onisr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_onisr0_t; - - - -typedef union ocb_ouder0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ouder0_t; - - - -typedef union ocb_ocisr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocisr0_t; - - - -typedef union ocb_odher0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t dbg_halt_en : 32; -#else - uint32_t dbg_halt_en : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_odher0_t; - - - -typedef union ocb_oisr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr0_t; - - - -typedef union ocb_oisr0_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr0_and_t; - - - -typedef union ocb_oisr0_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr0_or_t; - - - -typedef union ocb_oimr0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr0_t; - - - -typedef union ocb_oimr0_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr0_and_t; - - - -typedef union ocb_oimr0_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t debugger : 1; - uint32_t trace_trigger : 1; - uint32_t reserved_2 : 1; - uint32_t pba_error : 1; - uint32_t srt_error : 1; - uint32_t pore_sw_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pmc_error : 1; - uint32_t ocb_error : 1; - uint32_t spipss_error : 1; - uint32_t check_stop : 1; - uint32_t pmc_malf_alert : 1; - uint32_t adu_malf_alert : 1; - uint32_t external_trap : 1; - uint32_t occ_timer0 : 1; - uint32_t occ_timer1 : 1; - uint32_t pore_gpe0_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_sbe_error : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t reserved_22 : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t reserved_26 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_bcue_attn : 1; - uint32_t reserved_31 : 1; -#else - uint32_t reserved_31 : 1; - uint32_t pba_bcue_attn : 1; - uint32_t pba_bcde_attn : 1; - uint32_t pba_occ_push1 : 1; - uint32_t pba_occ_push0 : 1; - uint32_t reserved_26 : 1; - uint32_t adcfsm_ongoing : 1; - uint32_t pore_gpe1_complete : 1; - uint32_t pore_gpe0_complete : 1; - uint32_t reserved_22 : 1; - uint32_t pmc_interchip_msg_recv : 1; - uint32_t pore_sbe_error : 1; - uint32_t pore_gpe1_error : 1; - uint32_t pore_gpe0_error : 1; - uint32_t occ_timer1 : 1; - uint32_t occ_timer0 : 1; - uint32_t external_trap : 1; - uint32_t adu_malf_alert : 1; - uint32_t pmc_malf_alert : 1; - uint32_t check_stop : 1; - uint32_t spipss_error : 1; - uint32_t ocb_error : 1; - uint32_t pmc_error : 1; - uint32_t pore_sbe_fatal_error : 1; - uint32_t pore_gpe1_fatal_error : 1; - uint32_t pore_gpe0_fatal_error : 1; - uint32_t pore_sw_error : 1; - uint32_t srt_error : 1; - uint32_t pba_error : 1; - uint32_t reserved_2 : 1; - uint32_t trace_trigger : 1; - uint32_t debugger : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr0_or_t; - - - -typedef union ocb_oitr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_oitr1_t; - - - -typedef union ocb_oiepr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_oiepr1_t; - - - -typedef union ocb_ocir1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocir1_t; - - - -typedef union ocb_onisr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_onisr1_t; - - - -typedef union ocb_ouder1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ouder1_t; - - - -typedef union ocb_ocisr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocisr1_t; - - - -typedef union ocb_odher1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t dbg_halt_en : 32; -#else - uint32_t dbg_halt_en : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_odher1_t; - - - -typedef union ocb_oisr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr1_t; - - - -typedef union ocb_oisr1_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr1_and_t; - - - -typedef union ocb_oisr1_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oisr1_or_t; - - - -typedef union ocb_oimr1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr1_t; - - - -typedef union ocb_oimr1_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr1_and_t; - - - -typedef union ocb_oimr1_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved_32 : 1; - uint32_t reserved_33 : 1; - uint32_t occ_strm0_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm3_push : 1; - uint32_t reserved_42 : 1; - uint32_t reserved_43 : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_pstate_change : 1; - uint32_t reserved_48 : 1; - uint32_t reserved_49 : 1; - uint32_t pmc_idle_exit : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_enter : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pore_sbe_complete : 1; - uint32_t ipi0 : 1; - uint32_t ipi1 : 1; - uint32_t ipi2 : 1; - uint32_t ipi3 : 1; - uint32_t reserved_63 : 1; -#else - uint32_t reserved_63 : 1; - uint32_t ipi3 : 1; - uint32_t ipi2 : 1; - uint32_t ipi1 : 1; - uint32_t ipi0 : 1; - uint32_t pore_sbe_complete : 1; - uint32_t pssbridge_ongoing : 1; - uint32_t pmc_ocb_o2p_ongoing : 1; - uint32_t oci2spivid_ongoing : 1; - uint32_t pmc_interchip_msg_send_ongoing : 1; - uint32_t reserved_53 : 1; - uint32_t pmc_idle_enter : 1; - uint32_t pore_sw_complete : 1; - uint32_t pmc_idle_exit : 1; - uint32_t reserved_49 : 1; - uint32_t reserved_48 : 1; - uint32_t pmc_pstate_change : 1; - uint32_t pmc_sync : 1; - uint32_t pmc_protocol_ongoing : 1; - uint32_t pmc_voltage_change_ongoing : 1; - uint32_t reserved_43 : 1; - uint32_t reserved_42 : 1; - uint32_t occ_strm3_push : 1; - uint32_t occ_strm3_pull : 1; - uint32_t occ_strm2_push : 1; - uint32_t occ_strm2_pull : 1; - uint32_t occ_strm1_push : 1; - uint32_t occ_strm1_pull : 1; - uint32_t occ_strm0_push : 1; - uint32_t occ_strm0_pull : 1; - uint32_t reserved_33 : 1; - uint32_t reserved_32 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oimr1_or_t; - - - -typedef union ocb_occmisc { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t core_ext_intr : 1; - uint32_t reason_intr : 1; - uint32_t _reserved0 : 30; -#else - uint32_t _reserved0 : 30; - uint32_t reason_intr : 1; - uint32_t core_ext_intr : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occmisc_t; - - - -typedef union ocb_occmisc_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t core_ext_intr : 1; - uint32_t reason_intr : 1; - uint32_t _reserved0 : 30; -#else - uint32_t _reserved0 : 30; - uint32_t reason_intr : 1; - uint32_t core_ext_intr : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occmisc_and_t; - - - -typedef union ocb_occmisc_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t core_ext_intr : 1; - uint32_t reason_intr : 1; - uint32_t _reserved0 : 30; -#else - uint32_t _reserved0 : 30; - uint32_t reason_intr : 1; - uint32_t core_ext_intr : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occmisc_or_t; - - - -typedef union ocb_otrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t timeout : 1; - uint32_t control : 1; - uint32_t auto_reload : 1; - uint32_t reserved : 13; - uint32_t timer : 16; -#else - uint32_t timer : 16; - uint32_t reserved : 13; - uint32_t auto_reload : 1; - uint32_t control : 1; - uint32_t timeout : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_otrn_t; - -#endif // __ASSEMBLER__ -#define OCB_OTRN_TIMEOUT 0x80000000 -#define OCB_OTRN_CONTROL 0x40000000 -#define OCB_OTRN_AUTO_RELOAD 0x20000000 -#define OCB_OTRN_TIMER_MASK 0x0000ffff -#ifndef __ASSEMBLER__ - - -typedef union ocb_ohtmcr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t htm_src_sel : 2; - uint32_t htm_stop : 1; - uint32_t htm_marker_slave_adrs : 3; - uint32_t event2halt_mode : 2; - uint32_t event2halt_en : 11; - uint32_t reserved : 1; - uint32_t event2halt_halt : 1; - uint32_t _reserved0 : 11; -#else - uint32_t _reserved0 : 11; - uint32_t event2halt_halt : 1; - uint32_t reserved : 1; - uint32_t event2halt_en : 11; - uint32_t event2halt_mode : 2; - uint32_t htm_marker_slave_adrs : 3; - uint32_t htm_stop : 1; - uint32_t htm_src_sel : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ohtmcr_t; - - - -typedef union ocb_oehdr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t event2halt_delay : 20; - uint32_t _reserved0 : 12; -#else - uint32_t _reserved0 : 12; - uint32_t event2halt_delay : 20; -#endif // _BIG_ENDIAN - } fields; -} ocb_oehdr_t; - - - -typedef union ocb_ocbslbrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pull_oci_region : 2; - uint32_t pull_start : 27; - uint32_t _reserved0 : 3; -#else - uint32_t _reserved0 : 3; - uint32_t pull_start : 27; - uint32_t pull_oci_region : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbslbrn_t; - - - -typedef union ocb_ocbshbrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t push_oci_region : 2; - uint32_t push_start : 27; - uint32_t _reserved0 : 3; -#else - uint32_t _reserved0 : 3; - uint32_t push_start : 27; - uint32_t push_oci_region : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbshbrn_t; - - - -typedef union ocb_ocbslcsn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pull_full : 1; - uint32_t pull_empty : 1; - uint32_t reserved0 : 2; - uint32_t pull_intr_action : 2; - uint32_t pull_length : 5; - uint32_t reserved1 : 2; - uint32_t pull_write_ptr : 5; - uint32_t reserved2 : 3; - uint32_t pull_read_ptr : 5; - uint32_t reserved3 : 5; - uint32_t pull_enable : 1; -#else - uint32_t pull_enable : 1; - uint32_t reserved3 : 5; - uint32_t pull_read_ptr : 5; - uint32_t reserved2 : 3; - uint32_t pull_write_ptr : 5; - uint32_t reserved1 : 2; - uint32_t pull_length : 5; - uint32_t pull_intr_action : 2; - uint32_t reserved0 : 2; - uint32_t pull_empty : 1; - uint32_t pull_full : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbslcsn_t; - -#endif // __ASSEMBLER__ -#define OCB_OCBSLCSN_PULL_FULL 0x80000000 -#define OCB_OCBSLCSN_PULL_EMPTY 0x40000000 -#define OCB_OCBSLCSN_PULL_INTR_ACTION_MASK 0x0c000000 -#define OCB_OCBSLCSN_PULL_LENGTH_MASK 0x03e00000 -#define OCB_OCBSLCSN_PULL_WRITE_PTR_MASK 0x0007c000 -#define OCB_OCBSLCSN_PULL_READ_PTR_MASK 0x000007c0 -#define OCB_OCBSLCSN_PULL_ENABLE 0x00000001 -#ifndef __ASSEMBLER__ - - -typedef union ocb_ocbshcsn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t push_full : 1; - uint32_t push_empty : 1; - uint32_t reserved0 : 2; - uint32_t push_intr_action : 2; - uint32_t push_length : 5; - uint32_t reserved1 : 2; - uint32_t push_write_ptr : 5; - uint32_t reserved2 : 3; - uint32_t push_read_ptr : 5; - uint32_t reserved3 : 5; - uint32_t push_enable : 1; -#else - uint32_t push_enable : 1; - uint32_t reserved3 : 5; - uint32_t push_read_ptr : 5; - uint32_t reserved2 : 3; - uint32_t push_write_ptr : 5; - uint32_t reserved1 : 2; - uint32_t push_length : 5; - uint32_t push_intr_action : 2; - uint32_t reserved0 : 2; - uint32_t push_empty : 1; - uint32_t push_full : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbshcsn_t; - -#endif // __ASSEMBLER__ -#define OCB_OCBSHCSN_PUSH_FULL 0x80000000 -#define OCB_OCBSHCSN_PUSH_EMPTY 0x40000000 -#define OCB_OCBSHCSN_PUSH_INTR_ACTION_MASK 0x0c000000 -#define OCB_OCBSHCSN_PUSH_LENGTH_MASK 0x03e00000 -#define OCB_OCBSHCSN_PUSH_WRITE_PTR_MASK 0x0007c000 -#define OCB_OCBSHCSN_PUSH_READ_PTR_MASK 0x000007c0 -#define OCB_OCBSHCSN_PUSH_ENABLE 0x00000001 -#ifndef __ASSEMBLER__ - - -typedef union ocb_ocbslin { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved : 32; -#else - uint32_t reserved : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbslin_t; - - - -typedef union ocb_ocbshin { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved : 32; -#else - uint32_t reserved : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbshin_t; - - - -typedef union ocb_ocbsesn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t push_read_underflow : 1; - uint32_t pull_write_overflow : 1; - uint32_t _reserved0 : 30; -#else - uint32_t _reserved0 : 30; - uint32_t pull_write_overflow : 1; - uint32_t push_read_underflow : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbsesn_t; - - - -typedef union ocb_ocbicrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t allow_unsecure_pib_masters : 1; - uint32_t _reserved0 : 31; -#else - uint32_t _reserved0 : 31; - uint32_t allow_unsecure_pib_masters : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbicrn_t; - - - -typedef union ocb_ocblwcrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t linear_window_enable : 1; - uint32_t spare_0 : 3; - uint32_t linear_window_bar : 16; - uint32_t linear_window_mask : 12; -#else - uint32_t linear_window_mask : 12; - uint32_t linear_window_bar : 16; - uint32_t spare_0 : 3; - uint32_t linear_window_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocblwcrn_t; - - - -typedef union ocb_ocblwsrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t linear_window_scresp : 3; - uint32_t spare_0 : 5; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - uint32_t spare_0 : 5; - uint32_t linear_window_scresp : 3; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocblwsrn_t; - - - -typedef union ocb_ocblwsbrn { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t linear_window_region : 2; - uint32_t linear_window_base : 8; - uint32_t _reserved0 : 22; -#else - uint32_t _reserved0 : 22; - uint32_t linear_window_base : 8; - uint32_t linear_window_region : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocblwsbrn_t; - - - -typedef union ocb_ocichsw { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t m0_priority : 2; - uint32_t m1_priority : 2; - uint32_t m2_priority : 2; - uint32_t m3_priority : 2; - uint32_t m4_priority : 2; - uint32_t m5_priority : 2; - uint32_t m6_priority : 2; - uint32_t m7_priority : 2; - uint32_t dcu_priority_sel : 1; - uint32_t icu_priority_sel : 1; - uint32_t plbarb_lockerr : 1; - uint32_t _reserved0 : 13; -#else - uint32_t _reserved0 : 13; - uint32_t plbarb_lockerr : 1; - uint32_t icu_priority_sel : 1; - uint32_t dcu_priority_sel : 1; - uint32_t m7_priority : 2; - uint32_t m6_priority : 2; - uint32_t m5_priority : 2; - uint32_t m4_priority : 2; - uint32_t m3_priority : 2; - uint32_t m2_priority : 2; - uint32_t m1_priority : 2; - uint32_t m0_priority : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocichsw_t; - - - -typedef union ocb_ocr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_reset : 1; - uint64_t chip_reset : 1; - uint64_t system_reset : 1; - uint64_t oci_arb_reset : 1; - uint64_t trace_disable : 1; - uint64_t trace_event : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t ext_interrupt : 1; - uint64_t critical_interrupt : 1; - uint64_t spare : 7; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t spare : 7; - uint64_t critical_interrupt : 1; - uint64_t ext_interrupt : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t trace_event : 1; - uint64_t trace_disable : 1; - uint64_t oci_arb_reset : 1; - uint64_t system_reset : 1; - uint64_t chip_reset : 1; - uint64_t core_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocr_t; - - - -typedef union ocb_ocr_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_reset : 1; - uint64_t chip_reset : 1; - uint64_t system_reset : 1; - uint64_t oci_arb_reset : 1; - uint64_t trace_disable : 1; - uint64_t trace_event : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t ext_interrupt : 1; - uint64_t critical_interrupt : 1; - uint64_t spare : 7; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t spare : 7; - uint64_t critical_interrupt : 1; - uint64_t ext_interrupt : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t trace_event : 1; - uint64_t trace_disable : 1; - uint64_t oci_arb_reset : 1; - uint64_t system_reset : 1; - uint64_t chip_reset : 1; - uint64_t core_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocr_and_t; - - - -typedef union ocb_ocr_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_reset : 1; - uint64_t chip_reset : 1; - uint64_t system_reset : 1; - uint64_t oci_arb_reset : 1; - uint64_t trace_disable : 1; - uint64_t trace_event : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t ext_interrupt : 1; - uint64_t critical_interrupt : 1; - uint64_t spare : 7; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t spare : 7; - uint64_t critical_interrupt : 1; - uint64_t ext_interrupt : 1; - uint64_t dbg_unconditional_event : 1; - uint64_t trace_event : 1; - uint64_t trace_disable : 1; - uint64_t oci_arb_reset : 1; - uint64_t system_reset : 1; - uint64_t chip_reset : 1; - uint64_t core_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocr_or_t; - - - -typedef union ocb_ocdbg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 12; - uint64_t _reserved0 : 52; -#else - uint64_t _reserved0 : 52; - uint64_t value : 12; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocdbg_t; - - - -typedef union ocb_ocbarn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_region : 2; - uint64_t ocb_address : 27; - uint64_t reserved : 3; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t reserved : 3; - uint64_t ocb_address : 27; - uint64_t oci_region : 2; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbarn_t; - -#endif // __ASSEMBLER__ -#define OCB_OCBARN_OCI_REGION_MASK SIXTYFOUR_BIT_CONSTANT(0xc000000000000000) -#define OCB_OCBARN_OCB_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x3ffffff800000000) -#ifndef __ASSEMBLER__ - - -typedef union ocb_ocbcsrn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pull_read_underflow : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow_en : 1; - uint64_t ocb_stream_mode : 1; - uint64_t ocb_stream_type : 1; - uint64_t reserved1 : 2; - uint64_t ocb_oci_timeout : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_fsm_err : 1; - uint64_t _reserved0 : 49; -#else - uint64_t _reserved0 : 49; - uint64_t ocb_fsm_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_timeout : 1; - uint64_t reserved1 : 2; - uint64_t ocb_stream_type : 1; - uint64_t ocb_stream_mode : 1; - uint64_t push_write_overflow_en : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbcsrn_t; - -#endif // __ASSEMBLER__ -#define OCB_OCBCSRN_PULL_READ_UNDERFLOW SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define OCB_OCBCSRN_PULL_READ_UNDERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define OCB_OCBCSRN_OCB_STREAM_MODE SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define OCB_OCBCSRN_OCB_STREAM_TYPE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define OCB_OCBCSRN_OCB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define OCB_OCBCSRN_OCB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define OCB_OCBCSRN_OCB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define OCB_OCBCSRN_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define OCB_OCBCSRN_OCB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define OCB_OCBCSRN_OCB_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#ifndef __ASSEMBLER__ - - -typedef union ocb_ocbcsrn_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pull_read_underflow : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow_en : 1; - uint64_t ocb_stream_mode : 1; - uint64_t ocb_stream_type : 1; - uint64_t reserved1 : 2; - uint64_t ocb_oci_timeout : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_fsm_err : 1; - uint64_t _reserved0 : 49; -#else - uint64_t _reserved0 : 49; - uint64_t ocb_fsm_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_timeout : 1; - uint64_t reserved1 : 2; - uint64_t ocb_stream_type : 1; - uint64_t ocb_stream_mode : 1; - uint64_t push_write_overflow_en : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbcsrn_and_t; - - - -typedef union ocb_ocbcsrn_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pull_read_underflow : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow_en : 1; - uint64_t ocb_stream_mode : 1; - uint64_t ocb_stream_type : 1; - uint64_t reserved1 : 2; - uint64_t ocb_oci_timeout : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_fsm_err : 1; - uint64_t _reserved0 : 49; -#else - uint64_t _reserved0 : 49; - uint64_t ocb_fsm_err : 1; - uint64_t reserved2 : 1; - uint64_t ocb_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_oci_slave_error : 1; - uint64_t ocb_oci_read_data_parity : 1; - uint64_t ocb_oci_timeout : 1; - uint64_t reserved1 : 2; - uint64_t ocb_stream_type : 1; - uint64_t ocb_stream_mode : 1; - uint64_t push_write_overflow_en : 1; - uint64_t pull_read_underflow_en : 1; - uint64_t push_write_overflow : 1; - uint64_t pull_read_underflow : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbcsrn_or_t; - - - -typedef union ocb_ocbesrn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ocb_error_addr : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t ocb_error_addr : 32; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbesrn_t; - - - -typedef union ocb_ocbdrn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ocb_data : 64; -#else - uint64_t ocb_data : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_ocbdrn_t; - - - -typedef union ocb_osbcr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_block_unsecure_masters : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t occ_block_unsecure_masters : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_osbcr_t; - - - -typedef union ocb_otdcr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t trace_bus_en : 1; - uint64_t ocb_trace_mux_sel : 1; - uint64_t occ_trace_mux_sel : 2; - uint64_t oci_trace_mux_sel : 4; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t oci_trace_mux_sel : 4; - uint64_t occ_trace_mux_sel : 2; - uint64_t ocb_trace_mux_sel : 1; - uint64_t trace_bus_en : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_otdcr_t; - - - -typedef union ocb_oppcinj { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_err_inj_dcu : 1; - uint64_t oci_err_inj_icu : 1; - uint64_t oci_err_inj_ce_ue : 1; - uint64_t oci_err_inj_singl_cont : 1; - uint64_t _reserved0 : 60; -#else - uint64_t _reserved0 : 60; - uint64_t oci_err_inj_singl_cont : 1; - uint64_t oci_err_inj_ce_ue : 1; - uint64_t oci_err_inj_icu : 1; - uint64_t oci_err_inj_dcu : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_oppcinj_t; - - - -typedef union ocb_occlfir { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_fw0 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw3 : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t ocb_error : 1; - uint64_t pmc_error : 1; - uint64_t srt_ue : 1; - uint64_t srt_ce : 1; - uint64_t srt_read_error : 1; - uint64_t srt_write_error : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t external_trap : 1; - uint64_t ppc405_core_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc3_error : 1; - uint64_t srt_fsm_err : 1; - uint64_t jtagacc_err : 1; - uint64_t ocb_dw_err : 1; - uint64_t c405_ecc_ue : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t slw_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t c405dcu_m_timeout : 1; - uint64_t spare_fir : 12; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; -#else - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 12; - uint64_t c405dcu_m_timeout : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t slw_ocislv_err : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_ecc_ue : 1; - uint64_t ocb_dw_err : 1; - uint64_t jtagacc_err : 1; - uint64_t srt_fsm_err : 1; - uint64_t ocb_idc3_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_core_reset : 1; - uint64_t external_trap : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_write_error : 1; - uint64_t srt_read_error : 1; - uint64_t srt_ce : 1; - uint64_t srt_ue : 1; - uint64_t pmc_error : 1; - uint64_t ocb_error : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t occ_fw3 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw0 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfir_t; - -#endif // __ASSEMBLER__ -#define OCB_OCCLFIR_OCC_FW0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define OCB_OCCLFIR_OCC_FW1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define OCB_OCCLFIR_OCC_FW2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define OCB_OCCLFIR_OCC_FW3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define OCB_OCCLFIR_PMC_PORE_SW_MALF SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define OCB_OCCLFIR_PMC_OCC_HB_MALF SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define OCB_OCCLFIR_PORE_GPE0_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define OCB_OCCLFIR_PORE_GPE1_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define OCB_OCCLFIR_OCB_ERROR SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define OCB_OCCLFIR_PMC_ERROR SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define OCB_OCCLFIR_SRT_UE SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define OCB_OCCLFIR_SRT_CE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define OCB_OCCLFIR_SRT_READ_ERROR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define OCB_OCCLFIR_SRT_WRITE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define OCB_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define OCB_OCCLFIR_SRT_OCI_BE_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define OCB_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) -#define OCB_OCCLFIR_PORE_SW_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) -#define OCB_OCCLFIR_PORE_GPE0_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) -#define OCB_OCCLFIR_PORE_GPE1_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) -#define OCB_OCCLFIR_EXTERNAL_TRAP SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) -#define OCB_OCCLFIR_PPC405_CORE_RESET SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) -#define OCB_OCCLFIR_PPC405_CHIP_RESET SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) -#define OCB_OCCLFIR_PPC405_SYSTEM_RESET SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) -#define OCB_OCCLFIR_PPC405_DBGMSRWE SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) -#define OCB_OCCLFIR_PPC405_DBGSTOPACK SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) -#define OCB_OCCLFIR_OCB_DB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) -#define OCB_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) -#define OCB_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) -#define OCB_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) -#define OCB_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) -#define OCB_OCCLFIR_OCB_IDC0_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) -#define OCB_OCCLFIR_OCB_IDC1_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) -#define OCB_OCCLFIR_OCB_IDC2_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) -#define OCB_OCCLFIR_OCB_IDC3_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000020000000) -#define OCB_OCCLFIR_SRT_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000) -#define OCB_OCCLFIR_JTAGACC_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) -#define OCB_OCCLFIR_OCB_DW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) -#define OCB_OCCLFIR_C405_ECC_UE SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) -#define OCB_OCCLFIR_C405_ECC_CE SIXTYFOUR_BIT_CONSTANT(0x0000000001000000) -#define OCB_OCCLFIR_C405_OCI_MACHINECHECK SIXTYFOUR_BIT_CONSTANT(0x0000000000800000) -#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0000000000400000) -#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000000000200000) -#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000100000) -#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000) -#define OCB_OCCLFIR_SLW_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000) -#define OCB_OCCLFIR_GPE_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000020000) -#define OCB_OCCLFIR_OCB_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000010000) -#define OCB_OCCLFIR_C405ICU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000008000) -#define OCB_OCCLFIR_C405DCU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000004000) -#define OCB_OCCLFIR_SPARE_FIR_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000003ffc) -#define OCB_OCCLFIR_FIR_PARITY_ERR_DUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000002) -#define OCB_OCCLFIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000000001) -#ifndef __ASSEMBLER__ - - -typedef union ocb_occlfir_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_fw0 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw3 : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t ocb_error : 1; - uint64_t pmc_error : 1; - uint64_t srt_ue : 1; - uint64_t srt_ce : 1; - uint64_t srt_read_error : 1; - uint64_t srt_write_error : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t external_trap : 1; - uint64_t ppc405_core_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc3_error : 1; - uint64_t srt_fsm_err : 1; - uint64_t jtagacc_err : 1; - uint64_t ocb_dw_err : 1; - uint64_t c405_ecc_ue : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t slw_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t c405dcu_m_timeout : 1; - uint64_t spare_fir : 12; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; -#else - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 12; - uint64_t c405dcu_m_timeout : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t slw_ocislv_err : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_ecc_ue : 1; - uint64_t ocb_dw_err : 1; - uint64_t jtagacc_err : 1; - uint64_t srt_fsm_err : 1; - uint64_t ocb_idc3_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_core_reset : 1; - uint64_t external_trap : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_write_error : 1; - uint64_t srt_read_error : 1; - uint64_t srt_ce : 1; - uint64_t srt_ue : 1; - uint64_t pmc_error : 1; - uint64_t ocb_error : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t occ_fw3 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw0 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfir_and_t; - - - -typedef union ocb_occlfir_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_fw0 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw3 : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t ocb_error : 1; - uint64_t pmc_error : 1; - uint64_t srt_ue : 1; - uint64_t srt_ce : 1; - uint64_t srt_read_error : 1; - uint64_t srt_write_error : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t external_trap : 1; - uint64_t ppc405_core_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc3_error : 1; - uint64_t srt_fsm_err : 1; - uint64_t jtagacc_err : 1; - uint64_t ocb_dw_err : 1; - uint64_t c405_ecc_ue : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t slw_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t c405dcu_m_timeout : 1; - uint64_t spare_fir : 12; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; -#else - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 12; - uint64_t c405dcu_m_timeout : 1; - uint64_t c405icu_m_timeout : 1; - uint64_t ocb_ocislv_err : 1; - uint64_t gpe_ocislv_err : 1; - uint64_t slw_ocislv_err : 1; - uint64_t sram_spare_direct_error3 : 1; - uint64_t sram_spare_direct_error2 : 1; - uint64_t sram_spare_direct_error1 : 1; - uint64_t sram_spare_direct_error0 : 1; - uint64_t c405_oci_machinecheck : 1; - uint64_t c405_ecc_ce : 1; - uint64_t c405_ecc_ue : 1; - uint64_t ocb_dw_err : 1; - uint64_t jtagacc_err : 1; - uint64_t srt_fsm_err : 1; - uint64_t ocb_idc3_error : 1; - uint64_t ocb_idc2_error : 1; - uint64_t ocb_idc1_error : 1; - uint64_t ocb_idc0_error : 1; - uint64_t ocb_db_pib_data_parity_err : 1; - uint64_t ocb_pib_addr_parity_err : 1; - uint64_t ocb_db_oci_slave_error : 1; - uint64_t ocb_db_oci_read_data_parity : 1; - uint64_t ocb_db_oci_timeout : 1; - uint64_t ppc405_dbgstopack : 1; - uint64_t ppc405_dbgmsrwe : 1; - uint64_t ppc405_system_reset : 1; - uint64_t ppc405_chip_reset : 1; - uint64_t ppc405_core_reset : 1; - uint64_t external_trap : 1; - uint64_t pore_gpe1_error_err : 1; - uint64_t pore_gpe0_error_err : 1; - uint64_t pore_sw_error_err : 1; - uint64_t srt_oci_addr_parity_err : 1; - uint64_t srt_oci_be_parity_err : 1; - uint64_t srt_oci_write_data_parity : 1; - uint64_t srt_write_error : 1; - uint64_t srt_read_error : 1; - uint64_t srt_ce : 1; - uint64_t srt_ue : 1; - uint64_t pmc_error : 1; - uint64_t ocb_error : 1; - uint64_t pore_gpe1_fatal_err : 1; - uint64_t pore_gpe0_fatal_err : 1; - uint64_t pmc_occ_hb_malf : 1; - uint64_t pmc_pore_sw_malf : 1; - uint64_t occ_fw3 : 1; - uint64_t occ_fw2 : 1; - uint64_t occ_fw1 : 1; - uint64_t occ_fw0 : 1; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfir_or_t; - - - -typedef union ocb_occlfirmask { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfirmask_t; - - - -typedef union ocb_occlfirmask_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfirmask_and_t; - - - -typedef union ocb_occlfirmask_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfirmask_or_t; - - - -typedef union ocb_occlfiract0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfiract0_t; - - - -typedef union ocb_occlfiract1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} ocb_occlfiract1_t; - - - -typedef union ocb_occerrrpt { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t sram_cerrrpt : 10; - uint64_t jtagacc_cerrrpt : 6; - uint64_t c405_dcu_ecc_ue_cerrrpt : 1; - uint64_t c405_dcu_ecc_ce_cerrrpt : 1; - uint64_t c405_icu_ecc_ue_cerrrpt : 1; - uint64_t c405_icu_ecc_ce_cerrrpt : 1; - uint64_t slw_ocislv_err : 7; - uint64_t gpe_ocislv_err : 7; - uint64_t ocb_ocislv_err : 6; - uint64_t _reserved0 : 24; -#else - uint64_t _reserved0 : 24; - uint64_t ocb_ocislv_err : 6; - uint64_t gpe_ocislv_err : 7; - uint64_t slw_ocislv_err : 7; - uint64_t c405_icu_ecc_ce_cerrrpt : 1; - uint64_t c405_icu_ecc_ue_cerrrpt : 1; - uint64_t c405_dcu_ecc_ce_cerrrpt : 1; - uint64_t c405_dcu_ecc_ue_cerrrpt : 1; - uint64_t jtagacc_cerrrpt : 6; - uint64_t sram_cerrrpt : 10; -#endif // _BIG_ENDIAN - } fields; -} ocb_occerrrpt_t; - - - -typedef union ocb_scan_dummy_1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 48; - uint64_t value : 16; -#else - uint64_t value : 16; - uint64_t _reserved0 : 48; -#endif // _BIG_ENDIAN - } fields; -} ocb_scan_dummy_1_t; - - - -typedef union ocb_scan_dummy_2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 63; - uint64_t value : 1; -#else - uint64_t value : 1; - uint64_t _reserved0 : 63; -#endif // _BIG_ENDIAN - } fields; -} ocb_scan_dummy_2_t; - - -#endif // __ASSEMBLER__ -#endif // __OCB_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/ocb_register_addresses.h b/src/ssx/pgp/registers/ocb_register_addresses.h deleted file mode 100755 index 3290e59..0000000 --- a/src/ssx/pgp/registers/ocb_register_addresses.h +++ /dev/null @@ -1,148 +0,0 @@ -#ifndef __OCB_REGISTER_ADDRESSES_H__ -#define __OCB_REGISTER_ADDRESSES_H__ - -// $Id: ocb_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file ocb_register_addresses.h -/// \brief Symbolic addresses for the OCB unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define OCB_OCI_BASE 0x40050000 -#define OCB_OITR0 0x40050040 -#define OCB_OIEPR0 0x40050048 -#define OCB_OCIR0 0x40050050 -#define OCB_ONISR0 0x40050058 -#define OCB_OUDER0 0x40050060 -#define OCB_OCISR0 0x40050068 -#define OCB_ODHER0 0x40050070 -#define OCB_OISR0 0x40050000 -#define OCB_OISR0_AND 0x40050008 -#define OCB_OISR0_OR 0x40050010 -#define OCB_OIMR0 0x40050020 -#define OCB_OIMR0_AND 0x40050028 -#define OCB_OIMR0_OR 0x40050030 -#define OCB_OITR1 0x400500c0 -#define OCB_OIEPR1 0x400500c8 -#define OCB_OCIR1 0x400500d0 -#define OCB_ONISR1 0x400500d8 -#define OCB_OUDER1 0x400500e0 -#define OCB_OCISR1 0x400500e8 -#define OCB_ODHER1 0x400500f0 -#define OCB_OISR1 0x40050080 -#define OCB_OISR1_AND 0x40050088 -#define OCB_OISR1_OR 0x40050090 -#define OCB_OIMR1 0x400500a0 -#define OCB_OIMR1_AND 0x400500a8 -#define OCB_OIMR1_OR 0x400500b0 -#define OCB_OCCMISC 0x40050100 -#define OCB_OCCMISC_AND 0x40050108 -#define OCB_OCCMISC_OR 0x40050110 -#define OCB_OTRN(n) (OCB_OTR0 + ((OCB_OTR1 - OCB_OTR0) * (n))) -#define OCB_OTR0 0x40050800 -#define OCB_OTR1 0x40050808 -#define OCB_OHTMCR 0x40050118 -#define OCB_OEHDR 0x40050120 -#define OCB_OCBSLBRN(n) (OCB_OCBSLBR0 + ((OCB_OCBSLBR1 - OCB_OCBSLBR0) * (n))) -#define OCB_OCBSLBR0 0x40051000 -#define OCB_OCBSLBR1 0x40051080 -#define OCB_OCBSLBR2 0x40051100 -#define OCB_OCBSHBRN(n) (OCB_OCBSHBR0 + ((OCB_OCBSHBR1 - OCB_OCBSHBR0) * (n))) -#define OCB_OCBSHBR0 0x40051018 -#define OCB_OCBSHBR1 0x40051098 -#define OCB_OCBSHBR2 0x40051118 -#define OCB_OCBSLCSN(n) (OCB_OCBSLCS0 + ((OCB_OCBSLCS1 - OCB_OCBSLCS0) * (n))) -#define OCB_OCBSLCS0 0x40051008 -#define OCB_OCBSLCS1 0x40051088 -#define OCB_OCBSLCS2 0x40051108 -#define OCB_OCBSHCSN(n) (OCB_OCBSHCS0 + ((OCB_OCBSHCS1 - OCB_OCBSHCS0) * (n))) -#define OCB_OCBSHCS0 0x40051020 -#define OCB_OCBSHCS1 0x400510a0 -#define OCB_OCBSHCS2 0x40051120 -#define OCB_OCBSLIN(n) (OCB_OCBSLI0 + ((OCB_OCBSLI1 - OCB_OCBSLI0) * (n))) -#define OCB_OCBSLI0 0x40051010 -#define OCB_OCBSLI1 0x40051090 -#define OCB_OCBSLI2 0x40051110 -#define OCB_OCBSHIN(n) (OCB_OCBSHI0 + ((OCB_OCBSHI1 - OCB_OCBSHI0) * (n))) -#define OCB_OCBSHI0 0x40051028 -#define OCB_OCBSHI1 0x400510a8 -#define OCB_OCBSHI2 0x40051128 -#define OCB_OCBSESN(n) (OCB_OCBSES0 + ((OCB_OCBSES1 - OCB_OCBSES0) * (n))) -#define OCB_OCBSES0 0x40051030 -#define OCB_OCBSES1 0x400510b0 -#define OCB_OCBSES2 0x40051130 -#define OCB_OCBICRN(n) (OCB_OCBICR0 + ((OCB_OCBICR1 - OCB_OCBICR0) * (n))) -#define OCB_OCBICR0 0x40051038 -#define OCB_OCBICR1 0x400510b8 -#define OCB_OCBICR2 0x40051138 -#define OCB_OCBLWCRN(n) (OCB_OCBLWCR0 + ((OCB_OCBLWCR1 - OCB_OCBLWCR0) * (n))) -#define OCB_OCBLWCR0 0x40051040 -#define OCB_OCBLWCR1 0x400510c0 -#define OCB_OCBLWCR2 0x40051140 -#define OCB_OCBLWSRN(n) (OCB_OCBLWSR0 + ((OCB_OCBLWSR1 - OCB_OCBLWSR0) * (n))) -#define OCB_OCBLWSR0 0x40051050 -#define OCB_OCBLWSR1 0x400510d0 -#define OCB_OCBLWSR2 0x40051150 -#define OCB_OCBLWSBRN(n) (OCB_OCBLWSBR0 + ((OCB_OCBLWSBR1 - OCB_OCBLWSBR0) * (n))) -#define OCB_OCBLWSBR0 0x40051060 -#define OCB_OCBLWSBR1 0x400510e0 -#define OCB_OCBLWSBR2 0x40051160 -#define OCB_OCICHSW 0x40050128 -#define OCB_PIB_BASE 0x0006a000 -#define OCB_OCR 0x0006b000 -#define OCB_OCR_AND 0x0006b001 -#define OCB_OCR_OR 0x0006b002 -#define OCB_OCDBG 0x0006b003 -#define OCB_OCBARN(n) (OCB_OCBAR0 + ((OCB_OCBAR1 - OCB_OCBAR0) * (n))) -#define OCB_OCBAR0 0x0006b010 -#define OCB_OCBAR1 0x0006b030 -#define OCB_OCBAR2 0x0006b050 -#define OCB_OCBAR3 0x0006b070 -#define OCB_OCBCSRN(n) (OCB_OCBCSR0 + ((OCB_OCBCSR1 - OCB_OCBCSR0) * (n))) -#define OCB_OCBCSR0 0x0006b011 -#define OCB_OCBCSR1 0x0006b031 -#define OCB_OCBCSR2 0x0006b051 -#define OCB_OCBCSR3 0x0006b071 -#define OCB_OCBCSRN_AND(n) (OCB_OCBCSR0_AND + ((OCB_OCBCSR1_AND - OCB_OCBCSR0_AND) * (n))) -#define OCB_OCBCSR0_AND 0x0006b012 -#define OCB_OCBCSR1_AND 0x0006b032 -#define OCB_OCBCSR2_AND 0x0006b052 -#define OCB_OCBCSR3_AND 0x0006b072 -#define OCB_OCBCSRN_OR(n) (OCB_OCBCSR0_OR + ((OCB_OCBCSR1_OR - OCB_OCBCSR0_OR) * (n))) -#define OCB_OCBCSR0_OR 0x0006b013 -#define OCB_OCBCSR1_OR 0x0006b033 -#define OCB_OCBCSR2_OR 0x0006b053 -#define OCB_OCBCSR3_OR 0x0006b073 -#define OCB_OCBESRN(n) (OCB_OCBESR0 + ((OCB_OCBESR1 - OCB_OCBESR0) * (n))) -#define OCB_OCBESR0 0x0006b014 -#define OCB_OCBESR1 0x0006b034 -#define OCB_OCBESR2 0x0006b054 -#define OCB_OCBESR3 0x0006b074 -#define OCB_OCBDRN(n) (OCB_OCBDR0 + ((OCB_OCBDR1 - OCB_OCBDR0) * (n))) -#define OCB_OCBDR0 0x0006b015 -#define OCB_OCBDR1 0x0006b035 -#define OCB_OCBDR2 0x0006b055 -#define OCB_OCBDR3 0x0006b075 -#define OCB_OSBCR 0x0006b100 -#define OCB_OTDCR 0x0006b110 -#define OCB_OPPCINJ 0x0006b111 -#define OCB_FIRPIB_BASE 0x01010800 -#define OCB_OCCLFIR 0x01010800 -#define OCB_OCCLFIR_AND 0x01010801 -#define OCB_OCCLFIR_OR 0x01010802 -#define OCB_OCCLFIRMASK 0x01010803 -#define OCB_OCCLFIRMASK_AND 0x01010804 -#define OCB_OCCLFIRMASK_OR 0x01010805 -#define OCB_OCCLFIRACT0 0x01010806 -#define OCB_OCCLFIRACT1 0x01010807 -#define OCB_OCCERRRPT 0x0101080a - -#endif // __OCB_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/oha_firmware_registers.h b/src/ssx/pgp/registers/oha_firmware_registers.h deleted file mode 100755 index cba1500..0000000 --- a/src/ssx/pgp/registers/oha_firmware_registers.h +++ /dev/null @@ -1,1248 +0,0 @@ -#ifndef __OHA_FIRMWARE_REGISTERS_H__ -#define __OHA_FIRMWARE_REGISTERS_H__ - -// $Id: oha_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file oha_firmware_registers.h -/// \brief C register structs for the OHA unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union oha_activity_sample_mode_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_activity_sampling : 1; - uint64_t enable_ppt_trace : 1; - uint64_t l2_act_count_is_free_running : 1; - uint64_t l3_act_count_is_free_running : 1; - uint64_t activity_sample_l2l3_enable : 1; - uint64_t core_activity_sample_enable : 1; - uint64_t disable_activity_proxy_reset : 1; - uint64_t power_proxy_activity_range_select_vcs : 5; - uint64_t power_proxy_activity_range_select_vdd : 5; - uint64_t memory_activity_range_select : 4; - uint64_t avg_freq_counter_scaler : 3; - uint64_t ppt_trace_timer_match_val : 11; - uint64_t disable_ppt_int_timer_reset : 1; - uint64_t ppt_int_timer_select : 2; - uint64_t disable_ppt_cycle_counter_reset : 1; - uint64_t ppt_cycle_counter_scaler : 3; - uint64_t ppt_squash_timer_match_val : 6; - uint64_t ppt_timer_timeout_enable : 1; - uint64_t ppt_lpar_change_enable : 1; - uint64_t ppt_global_actual_change_enable : 1; - uint64_t ppt_local_voltage_change_enable : 1; - uint64_t ppt_ivrm_bypass_change_enable : 1; - uint64_t ppt_idle_entry_enable : 1; - uint64_t ppt_idle_exit_enable : 1; - uint64_t ppt_timer_timeout_priority : 1; - uint64_t ppt_lpar_change_priority : 1; - uint64_t ppt_global_actual_change_priority : 1; - uint64_t ppt_local_voltage_change_priority : 1; - uint64_t ppt_ivrm_bypass_change_priority : 1; - uint64_t ppt_idle_entry_priority : 1; - uint64_t ppt_idle_exit_priority : 1; - uint64_t ppt_legacy_mode : 1; - uint64_t _reserved0 : 1; -#else - uint64_t _reserved0 : 1; - uint64_t ppt_legacy_mode : 1; - uint64_t ppt_idle_exit_priority : 1; - uint64_t ppt_idle_entry_priority : 1; - uint64_t ppt_ivrm_bypass_change_priority : 1; - uint64_t ppt_local_voltage_change_priority : 1; - uint64_t ppt_global_actual_change_priority : 1; - uint64_t ppt_lpar_change_priority : 1; - uint64_t ppt_timer_timeout_priority : 1; - uint64_t ppt_idle_exit_enable : 1; - uint64_t ppt_idle_entry_enable : 1; - uint64_t ppt_ivrm_bypass_change_enable : 1; - uint64_t ppt_local_voltage_change_enable : 1; - uint64_t ppt_global_actual_change_enable : 1; - uint64_t ppt_lpar_change_enable : 1; - uint64_t ppt_timer_timeout_enable : 1; - uint64_t ppt_squash_timer_match_val : 6; - uint64_t ppt_cycle_counter_scaler : 3; - uint64_t disable_ppt_cycle_counter_reset : 1; - uint64_t ppt_int_timer_select : 2; - uint64_t disable_ppt_int_timer_reset : 1; - uint64_t ppt_trace_timer_match_val : 11; - uint64_t avg_freq_counter_scaler : 3; - uint64_t memory_activity_range_select : 4; - uint64_t power_proxy_activity_range_select_vdd : 5; - uint64_t power_proxy_activity_range_select_vcs : 5; - uint64_t disable_activity_proxy_reset : 1; - uint64_t core_activity_sample_enable : 1; - uint64_t activity_sample_l2l3_enable : 1; - uint64_t l3_act_count_is_free_running : 1; - uint64_t l2_act_count_is_free_running : 1; - uint64_t enable_ppt_trace : 1; - uint64_t enable_activity_sampling : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_activity_sample_mode_reg_t; - - - -typedef union oha_vcs_activity_cnt_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t l2_activity_count_24bit_vcs : 24; - uint64_t l3_activity_count_24bit_vcs : 24; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t l3_activity_count_24bit_vcs : 24; - uint64_t l2_activity_count_24bit_vcs : 24; -#endif // _BIG_ENDIAN - } fields; -} oha_vcs_activity_cnt_reg_t; - - - -typedef union oha_vdd_activity_cnt_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t l2_activity_count_24bit_vdd : 24; - uint64_t l3_activity_count_24bit_vdd : 24; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t l3_activity_count_24bit_vdd : 24; - uint64_t l2_activity_count_24bit_vdd : 24; -#endif // _BIG_ENDIAN - } fields; -} oha_vdd_activity_cnt_reg_t; - - - -typedef union oha_low_activity_detect_mode_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t low_activity_detect_sample_enable : 1; - uint64_t low_activity_detect_timer_select_for_entry : 8; - uint64_t low_activity_detect_timer_select_for_exit : 8; - uint64_t low_activity_detect_threshold_range : 4; - uint64_t low_activity_detect_threshold_entry : 16; - uint64_t low_activity_detect_threshold_exit : 16; - uint64_t _reserved0 : 11; -#else - uint64_t _reserved0 : 11; - uint64_t low_activity_detect_threshold_exit : 16; - uint64_t low_activity_detect_threshold_entry : 16; - uint64_t low_activity_detect_threshold_range : 4; - uint64_t low_activity_detect_timer_select_for_exit : 8; - uint64_t low_activity_detect_timer_select_for_entry : 8; - uint64_t low_activity_detect_sample_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_low_activity_detect_mode_reg_t; - - - -typedef union oha_activity_and_frequ_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t low_activity_detect_engaged : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t low_activity_detect_engaged : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_activity_and_frequ_reg_t; - - - -typedef union oha_counter_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t base_counter : 16; - uint64_t idle_detec_timer : 16; - uint64_t tod_count_msbs : 16; - uint64_t ppt_cycle_count_ovfl : 1; - uint64_t ppt_parity_error : 1; - uint64_t _reserved0 : 14; -#else - uint64_t _reserved0 : 14; - uint64_t ppt_parity_error : 1; - uint64_t ppt_cycle_count_ovfl : 1; - uint64_t tod_count_msbs : 16; - uint64_t idle_detec_timer : 16; - uint64_t base_counter : 16; -#endif // _BIG_ENDIAN - } fields; -} oha_counter_reg_t; - - - -typedef union oha_proxy_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t average_frequency : 32; - uint64_t special_memory_activity_cnt : 24; - uint64_t _reserved0 : 8; -#else - uint64_t _reserved0 : 8; - uint64_t special_memory_activity_cnt : 24; - uint64_t average_frequency : 32; -#endif // _BIG_ENDIAN - } fields; -} oha_proxy_reg_t; - - - -typedef union oha_proxy_legacy_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t aproxy_vdd : 16; - uint64_t aproxy_vcs : 16; - uint64_t memory_activity_cnt : 16; - uint64_t scaled_average_frequency : 16; -#else - uint64_t scaled_average_frequency : 16; - uint64_t memory_activity_cnt : 16; - uint64_t aproxy_vcs : 16; - uint64_t aproxy_vdd : 16; -#endif // _BIG_ENDIAN - } fields; -} oha_proxy_legacy_reg_t; - - - -typedef union oha_skitter_ctrl_mode_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t start_skitter_mux_sel : 3; - uint64_t stop_skitter_mux_sel : 3; - uint64_t skitter_timer_start_mux_sel : 3; - uint64_t disable_skitter_qualification_mode : 1; - uint64_t skitter_timer_enable_freerun_mode : 1; - uint64_t skitter_timer_range_select : 4; - uint64_t _reserved0 : 49; -#else - uint64_t _reserved0 : 49; - uint64_t skitter_timer_range_select : 4; - uint64_t skitter_timer_enable_freerun_mode : 1; - uint64_t disable_skitter_qualification_mode : 1; - uint64_t skitter_timer_start_mux_sel : 3; - uint64_t stop_skitter_mux_sel : 3; - uint64_t start_skitter_mux_sel : 3; -#endif // _BIG_ENDIAN - } fields; -} oha_skitter_ctrl_mode_reg_t; - - - -typedef union oha_cpm_ctrl_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cpm_bit_sel : 2; - uint64_t cpm_bit_sel_trig_0 : 3; - uint64_t cpm_bit_sel_trig_1 : 3; - uint64_t scom_marker : 8; - uint64_t cpm_mark_select : 2; - uint64_t cpm_htm_mode : 1; - uint64_t cpm_scom_mask : 8; - uint64_t cpm_scom_mode : 2; - uint64_t cpm_data_mode : 1; - uint64_t _reserved0 : 34; -#else - uint64_t _reserved0 : 34; - uint64_t cpm_data_mode : 1; - uint64_t cpm_scom_mode : 2; - uint64_t cpm_scom_mask : 8; - uint64_t cpm_htm_mode : 1; - uint64_t cpm_mark_select : 2; - uint64_t scom_marker : 8; - uint64_t cpm_bit_sel_trig_1 : 3; - uint64_t cpm_bit_sel_trig_0 : 3; - uint64_t cpm_bit_sel : 2; -#endif // _BIG_ENDIAN - } fields; -} oha_cpm_ctrl_reg_t; - - - -typedef union oha_cpm_hist_reset_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t hist_reset : 1; - uint64_t pconly_special_wakeup : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t pconly_special_wakeup : 1; - uint64_t hist_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_cpm_hist_reset_reg_t; - -#endif // __ASSEMBLER__ -#define OHA_CPM_HIST_RESET_REG_HIST_RESET SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define OHA_CPM_HIST_RESET_REG_PCONLY_SPECIAL_WAKEUP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#ifndef __ASSEMBLER__ - - -typedef union oha_ro_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t low_activity_detect_bit : 1; - uint64_t special_wakeup_completed : 1; - uint64_t architected_idle_state_from_core : 3; - uint64_t core_access_impossible : 1; - uint64_t eco_access_impossible : 1; - uint64_t spare_6bit : 6; - uint64_t current_aiss_fsm_state_vector : 7; - uint64_t eff_idle_state : 3; - uint64_t spare_1bit : 1; - uint64_t pc_tc_deep_idle_thread_state : 8; - uint64_t lpar_id : 12; - uint64_t ppt_fsm_l : 4; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t ppt_fsm_l : 4; - uint64_t lpar_id : 12; - uint64_t pc_tc_deep_idle_thread_state : 8; - uint64_t spare_1bit : 1; - uint64_t eff_idle_state : 3; - uint64_t current_aiss_fsm_state_vector : 7; - uint64_t spare_6bit : 6; - uint64_t eco_access_impossible : 1; - uint64_t core_access_impossible : 1; - uint64_t architected_idle_state_from_core : 3; - uint64_t special_wakeup_completed : 1; - uint64_t low_activity_detect_bit : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_ro_status_reg_t; - -#endif // __ASSEMBLER__ -#define OHA_RO_STATUS_REG_LOW_ACTIVITY_DETECT_BIT SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define OHA_RO_STATUS_REG_SPECIAL_WAKEUP_COMPLETED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define OHA_RO_STATUS_REG_ARCHITECTED_IDLE_STATE_FROM_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0x3800000000000000) -#define OHA_RO_STATUS_REG_CORE_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define OHA_RO_STATUS_REG_ECO_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define OHA_RO_STATUS_REG_SPARE_6BIT_MASK SIXTYFOUR_BIT_CONSTANT(0x01f8000000000000) -#define OHA_RO_STATUS_REG_CURRENT_AISS_FSM_STATE_VECTOR_MASK SIXTYFOUR_BIT_CONSTANT(0x0007f00000000000) -#define OHA_RO_STATUS_REG_EFF_IDLE_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x00000e0000000000) -#define OHA_RO_STATUS_REG_SPARE_1BIT SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) -#define OHA_RO_STATUS_REG_PC_TC_DEEP_IDLE_THREAD_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x000000ff00000000) -#define OHA_RO_STATUS_REG_LPAR_ID_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000fff00000) -#define OHA_RO_STATUS_REG_PPT_FSM_L_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000f0000) -#ifndef __ASSEMBLER__ - - -typedef union oha_mode_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_ignore_recov_errors : 1; - uint64_t enable_arch_idle_mode_sequencer : 1; - uint64_t treat_sleep_as_nap : 1; - uint64_t treat_winkle_as_sleep : 1; - uint64_t enable_pstate_tracing : 1; - uint64_t enable_suppress_purges_and_pcb_fence : 1; - uint64_t idle_state_override_en : 1; - uint64_t idle_state_override_value : 3; - uint64_t disable_aiss_core_handshake : 1; - uint64_t aiss_hang_detect_timer_sel : 4; - uint64_t enable_l2_purge_abort : 1; - uint64_t enable_l3_purge_abort : 1; - uint64_t tod_pulse_count_match_val : 14; - uint64_t trace_debug_mode_select : 2; - uint64_t lpft_mode : 1; - uint64_t _reserved0 : 30; -#else - uint64_t _reserved0 : 30; - uint64_t lpft_mode : 1; - uint64_t trace_debug_mode_select : 2; - uint64_t tod_pulse_count_match_val : 14; - uint64_t enable_l3_purge_abort : 1; - uint64_t enable_l2_purge_abort : 1; - uint64_t aiss_hang_detect_timer_sel : 4; - uint64_t disable_aiss_core_handshake : 1; - uint64_t idle_state_override_value : 3; - uint64_t idle_state_override_en : 1; - uint64_t enable_suppress_purges_and_pcb_fence : 1; - uint64_t enable_pstate_tracing : 1; - uint64_t treat_winkle_as_sleep : 1; - uint64_t treat_sleep_as_nap : 1; - uint64_t enable_arch_idle_mode_sequencer : 1; - uint64_t enable_ignore_recov_errors : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_mode_reg_t; - - - -typedef union oha_error_and_error_mask_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oha_error_mask : 8; - uint64_t oha_chiplet_errors : 8; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t oha_chiplet_errors : 8; - uint64_t oha_error_mask : 8; -#endif // _BIG_ENDIAN - } fields; -} oha_error_and_error_mask_reg_t; - - - -typedef union oha_arch_idle_state_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t aiss_thold_sequence_select : 1; - uint64_t disable_waiting_on_l3 : 1; - uint64_t idle_seq_timer_select : 2; - uint64_t allow_aiss_interrupts : 1; - uint64_t enable_reset_of_counters_while_sleepwinkle : 1; - uint64_t select_p7p_seq_wait_time : 1; - uint64_t disable_auto_sleep_entry : 1; - uint64_t disable_auto_winkle_entry : 1; - uint64_t reset_idle_state_sequencer : 1; - uint64_t _reserved0 : 54; -#else - uint64_t _reserved0 : 54; - uint64_t reset_idle_state_sequencer : 1; - uint64_t disable_auto_winkle_entry : 1; - uint64_t disable_auto_sleep_entry : 1; - uint64_t select_p7p_seq_wait_time : 1; - uint64_t enable_reset_of_counters_while_sleepwinkle : 1; - uint64_t allow_aiss_interrupts : 1; - uint64_t idle_seq_timer_select : 2; - uint64_t disable_waiting_on_l3 : 1; - uint64_t aiss_thold_sequence_select : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_arch_idle_state_reg_t; - - - -typedef union oha_pmu_config_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmu_pstate_threshold_a : 8; - uint64_t pmu_pstate_threshold_b : 8; - uint64_t pmu_configuration : 3; - uint64_t _reserved0 : 45; -#else - uint64_t _reserved0 : 45; - uint64_t pmu_configuration : 3; - uint64_t pmu_pstate_threshold_b : 8; - uint64_t pmu_pstate_threshold_a : 8; -#endif // _BIG_ENDIAN - } fields; -} oha_pmu_config_reg_t; - - - -typedef union oha_aiss_io_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare_2bits_b : 2; - uint64_t tc_tp_chiplet_pm_state : 4; - uint64_t tc_pb_sleep : 1; - uint64_t tc_tc_pm_thold_ctrl : 3; - uint64_t tc_l3_fence_lco : 1; - uint64_t tc_ncu_fence : 1; - uint64_t chksw_hw237039dis : 1; - uint64_t tc_l3_init_dram : 1; - uint64_t tc_pb_purge : 1; - uint64_t tc_pc_pm_wake_up : 1; - uint64_t spare_entry_for_config_bit : 1; - uint64_t reset_of_counters_while_sleepwinkle : 1; - uint64_t tc_chtm_purge : 1; - uint64_t tc_tp_terminate_pcb : 1; - uint64_t tc_oha_therm_purge_lvl : 1; - uint64_t pscom_core_fence_lvl : 1; - uint64_t pb_eco_fence_lvl : 1; - uint64_t core2cache_fence_req : 1; - uint64_t cache2core_fence_req : 1; - uint64_t pervasive_eco_fence_req : 1; - uint64_t tc_oha_pmx_fence_req_lvl_l : 1; - uint64_t updateohafreq : 1; - uint64_t req_idle_state_change : 1; - uint64_t tc_l2_purge : 1; - uint64_t tc_l3_purge : 1; - uint64_t tc_ncu_purge : 1; - uint64_t tc_l2_purge_abort : 1; - uint64_t tc_l3_purge_abort : 1; - uint64_t pc_tc_pm_state : 3; - uint64_t l2_purge_is_done : 1; - uint64_t l3_ncu_chtm_purge_done : 3; - uint64_t tc_tc_xstop_err : 1; - uint64_t tc_tc_recov_err : 1; - uint64_t pb_tc_purge_active_lvl : 1; - uint64_t l3_tc_dram_ready_lvl : 1; - uint64_t core_fsm_non_idle : 1; - uint64_t tc_pscom_core_fence_done : 1; - uint64_t tc_pmx_oha_fence_done : 1; - uint64_t l2_purge_abort_sticky : 1; - uint64_t l3_purge_abort_sticky : 1; - uint64_t _reserved0 : 14; -#else - uint64_t _reserved0 : 14; - uint64_t l3_purge_abort_sticky : 1; - uint64_t l2_purge_abort_sticky : 1; - uint64_t tc_pmx_oha_fence_done : 1; - uint64_t tc_pscom_core_fence_done : 1; - uint64_t core_fsm_non_idle : 1; - uint64_t l3_tc_dram_ready_lvl : 1; - uint64_t pb_tc_purge_active_lvl : 1; - uint64_t tc_tc_recov_err : 1; - uint64_t tc_tc_xstop_err : 1; - uint64_t l3_ncu_chtm_purge_done : 3; - uint64_t l2_purge_is_done : 1; - uint64_t pc_tc_pm_state : 3; - uint64_t tc_l3_purge_abort : 1; - uint64_t tc_l2_purge_abort : 1; - uint64_t tc_ncu_purge : 1; - uint64_t tc_l3_purge : 1; - uint64_t tc_l2_purge : 1; - uint64_t req_idle_state_change : 1; - uint64_t updateohafreq : 1; - uint64_t tc_oha_pmx_fence_req_lvl_l : 1; - uint64_t pervasive_eco_fence_req : 1; - uint64_t cache2core_fence_req : 1; - uint64_t core2cache_fence_req : 1; - uint64_t pb_eco_fence_lvl : 1; - uint64_t pscom_core_fence_lvl : 1; - uint64_t tc_oha_therm_purge_lvl : 1; - uint64_t tc_tp_terminate_pcb : 1; - uint64_t tc_chtm_purge : 1; - uint64_t reset_of_counters_while_sleepwinkle : 1; - uint64_t spare_entry_for_config_bit : 1; - uint64_t tc_pc_pm_wake_up : 1; - uint64_t tc_pb_purge : 1; - uint64_t tc_l3_init_dram : 1; - uint64_t chksw_hw237039dis : 1; - uint64_t tc_ncu_fence : 1; - uint64_t tc_l3_fence_lco : 1; - uint64_t tc_tc_pm_thold_ctrl : 3; - uint64_t tc_pb_sleep : 1; - uint64_t tc_tp_chiplet_pm_state : 4; - uint64_t spare_2bits_b : 2; -#endif // _BIG_ENDIAN - } fields; -} oha_aiss_io_reg_t; - - - -typedef union oha_ppt_bar_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ppt_bar : 46; - uint64_t ppt_size_mask : 7; - uint64_t ppt_address_scope : 3; - uint64_t _reserved0 : 8; -#else - uint64_t _reserved0 : 8; - uint64_t ppt_address_scope : 3; - uint64_t ppt_size_mask : 7; - uint64_t ppt_bar : 46; -#endif // _BIG_ENDIAN - } fields; -} oha_ppt_bar_reg_t; - - - -typedef union oha_l2_vcs_directory_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vcs_directory_read_weight_t; - - - -typedef union oha_l2_vcs_directory_write_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vcs_directory_write_weight_t; - - - -typedef union oha_l2_vcs_cache_full_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vcs_cache_full_read_weight_t; - - - -typedef union oha_l2_vcs_cache_targeted_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vcs_cache_targeted_read_weight_t; - - - -typedef union oha_l2_vcs_cache_write_cnt_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vcs_cache_write_cnt_weight_t; - - - -typedef union oha_l3_vcs_directory_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vcs_directory_read_weight_t; - - - -typedef union oha_l3_vcs_directory_write_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vcs_directory_write_weight_t; - - - -typedef union oha_l3_vcs_cache_access_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vcs_cache_access_weight_t; - - - -typedef union oha_l2_vdd_directory_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vdd_directory_read_weight_t; - - - -typedef union oha_l2_vdd_directory_write_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vdd_directory_write_weight_t; - - - -typedef union oha_l2_vdd_cache_full_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vdd_cache_full_read_weight_t; - - - -typedef union oha_l2_vdd_cache_targeted_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vdd_cache_targeted_read_weight_t; - - - -typedef union oha_l2_vdd_cache_write_cnt_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l2_vdd_cache_write_cnt_weight_t; - - - -typedef union oha_l3_vdd_directory_read_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vdd_directory_read_weight_t; - - - -typedef union oha_l3_vdd_directory_write_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vdd_directory_write_weight_t; - - - -typedef union oha_l3_vdd_cache_access_weight { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 6; - uint64_t _reserved0 : 58; -#else - uint64_t _reserved0 : 58; - uint64_t value : 6; -#endif // _BIG_ENDIAN - } fields; -} oha_l3_vdd_cache_access_weight_t; - - - -typedef union oha_chksw_hw132623dis { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t value : 1; -#endif // _BIG_ENDIAN - } fields; -} oha_chksw_hw132623dis_t; - - - -typedef union oha_activity_scale_factor_array { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 56; - uint64_t _reserved0 : 8; -#else - uint64_t _reserved0 : 8; - uint64_t value : 56; -#endif // _BIG_ENDIAN - } fields; -} oha_activity_scale_factor_array_t; - - - -typedef union oha_activity_scale_shift_factor_array { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 42; - uint64_t _reserved0 : 22; -#else - uint64_t _reserved0 : 22; - uint64_t value : 42; -#endif // _BIG_ENDIAN - } fields; -} oha_activity_scale_shift_factor_array_t; - - -#endif // __ASSEMBLER__ -#endif // __OHA_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/oha_register_addresses.h b/src/ssx/pgp/registers/oha_register_addresses.h deleted file mode 100755 index 1f07b37..0000000 --- a/src/ssx/pgp/registers/oha_register_addresses.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __OHA_REGISTER_ADDRESSES_H__ -#define __OHA_REGISTER_ADDRESSES_H__ - -// $Id: oha_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file oha_register_addresses.h -/// \brief Symbolic addresses for the OHA unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define OHA_PCB_BASE 0x10020000 -#define OHA_ACTIVITY_SAMPLE_MODE_REG 0x10020000 -#define OHA_VCS_ACTIVITY_CNT_REG 0x10020001 -#define OHA_VDD_ACTIVITY_CNT_REG 0x10020002 -#define OHA_LOW_ACTIVITY_DETECT_MODE_REG 0x10020003 -#define OHA_ACTIVITY_AND_FREQU_REG 0x10020004 -#define OHA_COUNTER_REG 0x10020005 -#define OHA_PROXY_REG 0x10020006 -#define OHA_PROXY_LEGACY_REG 0x10020007 -#define OHA_SKITTER_CTRL_MODE_REG 0x10020008 -#define OHA_CPM_CTRL_REG 0x1002000a -#define OHA_CPM_HIST_RESET_REG 0x10020013 -#define OHA_RO_STATUS_REG 0x1002000b -#define OHA_MODE_REG 0x1002000d -#define OHA_ERROR_AND_ERROR_MASK_REG 0x1002000e -#define OHA_ARCH_IDLE_STATE_REG 0x10020011 -#define OHA_PMU_CONFIG_REG 0x10020012 -#define OHA_AISS_IO_REG 0x10020014 -#define OHA_PPT_BAR_REG 0x10020015 - -#endif // __OHA_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pba_firmware_registers.h b/src/ssx/pgp/registers/pba_firmware_registers.h deleted file mode 100755 index 502ef51..0000000 --- a/src/ssx/pgp/registers/pba_firmware_registers.h +++ /dev/null @@ -1,2184 +0,0 @@ -#ifndef __PBA_FIRMWARE_REGISTERS_H__ -#define __PBA_FIRMWARE_REGISTERS_H__ - -// $Id: pba_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pba_firmware_registers.h -/// \brief C register structs for the PBA unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pba_barn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cmd_scope : 3; - uint64_t reserved0 : 1; - uint64_t reserved1 : 10; - uint64_t addr : 30; - uint64_t _reserved0 : 20; -#else - uint64_t _reserved0 : 20; - uint64_t addr : 30; - uint64_t reserved1 : 10; - uint64_t reserved0 : 1; - uint64_t cmd_scope : 3; -#endif // _BIG_ENDIAN - } fields; -} pba_barn_t; - -#endif // __ASSEMBLER__ -#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000) -#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000) -#ifndef __ASSEMBLER__ - - -typedef union pba_barmskn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 23; - uint64_t mask : 21; - uint64_t _reserved0 : 20; -#else - uint64_t _reserved0 : 20; - uint64_t mask : 21; - uint64_t reserved0 : 23; -#endif // _BIG_ENDIAN - } fields; -} pba_barmskn_t; - -#endif // __ASSEMBLER__ -#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000) -#ifndef __ASSEMBLER__ - - -typedef union pba_fir { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_fir_t; - -#endif // __ASSEMBLER__ -#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) -#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) -#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) -#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) -#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) -#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) -#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) -#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) -#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) -#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) -#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) -#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) -#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) -#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) -#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) -#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) -#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) -#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) -#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000) -#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000) -#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) -#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) -#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) -#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000) -#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000) -#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000) -#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000) -#ifndef __ASSEMBLER__ - - -typedef union pba_fir_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_fir_and_t; - - - -typedef union pba_fir_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_fir_or_t; - - - -typedef union pba_firmask { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_firmask_t; - - - -typedef union pba_firmask_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_firmask_and_t; - - - -typedef union pba_firmask_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_firmask_or_t; - - - -typedef union pba_firact0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_firact0_t; - - - -typedef union pba_firact1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_firact1_t; - - - -typedef union pba_occact { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t oci_apar_err : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_ce_fw : 1; - uint64_t oci_slave_init : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_rereqto : 1; - uint64_t pb_unexpcresp : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_crespto : 1; - uint64_t bcue_setup_err : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t internal_err : 1; - uint64_t illegal_cache_op : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t axpush_wrerr : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axflow_err : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_rsverr : 1; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t reserved41 : 3; - uint64_t fir_parity_err2 : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err2 : 1; - uint64_t reserved41 : 3; - uint64_t pb_ackdead_fw_wr : 1; - uint64_t axsnd_rsverr : 1; - uint64_t axsnd_rsvto : 1; - uint64_t axsnd_dlo_rtyto : 1; - uint64_t axsnd_dhi_rtyto : 1; - uint64_t axflow_err : 1; - uint64_t axrcv_rsvdata_to : 1; - uint64_t axrcv_dlo_to : 1; - uint64_t axrcv_dlo_err : 1; - uint64_t axpush_wrerr : 1; - uint64_t oci_bad_reg_addr : 1; - uint64_t illegal_cache_op : 1; - uint64_t internal_err : 1; - uint64_t bcde_oci_dataerr : 1; - uint64_t bcde_ce : 1; - uint64_t bcde_ue_err : 1; - uint64_t bcde_sue_err : 1; - uint64_t bcde_rddatato_err : 1; - uint64_t bcde_pb_adrerr : 1; - uint64_t bcde_pb_ack_dead : 1; - uint64_t bcde_setup_err : 1; - uint64_t bcue_oci_dataerr : 1; - uint64_t bcue_pb_adrerr : 1; - uint64_t bcue_pb_ack_dead : 1; - uint64_t bcue_setup_err : 1; - uint64_t pb_crespto : 1; - uint64_t pb_ackdead_fw : 1; - uint64_t pb_badcresp : 1; - uint64_t pb_wradrerr_fw : 1; - uint64_t pb_parity_err : 1; - uint64_t pb_unexpdata : 1; - uint64_t pb_unexpcresp : 1; - uint64_t oci_rereqto : 1; - uint64_t oci_wrpar_err : 1; - uint64_t oci_slave_init : 1; - uint64_t pb_ce_fw : 1; - uint64_t pb_ue_fw : 1; - uint64_t pb_sue_fw : 1; - uint64_t pb_rddatato_fw : 1; - uint64_t pb_rdadrerr_fw : 1; - uint64_t oci_apar_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_occact_t; - - - -typedef union pba_cfg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pbreq_slvfw_max_priority : 2; - uint64_t pbreq_bce_max_priority : 2; - uint64_t pbreq_data_hang_div : 5; - uint64_t pbreq_oper_hang_div : 5; - uint64_t pbreq_drop_priority_mask : 6; - uint64_t reserved20 : 4; - uint64_t chsw_hang_on_adrerror : 1; - uint64_t chsw_dis_ociabuspar_check : 1; - uint64_t chsw_dis_ocibepar_check : 1; - uint64_t chsw_hang_on_derror : 1; - uint64_t chsw_hang_on_rereq_timeout : 1; - uint64_t chsw_dis_write_match_rearb : 1; - uint64_t chsw_dis_ocidatapar_gen : 1; - uint64_t chsw_dis_ocidatapar_check : 1; - uint64_t chsw_dis_oper_hang : 1; - uint64_t chsw_dis_data_hang : 1; - uint64_t chsw_dis_ecc_check : 1; - uint64_t chsw_dis_retry_backoff : 1; - uint64_t chsw_hang_on_invalid_cresp : 1; - uint64_t chsw_en_scopeinc_on_bkill_inc : 1; - uint64_t chsw_dis_group_scope : 1; - uint64_t chsw_dis_rtag_parity_chk : 1; - uint64_t chsw_dis_pb_parity_chk : 1; - uint64_t _reserved0 : 23; -#else - uint64_t _reserved0 : 23; - uint64_t chsw_dis_pb_parity_chk : 1; - uint64_t chsw_dis_rtag_parity_chk : 1; - uint64_t chsw_dis_group_scope : 1; - uint64_t chsw_en_scopeinc_on_bkill_inc : 1; - uint64_t chsw_hang_on_invalid_cresp : 1; - uint64_t chsw_dis_retry_backoff : 1; - uint64_t chsw_dis_ecc_check : 1; - uint64_t chsw_dis_data_hang : 1; - uint64_t chsw_dis_oper_hang : 1; - uint64_t chsw_dis_ocidatapar_check : 1; - uint64_t chsw_dis_ocidatapar_gen : 1; - uint64_t chsw_dis_write_match_rearb : 1; - uint64_t chsw_hang_on_rereq_timeout : 1; - uint64_t chsw_hang_on_derror : 1; - uint64_t chsw_dis_ocibepar_check : 1; - uint64_t chsw_dis_ociabuspar_check : 1; - uint64_t chsw_hang_on_adrerror : 1; - uint64_t reserved20 : 4; - uint64_t pbreq_drop_priority_mask : 6; - uint64_t pbreq_oper_hang_div : 5; - uint64_t pbreq_data_hang_div : 5; - uint64_t pbreq_bce_max_priority : 2; - uint64_t pbreq_slvfw_max_priority : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_cfg_t; - - - -typedef union pba_errpt0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cerr_pb_rddatato_fw : 6; - uint64_t cerr_pb_rdadrerr_fw : 6; - uint64_t cerr_pb_wradrerr_fw : 4; - uint64_t cerr_pb_ackdead_fw_rd : 6; - uint64_t cerr_pb_ackdead_fw_wr : 2; - uint64_t cerr_pb_unexpcresp : 11; - uint64_t cerr_pb_unexpdata : 6; - uint64_t _reserved0 : 23; -#else - uint64_t _reserved0 : 23; - uint64_t cerr_pb_unexpdata : 6; - uint64_t cerr_pb_unexpcresp : 11; - uint64_t cerr_pb_ackdead_fw_wr : 2; - uint64_t cerr_pb_ackdead_fw_rd : 6; - uint64_t cerr_pb_wradrerr_fw : 4; - uint64_t cerr_pb_rdadrerr_fw : 6; - uint64_t cerr_pb_rddatato_fw : 6; -#endif // _BIG_ENDIAN - } fields; -} pba_errpt0_t; - - - -typedef union pba_errpt1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cerr_pb_badcresp : 12; - uint64_t cerr_pb_crespto : 12; - uint64_t cerr_oci_rereqto : 6; - uint64_t cerr_bcde_setup_err : 2; - uint64_t cerr_bcue_setup_err : 2; - uint64_t cerr_bcue_oci_dataerr : 2; - uint64_t _reserved0 : 28; -#else - uint64_t _reserved0 : 28; - uint64_t cerr_bcue_oci_dataerr : 2; - uint64_t cerr_bcue_setup_err : 2; - uint64_t cerr_bcde_setup_err : 2; - uint64_t cerr_oci_rereqto : 6; - uint64_t cerr_pb_crespto : 12; - uint64_t cerr_pb_badcresp : 12; -#endif // _BIG_ENDIAN - } fields; -} pba_errpt1_t; - - - -typedef union pba_errpt2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cerr_slv_internal_err : 8; - uint64_t cerr_bcde_internal_err : 4; - uint64_t cerr_bcue_internal_err : 4; - uint64_t cerr_bar_parity_err : 1; - uint64_t cerr_scomtb_err : 1; - uint64_t reserved18 : 2; - uint64_t cerr_pbdout_parity_err : 1; - uint64_t cerr_pb_parity_err : 3; - uint64_t cerr_axflow_err : 5; - uint64_t cerr_axpush_wrerr : 2; - uint64_t _reserved0 : 33; -#else - uint64_t _reserved0 : 33; - uint64_t cerr_axpush_wrerr : 2; - uint64_t cerr_axflow_err : 5; - uint64_t cerr_pb_parity_err : 3; - uint64_t cerr_pbdout_parity_err : 1; - uint64_t reserved18 : 2; - uint64_t cerr_scomtb_err : 1; - uint64_t cerr_bar_parity_err : 1; - uint64_t cerr_bcue_internal_err : 4; - uint64_t cerr_bcde_internal_err : 4; - uint64_t cerr_slv_internal_err : 8; -#endif // _BIG_ENDIAN - } fields; -} pba_errpt2_t; - - - -typedef union pba_rbufvaln { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t rd_slvnum : 2; - uint64_t cur_rd_addr : 23; - uint64_t spare1 : 3; - uint64_t prefetch : 1; - uint64_t spare2 : 2; - uint64_t abort : 1; - uint64_t spare3 : 1; - uint64_t buffer_status : 7; - uint64_t spare4 : 1; - uint64_t masterid : 3; - uint64_t _reserved0 : 20; -#else - uint64_t _reserved0 : 20; - uint64_t masterid : 3; - uint64_t spare4 : 1; - uint64_t buffer_status : 7; - uint64_t spare3 : 1; - uint64_t abort : 1; - uint64_t spare2 : 2; - uint64_t prefetch : 1; - uint64_t spare1 : 3; - uint64_t cur_rd_addr : 23; - uint64_t rd_slvnum : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_rbufvaln_t; - - - -typedef union pba_wbufvaln { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t wr_slvnum : 2; - uint64_t start_wr_addr : 30; - uint64_t spare1 : 3; - uint64_t wr_buffer_status : 5; - uint64_t spare2 : 1; - uint64_t wr_byte_count : 7; - uint64_t spare3 : 16; -#else - uint64_t spare3 : 16; - uint64_t wr_byte_count : 7; - uint64_t spare2 : 1; - uint64_t wr_buffer_status : 5; - uint64_t spare1 : 3; - uint64_t start_wr_addr : 30; - uint64_t wr_slvnum : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_wbufvaln_t; - - - -typedef union pba_mode { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 4; - uint64_t dis_rearb : 1; - uint64_t dis_mstid_match_pref_inv : 1; - uint64_t dis_slave_rdpipe : 1; - uint64_t dis_slave_wrpipe : 1; - uint64_t en_marker_ack : 1; - uint64_t dis_slvmatch_order : 1; - uint64_t en_second_wrbuf : 1; - uint64_t dis_rerequest_to : 1; - uint64_t inject_type : 2; - uint64_t inject_mode : 2; - uint64_t pba_region : 2; - uint64_t oci_marker_space : 3; - uint64_t bcde_ocitrans : 2; - uint64_t bcue_ocitrans : 2; - uint64_t dis_master_rd_pipe : 1; - uint64_t dis_master_wr_pipe : 1; - uint64_t en_slave_fairness : 1; - uint64_t en_event_count : 1; - uint64_t pb_noci_event_sel : 1; - uint64_t slv_event_mux : 2; - uint64_t enable_debug_bus : 1; - uint64_t debug_pb_not_oci : 1; - uint64_t debug_oci_mode : 5; - uint64_t reserved2 : 1; - uint64_t ocislv_fairness_mask : 5; - uint64_t ocislv_rereq_hang_div : 5; - uint64_t dis_chgrate_count : 1; - uint64_t pbreq_event_mux : 2; - uint64_t _reserved0 : 11; -#else - uint64_t _reserved0 : 11; - uint64_t pbreq_event_mux : 2; - uint64_t dis_chgrate_count : 1; - uint64_t ocislv_rereq_hang_div : 5; - uint64_t ocislv_fairness_mask : 5; - uint64_t reserved2 : 1; - uint64_t debug_oci_mode : 5; - uint64_t debug_pb_not_oci : 1; - uint64_t enable_debug_bus : 1; - uint64_t slv_event_mux : 2; - uint64_t pb_noci_event_sel : 1; - uint64_t en_event_count : 1; - uint64_t en_slave_fairness : 1; - uint64_t dis_master_wr_pipe : 1; - uint64_t dis_master_rd_pipe : 1; - uint64_t bcue_ocitrans : 2; - uint64_t bcde_ocitrans : 2; - uint64_t oci_marker_space : 3; - uint64_t pba_region : 2; - uint64_t inject_mode : 2; - uint64_t inject_type : 2; - uint64_t dis_rerequest_to : 1; - uint64_t en_second_wrbuf : 1; - uint64_t dis_slvmatch_order : 1; - uint64_t en_marker_ack : 1; - uint64_t dis_slave_wrpipe : 1; - uint64_t dis_slave_rdpipe : 1; - uint64_t dis_mstid_match_pref_inv : 1; - uint64_t dis_rearb : 1; - uint64_t reserved0 : 4; -#endif // _BIG_ENDIAN - } fields; -} pba_mode_t; - - - -typedef union pba_slvrst { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t set : 3; - uint64_t notimp1 : 1; - uint64_t in_prog : 4; - uint64_t busy_status : 4; - uint64_t _reserved0 : 52; -#else - uint64_t _reserved0 : 52; - uint64_t busy_status : 4; - uint64_t in_prog : 4; - uint64_t notimp1 : 1; - uint64_t set : 3; -#endif // _BIG_ENDIAN - } fields; -} pba_slvrst_t; - - - -typedef union pba_slvctln { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable : 1; - uint64_t mid_match_value : 3; - uint64_t _reserved0 : 1; - uint64_t mid_care_mask : 3; - uint64_t write_ttype : 3; - uint64_t _reserved1 : 4; - uint64_t read_ttype : 1; - uint64_t read_prefetch_ctl : 2; - uint64_t buf_invalidate_ctl : 1; - uint64_t buf_alloc_w : 1; - uint64_t buf_alloc_a : 1; - uint64_t buf_alloc_b : 1; - uint64_t buf_alloc_c : 1; - uint64_t _reserved2 : 1; - uint64_t dis_write_gather : 1; - uint64_t wr_gather_timeout : 3; - uint64_t write_tsize : 7; - uint64_t extaddr : 14; - uint64_t _reserved3 : 15; -#else - uint64_t _reserved3 : 15; - uint64_t extaddr : 14; - uint64_t write_tsize : 7; - uint64_t wr_gather_timeout : 3; - uint64_t dis_write_gather : 1; - uint64_t _reserved2 : 1; - uint64_t buf_alloc_c : 1; - uint64_t buf_alloc_b : 1; - uint64_t buf_alloc_a : 1; - uint64_t buf_alloc_w : 1; - uint64_t buf_invalidate_ctl : 1; - uint64_t read_prefetch_ctl : 2; - uint64_t read_ttype : 1; - uint64_t _reserved1 : 4; - uint64_t write_ttype : 3; - uint64_t mid_care_mask : 3; - uint64_t _reserved0 : 1; - uint64_t mid_match_value : 3; - uint64_t enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_slvctln_t; - - - -typedef union pba_bcde_ctl { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t stop : 1; - uint64_t start : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t start : 1; - uint64_t stop : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_bcde_ctl_t; - -#endif // __ASSEMBLER__ -#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#ifndef __ASSEMBLER__ - - -typedef union pba_bcde_set { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 2; - uint64_t copy_length : 6; - uint64_t _reserved1 : 56; -#else - uint64_t _reserved1 : 56; - uint64_t copy_length : 6; - uint64_t _reserved0 : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_bcde_set_t; - - - -typedef union pba_bcde_stat { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t running : 1; - uint64_t waiting : 1; - uint64_t wrcmp : 6; - uint64_t _reserved0 : 6; - uint64_t rdcmp : 6; - uint64_t debug : 9; - uint64_t stopped : 1; - uint64_t error : 1; - uint64_t done : 1; - uint64_t _reserved1 : 32; -#else - uint64_t _reserved1 : 32; - uint64_t done : 1; - uint64_t error : 1; - uint64_t stopped : 1; - uint64_t debug : 9; - uint64_t rdcmp : 6; - uint64_t _reserved0 : 6; - uint64_t wrcmp : 6; - uint64_t waiting : 1; - uint64_t running : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_bcde_stat_t; - - - -typedef union pba_bcde_pbadr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 2; - uint64_t pb_offset : 23; - uint64_t _reserved1 : 2; - uint64_t extaddr : 14; - uint64_t _reserved2 : 23; -#else - uint64_t _reserved2 : 23; - uint64_t extaddr : 14; - uint64_t _reserved1 : 2; - uint64_t pb_offset : 23; - uint64_t _reserved0 : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_bcde_pbadr_t; - - - -typedef union pba_bcde_ocibar { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t addr : 25; - uint64_t _reserved0 : 39; -#else - uint64_t _reserved0 : 39; - uint64_t addr : 25; -#endif // _BIG_ENDIAN - } fields; -} pba_bcde_ocibar_t; - - - -typedef union pba_bcue_ctl { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t stop : 1; - uint64_t start : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t start : 1; - uint64_t stop : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_bcue_ctl_t; - -#endif // __ASSEMBLER__ -#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#ifndef __ASSEMBLER__ - - -typedef union pba_bcue_set { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 2; - uint64_t copy_length : 6; - uint64_t _reserved1 : 56; -#else - uint64_t _reserved1 : 56; - uint64_t copy_length : 6; - uint64_t _reserved0 : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_bcue_set_t; - - - -typedef union pba_bcue_stat { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t running : 1; - uint64_t waiting : 1; - uint64_t wrcmp : 6; - uint64_t _reserved0 : 6; - uint64_t rdcmp : 6; - uint64_t debug : 9; - uint64_t stopped : 1; - uint64_t error : 1; - uint64_t done : 1; - uint64_t _reserved1 : 32; -#else - uint64_t _reserved1 : 32; - uint64_t done : 1; - uint64_t error : 1; - uint64_t stopped : 1; - uint64_t debug : 9; - uint64_t rdcmp : 6; - uint64_t _reserved0 : 6; - uint64_t wrcmp : 6; - uint64_t waiting : 1; - uint64_t running : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_bcue_stat_t; - - - -typedef union pba_bcue_pbadr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 2; - uint64_t pb_offset : 23; - uint64_t _reserved1 : 2; - uint64_t extaddr : 14; - uint64_t _reserved2 : 23; -#else - uint64_t _reserved2 : 23; - uint64_t extaddr : 14; - uint64_t _reserved1 : 2; - uint64_t pb_offset : 23; - uint64_t _reserved0 : 2; -#endif // _BIG_ENDIAN - } fields; -} pba_bcue_pbadr_t; - - - -typedef union pba_bcue_ocibar { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t addr : 25; - uint64_t _reserved0 : 39; -#else - uint64_t _reserved0 : 39; - uint64_t addr : 25; -#endif // _BIG_ENDIAN - } fields; -} pba_bcue_ocibar_t; - - - -typedef union pba_pbocrn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 16; - uint64_t event : 16; - uint64_t _reserved1 : 12; - uint64_t accum : 20; -#else - uint64_t accum : 20; - uint64_t _reserved1 : 12; - uint64_t event : 16; - uint64_t _reserved0 : 16; -#endif // _BIG_ENDIAN - } fields; -} pba_pbocrn_t; - - - -typedef union pba_xsndtx { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t snd_scope : 3; - uint64_t snd_qid : 1; - uint64_t snd_type : 1; - uint64_t snd_reservation : 1; - uint64_t spare6 : 2; - uint64_t snd_nodeid : 3; - uint64_t snd_chipid : 3; - uint64_t spare14 : 2; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t spare14 : 2; - uint64_t snd_chipid : 3; - uint64_t snd_nodeid : 3; - uint64_t spare6 : 2; - uint64_t snd_reservation : 1; - uint64_t snd_type : 1; - uint64_t snd_qid : 1; - uint64_t snd_scope : 3; -#endif // _BIG_ENDIAN - } fields; -} pba_xsndtx_t; - - - -typedef union pba_xcfg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pbax_en : 1; - uint64_t reservation_en : 1; - uint64_t snd_reset : 1; - uint64_t rcv_reset : 1; - uint64_t rcv_nodeid : 3; - uint64_t rcv_chipid : 3; - uint64_t spare10 : 2; - uint64_t rcv_brdcst_group : 8; - uint64_t rcv_datato_div : 5; - uint64_t spare25 : 2; - uint64_t snd_retry_count_overcom : 1; - uint64_t snd_retry_thresh : 8; - uint64_t snd_rsvto_div : 5; - uint64_t _reserved0 : 23; -#else - uint64_t _reserved0 : 23; - uint64_t snd_rsvto_div : 5; - uint64_t snd_retry_thresh : 8; - uint64_t snd_retry_count_overcom : 1; - uint64_t spare25 : 2; - uint64_t rcv_datato_div : 5; - uint64_t rcv_brdcst_group : 8; - uint64_t spare10 : 2; - uint64_t rcv_chipid : 3; - uint64_t rcv_nodeid : 3; - uint64_t rcv_reset : 1; - uint64_t snd_reset : 1; - uint64_t reservation_en : 1; - uint64_t pbax_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_xcfg_t; - - - -typedef union pba_xsndstat { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t snd_in_progress : 1; - uint64_t snd_error : 1; - uint64_t snd_status : 6; - uint64_t snd_retry_count : 8; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t snd_retry_count : 8; - uint64_t snd_status : 6; - uint64_t snd_error : 1; - uint64_t snd_in_progress : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_xsndstat_t; - - - -typedef union pba_xsnddat { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pbax_datahi : 32; - uint64_t pbax_datalo : 32; -#else - uint64_t pbax_datalo : 32; - uint64_t pbax_datahi : 32; -#endif // _BIG_ENDIAN - } fields; -} pba_xsnddat_t; - - - -typedef union pba_xrcvstat { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t rcv_in_progress : 1; - uint64_t rcv_error : 1; - uint64_t rcv_write_in_progress : 1; - uint64_t rcv_reservation_set : 1; - uint64_t rcv_capture : 14; - uint64_t _reserved0 : 46; -#else - uint64_t _reserved0 : 46; - uint64_t rcv_capture : 14; - uint64_t rcv_reservation_set : 1; - uint64_t rcv_write_in_progress : 1; - uint64_t rcv_error : 1; - uint64_t rcv_in_progress : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_xrcvstat_t; - - - -typedef union pba_xshbrn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t push_start : 29; - uint64_t _reserved0 : 35; -#else - uint64_t _reserved0 : 35; - uint64_t push_start : 29; -#endif // _BIG_ENDIAN - } fields; -} pba_xshbrn_t; - - - -typedef union pba_xshcsn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t push_full : 1; - uint64_t push_empty : 1; - uint64_t spare1 : 2; - uint64_t push_intr_action : 2; - uint64_t push_length : 5; - uint64_t notimp1 : 2; - uint64_t push_write_ptr : 5; - uint64_t notimp2 : 3; - uint64_t push_read_ptr : 5; - uint64_t notimp3 : 5; - uint64_t push_enable : 1; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t push_enable : 1; - uint64_t notimp3 : 5; - uint64_t push_read_ptr : 5; - uint64_t notimp2 : 3; - uint64_t push_write_ptr : 5; - uint64_t notimp1 : 2; - uint64_t push_length : 5; - uint64_t push_intr_action : 2; - uint64_t spare1 : 2; - uint64_t push_empty : 1; - uint64_t push_full : 1; -#endif // _BIG_ENDIAN - } fields; -} pba_xshcsn_t; - - - -typedef union pba_xshincn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 64; -#else - uint64_t reserved : 64; -#endif // _BIG_ENDIAN - } fields; -} pba_xshincn_t; - - -#endif // __ASSEMBLER__ -#endif // __PBA_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pba_register_addresses.h b/src/ssx/pgp/registers/pba_register_addresses.h deleted file mode 100755 index 1703629..0000000 --- a/src/ssx/pgp/registers/pba_register_addresses.h +++ /dev/null @@ -1,94 +0,0 @@ -#ifndef __PBA_REGISTER_ADDRESSES_H__ -#define __PBA_REGISTER_ADDRESSES_H__ - -// $Id: pba_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pba_register_addresses.h -/// \brief Symbolic addresses for the PBA unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define TRUSTEDPIB_BASE 0x02013f00 -#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n))) -#define PBA_BAR0 0x02013f00 -#define PBA_BAR1 0x02013f01 -#define PBA_BAR2 0x02013f02 -#define PBA_BAR3 0x02013f03 -#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n))) -#define PBA_BARMSK0 0x02013f04 -#define PBA_BARMSK1 0x02013f05 -#define PBA_BARMSK2 0x02013f06 -#define PBA_BARMSK3 0x02013f07 -#define PIB_BASE 0x02010840 -#define PBA_FIR 0x02010840 -#define PBA_FIR_AND 0x02010841 -#define PBA_FIR_OR 0x02010842 -#define PBA_FIRMASK 0x02010843 -#define PBA_FIRMASK_AND 0x02010844 -#define PBA_FIRMASK_OR 0x02010845 -#define PBA_FIRACT0 0x02010846 -#define PBA_FIRACT1 0x02010847 -#define PBA_OCCACT 0x0201084a -#define PBA_CFG 0x0201084b -#define PBA_ERRPT0 0x0201084c -#define PBA_ERRPT1 0x0201084d -#define PBA_ERRPT2 0x0201084e -#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n))) -#define PBA_RBUFVAL0 0x02010850 -#define PBA_RBUFVAL1 0x02010851 -#define PBA_RBUFVAL2 0x02010852 -#define PBA_RBUFVAL3 0x02010853 -#define PBA_RBUFVAL4 0x02010854 -#define PBA_RBUFVAL5 0x02010855 -#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n))) -#define PBA_WBUFVAL0 0x02010858 -#define PBA_WBUFVAL1 0x02010859 -#define OCI_BASE 0x40020000 -#define PBA_MODE 0x40020000 -#define PBA_SLVRST 0x40020008 -#define PBA_SLVCTLN(n) (PBA_SLVCTL0 + ((PBA_SLVCTL1 - PBA_SLVCTL0) * (n))) -#define PBA_SLVCTL0 0x40020020 -#define PBA_SLVCTL1 0x40020028 -#define PBA_SLVCTL2 0x40020030 -#define PBA_SLVCTL3 0x40020038 -#define PBA_BCDE_CTL 0x40020080 -#define PBA_BCDE_SET 0x40020088 -#define PBA_BCDE_STAT 0x40020090 -#define PBA_BCDE_PBADR 0x40020098 -#define PBA_BCDE_OCIBAR 0x400200a0 -#define PBA_BCUE_CTL 0x400200a8 -#define PBA_BCUE_SET 0x400200b0 -#define PBA_BCUE_STAT 0x400200b8 -#define PBA_BCUE_PBADR 0x400200c0 -#define PBA_BCUE_OCIBAR 0x400200c8 -#define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n))) -#define PBA_PBOCR0 0x400200d0 -#define PBA_PBOCR1 0x400200d8 -#define PBA_PBOCR2 0x400200e0 -#define PBA_PBOCR3 0x400200e8 -#define PBA_PBOCR4 0x400200f0 -#define PBA_PBOCR5 0x400200f8 -#define PBA_XSNDTX 0x40020100 -#define PBA_XCFG 0x40020108 -#define PBA_XSNDSTAT 0x40020110 -#define PBA_XSNDDAT 0x40020118 -#define PBA_XRCVSTAT 0x40020120 -#define PBA_XSHBRN(n) (PBA_XSHBR0 + ((PBA_XSHBR1 - PBA_XSHBR0) * (n))) -#define PBA_XSHBR0 0x40020130 -#define PBA_XSHBR1 0x40020150 -#define PBA_XSHCSN(n) (PBA_XSHCS0 + ((PBA_XSHCS1 - PBA_XSHCS0) * (n))) -#define PBA_XSHCS0 0x40020138 -#define PBA_XSHCS1 0x40020158 -#define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n))) -#define PBA_XSHINC0 0x40020140 -#define PBA_XSHINC1 0x40020160 - -#endif // __PBA_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pc_firmware_registers.h b/src/ssx/pgp/registers/pc_firmware_registers.h deleted file mode 100755 index 2c86308..0000000 --- a/src/ssx/pgp/registers/pc_firmware_registers.h +++ /dev/null @@ -1,442 +0,0 @@ -#ifndef __PC_FIRMWARE_REGISTERS_H__ -#define __PC_FIRMWARE_REGISTERS_H__ - -// $Id: pc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pc_firmware_registers.h -/// \brief C register structs for the PC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pc_pfth_modereg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pfth_cntr_dis : 1; - uint64_t pfth_charac_mode : 1; - uint64_t pfth_cntr_run_latch_gate_dis : 1; - uint64_t sprd_pfth_tx_run_latches : 8; - uint64_t tx_threads_stopped : 8; - uint64_t _reserved0 : 45; -#else - uint64_t _reserved0 : 45; - uint64_t tx_threads_stopped : 8; - uint64_t sprd_pfth_tx_run_latches : 8; - uint64_t pfth_cntr_run_latch_gate_dis : 1; - uint64_t pfth_charac_mode : 1; - uint64_t pfth_cntr_dis : 1; -#endif // _BIG_ENDIAN - } fields; -} pc_pfth_modereg_t; - - - -typedef union pc_occ_sprc { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 53; - uint64_t autoinc : 1; - uint64_t sprn : 7; - uint64_t reserved1 : 3; -#else - uint64_t reserved1 : 3; - uint64_t sprn : 7; - uint64_t autoinc : 1; - uint64_t reserved0 : 53; -#endif // _BIG_ENDIAN - } fields; -} pc_occ_sprc_t; - - - -typedef union pc_occ_sprd { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pc_occ_sprd_t; - - - -typedef union pc_pfth_oha_instr_cnt_sel { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 62; - uint64_t value : 2; -#else - uint64_t value : 2; - uint64_t _reserved0 : 62; -#endif // _BIG_ENDIAN - } fields; -} pc_pfth_oha_instr_cnt_sel_t; - - - -typedef union pc_pfth_throt_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t didt_trigger_enable : 1; - uint64_t isu_trigger_enable : 1; - uint64_t didt_throttle : 2; - uint64_t uthrottle : 2; - uint64_t force_suppress_speedup : 1; - uint64_t suppress_speedup_on_throttle : 1; - uint64_t core_slowdown : 1; - uint64_t suppress_on_slowdown : 1; - uint64_t isu_only_count_mode : 1; - uint64_t spare : 5; - uint64_t reserved : 48; -#else - uint64_t reserved : 48; - uint64_t spare : 5; - uint64_t isu_only_count_mode : 1; - uint64_t suppress_on_slowdown : 1; - uint64_t core_slowdown : 1; - uint64_t suppress_speedup_on_throttle : 1; - uint64_t force_suppress_speedup : 1; - uint64_t uthrottle : 2; - uint64_t didt_throttle : 2; - uint64_t isu_trigger_enable : 1; - uint64_t didt_trigger_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pc_pfth_throt_reg_t; - - - -typedef union pc_direct_controln { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 42; - uint64_t dc_prestart_sleep : 1; - uint64_t dc_prestart_winkle : 1; - uint64_t dc_clear_maint : 1; - uint64_t dc_ntc_flush : 1; - uint64_t reserved46 : 1; - uint64_t dc_prestart_nap : 1; - uint64_t dc_cancel_lost : 1; - uint64_t dc_reset_maint : 1; - uint64_t reserved50 : 1; - uint64_t dc_set_maint : 1; - uint64_t dc_goto_quiesce_state : 1; - uint64_t reserved53 : 1; - uint64_t dc_inj_test_hang : 2; - uint64_t dc_core_running : 1; - uint64_t dc_hang_inject : 1; - uint64_t dc_smt_start_suppress : 1; - uint64_t reserved59 : 1; - uint64_t dc_sreset_request : 1; - uint64_t dc_core_step : 1; - uint64_t dc_core_start : 1; - uint64_t dc_core_stop : 1; -#else - uint64_t dc_core_stop : 1; - uint64_t dc_core_start : 1; - uint64_t dc_core_step : 1; - uint64_t dc_sreset_request : 1; - uint64_t reserved59 : 1; - uint64_t dc_smt_start_suppress : 1; - uint64_t dc_hang_inject : 1; - uint64_t dc_core_running : 1; - uint64_t dc_inj_test_hang : 2; - uint64_t reserved53 : 1; - uint64_t dc_goto_quiesce_state : 1; - uint64_t dc_set_maint : 1; - uint64_t reserved50 : 1; - uint64_t dc_reset_maint : 1; - uint64_t dc_cancel_lost : 1; - uint64_t dc_prestart_nap : 1; - uint64_t reserved46 : 1; - uint64_t dc_ntc_flush : 1; - uint64_t dc_clear_maint : 1; - uint64_t dc_prestart_winkle : 1; - uint64_t dc_prestart_sleep : 1; - uint64_t reserved0 : 42; -#endif // _BIG_ENDIAN - } fields; -} pc_direct_controln_t; - - - -typedef union pc_ras_moderegn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 43; - uint64_t mr_thread_in_debug_mode : 1; - uint64_t mr_pmon_inhibit : 1; - uint64_t mr_fence_interrupts : 1; - uint64_t mr_stop_fetch : 1; - uint64_t mr_stop_prefetch : 1; - uint64_t mr_stop_dispatch : 1; - uint64_t mr_single_decode : 1; - uint64_t mr_do_single_mode : 1; - uint64_t mr_one_ppc_mode : 1; - uint64_t mr_hang_test_ctrl : 2; - uint64_t mr_attempt_gps_hr : 3; - uint64_t mr_hang_dis : 1; - uint64_t mr_on_corehng : 1; - uint64_t mr_on_ambihng : 1; - uint64_t mr_on_nesthng : 1; - uint64_t mr_recov_enable : 1; - uint64_t mr_block_hmi_on_maint : 1; - uint64_t mr_fence_intr_on_checkstop : 1; -#else - uint64_t mr_fence_intr_on_checkstop : 1; - uint64_t mr_block_hmi_on_maint : 1; - uint64_t mr_recov_enable : 1; - uint64_t mr_on_nesthng : 1; - uint64_t mr_on_ambihng : 1; - uint64_t mr_on_corehng : 1; - uint64_t mr_hang_dis : 1; - uint64_t mr_attempt_gps_hr : 3; - uint64_t mr_hang_test_ctrl : 2; - uint64_t mr_one_ppc_mode : 1; - uint64_t mr_do_single_mode : 1; - uint64_t mr_single_decode : 1; - uint64_t mr_stop_dispatch : 1; - uint64_t mr_stop_prefetch : 1; - uint64_t mr_stop_fetch : 1; - uint64_t mr_fence_interrupts : 1; - uint64_t mr_pmon_inhibit : 1; - uint64_t mr_thread_in_debug_mode : 1; - uint64_t reserved0 : 43; -#endif // _BIG_ENDIAN - } fields; -} pc_ras_moderegn_t; - - - -typedef union pc_ras_statusn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t quiesce_status : 20; - uint64_t reserved20 : 1; - uint64_t reserved21 : 1; - uint64_t reserved22 : 1; - uint64_t other_thread_active : 1; - uint64_t hang_fsm : 3; - uint64_t reserved27 : 1; - uint64_t hang_hist0 : 1; - uint64_t hang_hist1 : 1; - uint64_t hang_hist2 : 1; - uint64_t hang_hist3 : 1; - uint64_t reserved32 : 1; - uint64_t hr_comp_cnt : 8; - uint64_t smt_dead_stop : 1; - uint64_t stop_fetch : 1; - uint64_t stop_dispatch : 1; - uint64_t stop_completion : 1; - uint64_t hold_decode : 1; - uint64_t reserved46 : 1; - uint64_t reserved47 : 1; - uint64_t thread_enabled : 1; - uint64_t pow_status_thread_state : 4; - uint64_t reserved53 : 1; - uint64_t maint_single_mode : 1; - uint64_t reserved55 : 1; - uint64_t reserved56 : 1; - uint64_t reserved57 : 7; -#else - uint64_t reserved57 : 7; - uint64_t reserved56 : 1; - uint64_t reserved55 : 1; - uint64_t maint_single_mode : 1; - uint64_t reserved53 : 1; - uint64_t pow_status_thread_state : 4; - uint64_t thread_enabled : 1; - uint64_t reserved47 : 1; - uint64_t reserved46 : 1; - uint64_t hold_decode : 1; - uint64_t stop_completion : 1; - uint64_t stop_dispatch : 1; - uint64_t stop_fetch : 1; - uint64_t smt_dead_stop : 1; - uint64_t hr_comp_cnt : 8; - uint64_t reserved32 : 1; - uint64_t hang_hist3 : 1; - uint64_t hang_hist2 : 1; - uint64_t hang_hist1 : 1; - uint64_t hang_hist0 : 1; - uint64_t reserved27 : 1; - uint64_t hang_fsm : 3; - uint64_t other_thread_active : 1; - uint64_t reserved22 : 1; - uint64_t reserved21 : 1; - uint64_t reserved20 : 1; - uint64_t quiesce_status : 20; -#endif // _BIG_ENDIAN - } fields; -} pc_ras_statusn_t; - - - -typedef union pc_pow_statusn { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t thread_state : 4; - uint64_t thread_pow_state : 2; - uint64_t smt_mode : 3; - uint64_t hmi_intr : 1; - uint64_t maybe_ext_intr : 1; - uint64_t decr_intr : 1; - uint64_t maybe_debug_intr : 1; - uint64_t hdec_intr : 1; - uint64_t maybe_pmu_intr : 1; - uint64_t sp_attn_intr : 1; - uint64_t sreset_type : 3; - uint64_t reserved19 : 1; - uint64_t sreset_pending : 1; - uint64_t debug_fetch_stop : 1; - uint64_t async_pending : 1; - uint64_t core_pow_state : 3; - uint64_t reserved26 : 3; - uint64_t _reserved0 : 35; -#else - uint64_t _reserved0 : 35; - uint64_t reserved26 : 3; - uint64_t core_pow_state : 3; - uint64_t async_pending : 1; - uint64_t debug_fetch_stop : 1; - uint64_t sreset_pending : 1; - uint64_t reserved19 : 1; - uint64_t sreset_type : 3; - uint64_t sp_attn_intr : 1; - uint64_t maybe_pmu_intr : 1; - uint64_t hdec_intr : 1; - uint64_t maybe_debug_intr : 1; - uint64_t decr_intr : 1; - uint64_t maybe_ext_intr : 1; - uint64_t hmi_intr : 1; - uint64_t smt_mode : 3; - uint64_t thread_pow_state : 2; - uint64_t thread_state : 4; -#endif // _BIG_ENDIAN - } fields; -} pc_pow_statusn_t; - - -#endif // __ASSEMBLER__ -#endif // __PC_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pc_register_addresses.h b/src/ssx/pgp/registers/pc_register_addresses.h deleted file mode 100755 index 8b9baf2..0000000 --- a/src/ssx/pgp/registers/pc_register_addresses.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __PC_REGISTER_ADDRESSES_H__ -#define __PC_REGISTER_ADDRESSES_H__ - -// $Id: pc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pc_register_addresses.h -/// \brief Symbolic addresses for the PC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PC_PCB_BASE 0x10010000 -#define PC_PFTH_MODEREG 0x100132a7 -#define PC_OCC_SPRC 0x100132ab -#define PC_OCC_SPRD 0x100132ac -#define PC_PFTH_THROT_REG 0x100132ad -#define PC_DIRECT_CONTROLN(n) (PC_DIRECT_CONTROL0 + ((PC_DIRECT_CONTROL1 - PC_DIRECT_CONTROL0) * (n))) -#define PC_DIRECT_CONTROL0 0x10013000 -#define PC_DIRECT_CONTROL1 0x10013010 -#define PC_DIRECT_CONTROL2 0x10013020 -#define PC_DIRECT_CONTROL3 0x10013030 -#define PC_DIRECT_CONTROL4 0x10013040 -#define PC_DIRECT_CONTROL5 0x10013050 -#define PC_DIRECT_CONTROL6 0x10013060 -#define PC_DIRECT_CONTROL7 0x10013070 -#define PC_RAS_MODEREGN(n) (PC_RAS_MODEREG0 + ((PC_RAS_MODEREG1 - PC_RAS_MODEREG0) * (n))) -#define PC_RAS_MODEREG0 0x10013001 -#define PC_RAS_MODEREG1 0x10013011 -#define PC_RAS_MODEREG2 0x10013021 -#define PC_RAS_MODEREG3 0x10013031 -#define PC_RAS_MODEREG4 0x10013041 -#define PC_RAS_MODEREG5 0x10013051 -#define PC_RAS_MODEREG6 0x10013061 -#define PC_RAS_MODEREG7 0x10013071 -#define PC_RAS_STATUSN(n) (PC_RAS_STATUS0 + ((PC_RAS_STATUS1 - PC_RAS_STATUS0) * (n))) -#define PC_RAS_STATUS0 0x10013002 -#define PC_RAS_STATUS1 0x10013012 -#define PC_RAS_STATUS2 0x10013022 -#define PC_RAS_STATUS3 0x10013032 -#define PC_RAS_STATUS4 0x10013042 -#define PC_RAS_STATUS5 0x10013052 -#define PC_RAS_STATUS6 0x10013062 -#define PC_RAS_STATUS7 0x10013072 -#define PC_POW_STATUSN(n) (PC_POW_STATUS0 + ((PC_POW_STATUS1 - PC_POW_STATUS0) * (n))) -#define PC_POW_STATUS0 0x10013004 -#define PC_POW_STATUS1 0x10013014 -#define PC_POW_STATUS2 0x10013024 -#define PC_POW_STATUS3 0x10013034 -#define PC_POW_STATUS4 0x10013044 -#define PC_POW_STATUS5 0x10013054 -#define PC_POW_STATUS6 0x10013064 -#define PC_POW_STATUS7 0x10013074 - -#endif // __PC_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pcbs_firmware_registers.h b/src/ssx/pgp/registers/pcbs_firmware_registers.h deleted file mode 100755 index 1d268a2..0000000 --- a/src/ssx/pgp/registers/pcbs_firmware_registers.h +++ /dev/null @@ -1,2477 +0,0 @@ -#ifndef __PCBS_FIRMWARE_REGISTERS_H__ -#define __PCBS_FIRMWARE_REGISTERS_H__ - -// $Id: pcbs_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pcbs_firmware_registers.h -/// \brief C register structs for the PCBS unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pcbs_pmgp0_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pm_disable : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t dpll_thold : 1; - uint64_t perv_thold : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t thold_timer_sel : 2; - uint64_t block_all_wakeup_sources : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t l3_enable_switch : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t pmgp0_spare3 : 1; - uint64_t wakeup_int_type : 2; - uint64_t dpll_lock : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t regular_wkup_available : 1; - uint64_t block_reg_wkup_sources : 1; - uint64_t _reserved0 : 10; -#else - uint64_t _reserved0 : 10; - uint64_t block_reg_wkup_sources : 1; - uint64_t regular_wkup_available : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t dpll_lock : 1; - uint64_t wakeup_int_type : 2; - uint64_t pmgp0_spare3 : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t l3_enable_switch : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t block_all_wakeup_sources : 1; - uint64_t thold_timer_sel : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t perv_thold : 1; - uint64_t dpll_thold : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t pm_disable : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp0_reg_t; - - - -typedef union pcbs_pmgp0_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pm_disable : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t dpll_thold : 1; - uint64_t perv_thold : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t thold_timer_sel : 2; - uint64_t block_all_wakeup_sources : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t l3_enable_switch : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t pmgp0_spare3 : 1; - uint64_t wakeup_int_type : 2; - uint64_t dpll_lock : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t regular_wkup_available : 1; - uint64_t block_reg_wkup_sources : 1; - uint64_t _reserved0 : 10; -#else - uint64_t _reserved0 : 10; - uint64_t block_reg_wkup_sources : 1; - uint64_t regular_wkup_available : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t dpll_lock : 1; - uint64_t wakeup_int_type : 2; - uint64_t pmgp0_spare3 : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t l3_enable_switch : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t block_all_wakeup_sources : 1; - uint64_t thold_timer_sel : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t perv_thold : 1; - uint64_t dpll_thold : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t pm_disable : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp0_reg_and_t; - - - -typedef union pcbs_pmgp0_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pm_disable : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t dpll_thold : 1; - uint64_t perv_thold : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t thold_timer_sel : 2; - uint64_t block_all_wakeup_sources : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t l3_enable_switch : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t pmgp0_spare3 : 1; - uint64_t wakeup_int_type : 2; - uint64_t dpll_lock : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t regular_wkup_available : 1; - uint64_t block_reg_wkup_sources : 1; - uint64_t _reserved0 : 10; -#else - uint64_t _reserved0 : 10; - uint64_t block_reg_wkup_sources : 1; - uint64_t regular_wkup_available : 1; - uint64_t special_wkup_all_sources_ored : 1; - uint64_t dpll_lock : 1; - uint64_t wakeup_int_type : 2; - uint64_t pmgp0_spare3 : 1; - uint64_t chksw_hw259509_enable : 1; - uint64_t chksw_hw257534_disable : 1; - uint64_t chksw_hw245103_disable : 1; - uint64_t chksw_hw273115_disable : 1; - uint64_t chksw_hw241939_disable : 1; - uint64_t tp_cplt_ivrm_refbypass_dc : 1; - uint64_t l3_enable_switch : 1; - uint64_t pm_slv_winkle_fence : 1; - uint64_t tp_tc_dpll_testmode_dc : 1; - uint64_t block_all_wakeup_sources : 1; - uint64_t thold_timer_sel : 2; - uint64_t tp_clkglm_const_dc : 1; - uint64_t tp_clkglm_core_sel_dc : 2; - uint64_t special_wkup_done : 1; - uint64_t tp_clkglm_eco_sel_dc : 1; - uint64_t tp_clkglm_sel_dc : 3; - uint64_t tp_clk_async_reset_dc : 3; - uint64_t chksw_hw257424_disable : 1; - uint64_t tp_tc_pervasive_eco_fence : 1; - uint64_t tp_tc_core2cache_fence : 1; - uint64_t tp_tc_cache2core_fence : 1; - uint64_t dpll_testout_ctl : 8; - uint64_t pmgp0_spare_bit11 : 1; - uint64_t dpll_reset : 1; - uint64_t pmgp0_spare2 : 1; - uint64_t dpll_lock_sense : 1; - uint64_t pm_dpll_timer_ena : 1; - uint64_t cpm_cal_set_val : 1; - uint64_t cpm_cal_set_override_en : 1; - uint64_t perv_thold : 1; - uint64_t dpll_thold : 1; - uint64_t tp_tc_restart_core_domain : 1; - uint64_t pmgp0_spare_bit1 : 1; - uint64_t pm_disable : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp0_reg_or_t; - - - -typedef union pcbs_pmgp1_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t sleep_power_down_en : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t winkle_power_down_en : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t pm_spr_override_en : 1; - uint64_t force_safe_mode : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t pmicr_latency_en : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t _reserved0 : 43; -#else - uint64_t _reserved0 : 43; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t pmicr_latency_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t force_safe_mode : 1; - uint64_t pm_spr_override_en : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_down_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_down_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp1_reg_t; - - - -typedef union pcbs_pmgp1_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t sleep_power_down_en : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t winkle_power_down_en : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t pm_spr_override_en : 1; - uint64_t force_safe_mode : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t pmicr_latency_en : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t _reserved0 : 43; -#else - uint64_t _reserved0 : 43; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t pmicr_latency_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t force_safe_mode : 1; - uint64_t pm_spr_override_en : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_down_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_down_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp1_reg_and_t; - - - -typedef union pcbs_pmgp1_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t sleep_power_down_en : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t winkle_power_down_en : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t pm_spr_override_en : 1; - uint64_t force_safe_mode : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t pmicr_latency_en : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t _reserved0 : 43; -#else - uint64_t _reserved0 : 43; - uint64_t disable_force_deep_to_fast_winkle : 1; - uint64_t disable_force_deep_to_fast_sleep : 1; - uint64_t serialize_pfet_powerup : 1; - uint64_t serialize_pfet_powerdown : 1; - uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; - uint64_t pmicr_latency_en : 1; - uint64_t ivrm_safe_mode_force_active : 1; - uint64_t ivrm_safe_mode_en : 1; - uint64_t force_safe_mode : 1; - uint64_t pm_spr_override_en : 1; - uint64_t dpll_freq_override_enable : 1; - uint64_t endp_reset_pm_only : 1; - uint64_t oha_spc_wkup_override : 1; - uint64_t oha_pm_wkup_override : 1; - uint64_t oha_wkup_override_en : 1; - uint64_t winkle_power_off_sel : 1; - uint64_t winkle_power_up_en : 1; - uint64_t winkle_power_down_en : 1; - uint64_t sleep_power_off_sel : 1; - uint64_t sleep_power_up_en : 1; - uint64_t sleep_power_down_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmgp1_reg_or_t; - - - -typedef union pcbs_pfvddcntlstat_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_vdd_pfet_force_state : 2; - uint64_t eco_vdd_pfet_force_state : 2; - uint64_t core_vdd_pfet_val_override : 1; - uint64_t core_vdd_pfet_sel_override : 1; - uint64_t eco_vdd_pfet_val_override : 1; - uint64_t eco_vdd_pfet_sel_override : 1; - uint64_t core_vdd_pfet_enable_regulation_finger : 1; - uint64_t eco_vdd_pfet_enable_regulation_finger : 1; - uint64_t core_vdd_pfet_enable_value : 12; - uint64_t core_vdd_pfet_sel_value : 4; - uint64_t eco_vdd_pfet_enable_value : 12; - uint64_t eco_vdd_pfet_sel_value : 4; - uint64_t core_vdd_pg_state : 4; - uint64_t core_vdd_pg_sel : 4; - uint64_t eco_vdd_pg_state : 4; - uint64_t eco_vdd_pg_sel : 4; - uint64_t _reserved0 : 6; -#else - uint64_t _reserved0 : 6; - uint64_t eco_vdd_pg_sel : 4; - uint64_t eco_vdd_pg_state : 4; - uint64_t core_vdd_pg_sel : 4; - uint64_t core_vdd_pg_state : 4; - uint64_t eco_vdd_pfet_sel_value : 4; - uint64_t eco_vdd_pfet_enable_value : 12; - uint64_t core_vdd_pfet_sel_value : 4; - uint64_t core_vdd_pfet_enable_value : 12; - uint64_t eco_vdd_pfet_enable_regulation_finger : 1; - uint64_t core_vdd_pfet_enable_regulation_finger : 1; - uint64_t eco_vdd_pfet_sel_override : 1; - uint64_t eco_vdd_pfet_val_override : 1; - uint64_t core_vdd_pfet_sel_override : 1; - uint64_t core_vdd_pfet_val_override : 1; - uint64_t eco_vdd_pfet_force_state : 2; - uint64_t core_vdd_pfet_force_state : 2; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pfvddcntlstat_reg_t; - - - -typedef union pcbs_pfvcscntlstat_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_vcs_pfet_force_state : 2; - uint64_t eco_vcs_pfet_force_state : 2; - uint64_t core_vcs_pfet_val_override : 1; - uint64_t core_vcs_pfet_sel_override : 1; - uint64_t eco_vcs_pfet_val_override : 1; - uint64_t eco_vcs_pfet_sel_override : 1; - uint64_t core_vcs_pfet_enable_regulation_finger : 1; - uint64_t eco_vcs_pfet_enable_regulation_finger : 1; - uint64_t core_vcs_pfet_enable_value : 12; - uint64_t core_vcs_pfet_sel_value : 4; - uint64_t eco_vcs_pfet_enable_value : 12; - uint64_t eco_vcs_pfet_sel_value : 4; - uint64_t core_vcs_pg_state : 4; - uint64_t core_vcs_pg_sel : 4; - uint64_t eco_vcs_pg_state : 4; - uint64_t eco_vcs_pg_sel : 4; - uint64_t _reserved0 : 6; -#else - uint64_t _reserved0 : 6; - uint64_t eco_vcs_pg_sel : 4; - uint64_t eco_vcs_pg_state : 4; - uint64_t core_vcs_pg_sel : 4; - uint64_t core_vcs_pg_state : 4; - uint64_t eco_vcs_pfet_sel_value : 4; - uint64_t eco_vcs_pfet_enable_value : 12; - uint64_t core_vcs_pfet_sel_value : 4; - uint64_t core_vcs_pfet_enable_value : 12; - uint64_t eco_vcs_pfet_enable_regulation_finger : 1; - uint64_t core_vcs_pfet_enable_regulation_finger : 1; - uint64_t eco_vcs_pfet_sel_override : 1; - uint64_t eco_vcs_pfet_val_override : 1; - uint64_t core_vcs_pfet_sel_override : 1; - uint64_t core_vcs_pfet_val_override : 1; - uint64_t eco_vcs_pfet_force_state : 2; - uint64_t core_vcs_pfet_force_state : 2; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pfvcscntlstat_reg_t; - - - -typedef union pcbs_pfsense_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t tp_core_vdd_pfet_enable_sense : 12; - uint64_t tp_eco_vdd_pfet_enable_sense : 12; - uint64_t tp_core_vcs_pfet_enable_sense : 12; - uint64_t tp_eco_vcs_pfet_enable_sense : 12; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t tp_eco_vcs_pfet_enable_sense : 12; - uint64_t tp_core_vcs_pfet_enable_sense : 12; - uint64_t tp_eco_vdd_pfet_enable_sense : 12; - uint64_t tp_core_vdd_pfet_enable_sense : 12; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pfsense_reg_t; - - - -typedef union pcbs_pmerrsum_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pm_error : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t pm_error : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmerrsum_reg_t; - - - -typedef union pcbs_pmerr_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1; - uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1; - uint64_t pcbs_sleep_entry_notify_pmc_err : 1; - uint64_t pcbs_sleep_exit_invoke_pore_err : 1; - uint64_t pcbs_winkle_entry_notify_pmc_err : 1; - uint64_t pcbs_winkle_entry_send_int_assist_err : 1; - uint64_t pcbs_winkle_exit_notify_pmc_err : 1; - uint64_t pcbs_wait_dpll_lock_err : 1; - uint64_t pcbs_spare8_err : 1; - uint64_t pcbs_winkle_exit_send_int_assist_err : 1; - uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1; - uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1; - uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1; - uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1; - uint64_t pcbs_eco_rs_bypass_confusion_err : 1; - uint64_t pcbs_core_rs_bypass_confusion_err : 1; - uint64_t pcbs_read_lpst_in_pstate_mode_err : 1; - uint64_t pcbs_lpst_read_corr_err : 1; - uint64_t pcbs_lpst_read_uncorr_err : 1; - uint64_t pcbs_pfet_strength_overflow_err : 1; - uint64_t pcbs_vds_lookup_err : 1; - uint64_t pcbs_idle_interrupt_timeout_err : 1; - uint64_t pcbs_pstate_interrupt_timeout_err : 1; - uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1; - uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1; - uint64_t pcbs_global_actual_pstate_protocol_err : 1; - uint64_t pcbs_pmax_protocol_err : 1; - uint64_t pcbs_ivrm_gross_or_fine_err : 1; - uint64_t pcbs_ivrm_range_err : 1; - uint64_t pcbs_dpll_cpm_fmin_err : 1; - uint64_t pcbs_dpll_dco_full_err : 1; - uint64_t pcbs_dpll_dco_empty_err : 1; - uint64_t pcbs_dpll_int_err : 1; - uint64_t pcbs_fmin_and_not_cpmbit_err : 1; - uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1; - uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1; - uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1; - uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1; - uint64_t pcbs_occ_heartbeat_loss_err : 1; - uint64_t pcbs_spare39_err : 1; - uint64_t pcbs_spare40_err : 1; - uint64_t pcbs_spare41_err : 1; - uint64_t pcbs_spare42_err : 1; - uint64_t _reserved0 : 21; -#else - uint64_t _reserved0 : 21; - uint64_t pcbs_spare42_err : 1; - uint64_t pcbs_spare41_err : 1; - uint64_t pcbs_spare40_err : 1; - uint64_t pcbs_spare39_err : 1; - uint64_t pcbs_occ_heartbeat_loss_err : 1; - uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1; - uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1; - uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1; - uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1; - uint64_t pcbs_fmin_and_not_cpmbit_err : 1; - uint64_t pcbs_dpll_int_err : 1; - uint64_t pcbs_dpll_dco_empty_err : 1; - uint64_t pcbs_dpll_dco_full_err : 1; - uint64_t pcbs_dpll_cpm_fmin_err : 1; - uint64_t pcbs_ivrm_range_err : 1; - uint64_t pcbs_ivrm_gross_or_fine_err : 1; - uint64_t pcbs_pmax_protocol_err : 1; - uint64_t pcbs_global_actual_pstate_protocol_err : 1; - uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1; - uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1; - uint64_t pcbs_pstate_interrupt_timeout_err : 1; - uint64_t pcbs_idle_interrupt_timeout_err : 1; - uint64_t pcbs_vds_lookup_err : 1; - uint64_t pcbs_pfet_strength_overflow_err : 1; - uint64_t pcbs_lpst_read_uncorr_err : 1; - uint64_t pcbs_lpst_read_corr_err : 1; - uint64_t pcbs_read_lpst_in_pstate_mode_err : 1; - uint64_t pcbs_core_rs_bypass_confusion_err : 1; - uint64_t pcbs_eco_rs_bypass_confusion_err : 1; - uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1; - uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1; - uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1; - uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1; - uint64_t pcbs_winkle_exit_send_int_assist_err : 1; - uint64_t pcbs_spare8_err : 1; - uint64_t pcbs_wait_dpll_lock_err : 1; - uint64_t pcbs_winkle_exit_notify_pmc_err : 1; - uint64_t pcbs_winkle_entry_send_int_assist_err : 1; - uint64_t pcbs_winkle_entry_notify_pmc_err : 1; - uint64_t pcbs_sleep_exit_invoke_pore_err : 1; - uint64_t pcbs_sleep_entry_notify_pmc_err : 1; - uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1; - uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmerr_reg_t; - - - -typedef union pcbs_pmerrmask_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1; - uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1; - uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1; - uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1; - uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1; - uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1; - uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1; - uint64_t pcbs_wait_dpll_lock_err_mask : 1; - uint64_t pcbs_spare8_err_mask : 1; - uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1; - uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1; - uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1; - uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1; - uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1; - uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1; - uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1; - uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1; - uint64_t pcbs_lpst_read_corr_err_mask : 1; - uint64_t pcbs_lpst_read_uncorr_err_mask : 1; - uint64_t pcbs_pfet_strength_overflow_err_mask : 1; - uint64_t pcbs_vds_lookup_err_mask : 1; - uint64_t pcbs_idle_interrupt_timeout_err_mask : 1; - uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1; - uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1; - uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1; - uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1; - uint64_t pcbs_pmax_protocol_err_mask : 1; - uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1; - uint64_t pcbs_ivrm_range_err_mask : 1; - uint64_t pcbs_dpll_cpm_fmin_err_mask : 1; - uint64_t pcbs_dpll_dco_full_err_mask : 1; - uint64_t pcbs_dpll_dco_empty_err_mask : 1; - uint64_t pcbs_dpll_int_err_mask : 1; - uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1; - uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1; - uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1; - uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1; - uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1; - uint64_t pcbs_occ_heartbeat_loss_err_mask : 1; - uint64_t pcbs_spare39_err_mask : 1; - uint64_t pcbs_spare40_err_mask : 1; - uint64_t pcbs_spare41_err_mask : 1; - uint64_t pcbs_spare42_err_mask : 1; - uint64_t _reserved0 : 21; -#else - uint64_t _reserved0 : 21; - uint64_t pcbs_spare42_err_mask : 1; - uint64_t pcbs_spare41_err_mask : 1; - uint64_t pcbs_spare40_err_mask : 1; - uint64_t pcbs_spare39_err_mask : 1; - uint64_t pcbs_occ_heartbeat_loss_err_mask : 1; - uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1; - uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1; - uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1; - uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1; - uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1; - uint64_t pcbs_dpll_int_err_mask : 1; - uint64_t pcbs_dpll_dco_empty_err_mask : 1; - uint64_t pcbs_dpll_dco_full_err_mask : 1; - uint64_t pcbs_dpll_cpm_fmin_err_mask : 1; - uint64_t pcbs_ivrm_range_err_mask : 1; - uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1; - uint64_t pcbs_pmax_protocol_err_mask : 1; - uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1; - uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1; - uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1; - uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1; - uint64_t pcbs_idle_interrupt_timeout_err_mask : 1; - uint64_t pcbs_vds_lookup_err_mask : 1; - uint64_t pcbs_pfet_strength_overflow_err_mask : 1; - uint64_t pcbs_lpst_read_uncorr_err_mask : 1; - uint64_t pcbs_lpst_read_corr_err_mask : 1; - uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1; - uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1; - uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1; - uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1; - uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1; - uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1; - uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1; - uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1; - uint64_t pcbs_spare8_err_mask : 1; - uint64_t pcbs_wait_dpll_lock_err_mask : 1; - uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1; - uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1; - uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1; - uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1; - uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1; - uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1; - uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmerrmask_reg_t; - - - -typedef union pcbs_pmspcwkupfsp_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t fsp_special_wakeup : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t fsp_special_wakeup : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmspcwkupfsp_reg_t; - - - -typedef union pcbs_pmspcwkupocc_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_special_wakeup : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t occ_special_wakeup : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmspcwkupocc_reg_t; - - - -typedef union pcbs_pmspcwkupphyp_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t phyp_special_wakeup : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t phyp_special_wakeup : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmspcwkupphyp_reg_t; - - - -typedef union pcbs_pmstatehistphyp_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t phyp_pm_state : 3; - uint64_t phyp_past_core_instruct_stop : 1; - uint64_t phyp_past_core_clk_stop : 1; - uint64_t phyp_past_core_pwr_off : 1; - uint64_t phyp_past_eco_clk_stop : 1; - uint64_t phyp_past_eco_pwr_off : 1; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t phyp_past_eco_pwr_off : 1; - uint64_t phyp_past_eco_clk_stop : 1; - uint64_t phyp_past_core_pwr_off : 1; - uint64_t phyp_past_core_clk_stop : 1; - uint64_t phyp_past_core_instruct_stop : 1; - uint64_t phyp_pm_state : 3; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmstatehistphyp_reg_t; - - - -typedef union pcbs_pmstatehistfsp_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t fsp_pm_state : 3; - uint64_t fsp_past_core_instruct_stop : 1; - uint64_t fsp_past_core_clk_stop : 1; - uint64_t fsp_past_core_pwr_off : 1; - uint64_t fsp_past_eco_clk_stop : 1; - uint64_t fsp_past_eco_pwr_off : 1; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t fsp_past_eco_pwr_off : 1; - uint64_t fsp_past_eco_clk_stop : 1; - uint64_t fsp_past_core_pwr_off : 1; - uint64_t fsp_past_core_clk_stop : 1; - uint64_t fsp_past_core_instruct_stop : 1; - uint64_t fsp_pm_state : 3; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmstatehistfsp_reg_t; - - - -typedef union pcbs_pmstatehistocc_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_pm_state : 3; - uint64_t occ_past_core_instruct_stop : 1; - uint64_t occ_past_core_clk_stop : 1; - uint64_t occ_past_core_pwr_off : 1; - uint64_t occ_past_eco_clk_stop : 1; - uint64_t occ_past_eco_pwr_off : 1; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t occ_past_eco_pwr_off : 1; - uint64_t occ_past_eco_clk_stop : 1; - uint64_t occ_past_core_pwr_off : 1; - uint64_t occ_past_core_clk_stop : 1; - uint64_t occ_past_core_instruct_stop : 1; - uint64_t occ_pm_state : 3; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmstatehistocc_reg_t; - - - -typedef union pcbs_pmstatehistperf_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t perf_pm_state : 3; - uint64_t perf_past_core_instruct_stop : 1; - uint64_t perf_past_core_clk_stop : 1; - uint64_t perf_past_core_pwr_off : 1; - uint64_t perf_past_eco_clk_stop : 1; - uint64_t perf_past_eco_pwr_off : 1; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t perf_past_eco_pwr_off : 1; - uint64_t perf_past_eco_clk_stop : 1; - uint64_t perf_past_core_pwr_off : 1; - uint64_t perf_past_core_clk_stop : 1; - uint64_t perf_past_core_instruct_stop : 1; - uint64_t perf_pm_state : 3; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmstatehistperf_reg_t; - - - -typedef union pcbs_idlefsmgotocmd_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t idle_fsm_goto_cmd : 2; - uint64_t babystp_trigger_sleep_entry : 1; - uint64_t babystp_trigger_winkle_entry : 1; - uint64_t babystp_trigger_wakeup : 1; - uint64_t _reserved0 : 59; -#else - uint64_t _reserved0 : 59; - uint64_t babystp_trigger_wakeup : 1; - uint64_t babystp_trigger_winkle_entry : 1; - uint64_t babystp_trigger_sleep_entry : 1; - uint64_t idle_fsm_goto_cmd : 2; -#endif // _BIG_ENDIAN - } fields; -} pcbs_idlefsmgotocmd_reg_t; - - - -typedef union pcbs_corepfpudly_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_powup_dly0 : 4; - uint64_t core_powup_dly1 : 4; - uint64_t core_power_up_delay_sel : 12; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t core_power_up_delay_sel : 12; - uint64_t core_powup_dly1 : 4; - uint64_t core_powup_dly0 : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_corepfpudly_reg_t; - - - -typedef union pcbs_corepfpddly_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_powdn_dly0 : 4; - uint64_t core_powdn_dly1 : 4; - uint64_t core_power_dn_delay_sel : 12; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t core_power_dn_delay_sel : 12; - uint64_t core_powdn_dly1 : 4; - uint64_t core_powdn_dly0 : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_corepfpddly_reg_t; - - - -typedef union pcbs_corepfvret_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t core_vret_sel : 4; - uint64_t core_voff_sel : 4; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t core_voff_sel : 4; - uint64_t core_vret_sel : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_corepfvret_reg_t; - - - -typedef union pcbs_ecopfpudly_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t eco_powup_dly0 : 4; - uint64_t eco_powup_dly1 : 4; - uint64_t eco_power_up_delay_sel : 12; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t eco_power_up_delay_sel : 12; - uint64_t eco_powup_dly1 : 4; - uint64_t eco_powup_dly0 : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ecopfpudly_reg_t; - - - -typedef union pcbs_ecopfpddly_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t eco_powdn_dly0 : 4; - uint64_t eco_powdn_dly1 : 4; - uint64_t eco_power_dn_delay_sel : 12; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t eco_power_dn_delay_sel : 12; - uint64_t eco_powdn_dly1 : 4; - uint64_t eco_powdn_dly0 : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ecopfpddly_reg_t; - - - -typedef union pcbs_ecopfvret_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t eco_vret_sel : 4; - uint64_t eco_voff_sel : 4; - uint64_t _reserved0 : 56; -#else - uint64_t _reserved0 : 56; - uint64_t eco_voff_sel : 4; - uint64_t eco_vret_sel : 4; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ecopfvret_reg_t; - - - -typedef union pcbs_freq_ctrl_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dpll_fmin : 9; - uint64_t dpll_fmax : 9; - uint64_t dpll_fmax_bias : 4; - uint64_t frequ_at_pstate0 : 9; - uint64_t _reserved0 : 33; -#else - uint64_t _reserved0 : 33; - uint64_t frequ_at_pstate0 : 9; - uint64_t dpll_fmax_bias : 4; - uint64_t dpll_fmax : 9; - uint64_t dpll_fmin : 9; -#endif // _BIG_ENDIAN - } fields; -} pcbs_freq_ctrl_reg_t; - - - -typedef union pcbs_dpll_cpm_parm_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t lf_slewratexpi : 8; - uint64_t lf_use_cpmxpi : 1; - uint64_t ff_use_cpmxpi : 1; - uint64_t cpm_filter_enable : 1; - uint64_t ff_bypassxpi : 1; - uint64_t dco_override : 1; - uint64_t dco_incr : 1; - uint64_t dco_decr : 1; - uint64_t dpll_lock_timer_replacement_value : 9; - uint64_t pre_vret_pstate : 8; - uint64_t override_pcbs_dpll_synchronizer : 1; - uint64_t dpll_char_delta1 : 4; - uint64_t dpll_char_delta2 : 4; - uint64_t _reserved0 : 23; -#else - uint64_t _reserved0 : 23; - uint64_t dpll_char_delta2 : 4; - uint64_t dpll_char_delta1 : 4; - uint64_t override_pcbs_dpll_synchronizer : 1; - uint64_t pre_vret_pstate : 8; - uint64_t dpll_lock_timer_replacement_value : 9; - uint64_t dco_decr : 1; - uint64_t dco_incr : 1; - uint64_t dco_override : 1; - uint64_t ff_bypassxpi : 1; - uint64_t cpm_filter_enable : 1; - uint64_t ff_use_cpmxpi : 1; - uint64_t lf_use_cpmxpi : 1; - uint64_t lf_slewratexpi : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_dpll_cpm_parm_reg_t; - - - -typedef union pcbs_power_management_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t global_pstate_actual : 8; - int64_t local_pstate_actual : 8; - int64_t pv_min : 8; - int64_t pvf_max : 8; - uint64_t spr_em_disabled : 1; - uint64_t psafe_mode_active : 1; - uint64_t ivrm_safe_mode_active : 1; - uint64_t ivrm_enable : 1; - uint64_t all_fsms_in_safe_state : 1; - uint64_t pmsr_spares : 4; - uint64_t _reserved0 : 23; -#else - uint64_t _reserved0 : 23; - uint64_t pmsr_spares : 4; - uint64_t all_fsms_in_safe_state : 1; - uint64_t ivrm_enable : 1; - uint64_t ivrm_safe_mode_active : 1; - uint64_t psafe_mode_active : 1; - uint64_t spr_em_disabled : 1; - int64_t pvf_max : 8; - int64_t pv_min : 8; - int64_t local_pstate_actual : 8; - int64_t global_pstate_actual : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_power_management_status_reg_t; - - - -typedef union pcbs_ivrm_control_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ivrm_fsm_enable : 1; - uint64_t use_ivrm_for_vret : 1; - uint64_t binsearch_cal_ena : 1; - uint64_t pvref_en : 1; - uint64_t ivrm_core_vdd_bypass_b : 1; - uint64_t ivrm_core_vdd_poweron : 1; - uint64_t ivrm_core_vcs_bypass_b : 1; - uint64_t ivrm_core_vcs_poweron : 1; - uint64_t ivrm_eco_vdd_bypass_b : 1; - uint64_t ivrm_eco_vdd_poweron : 1; - uint64_t ivrm_eco_vcs_bypass_b : 1; - uint64_t ivrm_eco_vcs_poweron : 1; - uint64_t ivrm_vret_vdd : 7; - uint64_t ivrm_vret_vcs : 7; - uint64_t ivrm_vret_core_vdd_pfet_strength : 5; - uint64_t ivrm_vret_core_vcs_pfet_strength : 5; - uint64_t ivrm_vret_eco_vdd_pfet_strength : 5; - uint64_t ivrm_vret_eco_vcs_pfet_strength : 5; - uint64_t pvref_fail : 1; - uint64_t ivrm_pref_error_gross : 1; - uint64_t ivrm_pref_error_fine : 1; - uint64_t ivrm_core_vdd_range_hi : 1; - uint64_t ivrm_core_vdd_range_lo : 1; - uint64_t ivrm_eco_vdd_range_hi : 1; - uint64_t ivrm_eco_vdd_range_lo : 1; - uint64_t ivrm_core_vcs_range_hi : 1; - uint64_t ivrm_core_vcs_range_lo : 1; - uint64_t ivrm_eco_vcs_range_hi : 1; - uint64_t ivrm_eco_vcs_range_lo : 1; - uint64_t binsearch_cal_done : 1; - uint64_t ivrm_core_vdd_pfet_low_vout : 1; - uint64_t ivrm_core_vcs_pfet_low_vout : 1; - uint64_t ivrm_eco_vdd_pfet_low_vout : 1; - uint64_t ivrm_eco_vcs_pfet_low_vout : 1; - uint64_t ivrm_power_down_disable : 1; - uint64_t _reserved0 : 1; -#else - uint64_t _reserved0 : 1; - uint64_t ivrm_power_down_disable : 1; - uint64_t ivrm_eco_vcs_pfet_low_vout : 1; - uint64_t ivrm_eco_vdd_pfet_low_vout : 1; - uint64_t ivrm_core_vcs_pfet_low_vout : 1; - uint64_t ivrm_core_vdd_pfet_low_vout : 1; - uint64_t binsearch_cal_done : 1; - uint64_t ivrm_eco_vcs_range_lo : 1; - uint64_t ivrm_eco_vcs_range_hi : 1; - uint64_t ivrm_core_vcs_range_lo : 1; - uint64_t ivrm_core_vcs_range_hi : 1; - uint64_t ivrm_eco_vdd_range_lo : 1; - uint64_t ivrm_eco_vdd_range_hi : 1; - uint64_t ivrm_core_vdd_range_lo : 1; - uint64_t ivrm_core_vdd_range_hi : 1; - uint64_t ivrm_pref_error_fine : 1; - uint64_t ivrm_pref_error_gross : 1; - uint64_t pvref_fail : 1; - uint64_t ivrm_vret_eco_vcs_pfet_strength : 5; - uint64_t ivrm_vret_eco_vdd_pfet_strength : 5; - uint64_t ivrm_vret_core_vcs_pfet_strength : 5; - uint64_t ivrm_vret_core_vdd_pfet_strength : 5; - uint64_t ivrm_vret_vcs : 7; - uint64_t ivrm_vret_vdd : 7; - uint64_t ivrm_eco_vcs_poweron : 1; - uint64_t ivrm_eco_vcs_bypass_b : 1; - uint64_t ivrm_eco_vdd_poweron : 1; - uint64_t ivrm_eco_vdd_bypass_b : 1; - uint64_t ivrm_core_vcs_poweron : 1; - uint64_t ivrm_core_vcs_bypass_b : 1; - uint64_t ivrm_core_vdd_poweron : 1; - uint64_t ivrm_core_vdd_bypass_b : 1; - uint64_t pvref_en : 1; - uint64_t binsearch_cal_ena : 1; - uint64_t use_ivrm_for_vret : 1; - uint64_t ivrm_fsm_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ivrm_control_status_reg_t; - - - -typedef union pcbs_ivrm_value_setting_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ivrm_core_vdd_ivid : 8; - uint64_t ivrm_core_vcs_ivid : 8; - uint64_t ivrm_eco_vdd_ivid : 8; - uint64_t ivrm_eco_vcs_ivid : 8; - uint64_t ivrm_core_vdd_pfet_strength : 5; - uint64_t ivrm_core_vcs_pfet_strength : 5; - uint64_t ivrm_eco_vdd_pfet_strength : 5; - uint64_t ivrm_eco_vcs_pfet_strength : 5; - uint64_t ivrm_vdd_core_pfetstr_valid : 1; - uint64_t ivrm_vcs_core_pfetstr_valid : 1; - uint64_t ivrm_vdd_eco_pfetstr_valid : 1; - uint64_t ivrm_vcs_eco_pfetstr_valid : 1; - uint64_t core_vdd_vpump_en : 1; - uint64_t core_vcs_vpump_en : 1; - uint64_t eco_vdd_vpump_en : 1; - uint64_t eco_vcs_vpump_en : 1; - uint64_t _reserved0 : 4; -#else - uint64_t _reserved0 : 4; - uint64_t eco_vcs_vpump_en : 1; - uint64_t eco_vdd_vpump_en : 1; - uint64_t core_vcs_vpump_en : 1; - uint64_t core_vdd_vpump_en : 1; - uint64_t ivrm_vcs_eco_pfetstr_valid : 1; - uint64_t ivrm_vdd_eco_pfetstr_valid : 1; - uint64_t ivrm_vcs_core_pfetstr_valid : 1; - uint64_t ivrm_vdd_core_pfetstr_valid : 1; - uint64_t ivrm_eco_vcs_pfet_strength : 5; - uint64_t ivrm_eco_vdd_pfet_strength : 5; - uint64_t ivrm_core_vcs_pfet_strength : 5; - uint64_t ivrm_core_vdd_pfet_strength : 5; - uint64_t ivrm_eco_vcs_ivid : 8; - uint64_t ivrm_eco_vdd_ivid : 8; - uint64_t ivrm_core_vcs_ivid : 8; - uint64_t ivrm_core_vdd_ivid : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ivrm_value_setting_reg_t; - - - -typedef union pcbs_pcbspm_mode_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_pstate_mode : 1; - uint64_t global_pstate_change_for_idle_state_enabled : 1; - uint64_t enable_global_pstate_req : 1; - uint64_t enable_winkle_with_cpm_mode : 1; - uint64_t enable_clipping_of_global_pstate_req : 1; - uint64_t chksw_hw214553 : 1; - uint64_t enable_pmc_pmax_sync_notification : 1; - uint64_t dpll_lock_replacement_timer_mode_en : 1; - uint64_t dpll_freqout_mode_en : 1; - uint64_t dpll_flock_mode_en : 1; - uint64_t enable_sense_delay_characterization : 1; - uint64_t sense_delay_timer_val : 7; - uint64_t cpm_fmin_clip_error_sel : 2; - uint64_t dbg_trace_sel : 4; - uint64_t trace_data_sel : 2; - uint64_t tp_cplt_ivrm_vpp_tune : 4; - uint64_t _reserved0 : 34; -#else - uint64_t _reserved0 : 34; - uint64_t tp_cplt_ivrm_vpp_tune : 4; - uint64_t trace_data_sel : 2; - uint64_t dbg_trace_sel : 4; - uint64_t cpm_fmin_clip_error_sel : 2; - uint64_t sense_delay_timer_val : 7; - uint64_t enable_sense_delay_characterization : 1; - uint64_t dpll_flock_mode_en : 1; - uint64_t dpll_freqout_mode_en : 1; - uint64_t dpll_lock_replacement_timer_mode_en : 1; - uint64_t enable_pmc_pmax_sync_notification : 1; - uint64_t chksw_hw214553 : 1; - uint64_t enable_clipping_of_global_pstate_req : 1; - uint64_t enable_winkle_with_cpm_mode : 1; - uint64_t enable_global_pstate_req : 1; - uint64_t global_pstate_change_for_idle_state_enabled : 1; - uint64_t enable_pstate_mode : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pcbspm_mode_reg_t; - -#endif // __ASSEMBLER__ -#define PCBS_PCBSPM_MODE_REG_ENABLE_PSTATE_MODE SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PCBS_PCBSPM_MODE_REG_GLOBAL_PSTATE_CHANGE_FOR_IDLE_STATE_ENABLED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PCBS_PCBSPM_MODE_REG_ENABLE_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PCBS_PCBSPM_MODE_REG_ENABLE_WINKLE_WITH_CPM_MODE SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PCBS_PCBSPM_MODE_REG_ENABLE_CLIPPING_OF_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define PCBS_PCBSPM_MODE_REG_CHKSW_HW214553 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define PCBS_PCBSPM_MODE_REG_ENABLE_PMC_PMAX_SYNC_NOTIFICATION SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define PCBS_PCBSPM_MODE_REG_DPLL_LOCK_REPLACEMENT_TIMER_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PCBS_PCBSPM_MODE_REG_DPLL_FREQOUT_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PCBS_PCBSPM_MODE_REG_DPLL_FLOCK_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PCBS_PCBSPM_MODE_REG_ENABLE_SENSE_DELAY_CHARACTERIZATION SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PCBS_PCBSPM_MODE_REG_SENSE_DELAY_TIMER_VAL_MASK SIXTYFOUR_BIT_CONSTANT(0x001fc00000000000) -#define PCBS_PCBSPM_MODE_REG_CPM_FMIN_CLIP_ERROR_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x0000300000000000) -#define PCBS_PCBSPM_MODE_REG_DBG_TRACE_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000f0000000000) -#define PCBS_PCBSPM_MODE_REG_TRACE_DATA_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x000000c000000000) -#define PCBS_PCBSPM_MODE_REG_TP_CPLT_IVRM_VPP_TUNE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000003c00000000) -#ifndef __ASSEMBLER__ - - -typedef union pcbs_ivrm_pfetstr_sense_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ivrm_core_vdd_pfetstr_sns : 5; - uint64_t ivrm_core_vcs_pfetstr_sns : 5; - uint64_t ivrm_eco_vdd_pfetstr_sns : 5; - uint64_t ivrm_eco_vcs_pfetstr_sns : 5; - uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1; - uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1; - uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1; - uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1; - uint64_t core_vdd_bypass_b_sense : 1; - uint64_t core_vcs_bypass_b_sense : 1; - uint64_t eco_vdd_bypass_b_sense : 1; - uint64_t eco_vcs_bypass_b_sense : 1; - uint64_t core_vdd_poweron_sense : 1; - uint64_t core_vcs_poweron_sense : 1; - uint64_t eco_vdd_poweron_sense : 1; - uint64_t eco_vcs_poweron_sense : 1; - uint64_t core_vdd_vpump_en_sense : 1; - uint64_t core_vcs_vpump_en_sense : 1; - uint64_t eco_vdd_vpump_en_sense : 1; - uint64_t eco_vcs_vpump_en_sense : 1; - uint64_t core_vdd_pfet_low_vout_sns : 1; - uint64_t core_vcs_pfet_low_vout_sns : 1; - uint64_t eco_vdd_pfet_low_vout_sns : 1; - uint64_t eco_vcs_pfet_low_vout_sns : 1; - uint64_t _reserved0 : 24; -#else - uint64_t _reserved0 : 24; - uint64_t eco_vcs_pfet_low_vout_sns : 1; - uint64_t eco_vdd_pfet_low_vout_sns : 1; - uint64_t core_vcs_pfet_low_vout_sns : 1; - uint64_t core_vdd_pfet_low_vout_sns : 1; - uint64_t eco_vcs_vpump_en_sense : 1; - uint64_t eco_vdd_vpump_en_sense : 1; - uint64_t core_vcs_vpump_en_sense : 1; - uint64_t core_vdd_vpump_en_sense : 1; - uint64_t eco_vcs_poweron_sense : 1; - uint64_t eco_vdd_poweron_sense : 1; - uint64_t core_vcs_poweron_sense : 1; - uint64_t core_vdd_poweron_sense : 1; - uint64_t eco_vcs_bypass_b_sense : 1; - uint64_t eco_vdd_bypass_b_sense : 1; - uint64_t core_vcs_bypass_b_sense : 1; - uint64_t core_vdd_bypass_b_sense : 1; - uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1; - uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1; - uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1; - uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1; - uint64_t ivrm_eco_vcs_pfetstr_sns : 5; - uint64_t ivrm_eco_vdd_pfetstr_sns : 5; - uint64_t ivrm_core_vcs_pfetstr_sns : 5; - uint64_t ivrm_core_vdd_pfetstr_sns : 5; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ivrm_pfetstr_sense_reg_t; - - - -typedef union pcbs_power_management_idle_control_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t nap_pstate_req : 8; - uint64_t nap_pstate_en : 1; - uint64_t nap_global_en : 1; - uint64_t nap_latency : 2; - uint64_t reserved_ppmicr_0 : 4; - int64_t sleep_pstate_req : 8; - uint64_t sleep_pstate_en : 1; - uint64_t sleep_global_en : 1; - uint64_t sleep_latency : 2; - uint64_t reserved_ppmicr_1 : 4; - int64_t winkle_pstate_req : 8; - uint64_t winkle_pstate_en : 1; - uint64_t winkle_global_en : 1; - uint64_t winkle_latency : 2; - uint64_t reserved_ppmicr_2 : 4; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t reserved_ppmicr_2 : 4; - uint64_t winkle_latency : 2; - uint64_t winkle_global_en : 1; - uint64_t winkle_pstate_en : 1; - int64_t winkle_pstate_req : 8; - uint64_t reserved_ppmicr_1 : 4; - uint64_t sleep_latency : 2; - uint64_t sleep_global_en : 1; - uint64_t sleep_pstate_en : 1; - int64_t sleep_pstate_req : 8; - uint64_t reserved_ppmicr_0 : 4; - uint64_t nap_latency : 2; - uint64_t nap_global_en : 1; - uint64_t nap_pstate_en : 1; - int64_t nap_pstate_req : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_power_management_idle_control_reg_t; - - - -typedef union pcbs_power_management_control_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t global_pstate_req : 8; - int64_t local_pstate_req : 8; - uint64_t auto_override0_pstate_limit_en : 1; - uint64_t auto_override1_pstate_limit_en : 1; - uint64_t reserved_ppmcr : 6; - int64_t auto_override_pstate0 : 8; - int64_t auto_override_pstate1 : 8; - uint64_t _reserved0 : 24; -#else - uint64_t _reserved0 : 24; - int64_t auto_override_pstate1 : 8; - int64_t auto_override_pstate0 : 8; - uint64_t reserved_ppmcr : 6; - uint64_t auto_override1_pstate_limit_en : 1; - uint64_t auto_override0_pstate_limit_en : 1; - int64_t local_pstate_req : 8; - int64_t global_pstate_req : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_power_management_control_reg_t; - - - -typedef union pcbs_pmc_vf_ctrl_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t pglobal_actual : 8; - uint64_t maxregvcs : 8; - uint64_t maxregvdd : 8; - uint64_t evidvcs_eff : 8; - uint64_t evidvdd_eff : 8; - uint64_t _reserved0 : 24; -#else - uint64_t _reserved0 : 24; - uint64_t evidvdd_eff : 8; - uint64_t evidvcs_eff : 8; - uint64_t maxregvdd : 8; - uint64_t maxregvcs : 8; - int64_t pglobal_actual : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pmc_vf_ctrl_reg_t; - - - -typedef union pcbs_undervolting_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t puv_min : 8; - int64_t puv_max : 8; - uint64_t kuv : 6; - uint64_t _reserved0 : 42; -#else - uint64_t _reserved0 : 42; - uint64_t kuv : 6; - int64_t puv_max : 8; - int64_t puv_min : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_undervolting_reg_t; - - - -typedef union pcbs_pstate_index_bound_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t lpsi_min : 8; - uint64_t lpsi_entries_minus_1 : 7; - uint64_t _reserved0 : 49; -#else - uint64_t _reserved0 : 49; - uint64_t lpsi_entries_minus_1 : 7; - uint64_t lpsi_min : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pstate_index_bound_reg_t; - - - -typedef union pcbs_power_management_bounds_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t pmin_clip : 8; - int64_t pmax_clip : 8; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - int64_t pmax_clip : 8; - int64_t pmin_clip : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_power_management_bounds_reg_t; - - - -typedef union pcbs_pstate_table_ctrl_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pstate_table_address : 7; - uint64_t _reserved0 : 57; -#else - uint64_t _reserved0 : 57; - uint64_t pstate_table_address : 7; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pstate_table_ctrl_reg_t; - - - -typedef union pcbs_pstate_table_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pstate_data : 64; -#else - uint64_t pstate_data : 64; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pstate_table_reg_t; - - - -typedef union pcbs_pstate_step_target_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t local_pstate_eff_req : 8; - int64_t local_pstate_target : 8; - int64_t local_core_pstate_step_target : 8; - int64_t local_eco_pstate_step_target : 8; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - int64_t local_eco_pstate_step_target : 8; - int64_t local_core_pstate_step_target : 8; - int64_t local_pstate_target : 8; - int64_t local_pstate_eff_req : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_pstate_step_target_reg_t; - - - -typedef union pcbs_dpll_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dpll_ff_freqout : 15; - uint64_t dpll_frequ_change : 1; - uint64_t dpll_status_spare_bit1 : 1; - uint64_t pmax_sync_pending : 1; - uint64_t ga_ack_pending : 1; - int64_t capped_global_pstate_req : 8; - uint64_t dpll_fmax_and_cpmbit2 : 1; - uint64_t dpll_fmax_and_cpmbit3 : 1; - uint64_t dpll_fmax_and_cpmbit4 : 1; - uint64_t dpll_fmin_and_not_cpmbit2 : 1; - uint64_t dpll_fmin_and_not_cpmbit1 : 1; - uint64_t dpll_fmin_and_not_cpmbit0 : 1; - uint64_t dpll_faster_than_fmax_plus_delta1 : 1; - uint64_t dpll_slower_than_fmin_minus_delta2 : 1; - uint64_t dpll_max_freqout_after_last_read : 14; - uint64_t dpll_min_freqout_after_last_read : 14; - uint64_t _reserved0 : 1; -#else - uint64_t _reserved0 : 1; - uint64_t dpll_min_freqout_after_last_read : 14; - uint64_t dpll_max_freqout_after_last_read : 14; - uint64_t dpll_slower_than_fmin_minus_delta2 : 1; - uint64_t dpll_faster_than_fmax_plus_delta1 : 1; - uint64_t dpll_fmin_and_not_cpmbit0 : 1; - uint64_t dpll_fmin_and_not_cpmbit1 : 1; - uint64_t dpll_fmin_and_not_cpmbit2 : 1; - uint64_t dpll_fmax_and_cpmbit4 : 1; - uint64_t dpll_fmax_and_cpmbit3 : 1; - uint64_t dpll_fmax_and_cpmbit2 : 1; - int64_t capped_global_pstate_req : 8; - uint64_t ga_ack_pending : 1; - uint64_t pmax_sync_pending : 1; - uint64_t dpll_status_spare_bit1 : 1; - uint64_t dpll_frequ_change : 1; - uint64_t dpll_ff_freqout : 15; -#endif // _BIG_ENDIAN - } fields; -} pcbs_dpll_status_reg_t; - - - -typedef union pcbs_ivrm_vid_control_reg0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ivrm_req_pstate_stepdelay_rising : 8; - uint64_t ivrm_req_pstate_stepdelay_lowering : 8; - uint64_t _reserved0 : 48; -#else - uint64_t _reserved0 : 48; - uint64_t ivrm_req_pstate_stepdelay_lowering : 8; - uint64_t ivrm_req_pstate_stepdelay_rising : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ivrm_vid_control_reg0_t; - - - -typedef union pcbs_ivrm_vid_control_reg1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ivrm_stabilize_delay_run : 8; - uint64_t ivrm_stabilize_delay_idle : 8; - uint64_t ivrm_pfstr_prop_delay : 8; - uint64_t ivrm_pfstrvalid_prop_delay : 8; - uint64_t ivrm_vpump_poweron_time : 8; - uint64_t ivrm_bypass_delay : 8; - uint64_t pfet_vpump_enable_delay : 8; - uint64_t ivrm_vid_vout_threshold : 7; - uint64_t _reserved0 : 1; -#else - uint64_t _reserved0 : 1; - uint64_t ivrm_vid_vout_threshold : 7; - uint64_t pfet_vpump_enable_delay : 8; - uint64_t ivrm_bypass_delay : 8; - uint64_t ivrm_vpump_poweron_time : 8; - uint64_t ivrm_pfstrvalid_prop_delay : 8; - uint64_t ivrm_pfstr_prop_delay : 8; - uint64_t ivrm_stabilize_delay_idle : 8; - uint64_t ivrm_stabilize_delay_run : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_ivrm_vid_control_reg1_t; - - - -typedef union pcbs_occ_heartbeat_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t occ_heartbeat_time : 8; - uint64_t occ_heartbeat_enable : 1; - uint64_t occ_heartbeat_reg_addr_offset : 8; - int64_t psafe : 8; - uint64_t _reserved0 : 39; -#else - uint64_t _reserved0 : 39; - int64_t psafe : 8; - uint64_t occ_heartbeat_reg_addr_offset : 8; - uint64_t occ_heartbeat_enable : 1; - uint64_t occ_heartbeat_time : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_occ_heartbeat_reg_t; - - - -typedef union pcbs_resonant_clock_control_reg0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t resclk_dis : 1; - uint64_t resclk_control_mode : 1; - uint64_t resclk_sync_pw : 3; - uint64_t res_sync_delay_cnt : 7; - uint64_t res_csb_str_instr_lo : 15; - uint64_t res_csb_str_instr_hi : 15; - uint64_t _reserved0 : 22; -#else - uint64_t _reserved0 : 22; - uint64_t res_csb_str_instr_hi : 15; - uint64_t res_csb_str_instr_lo : 15; - uint64_t res_sync_delay_cnt : 7; - uint64_t resclk_sync_pw : 3; - uint64_t resclk_control_mode : 1; - uint64_t resclk_dis : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_resonant_clock_control_reg0_t; - - - -typedef union pcbs_resonant_clock_control_reg1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - int64_t full_csb_ps : 8; - int64_t res_low_lower_ps : 8; - int64_t res_low_upper_ps : 8; - int64_t res_high_lower_ps : 8; - int64_t res_high_upper_ps : 8; - uint64_t nonres_csb_value_ti : 4; - uint64_t full_csb_value_ti : 4; - uint64_t resclk_value : 9; - uint64_t resclk_core_sync_value : 1; - uint64_t csb_eco_sync_value : 1; - uint64_t _reserved0 : 5; -#else - uint64_t _reserved0 : 5; - uint64_t csb_eco_sync_value : 1; - uint64_t resclk_core_sync_value : 1; - uint64_t resclk_value : 9; - uint64_t full_csb_value_ti : 4; - uint64_t nonres_csb_value_ti : 4; - int64_t res_high_upper_ps : 8; - int64_t res_high_lower_ps : 8; - int64_t res_low_upper_ps : 8; - int64_t res_low_lower_ps : 8; - int64_t full_csb_ps : 8; -#endif // _BIG_ENDIAN - } fields; -} pcbs_resonant_clock_control_reg1_t; - - - -typedef union pcbs_resonant_clock_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t resclk_state : 1; - uint64_t res_hi_induct_en : 1; - uint64_t resclk_inprogress : 1; - uint64_t resclk_full_csb : 1; - uint64_t _reserved0 : 60; -#else - uint64_t _reserved0 : 60; - uint64_t resclk_full_csb : 1; - uint64_t resclk_inprogress : 1; - uint64_t res_hi_induct_en : 1; - uint64_t resclk_state : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_resonant_clock_status_reg_t; - - - -typedef union pcbs_local_pstate_frequency_target_control_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t delay_time : 3; - uint64_t record_transitions : 1; - uint64_t multiplier : 15; - uint64_t enable_lpft_function : 1; - uint64_t _reserved0 : 44; -#else - uint64_t _reserved0 : 44; - uint64_t enable_lpft_function : 1; - uint64_t multiplier : 15; - uint64_t record_transitions : 1; - uint64_t delay_time : 3; -#endif // _BIG_ENDIAN - } fields; -} pcbs_local_pstate_frequency_target_control_reg_t; - - - -typedef union pcbs_local_pstate_frequency_target_status_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t valid : 1; - uint64_t cpm_dpll : 1; - uint64_t ivrm : 1; - uint64_t transition : 1; - uint64_t stable : 1; - uint64_t delta : 24; - uint64_t cumulative : 24; - uint64_t pstate : 8; - uint64_t _reserved0 : 3; -#else - uint64_t _reserved0 : 3; - uint64_t pstate : 8; - uint64_t cumulative : 24; - uint64_t delta : 24; - uint64_t stable : 1; - uint64_t transition : 1; - uint64_t ivrm : 1; - uint64_t cpm_dpll : 1; - uint64_t valid : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_local_pstate_frequency_target_status_reg_t; - - - -typedef union pcbs_fsm_monitor1_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t babystep_main_fsm : 7; - uint64_t babystep_slave_fsm : 5; - uint64_t core_railstepper_main_fsm : 5; - uint64_t eco_railstepper_main_fsm : 5; - uint64_t core_railstepper_sub_fsm : 4; - uint64_t eco_railstepper_sub_fsm : 4; - uint64_t core_railstepper_byp_fsm : 5; - uint64_t eco_railstepper_byp_fsm : 5; - uint64_t ivrm_core_vdd_sequencer_fsm : 6; - uint64_t ivrm_core_vcs_sequencer_fsm : 6; - uint64_t ivrm_eco_vdd_sequencer_fsm : 6; - uint64_t ivrm_eco_vcs_sequencer_fsm : 6; -#else - uint64_t ivrm_eco_vcs_sequencer_fsm : 6; - uint64_t ivrm_eco_vdd_sequencer_fsm : 6; - uint64_t ivrm_core_vcs_sequencer_fsm : 6; - uint64_t ivrm_core_vdd_sequencer_fsm : 6; - uint64_t eco_railstepper_byp_fsm : 5; - uint64_t core_railstepper_byp_fsm : 5; - uint64_t eco_railstepper_sub_fsm : 4; - uint64_t core_railstepper_sub_fsm : 4; - uint64_t eco_railstepper_main_fsm : 5; - uint64_t core_railstepper_main_fsm : 5; - uint64_t babystep_slave_fsm : 5; - uint64_t babystep_main_fsm : 7; -#endif // _BIG_ENDIAN - } fields; -} pcbs_fsm_monitor1_reg_t; - - - -typedef union pcbs_fsm_monitor2_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t resclk_band_fsm : 7; - uint64_t resclk_lowres_fsm : 4; - uint64_t resclk_highres_fsm : 4; - uint64_t resclk_fullcsb_fsm : 4; - uint64_t resclk_update_fsm : 4; - uint64_t idle_transition_fsm : 7; - uint64_t peco_step_target_uv : 8; - uint64_t pcore_step_target_uv : 8; - uint64_t _reserved0 : 18; -#else - uint64_t _reserved0 : 18; - uint64_t pcore_step_target_uv : 8; - uint64_t peco_step_target_uv : 8; - uint64_t idle_transition_fsm : 7; - uint64_t resclk_update_fsm : 4; - uint64_t resclk_fullcsb_fsm : 4; - uint64_t resclk_highres_fsm : 4; - uint64_t resclk_lowres_fsm : 4; - uint64_t resclk_band_fsm : 7; -#endif // _BIG_ENDIAN - } fields; -} pcbs_fsm_monitor2_reg_t; - - - -typedef union pcbs_chksw_unassisted_interrupts { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 1; - uint64_t _reserved0 : 63; -#else - uint64_t _reserved0 : 63; - uint64_t value : 1; -#endif // _BIG_ENDIAN - } fields; -} pcbs_chksw_unassisted_interrupts_t; - - -#endif // __ASSEMBLER__ -#endif // __PCBS_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pcbs_register_addresses.h b/src/ssx/pgp/registers/pcbs_register_addresses.h deleted file mode 100755 index 8c465d1..0000000 --- a/src/ssx/pgp/registers/pcbs_register_addresses.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef __PCBS_REGISTER_ADDRESSES_H__ -#define __PCBS_REGISTER_ADDRESSES_H__ - -// $Id: pcbs_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pcbs_register_addresses.h -/// \brief Symbolic addresses for the PCBS unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PCBS_PIB_BASE 0x100f0100 -#define PCBS_PMGP0_REG 0x100f0100 -#define PCBS_PMGP0_REG_AND 0x100f0101 -#define PCBS_PMGP0_REG_OR 0x100f0102 -#define PCBS_PMGP1_REG 0x100f0103 -#define PCBS_PMGP1_REG_AND 0x100f0104 -#define PCBS_PMGP1_REG_OR 0x100f0105 -#define PCBS_PFVDDCNTLSTAT_REG 0x100f0106 -#define PCBS_PFVCSCNTLSTAT_REG 0x100f010e -#define PCBS_PFSENSE_REG 0x100f0107 -#define PCBS_PMERRSUM_REG 0x100f0108 -#define PCBS_PMERR_REG 0x100f0109 -#define PCBS_PMERRMASK_REG 0x100f010a -#define PCBS_PMSPCWKUPFSP_REG 0x100f010b -#define PCBS_PMSPCWKUPOCC_REG 0x100f010c -#define PCBS_PMSPCWKUPPHYP_REG 0x100f010d -#define PCBS_PMSTATEHISTPHYP_REG 0x100f0110 -#define PCBS_PMSTATEHISTFSP_REG 0x100f0111 -#define PCBS_PMSTATEHISTOCC_REG 0x100f0112 -#define PCBS_PMSTATEHISTPERF_REG 0x100f0113 -#define PCBS_IDLEFSMGOTOCMD_REG 0x100f0114 -#define PCBS_COREPFPUDLY_REG 0x100f012c -#define PCBS_COREPFPDDLY_REG 0x100f012d -#define PCBS_COREPFVRET_REG 0x100f0130 -#define PCBS_ECOPFPUDLY_REG 0x100f014c -#define PCBS_ECOPFPDDLY_REG 0x100f014d -#define PCBS_ECOPFVRET_REG 0x100f0150 -#define PCBS_FREQ_CTRL_REG 0x100f0151 -#define PCBS_DPLL_CPM_PARM_REG 0x100f0152 -#define PCBS_POWER_MANAGEMENT_STATUS_REG 0x100f0153 -#define PCBS_IVRM_CONTROL_STATUS_REG 0x100f0154 -#define PCBS_IVRM_VALUE_SETTING_REG 0x100f0155 -#define PCBS_PCBSPM_MODE_REG 0x100f0156 -#define PCBS_IVRM_PFETSTR_SENSE_REG 0x100f0157 -#define PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG 0x100f0158 -#define PCBS_POWER_MANAGEMENT_CONTROL_REG 0x100f0159 -#define PCBS_PMC_VF_CTRL_REG 0x100f015a -#define PCBS_UNDERVOLTING_REG 0x100f015b -#define PCBS_PSTATE_INDEX_BOUND_REG 0x100f015c -#define PCBS_POWER_MANAGEMENT_BOUNDS_REG 0x100f015d -#define PCBS_PSTATE_TABLE_CTRL_REG 0x100f015e -#define PCBS_PSTATE_TABLE_REG 0x100f015f -#define PCBS_PSTATE_STEP_TARGET_REG 0x100f0160 -#define PCBS_DPLL_STATUS_REG 0x100f0161 -#define PCBS_IVRM_VID_CONTROL_REG0 0x100f0162 -#define PCBS_IVRM_VID_CONTROL_REG1 0x100f0163 -#define PCBS_OCC_HEARTBEAT_REG 0x100f0164 -#define PCBS_RESONANT_CLOCK_CONTROL_REG0 0x100f0165 -#define PCBS_RESONANT_CLOCK_CONTROL_REG1 0x100f0166 -#define PCBS_RESONANT_CLOCK_STATUS_REG 0x100f0167 -#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_CONTROL_REG 0x100f0168 -#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_STATUS_REG 0x100f0169 -#define PCBS_FSM_MONITOR1_REG 0x100f0170 -#define PCBS_FSM_MONITOR2_REG 0x100f0171 - -#endif // __PCBS_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pibmem_firmware_registers.h b/src/ssx/pgp/registers/pibmem_firmware_registers.h deleted file mode 100644 index 3b36fc1..0000000 --- a/src/ssx/pgp/registers/pibmem_firmware_registers.h +++ /dev/null @@ -1,264 +0,0 @@ -#ifndef __PIBMEM_FIRMWARE_REGISTERS_H__ -#define __PIBMEM_FIRMWARE_REGISTERS_H__ - -// $Id: pibmem_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pibmem_firmware_registers.h -/// \brief C register structs for the PIBMEM unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pibmem_data0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pibmem_data0_t; - - - -typedef union pibmem_control { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t auto_pre_increment : 1; - uint64_t auto_post_decrement : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t auto_post_decrement : 1; - uint64_t auto_pre_increment : 1; -#endif // _BIG_ENDIAN - } fields; -} pibmem_control_t; - - - -typedef union pibmem_address { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 48; - uint64_t address : 16; -#else - uint64_t address : 16; - uint64_t reserved0 : 48; -#endif // _BIG_ENDIAN - } fields; -} pibmem_address_t; - - - -typedef union pibmem_data { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pibmem_data_t; - - - -typedef union pibmem_data_inc { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pibmem_data_inc_t; - - - -typedef union pibmem_data_dec { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pibmem_data_dec_t; - - - -typedef union pibmem_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t addr_invalid : 1; - uint64_t write_invalid : 1; - uint64_t read_invalid : 1; - uint64_t ecc_uncorrected_error : 1; - uint64_t ecc_corrected_error : 1; - uint64_t bad_array_address : 1; - uint64_t reserved6 : 5; - uint64_t fsm_present_state : 7; - uint64_t _reserved0 : 46; -#else - uint64_t _reserved0 : 46; - uint64_t fsm_present_state : 7; - uint64_t reserved6 : 5; - uint64_t bad_array_address : 1; - uint64_t ecc_corrected_error : 1; - uint64_t ecc_uncorrected_error : 1; - uint64_t read_invalid : 1; - uint64_t write_invalid : 1; - uint64_t addr_invalid : 1; -#endif // _BIG_ENDIAN - } fields; -} pibmem_status_t; - - - -typedef union pibmem_reset { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reset_code : 2; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t reset_code : 2; -#endif // _BIG_ENDIAN - } fields; -} pibmem_reset_t; - - - -typedef union pibmem_repair { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 64; -#else - uint64_t value : 64; -#endif // _BIG_ENDIAN - } fields; -} pibmem_repair_t; - - -#endif // __ASSEMBLER__ -#endif // __PIBMEM_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pibmem_register_addresses.h b/src/ssx/pgp/registers/pibmem_register_addresses.h deleted file mode 100644 index 0cffaa2..0000000 --- a/src/ssx/pgp/registers/pibmem_register_addresses.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __PIBMEM_REGISTER_ADDRESSES_H__ -#define __PIBMEM_REGISTER_ADDRESSES_H__ - -// $Id: pibmem_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pibmem_register_addresses.h -/// \brief Symbolic addresses for the PIBMEM unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PIBMEM_PIB_BASE 0x00080000 -#define PIBMEM_DATA0 0x00080000 -#define PIBMEM_CONTROL 0x00088000 -#define PIBMEM_ADDRESS 0x00088001 -#define PIBMEM_DATA 0x00088002 -#define PIBMEM_DATA_INC 0x00088003 -#define PIBMEM_DATA_DEC 0x00088004 -#define PIBMEM_STATUS 0x00088005 -#define PIBMEM_RESET 0x00088006 -#define PIBMEM_REPAIR 0x00088007 - -#endif // __PIBMEM_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h b/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h deleted file mode 100755 index 583e95d..0000000 --- a/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h +++ /dev/null @@ -1,215 +0,0 @@ -#ifndef __PLB_ARBITER_FIRMWARE_REGISTERS_H__ -#define __PLB_ARBITER_FIRMWARE_REGISTERS_H__ - -// $Id: plb_arbiter_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file plb_arbiter_firmware_registers.h -/// \brief C register structs for the PLB_ARBITER unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union plb_prev { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} plb_prev_t; - - - -typedef union plb_pacr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t ppm : 1; - uint32_t ppo : 3; - uint32_t hbu : 1; - uint32_t rdp : 2; - uint32_t wrp : 1; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - uint32_t wrp : 1; - uint32_t rdp : 2; - uint32_t hbu : 1; - uint32_t ppo : 3; - uint32_t ppm : 1; -#endif // _BIG_ENDIAN - } fields; -} plb_pacr_t; - - - -typedef union plb_pesr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pte0 : 1; - uint32_t rw0 : 1; - uint32_t flk0 : 1; - uint32_t alk0 : 1; - uint32_t pte1 : 1; - uint32_t rw1 : 1; - uint32_t flk1 : 1; - uint32_t alk1 : 1; - uint32_t pte2 : 1; - uint32_t rw2 : 1; - uint32_t flk2 : 1; - uint32_t alk2 : 1; - uint32_t pte3 : 1; - uint32_t rw3 : 1; - uint32_t flk3 : 1; - uint32_t alk3 : 1; - uint32_t pte4 : 1; - uint32_t rw4 : 1; - uint32_t flk4 : 1; - uint32_t alk4 : 1; - uint32_t pte5 : 1; - uint32_t rw5 : 1; - uint32_t flk5 : 1; - uint32_t alk5 : 1; - uint32_t pte6 : 1; - uint32_t rw6 : 1; - uint32_t flk6 : 1; - uint32_t alk6 : 1; - uint32_t pte7 : 1; - uint32_t rw7 : 1; - uint32_t flk7 : 1; - uint32_t alk7 : 1; -#else - uint32_t alk7 : 1; - uint32_t flk7 : 1; - uint32_t rw7 : 1; - uint32_t pte7 : 1; - uint32_t alk6 : 1; - uint32_t flk6 : 1; - uint32_t rw6 : 1; - uint32_t pte6 : 1; - uint32_t alk5 : 1; - uint32_t flk5 : 1; - uint32_t rw5 : 1; - uint32_t pte5 : 1; - uint32_t alk4 : 1; - uint32_t flk4 : 1; - uint32_t rw4 : 1; - uint32_t pte4 : 1; - uint32_t alk3 : 1; - uint32_t flk3 : 1; - uint32_t rw3 : 1; - uint32_t pte3 : 1; - uint32_t alk2 : 1; - uint32_t flk2 : 1; - uint32_t rw2 : 1; - uint32_t pte2 : 1; - uint32_t alk1 : 1; - uint32_t flk1 : 1; - uint32_t rw1 : 1; - uint32_t pte1 : 1; - uint32_t alk0 : 1; - uint32_t flk0 : 1; - uint32_t rw0 : 1; - uint32_t pte0 : 1; -#endif // _BIG_ENDIAN - } fields; -} plb_pesr_t; - - - -typedef union plb_pearl { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} plb_pearl_t; - - - -typedef union plb_pearh { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} plb_pearh_t; - - - -typedef union plb_sto_pesr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t icu_te : 1; - uint32_t icu_rw : 1; - uint32_t reserved2 : 2; - uint32_t dcu_te : 1; - uint32_t dcu_rw : 1; - uint32_t reserved6 : 2; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - uint32_t reserved6 : 2; - uint32_t dcu_rw : 1; - uint32_t dcu_te : 1; - uint32_t reserved2 : 2; - uint32_t icu_rw : 1; - uint32_t icu_te : 1; -#endif // _BIG_ENDIAN - } fields; -} plb_sto_pesr_t; - - - -typedef union plb_sto_pear { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t value : 32; -#else - uint32_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} plb_sto_pear_t; - - -#endif // __ASSEMBLER__ -#endif // __PLB_ARBITER_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/plb_arbiter_register_addresses.h b/src/ssx/pgp/registers/plb_arbiter_register_addresses.h deleted file mode 100755 index 2bc2f41..0000000 --- a/src/ssx/pgp/registers/plb_arbiter_register_addresses.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __PLB_ARBITER_REGISTER_ADDRESSES_H__ -#define __PLB_ARBITER_REGISTER_ADDRESSES_H__ - -// $Id: plb_arbiter_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file plb_arbiter_register_addresses.h -/// \brief Symbolic addresses for the PLB_ARBITER unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PLB_DCR_BASE 0x90 -#define PLB_PREV 0x00000092 -#define PLB_PACR 0x00000093 -#define PLB_PESR 0x00000094 -#define PLB_PEARL 0x00000096 -#define PLB_PEARH 0x00000097 -#define PLB_STO_PESR 0x00000099 -#define PLB_STO_PEAR 0x00000098 - -#endif // __PLB_ARBITER_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pmc_firmware_registers.h b/src/ssx/pgp/registers/pmc_firmware_registers.h deleted file mode 100755 index 76642a4..0000000 --- a/src/ssx/pgp/registers/pmc_firmware_registers.h +++ /dev/null @@ -1,3140 +0,0 @@ -#ifndef __PMC_FIRMWARE_REGISTERS_H__ -#define __PMC_FIRMWARE_REGISTERS_H__ - -// $Id: pmc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pmc_firmware_registers.h -/// \brief C register structs for the PMC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pmc_mode_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t enable_hw_pstate_mode : 1; - uint32_t enable_fw_auction_pstate_mode : 1; - uint32_t enable_fw_pstate_mode : 1; - uint32_t enable_pstate_voltage_changes : 1; - uint32_t enable_global_actual_pstate_forwarding : 1; - uint32_t halt_pstate_master_fsm : 1; - uint32_t enable_interchip_interface : 1; - uint32_t interchip_mode : 1; - uint32_t enable_interchip_pstate_in_haps : 1; - uint32_t enable_pstate_stepping : 1; - uint32_t honor_oha_idle_state_requests : 1; - uint32_t vid_endianess : 1; - uint32_t reset_all_pmc_registers : 1; - uint32_t safe_mode_without_spivid : 1; - uint32_t halt_idle_state_master_fsm : 1; - uint32_t interchip_halt_if : 1; - uint32_t unfreeze_pstate_processing : 1; - uint32_t spivid_reset_if : 1; - uint32_t unfreeze_istate_processing : 1; - uint32_t _reserved0 : 13; -#else - uint32_t _reserved0 : 13; - uint32_t unfreeze_istate_processing : 1; - uint32_t spivid_reset_if : 1; - uint32_t unfreeze_pstate_processing : 1; - uint32_t interchip_halt_if : 1; - uint32_t halt_idle_state_master_fsm : 1; - uint32_t safe_mode_without_spivid : 1; - uint32_t reset_all_pmc_registers : 1; - uint32_t vid_endianess : 1; - uint32_t honor_oha_idle_state_requests : 1; - uint32_t enable_pstate_stepping : 1; - uint32_t enable_interchip_pstate_in_haps : 1; - uint32_t interchip_mode : 1; - uint32_t enable_interchip_interface : 1; - uint32_t halt_pstate_master_fsm : 1; - uint32_t enable_global_actual_pstate_forwarding : 1; - uint32_t enable_pstate_voltage_changes : 1; - uint32_t enable_fw_pstate_mode : 1; - uint32_t enable_fw_auction_pstate_mode : 1; - uint32_t enable_hw_pstate_mode : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_mode_reg_t; - - - -typedef union pmc_hardware_auction_pstate_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t haps : 8; - uint32_t kuv_actual : 8; - uint32_t kuv_received : 8; - uint32_t _reserved0 : 8; -#else - uint32_t _reserved0 : 8; - uint32_t kuv_received : 8; - uint32_t kuv_actual : 8; - int32_t haps : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_hardware_auction_pstate_reg_t; - - - -typedef union pmc_pstate_monitor_and_ctrl_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t gpst_val : 8; - int32_t gpsst : 8; - int32_t gpsa : 8; - int32_t gapr : 8; -#else - int32_t gapr : 8; - int32_t gpsa : 8; - int32_t gpsst : 8; - int32_t gpst_val : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_pstate_monitor_and_ctrl_reg_t; - - - -typedef union pmc_rail_bounds_register { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pmin_rail : 8; - int32_t pmax_rail : 8; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - int32_t pmax_rail : 8; - int32_t pmin_rail : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_rail_bounds_register_t; - - - -typedef union pmc_global_pstate_bounds_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t gpsi_min : 8; - uint32_t gpst_number_of_entries_minus_one : 7; - uint32_t _reserved0 : 17; -#else - uint32_t _reserved0 : 17; - uint32_t gpst_number_of_entries_minus_one : 7; - uint32_t gpsi_min : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_global_pstate_bounds_reg_t; - - - -typedef union pmc_parameter_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pstate_stepsize : 7; - uint32_t vrm_stepdelay_range : 4; - uint32_t vrm_stepdelay_value : 4; - uint32_t hangpulse_predivider : 6; - uint32_t gpsa_timeout_value : 8; - uint32_t gpsa_timeout_value_sel : 1; - uint32_t _reserved0 : 2; -#else - uint32_t _reserved0 : 2; - uint32_t gpsa_timeout_value_sel : 1; - uint32_t gpsa_timeout_value : 8; - uint32_t hangpulse_predivider : 6; - uint32_t vrm_stepdelay_value : 4; - uint32_t vrm_stepdelay_range : 4; - uint32_t pstate_stepsize : 7; -#endif // _BIG_ENDIAN - } fields; -} pmc_parameter_reg0_t; - - - -typedef union pmc_parameter_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t ba_sram_pstate_table : 22; - int32_t pvsafe : 8; - uint32_t _reserved0 : 2; -#else - uint32_t _reserved0 : 2; - int32_t pvsafe : 8; - uint32_t ba_sram_pstate_table : 22; -#endif // _BIG_ENDIAN - } fields; -} pmc_parameter_reg1_t; - - - -typedef union pmc_eff_global_actual_voltage_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t maxreg_vdd : 8; - uint32_t maxreg_vcs : 8; - uint32_t eff_evid_vdd : 8; - uint32_t eff_evid_vcs : 8; -#else - uint32_t eff_evid_vcs : 8; - uint32_t eff_evid_vdd : 8; - uint32_t maxreg_vcs : 8; - uint32_t maxreg_vdd : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_eff_global_actual_voltage_reg_t; - - - -typedef union pmc_global_actual_voltage_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t evid_vdd : 8; - uint32_t evid_vcs : 8; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t evid_vcs : 8; - uint32_t evid_vdd : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_global_actual_voltage_reg_t; - - - -typedef union pmc_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pstate_processing_is_suspended : 1; - uint32_t gpsa_bdcst_error : 1; - uint32_t gpsa_bdcst_resp_info : 3; - uint32_t gpsa_vchg_error : 1; - uint32_t gpsa_timeout_error : 1; - uint32_t gpsa_chg_ongoing : 1; - uint32_t volt_chg_ongoing : 1; - uint32_t brd_cst_ongoing : 1; - uint32_t gps_table_error : 1; - uint32_t pstate_interchip_error : 1; - uint32_t istate_processing_is_suspended : 1; - uint32_t safe_mode_engaged : 1; - uint32_t _reserved0 : 18; -#else - uint32_t _reserved0 : 18; - uint32_t safe_mode_engaged : 1; - uint32_t istate_processing_is_suspended : 1; - uint32_t pstate_interchip_error : 1; - uint32_t gps_table_error : 1; - uint32_t brd_cst_ongoing : 1; - uint32_t volt_chg_ongoing : 1; - uint32_t gpsa_chg_ongoing : 1; - uint32_t gpsa_timeout_error : 1; - uint32_t gpsa_vchg_error : 1; - uint32_t gpsa_bdcst_resp_info : 3; - uint32_t gpsa_bdcst_error : 1; - uint32_t pstate_processing_is_suspended : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_status_reg_t; - - - -typedef union pmc_phase_enable_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t phase_enable : 4; - uint32_t _reserved0 : 28; -#else - uint32_t _reserved0 : 28; - uint32_t phase_enable : 4; -#endif // _BIG_ENDIAN - } fields; -} pmc_phase_enable_reg_t; - - - -typedef union pmc_undervolting_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t puv_min : 8; - int32_t puv_max : 8; - uint32_t kuv_request : 8; - uint32_t _reserved0 : 8; -#else - uint32_t _reserved0 : 8; - uint32_t kuv_request : 8; - int32_t puv_max : 8; - int32_t puv_min : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_undervolting_reg_t; - - - -typedef union pmc_core_deconfiguration_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t core_chiplet_deconf_vector : 16; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t core_chiplet_deconf_vector : 16; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_deconfiguration_reg_t; - - - -typedef union pmc_intchp_ctrl_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_ga_fsm_enable : 1; - uint32_t interchip_recv_done_valid_without_if_en : 1; - uint32_t pmcic1_reserved_2 : 1; - uint32_t interchip_cpha : 1; - uint32_t interchip_clock_divider : 10; - uint32_t pmcicr1_reserved_14_17 : 4; - uint32_t pmcicr1_reserved_18_20 : 3; - uint32_t _reserved0 : 11; -#else - uint32_t _reserved0 : 11; - uint32_t pmcicr1_reserved_18_20 : 3; - uint32_t pmcicr1_reserved_14_17 : 4; - uint32_t interchip_clock_divider : 10; - uint32_t interchip_cpha : 1; - uint32_t pmcic1_reserved_2 : 1; - uint32_t interchip_recv_done_valid_without_if_en : 1; - uint32_t interchip_ga_fsm_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_ctrl_reg1_t; - - - -typedef union pmc_intchp_ctrl_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_ping_send : 1; - uint32_t interchip_ping_detect_clear : 1; - uint32_t interchip_ping_mode : 1; - uint32_t pmcic2_reserved3 : 1; - uint32_t pmcic2_reserved4 : 1; - uint32_t pmcic2_reserved5_7 : 3; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - uint32_t pmcic2_reserved5_7 : 3; - uint32_t pmcic2_reserved4 : 1; - uint32_t pmcic2_reserved3 : 1; - uint32_t interchip_ping_mode : 1; - uint32_t interchip_ping_detect_clear : 1; - uint32_t interchip_ping_send : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_ctrl_reg2_t; - - - -typedef union pmc_intchp_ctrl_reg4 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_ecc_gen_en : 1; - uint32_t interchip_ecc_check_en : 1; - uint32_t interchip_msg_rcv_overflow_check_en : 1; - uint32_t interchip_ecc_ue_block_en : 1; - uint32_t chksw_hw221732 : 1; - uint32_t slave_occ_timeout_forces_safe_mode_disable : 1; - uint32_t pmcic4_reserved6_7 : 2; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - uint32_t pmcic4_reserved6_7 : 2; - uint32_t slave_occ_timeout_forces_safe_mode_disable : 1; - uint32_t chksw_hw221732 : 1; - uint32_t interchip_ecc_ue_block_en : 1; - uint32_t interchip_msg_rcv_overflow_check_en : 1; - uint32_t interchip_ecc_check_en : 1; - uint32_t interchip_ecc_gen_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_ctrl_reg4_t; - - - -typedef union pmc_intchp_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_ga_ongoing : 1; - uint32_t interchip_ecc_ue : 1; - uint32_t interchip_ecc_ce : 1; - uint32_t interchip_ping_detected : 1; - uint32_t interchip_ping_ack_detected : 1; - uint32_t interchip_msg_send_ongoing : 1; - uint32_t interchip_msg_recv_detected : 1; - uint32_t interchip_fsm_err : 1; - uint32_t interchip_ping_detect_count : 8; - uint32_t interchip_slave_error_code : 4; - uint32_t interchip_msg_snd_overflow_detected : 1; - uint32_t interchip_msg_rcv_overflow_detected : 1; - uint32_t interchip_ecc_ue_err : 1; - uint32_t _reserved0 : 9; -#else - uint32_t _reserved0 : 9; - uint32_t interchip_ecc_ue_err : 1; - uint32_t interchip_msg_rcv_overflow_detected : 1; - uint32_t interchip_msg_snd_overflow_detected : 1; - uint32_t interchip_slave_error_code : 4; - uint32_t interchip_ping_detect_count : 8; - uint32_t interchip_fsm_err : 1; - uint32_t interchip_msg_recv_detected : 1; - uint32_t interchip_msg_send_ongoing : 1; - uint32_t interchip_ping_ack_detected : 1; - uint32_t interchip_ping_detected : 1; - uint32_t interchip_ecc_ce : 1; - uint32_t interchip_ecc_ue : 1; - uint32_t interchip_ga_ongoing : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_status_reg_t; - - - -typedef union pmc_intchp_command_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_reset_if : 1; - uint32_t interchip_halt_msg_fsm : 1; - uint32_t interchip_clear_sticky_bits : 1; - uint32_t _reserved0 : 29; -#else - uint32_t _reserved0 : 29; - uint32_t interchip_clear_sticky_bits : 1; - uint32_t interchip_halt_msg_fsm : 1; - uint32_t interchip_reset_if : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_command_reg_t; - - - -typedef union pmc_intchp_msg_wdata { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_msg_wdata : 32; -#else - uint32_t interchip_msg_wdata : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_msg_wdata_t; - - - -typedef union pmc_intchp_msg_rdata { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t interchip_msg_rdata : 32; -#else - uint32_t interchip_msg_rdata : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_msg_rdata_t; - - - -typedef union pmc_intchp_pstate_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pstate_interchip : 8; - uint32_t _reserved0 : 24; -#else - uint32_t _reserved0 : 24; - int32_t pstate_interchip : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_pstate_reg_t; - - - -typedef union pmc_intchp_globack_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t gaack_interchip : 1; - int32_t gaack_interchip_pstate : 8; - uint32_t _reserved0 : 23; -#else - uint32_t _reserved0 : 23; - int32_t gaack_interchip_pstate : 8; - uint32_t gaack_interchip : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_intchp_globack_reg_t; - - - -typedef union pmc_fsmstate_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t mis_fsm_state : 3; - uint32_t mps_fsm_state : 5; - uint32_t svs_fsm_state : 4; - uint32_t o2s_fsm_state : 4; - uint32_t m2p_fsm_state : 4; - uint32_t o2p_fsm_state : 4; - uint32_t icp_msg_fsm_state : 5; - uint32_t _reserved0 : 3; -#else - uint32_t _reserved0 : 3; - uint32_t icp_msg_fsm_state : 5; - uint32_t o2p_fsm_state : 4; - uint32_t m2p_fsm_state : 4; - uint32_t o2s_fsm_state : 4; - uint32_t svs_fsm_state : 4; - uint32_t mps_fsm_state : 5; - uint32_t mis_fsm_state : 3; -#endif // _BIG_ENDIAN - } fields; -} pmc_fsmstate_status_reg_t; - - - -typedef union pmc_trace_mode_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmc_trace_mode : 4; - uint32_t trace_sel_data : 2; - uint32_t _reserved0 : 26; -#else - uint32_t _reserved0 : 26; - uint32_t trace_sel_data : 2; - uint32_t pmc_trace_mode : 4; -#endif // _BIG_ENDIAN - } fields; -} pmc_trace_mode_reg_t; - - - -typedef union pmc_spiv_ctrl_reg0a { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_frame_size : 6; - uint32_t spivid_out_count1 : 6; - uint32_t spivid_in_delay1 : 6; - uint32_t spivid_in_count1 : 6; - uint32_t _reserved0 : 8; -#else - uint32_t _reserved0 : 8; - uint32_t spivid_in_count1 : 6; - uint32_t spivid_in_delay1 : 6; - uint32_t spivid_out_count1 : 6; - uint32_t spivid_frame_size : 6; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg0a_t; - - - -typedef union pmc_spiv_ctrl_reg0b { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_out_count2 : 6; - uint32_t spivid_in_delay2 : 6; - uint32_t spivid_in_count2 : 6; - uint32_t _reserved0 : 14; -#else - uint32_t _reserved0 : 14; - uint32_t spivid_in_count2 : 6; - uint32_t spivid_in_delay2 : 6; - uint32_t spivid_out_count2 : 6; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg0b_t; - - - -typedef union pmc_spiv_ctrl_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_fsm_enable : 1; - uint32_t pmcscr1_reserved_1 : 1; - uint32_t spivid_cpol : 1; - uint32_t spivid_cpha : 1; - uint32_t spivid_clock_divider : 10; - uint32_t pmcscr1_reserved_2 : 4; - uint32_t spivid_port_enable : 3; - uint32_t _reserved0 : 11; -#else - uint32_t _reserved0 : 11; - uint32_t spivid_port_enable : 3; - uint32_t pmcscr1_reserved_2 : 4; - uint32_t spivid_clock_divider : 10; - uint32_t spivid_cpha : 1; - uint32_t spivid_cpol : 1; - uint32_t pmcscr1_reserved_1 : 1; - uint32_t spivid_fsm_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg1_t; - - - -typedef union pmc_spiv_ctrl_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_inter_frame_delay_write_status : 17; - uint32_t _reserved0 : 15; -#else - uint32_t _reserved0 : 15; - uint32_t spivid_inter_frame_delay_write_status : 17; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg2_t; - - - -typedef union pmc_spiv_ctrl_reg3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_inter_retry_delay : 17; - uint32_t pmc_100ns_pls_range : 6; - uint32_t _reserved0 : 9; -#else - uint32_t _reserved0 : 9; - uint32_t pmc_100ns_pls_range : 6; - uint32_t spivid_inter_retry_delay : 17; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg3_t; - - - -typedef union pmc_spiv_ctrl_reg4 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_crc_gen_en : 1; - uint32_t spivid_crc_check_en : 1; - uint32_t spivid_majority_vote_en : 1; - uint32_t spivid_max_retries : 5; - uint32_t spivid_crc_polynomial_enables : 8; - uint32_t spivid_crc_const_gen_enable : 1; - uint32_t spivid_crc_const_check_enable : 1; - uint32_t spivid_frame_sync_wrong_enable : 1; - uint32_t _reserved0 : 13; -#else - uint32_t _reserved0 : 13; - uint32_t spivid_frame_sync_wrong_enable : 1; - uint32_t spivid_crc_const_check_enable : 1; - uint32_t spivid_crc_const_gen_enable : 1; - uint32_t spivid_crc_polynomial_enables : 8; - uint32_t spivid_max_retries : 5; - uint32_t spivid_majority_vote_en : 1; - uint32_t spivid_crc_check_en : 1; - uint32_t spivid_crc_gen_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_ctrl_reg4_t; - - - -typedef union pmc_spiv_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_ongoing : 1; - uint32_t spivid_crc_error0 : 1; - uint32_t spivid_crc_error1 : 1; - uint32_t spivid_crc_error2 : 1; - uint32_t spivid_retry_timeout : 1; - uint32_t pmcssr_reserved_1 : 2; - uint32_t spivid_fsm_err : 1; - uint32_t spivid_majority_detected_a_minority0 : 1; - uint32_t spivid_majority_detected_a_minority1 : 1; - uint32_t spivid_majority_detected_a_minority2 : 1; - uint32_t spivid_majority_nr_of_minorities0 : 4; - uint32_t spivid_majority_nr_of_minorities1 : 4; - uint32_t spivid_majority_nr_of_minorities2 : 4; - uint32_t _reserved0 : 9; -#else - uint32_t _reserved0 : 9; - uint32_t spivid_majority_nr_of_minorities2 : 4; - uint32_t spivid_majority_nr_of_minorities1 : 4; - uint32_t spivid_majority_nr_of_minorities0 : 4; - uint32_t spivid_majority_detected_a_minority2 : 1; - uint32_t spivid_majority_detected_a_minority1 : 1; - uint32_t spivid_majority_detected_a_minority0 : 1; - uint32_t spivid_fsm_err : 1; - uint32_t pmcssr_reserved_1 : 2; - uint32_t spivid_retry_timeout : 1; - uint32_t spivid_crc_error2 : 1; - uint32_t spivid_crc_error1 : 1; - uint32_t spivid_crc_error0 : 1; - uint32_t spivid_ongoing : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_status_reg_t; - - - -typedef union pmc_spiv_command_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t spivid_halt_fsm : 1; - uint32_t _reserved0 : 31; -#else - uint32_t _reserved0 : 31; - uint32_t spivid_halt_fsm : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_spiv_command_reg_t; - - - -typedef union pmc_o2s_ctrl_reg0a { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_frame_size : 6; - uint32_t o2s_out_count1 : 6; - uint32_t o2s_in_delay1 : 6; - uint32_t o2s_in_count1 : 6; - uint32_t _reserved0 : 8; -#else - uint32_t _reserved0 : 8; - uint32_t o2s_in_count1 : 6; - uint32_t o2s_in_delay1 : 6; - uint32_t o2s_out_count1 : 6; - uint32_t o2s_frame_size : 6; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_ctrl_reg0a_t; - - - -typedef union pmc_o2s_ctrl_reg0b { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_out_count2 : 6; - uint32_t o2s_in_delay2 : 6; - uint32_t o2s_in_count2 : 6; - uint32_t _reserved0 : 14; -#else - uint32_t _reserved0 : 14; - uint32_t o2s_in_count2 : 6; - uint32_t o2s_in_delay2 : 6; - uint32_t o2s_out_count2 : 6; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_ctrl_reg0b_t; - - - -typedef union pmc_o2s_ctrl_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_bridge_enable : 1; - uint32_t pmcocr1_reserved_1 : 1; - uint32_t o2s_cpol : 1; - uint32_t o2s_cpha : 1; - uint32_t o2s_clock_divider : 10; - uint32_t pmcocr1_reserved_2 : 3; - uint32_t o2s_nr_of_frames : 1; - uint32_t o2s_port_enable : 3; - uint32_t _reserved0 : 11; -#else - uint32_t _reserved0 : 11; - uint32_t o2s_port_enable : 3; - uint32_t o2s_nr_of_frames : 1; - uint32_t pmcocr1_reserved_2 : 3; - uint32_t o2s_clock_divider : 10; - uint32_t o2s_cpha : 1; - uint32_t o2s_cpol : 1; - uint32_t pmcocr1_reserved_1 : 1; - uint32_t o2s_bridge_enable : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_ctrl_reg1_t; - - - -typedef union pmc_o2s_ctrl_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_inter_frame_delay : 17; - uint32_t _reserved0 : 15; -#else - uint32_t _reserved0 : 15; - uint32_t o2s_inter_frame_delay : 17; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_ctrl_reg2_t; - - - -typedef union pmc_o2s_ctrl_reg4 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_crc_gen_en : 1; - uint32_t o2s_crc_check_en : 1; - uint32_t o2s_majority_vote_en : 1; - uint32_t o2s_max_retries : 5; - uint32_t pmcocr4_reserved8_15 : 8; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t pmcocr4_reserved8_15 : 8; - uint32_t o2s_max_retries : 5; - uint32_t o2s_majority_vote_en : 1; - uint32_t o2s_crc_check_en : 1; - uint32_t o2s_crc_gen_en : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_ctrl_reg4_t; - - - -typedef union pmc_o2s_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_ongoing : 1; - uint32_t o2s_crc_error0 : 1; - uint32_t o2s_crc_error1 : 1; - uint32_t o2s_crc_error2 : 1; - uint32_t o2s_retry_timeout : 1; - uint32_t o2s_write_while_bridge_busy_err : 1; - uint32_t pmcosr_reserved_6 : 1; - uint32_t o2s_fsm_err : 1; - uint32_t o2s_majority_detected_a_minority0 : 1; - uint32_t o2s_majority_detected_a_minority1 : 1; - uint32_t o2s_majority_detected_a_minority2 : 1; - uint32_t o2s_majority_nr_of_minorities0 : 4; - uint32_t o2s_majority_nr_of_minorities1 : 4; - uint32_t o2s_majority_nr_of_minorities2 : 4; - uint32_t _reserved0 : 9; -#else - uint32_t _reserved0 : 9; - uint32_t o2s_majority_nr_of_minorities2 : 4; - uint32_t o2s_majority_nr_of_minorities1 : 4; - uint32_t o2s_majority_nr_of_minorities0 : 4; - uint32_t o2s_majority_detected_a_minority2 : 1; - uint32_t o2s_majority_detected_a_minority1 : 1; - uint32_t o2s_majority_detected_a_minority0 : 1; - uint32_t o2s_fsm_err : 1; - uint32_t pmcosr_reserved_6 : 1; - uint32_t o2s_write_while_bridge_busy_err : 1; - uint32_t o2s_retry_timeout : 1; - uint32_t o2s_crc_error2 : 1; - uint32_t o2s_crc_error1 : 1; - uint32_t o2s_crc_error0 : 1; - uint32_t o2s_ongoing : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_status_reg_t; - - - -typedef union pmc_o2s_command_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_halt_retries : 1; - uint32_t o2s_clear_sticky_bits : 1; - uint32_t _reserved0 : 30; -#else - uint32_t _reserved0 : 30; - uint32_t o2s_clear_sticky_bits : 1; - uint32_t o2s_halt_retries : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_command_reg_t; - - - -typedef union pmc_o2s_wdata_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_wdata : 32; -#else - uint32_t o2s_wdata : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_wdata_reg_t; - - - -typedef union pmc_o2s_rdata_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2s_rdata : 32; -#else - uint32_t o2s_rdata : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2s_rdata_reg_t; - - - -typedef union pmc_o2p_addr_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_write_plus_read : 1; - uint32_t o2p_mc : 1; - uint32_t o2p_slave_addr : 6; - uint32_t o2p_read_not_write : 1; - uint32_t reserved_bit_pmco2par2 : 3; - uint32_t o2p_pcb_port : 4; - uint32_t o2p_pcb_reg_addr : 16; -#else - uint32_t o2p_pcb_reg_addr : 16; - uint32_t o2p_pcb_port : 4; - uint32_t reserved_bit_pmco2par2 : 3; - uint32_t o2p_read_not_write : 1; - uint32_t o2p_slave_addr : 6; - uint32_t o2p_mc : 1; - uint32_t o2p_write_plus_read : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_addr_reg_t; - - - -typedef union pmc_o2p_ctrl_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_ongoing : 1; - uint32_t o2p_scresp : 3; - uint32_t o2p_write_while_bridge_busy_err : 1; - uint32_t o2p_fsm_err : 1; - uint32_t o2p_abort : 1; - uint32_t o2p_parity_error : 1; - uint32_t o2p_clear_sticky_bits : 1; - uint32_t _reserved0 : 23; -#else - uint32_t _reserved0 : 23; - uint32_t o2p_clear_sticky_bits : 1; - uint32_t o2p_parity_error : 1; - uint32_t o2p_abort : 1; - uint32_t o2p_fsm_err : 1; - uint32_t o2p_write_while_bridge_busy_err : 1; - uint32_t o2p_scresp : 3; - uint32_t o2p_ongoing : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_ctrl_status_reg_t; - - - -typedef union pmc_o2p_send_data_hi_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_send_data_hi : 32; -#else - uint32_t o2p_send_data_hi : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_send_data_hi_reg_t; - - - -typedef union pmc_o2p_send_data_lo_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_send_data_lo : 32; -#else - uint32_t o2p_send_data_lo : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_send_data_lo_reg_t; - - - -typedef union pmc_o2p_recv_data_hi_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_receive_data_hi : 32; -#else - uint32_t o2p_receive_data_hi : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_recv_data_hi_reg_t; - - - -typedef union pmc_o2p_recv_data_lo_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t o2p_receive_data_lo : 32; -#else - uint32_t o2p_receive_data_lo : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_o2p_recv_data_lo_reg_t; - - - -typedef union pmc_occ_heartbeat_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmc_occ_heartbeat_time : 16; - uint32_t pmc_occ_heartbeat_en : 1; - uint32_t _reserved0 : 15; -#else - uint32_t _reserved0 : 15; - uint32_t pmc_occ_heartbeat_en : 1; - uint32_t pmc_occ_heartbeat_time : 16; -#endif // _BIG_ENDIAN - } fields; -} pmc_occ_heartbeat_reg_t; - - - -typedef union pmc_error_int_mask_hi_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmc_error_int_mask_hi : 32; -#else - uint32_t pmc_error_int_mask_hi : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_error_int_mask_hi_reg_t; - - - -typedef union pmc_error_int_mask_lo_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmc_error_int_mask_lo : 32; -#else - uint32_t pmc_error_int_mask_lo : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_error_int_mask_lo_reg_t; - - - -typedef union pmc_idle_suspend_mask_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmc_idle_suspend_mask : 16; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t pmc_idle_suspend_mask : 16; -#endif // _BIG_ENDIAN - } fields; -} pmc_idle_suspend_mask_reg_t; - - - -typedef union pmc_pend_idle_req_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t idle_pending_0 : 1; - uint32_t idle_op_0 : 2; - uint32_t idle_type_0 : 1; - uint32_t idle_scope_0 : 1; - uint32_t assist_mode_0 : 1; - uint32_t reserved_pirr_0 : 2; - uint32_t idle_pending_1 : 1; - uint32_t idle_op_1 : 2; - uint32_t idle_type_1 : 1; - uint32_t idle_scope_1 : 1; - uint32_t assist_mode_1 : 1; - uint32_t reserved_pirr_1 : 2; - uint32_t idle_pending_2 : 1; - uint32_t idle_op_2 : 2; - uint32_t idle_type_2 : 1; - uint32_t idle_scope_2 : 1; - uint32_t assist_mode_2 : 1; - uint32_t reserved_pirr_2 : 2; - uint32_t idle_pending_3 : 1; - uint32_t idle_op_3 : 2; - uint32_t idle_type_3 : 1; - uint32_t idle_scope_3 : 1; - uint32_t assist_mode_3 : 1; - uint32_t reserved_pirr_3 : 2; -#else - uint32_t reserved_pirr_3 : 2; - uint32_t assist_mode_3 : 1; - uint32_t idle_scope_3 : 1; - uint32_t idle_type_3 : 1; - uint32_t idle_op_3 : 2; - uint32_t idle_pending_3 : 1; - uint32_t reserved_pirr_2 : 2; - uint32_t assist_mode_2 : 1; - uint32_t idle_scope_2 : 1; - uint32_t idle_type_2 : 1; - uint32_t idle_op_2 : 2; - uint32_t idle_pending_2 : 1; - uint32_t reserved_pirr_1 : 2; - uint32_t assist_mode_1 : 1; - uint32_t idle_scope_1 : 1; - uint32_t idle_type_1 : 1; - uint32_t idle_op_1 : 2; - uint32_t idle_pending_1 : 1; - uint32_t reserved_pirr_0 : 2; - uint32_t assist_mode_0 : 1; - uint32_t idle_scope_0 : 1; - uint32_t idle_type_0 : 1; - uint32_t idle_op_0 : 2; - uint32_t idle_pending_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pend_idle_req_reg0_t; - - - -typedef union pmc_pend_idle_req_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t idle_pending_4 : 1; - uint32_t idle_op_4 : 2; - uint32_t idle_type_4 : 1; - uint32_t idle_scope_4 : 1; - uint32_t assist_mode_4 : 1; - uint32_t reserved_pirr_4 : 2; - uint32_t idle_pending_5 : 1; - uint32_t idle_op_5 : 2; - uint32_t idle_type_5 : 1; - uint32_t idle_scope_5 : 1; - uint32_t assist_mode_5 : 1; - uint32_t reserved_pirr_5 : 2; - uint32_t idle_pending_6 : 1; - uint32_t idle_op_6 : 2; - uint32_t idle_type_6 : 1; - uint32_t idle_scope_6 : 1; - uint32_t assist_mode_6 : 1; - uint32_t reserved_pirr_6 : 2; - uint32_t idle_pending_7 : 1; - uint32_t idle_op_7 : 2; - uint32_t idle_type_7 : 1; - uint32_t idle_scope_7 : 1; - uint32_t assist_mode_7 : 1; - uint32_t reserved_pirr_7 : 2; -#else - uint32_t reserved_pirr_7 : 2; - uint32_t assist_mode_7 : 1; - uint32_t idle_scope_7 : 1; - uint32_t idle_type_7 : 1; - uint32_t idle_op_7 : 2; - uint32_t idle_pending_7 : 1; - uint32_t reserved_pirr_6 : 2; - uint32_t assist_mode_6 : 1; - uint32_t idle_scope_6 : 1; - uint32_t idle_type_6 : 1; - uint32_t idle_op_6 : 2; - uint32_t idle_pending_6 : 1; - uint32_t reserved_pirr_5 : 2; - uint32_t assist_mode_5 : 1; - uint32_t idle_scope_5 : 1; - uint32_t idle_type_5 : 1; - uint32_t idle_op_5 : 2; - uint32_t idle_pending_5 : 1; - uint32_t reserved_pirr_4 : 2; - uint32_t assist_mode_4 : 1; - uint32_t idle_scope_4 : 1; - uint32_t idle_type_4 : 1; - uint32_t idle_op_4 : 2; - uint32_t idle_pending_4 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pend_idle_req_reg1_t; - - - -typedef union pmc_pend_idle_req_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t idle_pending_8 : 1; - uint32_t idle_op_8 : 2; - uint32_t idle_type_8 : 1; - uint32_t idle_scope_8 : 1; - uint32_t assist_mode_8 : 1; - uint32_t reserved_pirr_8 : 2; - uint32_t idle_pending_9 : 1; - uint32_t idle_op_9 : 2; - uint32_t idle_type_9 : 1; - uint32_t idle_scope_9 : 1; - uint32_t assist_mode_9 : 1; - uint32_t reserved_pirr_9 : 2; - uint32_t idle_pending_10 : 1; - uint32_t idle_op_10 : 2; - uint32_t idle_type_10 : 1; - uint32_t idle_scope_10 : 1; - uint32_t assist_mode_10 : 1; - uint32_t reserved_pirr_10 : 2; - uint32_t idle_pending_11 : 1; - uint32_t idle_op_11 : 2; - uint32_t idle_type_11 : 1; - uint32_t idle_scope_11 : 1; - uint32_t assist_mode_11 : 1; - uint32_t reserved_pirr_11 : 2; -#else - uint32_t reserved_pirr_11 : 2; - uint32_t assist_mode_11 : 1; - uint32_t idle_scope_11 : 1; - uint32_t idle_type_11 : 1; - uint32_t idle_op_11 : 2; - uint32_t idle_pending_11 : 1; - uint32_t reserved_pirr_10 : 2; - uint32_t assist_mode_10 : 1; - uint32_t idle_scope_10 : 1; - uint32_t idle_type_10 : 1; - uint32_t idle_op_10 : 2; - uint32_t idle_pending_10 : 1; - uint32_t reserved_pirr_9 : 2; - uint32_t assist_mode_9 : 1; - uint32_t idle_scope_9 : 1; - uint32_t idle_type_9 : 1; - uint32_t idle_op_9 : 2; - uint32_t idle_pending_9 : 1; - uint32_t reserved_pirr_8 : 2; - uint32_t assist_mode_8 : 1; - uint32_t idle_scope_8 : 1; - uint32_t idle_type_8 : 1; - uint32_t idle_op_8 : 2; - uint32_t idle_pending_8 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pend_idle_req_reg2_t; - - - -typedef union pmc_pend_idle_req_reg3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t idle_pending_12 : 1; - uint32_t idle_op_12 : 2; - uint32_t idle_type_12 : 1; - uint32_t idle_scope_12 : 1; - uint32_t assist_mode_12 : 1; - uint32_t reserved_pirr_12 : 2; - uint32_t idle_pending_13 : 1; - uint32_t idle_op_13 : 2; - uint32_t idle_type_13 : 1; - uint32_t idle_scope_13 : 1; - uint32_t assist_mode_13 : 1; - uint32_t reserved_pirr_13 : 2; - uint32_t idle_pending_14 : 1; - uint32_t idle_op_14 : 2; - uint32_t idle_type_14 : 1; - uint32_t idle_scope_14 : 1; - uint32_t assist_mode_14 : 1; - uint32_t reserved_pirr_14 : 2; - uint32_t idle_pending_15 : 1; - uint32_t idle_op_15 : 2; - uint32_t idle_type_15 : 1; - uint32_t idle_scope_15 : 1; - uint32_t assist_mode_15 : 1; - uint32_t reserved_pirr_15 : 2; -#else - uint32_t reserved_pirr_15 : 2; - uint32_t assist_mode_15 : 1; - uint32_t idle_scope_15 : 1; - uint32_t idle_type_15 : 1; - uint32_t idle_op_15 : 2; - uint32_t idle_pending_15 : 1; - uint32_t reserved_pirr_14 : 2; - uint32_t assist_mode_14 : 1; - uint32_t idle_scope_14 : 1; - uint32_t idle_type_14 : 1; - uint32_t idle_op_14 : 2; - uint32_t idle_pending_14 : 1; - uint32_t reserved_pirr_13 : 2; - uint32_t assist_mode_13 : 1; - uint32_t idle_scope_13 : 1; - uint32_t idle_type_13 : 1; - uint32_t idle_op_13 : 2; - uint32_t idle_pending_13 : 1; - uint32_t reserved_pirr_12 : 2; - uint32_t assist_mode_12 : 1; - uint32_t idle_scope_12 : 1; - uint32_t idle_type_12 : 1; - uint32_t idle_op_12 : 2; - uint32_t idle_pending_12 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pend_idle_req_reg3_t; - - - -typedef union pmc_sleep_int_req_vec_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t fastsleepentry_int_req_vec : 32; -#else - uint32_t fastsleepentry_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_sleep_int_req_vec_reg0_t; - - - -typedef union pmc_sleep_int_req_vec_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deepsleepentry_int_req_vec : 32; -#else - uint32_t deepsleepentry_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_sleep_int_req_vec_reg1_t; - - - -typedef union pmc_sleep_int_req_vec_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t fastsleepexit_int_req_vec : 32; -#else - uint32_t fastsleepexit_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_sleep_int_req_vec_reg2_t; - - - -typedef union pmc_sleep_int_req_vec_reg3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deepsleepexit_int_req_vec : 32; -#else - uint32_t deepsleepexit_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_sleep_int_req_vec_reg3_t; - - - -typedef union pmc_winkle_int_req_vec_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t fastwinkleentry_int_req_vec : 32; -#else - uint32_t fastwinkleentry_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_winkle_int_req_vec_reg0_t; - - - -typedef union pmc_winkle_int_req_vec_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deepwinkleentry_int_req_vec : 32; -#else - uint32_t deepwinkleentry_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_winkle_int_req_vec_reg1_t; - - - -typedef union pmc_winkle_int_req_vec_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t fastwinkleexit_int_req_vec : 32; -#else - uint32_t fastwinkleexit_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_winkle_int_req_vec_reg2_t; - - - -typedef union pmc_winkle_int_req_vec_reg3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deepwinkleexit_int_req_vec : 32; -#else - uint32_t deepwinkleexit_int_req_vec : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_winkle_int_req_vec_reg3_t; - - - -typedef union pmc_nap_int_req_vec_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t napentry_int_req_vec : 16; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t napentry_int_req_vec : 16; -#endif // _BIG_ENDIAN - } fields; -} pmc_nap_int_req_vec_reg0_t; - - - -typedef union pmc_nap_int_req_vec_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t napexit_int_req_vec : 25; - uint32_t _reserved0 : 7; -#else - uint32_t _reserved0 : 7; - uint32_t napexit_int_req_vec : 25; -#endif // _BIG_ENDIAN - } fields; -} pmc_nap_int_req_vec_reg1_t; - - - -typedef union pmc_pore_req_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porrr_reserved0 : 8; - uint32_t porrr_start_vector : 4; - uint32_t porrr_reserved1 : 8; - uint32_t porrr_pore_busy : 1; - uint32_t porrr_pore_suspended : 1; - uint32_t porrr_porrtc_busy : 1; - uint32_t _reserved0 : 9; -#else - uint32_t _reserved0 : 9; - uint32_t porrr_porrtc_busy : 1; - uint32_t porrr_pore_suspended : 1; - uint32_t porrr_pore_busy : 1; - uint32_t porrr_reserved1 : 8; - uint32_t porrr_start_vector : 4; - uint32_t porrr_reserved0 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_req_reg0_t; - - - -typedef union pmc_pore_req_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porrr_chiplet_enable_0 : 1; - uint32_t porrr_chiplet_enable_1 : 1; - uint32_t porrr_chiplet_enable_2 : 1; - uint32_t porrr_chiplet_enable_3 : 1; - uint32_t porrr_chiplet_enable_4 : 1; - uint32_t porrr_chiplet_enable_5 : 1; - uint32_t porrr_chiplet_enable_6 : 1; - uint32_t porrr_chiplet_enable_7 : 1; - uint32_t porrr_chiplet_enable_8 : 1; - uint32_t porrr_chiplet_enable_9 : 1; - uint32_t porrr_chiplet_enable_10 : 1; - uint32_t porrr_chiplet_enable_11 : 1; - uint32_t porrr_chiplet_enable_12 : 1; - uint32_t porrr_chiplet_enable_13 : 1; - uint32_t porrr_chiplet_enable_14 : 1; - uint32_t porrr_chiplet_enable_15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t porrr_chiplet_enable_15 : 1; - uint32_t porrr_chiplet_enable_14 : 1; - uint32_t porrr_chiplet_enable_13 : 1; - uint32_t porrr_chiplet_enable_12 : 1; - uint32_t porrr_chiplet_enable_11 : 1; - uint32_t porrr_chiplet_enable_10 : 1; - uint32_t porrr_chiplet_enable_9 : 1; - uint32_t porrr_chiplet_enable_8 : 1; - uint32_t porrr_chiplet_enable_7 : 1; - uint32_t porrr_chiplet_enable_6 : 1; - uint32_t porrr_chiplet_enable_5 : 1; - uint32_t porrr_chiplet_enable_4 : 1; - uint32_t porrr_chiplet_enable_3 : 1; - uint32_t porrr_chiplet_enable_2 : 1; - uint32_t porrr_chiplet_enable_1 : 1; - uint32_t porrr_chiplet_enable_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_req_reg1_t; - - - -typedef union pmc_pore_req_stat_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porrs_reserved0 : 8; - uint32_t porrs_start_vector : 4; - uint32_t pore_rc : 8; - uint32_t porrs_reserved1 : 1; - uint32_t porrs_recovery_write : 1; - uint32_t _reserved0 : 10; -#else - uint32_t _reserved0 : 10; - uint32_t porrs_recovery_write : 1; - uint32_t porrs_reserved1 : 1; - uint32_t pore_rc : 8; - uint32_t porrs_start_vector : 4; - uint32_t porrs_reserved0 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_req_stat_reg_t; - - - -typedef union pmc_pore_req_tout_th_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porrtt_timeout_threshold : 8; - uint32_t porrtc_no_predivide : 1; - uint32_t _reserved0 : 23; -#else - uint32_t _reserved0 : 23; - uint32_t porrtc_no_predivide : 1; - uint32_t porrtt_timeout_threshold : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_req_tout_th_reg_t; - - - -typedef union pmc_deep_exit_mask_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t chiplet_deep_exit_mask0 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_deep_exit_mask_reg_t; - - - -typedef union pmc_deep_exit_mask_reg_and { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t chiplet_deep_exit_mask0 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_deep_exit_mask_reg_and_t; - - - -typedef union pmc_deep_exit_mask_reg_or { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t chiplet_deep_exit_mask0 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t chiplet_deep_exit_mask15 : 1; - uint32_t chiplet_deep_exit_mask14 : 1; - uint32_t chiplet_deep_exit_mask13 : 1; - uint32_t chiplet_deep_exit_mask12 : 1; - uint32_t chiplet_deep_exit_mask11 : 1; - uint32_t chiplet_deep_exit_mask10 : 1; - uint32_t chiplet_deep_exit_mask9 : 1; - uint32_t chiplet_deep_exit_mask8 : 1; - uint32_t chiplet_deep_exit_mask7 : 1; - uint32_t chiplet_deep_exit_mask6 : 1; - uint32_t chiplet_deep_exit_mask5 : 1; - uint32_t chiplet_deep_exit_mask4 : 1; - uint32_t chiplet_deep_exit_mask3 : 1; - uint32_t chiplet_deep_exit_mask2 : 1; - uint32_t chiplet_deep_exit_mask1 : 1; - uint32_t chiplet_deep_exit_mask0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_deep_exit_mask_reg_or_t; - - - -typedef union pmc_core_pstate_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pstate_core0 : 8; - int32_t pstate_core1 : 8; - int32_t pstate_core2 : 8; - int32_t pstate_core3 : 8; -#else - int32_t pstate_core3 : 8; - int32_t pstate_core2 : 8; - int32_t pstate_core1 : 8; - int32_t pstate_core0 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_pstate_reg0_t; - - - -typedef union pmc_core_pstate_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pstate_core4 : 8; - int32_t pstate_core5 : 8; - int32_t pstate_core6 : 8; - int32_t pstate_core7 : 8; -#else - int32_t pstate_core7 : 8; - int32_t pstate_core6 : 8; - int32_t pstate_core5 : 8; - int32_t pstate_core4 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_pstate_reg1_t; - - - -typedef union pmc_core_pstate_reg2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pstate_core8 : 8; - int32_t pstate_core9 : 8; - int32_t pstate_core10 : 8; - int32_t pstate_core11 : 8; -#else - int32_t pstate_core11 : 8; - int32_t pstate_core10 : 8; - int32_t pstate_core9 : 8; - int32_t pstate_core8 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_pstate_reg2_t; - - - -typedef union pmc_core_pstate_reg3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - int32_t pstate_core12 : 8; - int32_t pstate_core13 : 8; - int32_t pstate_core14 : 8; - int32_t pstate_core15 : 8; -#else - int32_t pstate_core15 : 8; - int32_t pstate_core14 : 8; - int32_t pstate_core13 : 8; - int32_t pstate_core12 : 8; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_pstate_reg3_t; - - - -typedef union pmc_core_power_donation_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t power_donation_core0 : 1; - uint32_t power_donation_core1 : 1; - uint32_t power_donation_core2 : 1; - uint32_t power_donation_core3 : 1; - uint32_t power_donation_core4 : 1; - uint32_t power_donation_core5 : 1; - uint32_t power_donation_core6 : 1; - uint32_t power_donation_core7 : 1; - uint32_t power_donation_core8 : 1; - uint32_t power_donation_core9 : 1; - uint32_t power_donation_core10 : 1; - uint32_t power_donation_core11 : 1; - uint32_t power_donation_core12 : 1; - uint32_t power_donation_core13 : 1; - uint32_t power_donation_core14 : 1; - uint32_t power_donation_core15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t power_donation_core15 : 1; - uint32_t power_donation_core14 : 1; - uint32_t power_donation_core13 : 1; - uint32_t power_donation_core12 : 1; - uint32_t power_donation_core11 : 1; - uint32_t power_donation_core10 : 1; - uint32_t power_donation_core9 : 1; - uint32_t power_donation_core8 : 1; - uint32_t power_donation_core7 : 1; - uint32_t power_donation_core6 : 1; - uint32_t power_donation_core5 : 1; - uint32_t power_donation_core4 : 1; - uint32_t power_donation_core3 : 1; - uint32_t power_donation_core2 : 1; - uint32_t power_donation_core1 : 1; - uint32_t power_donation_core0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_core_power_donation_reg_t; - - - -typedef union pmc_pmax_sync_collection_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmax_sync0 : 1; - uint32_t pmax_sync1 : 1; - uint32_t pmax_sync2 : 1; - uint32_t pmax_sync3 : 1; - uint32_t pmax_sync4 : 1; - uint32_t pmax_sync5 : 1; - uint32_t pmax_sync6 : 1; - uint32_t pmax_sync7 : 1; - uint32_t pmax_sync8 : 1; - uint32_t pmax_sync9 : 1; - uint32_t pmax_sync10 : 1; - uint32_t pmax_sync11 : 1; - uint32_t pmax_sync12 : 1; - uint32_t pmax_sync13 : 1; - uint32_t pmax_sync14 : 1; - uint32_t pmax_sync15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t pmax_sync15 : 1; - uint32_t pmax_sync14 : 1; - uint32_t pmax_sync13 : 1; - uint32_t pmax_sync12 : 1; - uint32_t pmax_sync11 : 1; - uint32_t pmax_sync10 : 1; - uint32_t pmax_sync9 : 1; - uint32_t pmax_sync8 : 1; - uint32_t pmax_sync7 : 1; - uint32_t pmax_sync6 : 1; - uint32_t pmax_sync5 : 1; - uint32_t pmax_sync4 : 1; - uint32_t pmax_sync3 : 1; - uint32_t pmax_sync2 : 1; - uint32_t pmax_sync1 : 1; - uint32_t pmax_sync0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pmax_sync_collection_reg_t; - - - -typedef union pmc_pmax_sync_collection_mask_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t pmax_sync_mask0 : 1; - uint32_t pmax_sync_mask1 : 1; - uint32_t pmax_sync_mask2 : 1; - uint32_t pmax_sync_mask3 : 1; - uint32_t pmax_sync_mask4 : 1; - uint32_t pmax_sync_mask5 : 1; - uint32_t pmax_sync_mask6 : 1; - uint32_t pmax_sync_mask7 : 1; - uint32_t pmax_sync_mask8 : 1; - uint32_t pmax_sync_mask9 : 1; - uint32_t pmax_sync_mask10 : 1; - uint32_t pmax_sync_mask11 : 1; - uint32_t pmax_sync_mask12 : 1; - uint32_t pmax_sync_mask13 : 1; - uint32_t pmax_sync_mask14 : 1; - uint32_t pmax_sync_mask15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t pmax_sync_mask15 : 1; - uint32_t pmax_sync_mask14 : 1; - uint32_t pmax_sync_mask13 : 1; - uint32_t pmax_sync_mask12 : 1; - uint32_t pmax_sync_mask11 : 1; - uint32_t pmax_sync_mask10 : 1; - uint32_t pmax_sync_mask9 : 1; - uint32_t pmax_sync_mask8 : 1; - uint32_t pmax_sync_mask7 : 1; - uint32_t pmax_sync_mask6 : 1; - uint32_t pmax_sync_mask5 : 1; - uint32_t pmax_sync_mask4 : 1; - uint32_t pmax_sync_mask3 : 1; - uint32_t pmax_sync_mask2 : 1; - uint32_t pmax_sync_mask1 : 1; - uint32_t pmax_sync_mask0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_pmax_sync_collection_mask_reg_t; - - - -typedef union pmc_gpsa_ack_collection_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t gpsa_ack0 : 1; - uint32_t gpsa_ack1 : 1; - uint32_t gpsa_ack2 : 1; - uint32_t gpsa_ack3 : 1; - uint32_t gpsa_ack4 : 1; - uint32_t gpsa_ack5 : 1; - uint32_t gpsa_ack6 : 1; - uint32_t gpsa_ack7 : 1; - uint32_t gpsa_ack8 : 1; - uint32_t gpsa_ack9 : 1; - uint32_t gpsa_ack10 : 1; - uint32_t gpsa_ack11 : 1; - uint32_t gpsa_ack12 : 1; - uint32_t gpsa_ack13 : 1; - uint32_t gpsa_ack14 : 1; - uint32_t gpsa_ack15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t gpsa_ack15 : 1; - uint32_t gpsa_ack14 : 1; - uint32_t gpsa_ack13 : 1; - uint32_t gpsa_ack12 : 1; - uint32_t gpsa_ack11 : 1; - uint32_t gpsa_ack10 : 1; - uint32_t gpsa_ack9 : 1; - uint32_t gpsa_ack8 : 1; - uint32_t gpsa_ack7 : 1; - uint32_t gpsa_ack6 : 1; - uint32_t gpsa_ack5 : 1; - uint32_t gpsa_ack4 : 1; - uint32_t gpsa_ack3 : 1; - uint32_t gpsa_ack2 : 1; - uint32_t gpsa_ack1 : 1; - uint32_t gpsa_ack0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_gpsa_ack_collection_reg_t; - - - -typedef union pmc_gpsa_ack_collection_mask_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t gpsa_ack_mask0 : 1; - uint32_t gpsa_ack_mask1 : 1; - uint32_t gpsa_ack_mask2 : 1; - uint32_t gpsa_ack_mask3 : 1; - uint32_t gpsa_ack_mask4 : 1; - uint32_t gpsa_ack_mask5 : 1; - uint32_t gpsa_ack_mask6 : 1; - uint32_t gpsa_ack_mask7 : 1; - uint32_t gpsa_ack_mask8 : 1; - uint32_t gpsa_ack_mask9 : 1; - uint32_t gpsa_ack_mask10 : 1; - uint32_t gpsa_ack_mask11 : 1; - uint32_t gpsa_ack_mask12 : 1; - uint32_t gpsa_ack_mask13 : 1; - uint32_t gpsa_ack_mask14 : 1; - uint32_t gpsa_ack_mask15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t gpsa_ack_mask15 : 1; - uint32_t gpsa_ack_mask14 : 1; - uint32_t gpsa_ack_mask13 : 1; - uint32_t gpsa_ack_mask12 : 1; - uint32_t gpsa_ack_mask11 : 1; - uint32_t gpsa_ack_mask10 : 1; - uint32_t gpsa_ack_mask9 : 1; - uint32_t gpsa_ack_mask8 : 1; - uint32_t gpsa_ack_mask7 : 1; - uint32_t gpsa_ack_mask6 : 1; - uint32_t gpsa_ack_mask5 : 1; - uint32_t gpsa_ack_mask4 : 1; - uint32_t gpsa_ack_mask3 : 1; - uint32_t gpsa_ack_mask2 : 1; - uint32_t gpsa_ack_mask1 : 1; - uint32_t gpsa_ack_mask0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_gpsa_ack_collection_mask_reg_t; - - - -typedef union pmc_pore_scratch_reg0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porscr_scratch0 : 32; -#else - uint32_t porscr_scratch0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_scratch_reg0_t; - - - -typedef union pmc_pore_scratch_reg1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t porscr_scratch1 : 32; -#else - uint32_t porscr_scratch1 : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_pore_scratch_reg1_t; - - - -typedef union pmc_deep_idle_exit_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deep_exit_pending_and_masked_0 : 1; - uint32_t deep_exit_pending_and_masked_1 : 1; - uint32_t deep_exit_pending_and_masked_2 : 1; - uint32_t deep_exit_pending_and_masked_3 : 1; - uint32_t deep_exit_pending_and_masked_4 : 1; - uint32_t deep_exit_pending_and_masked_5 : 1; - uint32_t deep_exit_pending_and_masked_6 : 1; - uint32_t deep_exit_pending_and_masked_7 : 1; - uint32_t deep_exit_pending_and_masked_8 : 1; - uint32_t deep_exit_pending_and_masked_9 : 1; - uint32_t deep_exit_pending_and_masked_10 : 1; - uint32_t deep_exit_pending_and_masked_11 : 1; - uint32_t deep_exit_pending_and_masked_12 : 1; - uint32_t deep_exit_pending_and_masked_13 : 1; - uint32_t deep_exit_pending_and_masked_14 : 1; - uint32_t deep_exit_pending_and_masked_15 : 1; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t deep_exit_pending_and_masked_15 : 1; - uint32_t deep_exit_pending_and_masked_14 : 1; - uint32_t deep_exit_pending_and_masked_13 : 1; - uint32_t deep_exit_pending_and_masked_12 : 1; - uint32_t deep_exit_pending_and_masked_11 : 1; - uint32_t deep_exit_pending_and_masked_10 : 1; - uint32_t deep_exit_pending_and_masked_9 : 1; - uint32_t deep_exit_pending_and_masked_8 : 1; - uint32_t deep_exit_pending_and_masked_7 : 1; - uint32_t deep_exit_pending_and_masked_6 : 1; - uint32_t deep_exit_pending_and_masked_5 : 1; - uint32_t deep_exit_pending_and_masked_4 : 1; - uint32_t deep_exit_pending_and_masked_3 : 1; - uint32_t deep_exit_pending_and_masked_2 : 1; - uint32_t deep_exit_pending_and_masked_1 : 1; - uint32_t deep_exit_pending_and_masked_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_deep_idle_exit_reg_t; - - - -typedef union pmc_deep_status_reg { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t deep_idle_state_core0 : 1; - uint32_t deep_idle_state_core1 : 1; - uint32_t deep_idle_state_core2 : 1; - uint32_t deep_idle_state_core3 : 1; - uint32_t deep_idle_state_core4 : 1; - uint32_t deep_idle_state_core5 : 1; - uint32_t deep_idle_state_core6 : 1; - uint32_t deep_idle_state_core7 : 1; - uint32_t deep_idle_state_core8 : 1; - uint32_t deep_idle_state_core9 : 1; - uint32_t deep_idle_state_core10 : 1; - uint32_t deep_idle_state_core11 : 1; - uint32_t deep_idle_state_core12 : 1; - uint32_t deep_idle_state_core13 : 1; - uint32_t deep_idle_state_core14 : 1; - uint32_t deep_idle_state_core15 : 1; - uint32_t winkle_state_core0 : 1; - uint32_t winkle_state_core1 : 1; - uint32_t winkle_state_core2 : 1; - uint32_t winkle_state_core3 : 1; - uint32_t winkle_state_core4 : 1; - uint32_t winkle_state_core5 : 1; - uint32_t winkle_state_core6 : 1; - uint32_t winkle_state_core7 : 1; - uint32_t winkle_state_core8 : 1; - uint32_t winkle_state_core9 : 1; - uint32_t winkle_state_core10 : 1; - uint32_t winkle_state_core11 : 1; - uint32_t winkle_state_core12 : 1; - uint32_t winkle_state_core13 : 1; - uint32_t winkle_state_core14 : 1; - uint32_t winkle_state_core15 : 1; -#else - uint32_t winkle_state_core15 : 1; - uint32_t winkle_state_core14 : 1; - uint32_t winkle_state_core13 : 1; - uint32_t winkle_state_core12 : 1; - uint32_t winkle_state_core11 : 1; - uint32_t winkle_state_core10 : 1; - uint32_t winkle_state_core9 : 1; - uint32_t winkle_state_core8 : 1; - uint32_t winkle_state_core7 : 1; - uint32_t winkle_state_core6 : 1; - uint32_t winkle_state_core5 : 1; - uint32_t winkle_state_core4 : 1; - uint32_t winkle_state_core3 : 1; - uint32_t winkle_state_core2 : 1; - uint32_t winkle_state_core1 : 1; - uint32_t winkle_state_core0 : 1; - uint32_t deep_idle_state_core15 : 1; - uint32_t deep_idle_state_core14 : 1; - uint32_t deep_idle_state_core13 : 1; - uint32_t deep_idle_state_core12 : 1; - uint32_t deep_idle_state_core11 : 1; - uint32_t deep_idle_state_core10 : 1; - uint32_t deep_idle_state_core9 : 1; - uint32_t deep_idle_state_core8 : 1; - uint32_t deep_idle_state_core7 : 1; - uint32_t deep_idle_state_core6 : 1; - uint32_t deep_idle_state_core5 : 1; - uint32_t deep_idle_state_core4 : 1; - uint32_t deep_idle_state_core3 : 1; - uint32_t deep_idle_state_core2 : 1; - uint32_t deep_idle_state_core1 : 1; - uint32_t deep_idle_state_core0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_deep_status_reg_t; - - - -typedef union pmc_ba_pore_exe_trigger_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_ba_pore_exe_trigger_reg_t; - - - -typedef union pmc_pcbs_gaps_brdcast_addr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t value : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t value : 32; -#endif // _BIG_ENDIAN - } fields; -} pmc_pcbs_gaps_brdcast_addr_t; - - - -typedef union pmc_lfir_err_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t lfir_pstate_oci_master_rderr : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t spare_fir : 10; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 10; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_oci_master_rderr : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_reg_t; - - - -typedef union pmc_lfir_err_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t lfir_pstate_oci_master_rderr : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t spare_fir : 10; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 10; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_oci_master_rderr : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_reg_and_t; - - - -typedef union pmc_lfir_err_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t lfir_pstate_oci_master_rderr : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t spare_fir : 10; - uint64_t fir_parity_err_dup : 1; - uint64_t fir_parity_err : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t fir_parity_err : 1; - uint64_t fir_parity_err_dup : 1; - uint64_t spare_fir : 10; - uint64_t lfir_if_comp_parity_error : 1; - uint64_t lfir_oci_slave_err : 1; - uint64_t lfir_o2p_fsm_err : 1; - uint64_t lfir_o2p_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_majority_detected_a_minority : 1; - uint64_t lfir_o2s_fsm_err : 1; - uint64_t lfir_o2s_write_while_bridge_busy_err : 1; - uint64_t lfir_o2s_retry_timeout : 1; - uint64_t lfir_o2s_crc_error2 : 1; - uint64_t lfir_o2s_crc_error1 : 1; - uint64_t lfir_o2s_crc_error0 : 1; - uint64_t lfir_spivid_majority_detected_a_minority : 1; - uint64_t lfir_spivid_fsm_err : 1; - uint64_t lfir_spivid_retry_timeout : 1; - uint64_t lfir_spivid_crc_error2 : 1; - uint64_t lfir_spivid_crc_error1 : 1; - uint64_t lfir_spivid_crc_error0 : 1; - uint64_t lfir_pmc_occ_heartbeat_timeout : 1; - uint64_t lfir_int_comp_parity_err : 1; - uint64_t lfir_idle_internal_err : 1; - uint64_t lfir_idle_oci_master_write_timeout_err : 1; - uint64_t lfir_idle_poresw_timeout_err : 1; - uint64_t lfir_idle_poresw_write_while_inactive_err : 1; - uint64_t lfir_idle_poresw_status_value_err : 1; - uint64_t lfir_idle_poresw_status_rc_err : 1; - uint64_t lfir_idle_poresw_fatal_err : 1; - uint64_t lfir_ms_comp_parity_err : 1; - uint64_t lfir_pstate_ms_fsm_err : 1; - uint64_t lfir_pstate_interchip_errorframe_err : 1; - uint64_t lfir_pstate_interchip_ue_err : 1; - uint64_t lfir_pstate_oci_master_to_err : 1; - uint64_t lfir_pstate_pib_master_offline_err : 1; - uint64_t lfir_pstate_pib_master_nonoffline_err : 1; - uint64_t lfir_pstate_gack_to_err : 1; - uint64_t lfir_pstate_gpst_checkbyte_err : 1; - uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; - uint64_t lfir_pstate_oci_master_rderr : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_reg_or_t; - - - -typedef union pmc_lfir_err_mask_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_mask_0 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_mask_reg_t; - - - -typedef union pmc_lfir_err_mask_reg_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_mask_0 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_mask_reg_and_t; - - - -typedef union pmc_lfir_err_mask_reg_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_mask_0 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_mask1_48 : 1; - uint64_t pmc_lfir_mask1_47 : 1; - uint64_t pmc_lfir_mask1_37_46 : 10; - uint64_t pmc_lfir_mask_36 : 1; - uint64_t pmc_lfir_mask_35 : 1; - uint64_t pmc_lfir_mask_34 : 1; - uint64_t pmc_lfir_mask_33 : 1; - uint64_t pmc_lfir_mask_32 : 1; - uint64_t pmc_lfir_mask_31 : 1; - uint64_t pmc_lfir_mask_30 : 1; - uint64_t pmc_lfir_mask_29 : 1; - uint64_t pmc_lfir_mask_28 : 1; - uint64_t pmc_lfir_mask_27 : 1; - uint64_t pmc_lfir_mask_26 : 1; - uint64_t pmc_lfir_mask_25 : 1; - uint64_t pmc_lfir_mask_24 : 1; - uint64_t pmc_lfir_mask_23 : 1; - uint64_t pmc_lfir_mask_22 : 1; - uint64_t pmc_lfir_mask_21 : 1; - uint64_t pmc_lfir_mask_20 : 1; - uint64_t pmc_lfir_mask_19 : 1; - uint64_t pmc_lfir_mask_18 : 1; - uint64_t pmc_lfir_mask_17 : 1; - uint64_t pmc_lfir_mask_16 : 1; - uint64_t pmc_lfir_mask_15 : 1; - uint64_t pmc_lfir_mask_14 : 1; - uint64_t pmc_lfir_mask_13 : 1; - uint64_t pmc_lfir_mask_12 : 1; - uint64_t pmc_lfir_mask_11 : 1; - uint64_t pmc_lfir_mask_10 : 1; - uint64_t pmc_lfir_mask_9 : 1; - uint64_t pmc_lfir_mask_8 : 1; - uint64_t pmc_lfir_mask_7 : 1; - uint64_t pmc_lfir_mask_6 : 1; - uint64_t pmc_lfir_mask_5 : 1; - uint64_t pmc_lfir_mask_4 : 1; - uint64_t pmc_lfir_mask_3 : 1; - uint64_t pmc_lfir_mask_2 : 1; - uint64_t pmc_lfir_mask_1 : 1; - uint64_t pmc_lfir_mask_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_err_mask_reg_or_t; - - - -typedef union pmc_lfir_action0_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_action0_0 : 1; - uint64_t pmc_lfir_action0_1 : 1; - uint64_t pmc_lfir_action0_2 : 1; - uint64_t pmc_lfir_action0_3 : 1; - uint64_t pmc_lfir_action0_4 : 1; - uint64_t pmc_lfir_action0_5 : 1; - uint64_t pmc_lfir_action0_6 : 1; - uint64_t pmc_lfir_action0_7 : 1; - uint64_t pmc_lfir_action0_8 : 1; - uint64_t pmc_lfir_action0_9 : 1; - uint64_t pmc_lfir_action0_10 : 1; - uint64_t pmc_lfir_action0_11 : 1; - uint64_t pmc_lfir_action0_12 : 1; - uint64_t pmc_lfir_action0_13 : 1; - uint64_t pmc_lfir_action0_14 : 1; - uint64_t pmc_lfir_action0_15 : 1; - uint64_t pmc_lfir_action0_16 : 1; - uint64_t pmc_lfir_action0_17 : 1; - uint64_t pmc_lfir_action0_18 : 1; - uint64_t pmc_lfir_action0_19 : 1; - uint64_t pmc_lfir_action0_20 : 1; - uint64_t pmc_lfir_action0_21 : 1; - uint64_t pmc_lfir_action0_22 : 1; - uint64_t pmc_lfir_action0_23 : 1; - uint64_t pmc_lfir_action0_24 : 1; - uint64_t pmc_lfir_action0_25 : 1; - uint64_t pmc_lfir_action0_26 : 1; - uint64_t pmc_lfir_action0_27 : 1; - uint64_t pmc_lfir_action0_28 : 1; - uint64_t pmc_lfir_action0_29 : 1; - uint64_t pmc_lfir_action0_30 : 1; - uint64_t pmc_lfir_action0_31 : 1; - uint64_t pmc_lfir_action0_32 : 1; - uint64_t pmc_lfir_action0_33 : 1; - uint64_t pmc_lfir_action0_34 : 1; - uint64_t pmc_lfir_action0_35 : 1; - uint64_t pmc_lfir_action0_36 : 1; - uint64_t pmc_lfir_action0_37_46 : 10; - uint64_t pmc_lfir_action0_47 : 1; - uint64_t pmc_lfir_action0_48 : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_action0_48 : 1; - uint64_t pmc_lfir_action0_47 : 1; - uint64_t pmc_lfir_action0_37_46 : 10; - uint64_t pmc_lfir_action0_36 : 1; - uint64_t pmc_lfir_action0_35 : 1; - uint64_t pmc_lfir_action0_34 : 1; - uint64_t pmc_lfir_action0_33 : 1; - uint64_t pmc_lfir_action0_32 : 1; - uint64_t pmc_lfir_action0_31 : 1; - uint64_t pmc_lfir_action0_30 : 1; - uint64_t pmc_lfir_action0_29 : 1; - uint64_t pmc_lfir_action0_28 : 1; - uint64_t pmc_lfir_action0_27 : 1; - uint64_t pmc_lfir_action0_26 : 1; - uint64_t pmc_lfir_action0_25 : 1; - uint64_t pmc_lfir_action0_24 : 1; - uint64_t pmc_lfir_action0_23 : 1; - uint64_t pmc_lfir_action0_22 : 1; - uint64_t pmc_lfir_action0_21 : 1; - uint64_t pmc_lfir_action0_20 : 1; - uint64_t pmc_lfir_action0_19 : 1; - uint64_t pmc_lfir_action0_18 : 1; - uint64_t pmc_lfir_action0_17 : 1; - uint64_t pmc_lfir_action0_16 : 1; - uint64_t pmc_lfir_action0_15 : 1; - uint64_t pmc_lfir_action0_14 : 1; - uint64_t pmc_lfir_action0_13 : 1; - uint64_t pmc_lfir_action0_12 : 1; - uint64_t pmc_lfir_action0_11 : 1; - uint64_t pmc_lfir_action0_10 : 1; - uint64_t pmc_lfir_action0_9 : 1; - uint64_t pmc_lfir_action0_8 : 1; - uint64_t pmc_lfir_action0_7 : 1; - uint64_t pmc_lfir_action0_6 : 1; - uint64_t pmc_lfir_action0_5 : 1; - uint64_t pmc_lfir_action0_4 : 1; - uint64_t pmc_lfir_action0_3 : 1; - uint64_t pmc_lfir_action0_2 : 1; - uint64_t pmc_lfir_action0_1 : 1; - uint64_t pmc_lfir_action0_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_action0_reg_t; - - - -typedef union pmc_lfir_action1_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_action1_0 : 1; - uint64_t pmc_lfir_action1_1 : 1; - uint64_t pmc_lfir_action1_2 : 1; - uint64_t pmc_lfir_action1_3 : 1; - uint64_t pmc_lfir_action1_4 : 1; - uint64_t pmc_lfir_action1_5 : 1; - uint64_t pmc_lfir_action1_6 : 1; - uint64_t pmc_lfir_action1_7 : 1; - uint64_t pmc_lfir_action1_8 : 1; - uint64_t pmc_lfir_action1_9 : 1; - uint64_t pmc_lfir_action1_10 : 1; - uint64_t pmc_lfir_action1_11 : 1; - uint64_t pmc_lfir_action1_12 : 1; - uint64_t pmc_lfir_action1_13 : 1; - uint64_t pmc_lfir_action1_14 : 1; - uint64_t pmc_lfir_action1_15 : 1; - uint64_t pmc_lfir_action1_16 : 1; - uint64_t pmc_lfir_action1_17 : 1; - uint64_t pmc_lfir_action1_18 : 1; - uint64_t pmc_lfir_action1_19 : 1; - uint64_t pmc_lfir_action1_20 : 1; - uint64_t pmc_lfir_action1_21 : 1; - uint64_t pmc_lfir_action1_22 : 1; - uint64_t pmc_lfir_action1_23 : 1; - uint64_t pmc_lfir_action1_24 : 1; - uint64_t pmc_lfir_action1_25 : 1; - uint64_t pmc_lfir_action1_26 : 1; - uint64_t pmc_lfir_action1_27 : 1; - uint64_t pmc_lfir_action1_28 : 1; - uint64_t pmc_lfir_action1_29 : 1; - uint64_t pmc_lfir_action1_30 : 1; - uint64_t pmc_lfir_action1_31 : 1; - uint64_t pmc_lfir_action1_32 : 1; - uint64_t pmc_lfir_action1_33 : 1; - uint64_t pmc_lfir_action1_34 : 1; - uint64_t pmc_lfir_action1_35 : 1; - uint64_t pmc_lfir_action1_36 : 1; - uint64_t pmc_lfir_action1_37_46 : 10; - uint64_t pmc_lfir_action1_47 : 1; - uint64_t pmc_lfir_action1_48 : 1; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_action1_48 : 1; - uint64_t pmc_lfir_action1_47 : 1; - uint64_t pmc_lfir_action1_37_46 : 10; - uint64_t pmc_lfir_action1_36 : 1; - uint64_t pmc_lfir_action1_35 : 1; - uint64_t pmc_lfir_action1_34 : 1; - uint64_t pmc_lfir_action1_33 : 1; - uint64_t pmc_lfir_action1_32 : 1; - uint64_t pmc_lfir_action1_31 : 1; - uint64_t pmc_lfir_action1_30 : 1; - uint64_t pmc_lfir_action1_29 : 1; - uint64_t pmc_lfir_action1_28 : 1; - uint64_t pmc_lfir_action1_27 : 1; - uint64_t pmc_lfir_action1_26 : 1; - uint64_t pmc_lfir_action1_25 : 1; - uint64_t pmc_lfir_action1_24 : 1; - uint64_t pmc_lfir_action1_23 : 1; - uint64_t pmc_lfir_action1_22 : 1; - uint64_t pmc_lfir_action1_21 : 1; - uint64_t pmc_lfir_action1_20 : 1; - uint64_t pmc_lfir_action1_19 : 1; - uint64_t pmc_lfir_action1_18 : 1; - uint64_t pmc_lfir_action1_17 : 1; - uint64_t pmc_lfir_action1_16 : 1; - uint64_t pmc_lfir_action1_15 : 1; - uint64_t pmc_lfir_action1_14 : 1; - uint64_t pmc_lfir_action1_13 : 1; - uint64_t pmc_lfir_action1_12 : 1; - uint64_t pmc_lfir_action1_11 : 1; - uint64_t pmc_lfir_action1_10 : 1; - uint64_t pmc_lfir_action1_9 : 1; - uint64_t pmc_lfir_action1_8 : 1; - uint64_t pmc_lfir_action1_7 : 1; - uint64_t pmc_lfir_action1_6 : 1; - uint64_t pmc_lfir_action1_5 : 1; - uint64_t pmc_lfir_action1_4 : 1; - uint64_t pmc_lfir_action1_3 : 1; - uint64_t pmc_lfir_action1_2 : 1; - uint64_t pmc_lfir_action1_1 : 1; - uint64_t pmc_lfir_action1_0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_action1_reg_t; - - - -typedef union pmc_lfir_wof_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pmc_lfir_wof : 49; - uint64_t _reserved0 : 15; -#else - uint64_t _reserved0 : 15; - uint64_t pmc_lfir_wof : 49; -#endif // _BIG_ENDIAN - } fields; -} pmc_lfir_wof_reg_t; - - -#endif // __ASSEMBLER__ -#endif // __PMC_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pmc_register_addresses.h b/src/ssx/pgp/registers/pmc_register_addresses.h deleted file mode 100755 index 96f8dac..0000000 --- a/src/ssx/pgp/registers/pmc_register_addresses.h +++ /dev/null @@ -1,116 +0,0 @@ -#ifndef __PMC_REGISTER_ADDRESSES_H__ -#define __PMC_REGISTER_ADDRESSES_H__ - -// $Id: pmc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pmc_register_addresses.h -/// \brief Symbolic addresses for the PMC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PMC_OCI_BASE 0x40010000 -#define PMC_MODE_REG 0x40010000 -#define PMC_HARDWARE_AUCTION_PSTATE_REG 0x40010008 -#define PMC_PSTATE_MONITOR_AND_CTRL_REG 0x40010010 -#define PMC_RAIL_BOUNDS_REGISTER 0x40010018 -#define PMC_GLOBAL_PSTATE_BOUNDS_REG 0x40010020 -#define PMC_PARAMETER_REG0 0x40010028 -#define PMC_PARAMETER_REG1 0x40010030 -#define PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010038 -#define PMC_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010040 -#define PMC_STATUS_REG 0x40010048 -#define PMC_PHASE_ENABLE_REG 0x40010050 -#define PMC_UNDERVOLTING_REG 0x40010060 -#define PMC_CORE_DECONFIGURATION_REG 0x40010068 -#define PMC_INTCHP_CTRL_REG1 0x40010080 -#define PMC_INTCHP_CTRL_REG2 0x40010088 -#define PMC_INTCHP_CTRL_REG4 0x40010090 -#define PMC_INTCHP_STATUS_REG 0x40010098 -#define PMC_INTCHP_COMMAND_REG 0x400100a0 -#define PMC_INTCHP_MSG_WDATA 0x400100a8 -#define PMC_INTCHP_MSG_RDATA 0x400100b0 -#define PMC_INTCHP_PSTATE_REG 0x400100b8 -#define PMC_INTCHP_GLOBACK_REG 0x400100c0 -#define PMC_FSMSTATE_STATUS_REG 0x40010100 -#define PMC_TRACE_MODE_REG 0x40010180 -#define PMC_SPIV_CTRL_REG0A 0x40010200 -#define PMC_SPIV_CTRL_REG0B 0x40010208 -#define PMC_SPIV_CTRL_REG1 0x40010210 -#define PMC_SPIV_CTRL_REG2 0x40010218 -#define PMC_SPIV_CTRL_REG3 0x40010220 -#define PMC_SPIV_CTRL_REG4 0x40010228 -#define PMC_SPIV_STATUS_REG 0x40010230 -#define PMC_SPIV_COMMAND_REG 0x40010238 -#define PMC_O2S_CTRL_REG0A 0x40010280 -#define PMC_O2S_CTRL_REG0B 0x40010288 -#define PMC_O2S_CTRL_REG1 0x40010290 -#define PMC_O2S_CTRL_REG2 0x40010298 -#define PMC_O2S_CTRL_REG4 0x400102a8 -#define PMC_O2S_STATUS_REG 0x400102b0 -#define PMC_O2S_COMMAND_REG 0x400102b8 -#define PMC_O2S_WDATA_REG 0x400102c0 -#define PMC_O2S_RDATA_REG 0x400102c8 -#define PMC_O2P_ADDR_REG 0x40010300 -#define PMC_O2P_CTRL_STATUS_REG 0x40010308 -#define PMC_O2P_SEND_DATA_HI_REG 0x40010310 -#define PMC_O2P_SEND_DATA_LO_REG 0x40010318 -#define PMC_O2P_RECV_DATA_HI_REG 0x40010320 -#define PMC_O2P_RECV_DATA_LO_REG 0x40010328 -#define PMC_OCC_HEARTBEAT_REG 0x40010330 -#define PMC_ERROR_INT_MASK_HI_REG 0x40010338 -#define PMC_ERROR_INT_MASK_LO_REG 0x40010340 -#define PMC_IDLE_SUSPEND_MASK_REG 0x40010348 -#define PMC_PEND_IDLE_REQ_REG0 0x40010400 -#define PMC_PEND_IDLE_REQ_REG1 0x40010408 -#define PMC_PEND_IDLE_REQ_REG2 0x40010410 -#define PMC_PEND_IDLE_REQ_REG3 0x40010418 -#define PMC_SLEEP_INT_REQ_VEC_REG0 0x40010420 -#define PMC_SLEEP_INT_REQ_VEC_REG1 0x40010428 -#define PMC_SLEEP_INT_REQ_VEC_REG2 0x40010430 -#define PMC_SLEEP_INT_REQ_VEC_REG3 0x40010438 -#define PMC_WINKLE_INT_REQ_VEC_REG0 0x40010440 -#define PMC_WINKLE_INT_REQ_VEC_REG1 0x40010448 -#define PMC_WINKLE_INT_REQ_VEC_REG2 0x40010450 -#define PMC_WINKLE_INT_REQ_VEC_REG3 0x40010458 -#define PMC_NAP_INT_REQ_VEC_REG0 0x40010460 -#define PMC_NAP_INT_REQ_VEC_REG1 0x40010468 -#define PMC_PORE_REQ_REG0 0x40010470 -#define PMC_PORE_REQ_REG1 0x40010478 -#define PMC_PORE_REQ_STAT_REG 0x40010480 -#define PMC_PORE_REQ_TOUT_TH_REG 0x40010488 -#define PMC_DEEP_EXIT_MASK_REG 0x40010490 -#define PMC_DEEP_EXIT_MASK_REG_AND 0x40010500 -#define PMC_DEEP_EXIT_MASK_REG_OR 0x40010508 -#define PMC_CORE_PSTATE_REG0 0x400104a0 -#define PMC_CORE_PSTATE_REG1 0x400104a8 -#define PMC_CORE_PSTATE_REG2 0x400104b0 -#define PMC_CORE_PSTATE_REG3 0x400104b8 -#define PMC_CORE_POWER_DONATION_REG 0x400104c0 -#define PMC_PMAX_SYNC_COLLECTION_REG 0x400104c8 -#define PMC_PMAX_SYNC_COLLECTION_MASK_REG 0x400104d0 -#define PMC_GPSA_ACK_COLLECTION_REG 0x400104d8 -#define PMC_GPSA_ACK_COLLECTION_MASK_REG 0x400104e0 -#define PMC_PORE_SCRATCH_REG0 0x400104e8 -#define PMC_PORE_SCRATCH_REG1 0x400104f0 -#define PMC_DEEP_IDLE_EXIT_REG 0x400104f8 -#define PMC_DEEP_STATUS_REG 0x40010510 -#define PMC_PIB_BASE 0x01010840 -#define PMC_LFIR_ERR_REG 0x01010840 -#define PMC_LFIR_ERR_REG_AND 0x01010841 -#define PMC_LFIR_ERR_REG_OR 0x01010842 -#define PMC_LFIR_ERR_MASK_REG 0x01010843 -#define PMC_LFIR_ERR_MASK_REG_AND 0x01010844 -#define PMC_LFIR_ERR_MASK_REG_OR 0x01010845 -#define PMC_LFIR_ACTION0_REG 0x01010846 -#define PMC_LFIR_ACTION1_REG 0x01010847 -#define PMC_LFIR_WOF_REG 0x01010848 - -#endif // __PMC_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/pore_firmware_registers.h b/src/ssx/pgp/registers/pore_firmware_registers.h deleted file mode 100755 index 76127d9..0000000 --- a/src/ssx/pgp/registers/pore_firmware_registers.h +++ /dev/null @@ -1,906 +0,0 @@ -#ifndef __PORE_FIRMWARE_REGISTERS_H__ -#define __PORE_FIRMWARE_REGISTERS_H__ - -// $Id: pore_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pore_firmware_registers.h -/// \brief C register structs for the PORE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pore_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cur_state : 8; - uint64_t freeze_action : 1; - uint64_t interrupt_pending : 1; - uint64_t spare : 2; - uint64_t stack_pointer : 4; - uint64_t pc : 48; -#else - uint64_t pc : 48; - uint64_t stack_pointer : 4; - uint64_t spare : 2; - uint64_t interrupt_pending : 1; - uint64_t freeze_action : 1; - uint64_t cur_state : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_status_t; - -#endif // __ASSEMBLER__ -#define PORE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) -#define PORE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000) -#define PORE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000) -#define PORE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) -#ifndef __ASSEMBLER__ - - -typedef union pore_control { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t start_stop : 1; - uint64_t continue_step : 1; - uint64_t skip : 1; - uint64_t set_pc : 1; - uint64_t set_tp_scan_clk : 3; - uint64_t lock_exe_trig : 1; - uint64_t freeze_mask : 1; - uint64_t check_parity : 1; - uint64_t prv_parity : 1; - uint64_t trap_enable : 1; - uint64_t narrow_mode_trace : 1; - uint64_t interruptible : 1; - uint64_t pore_done_override : 1; - uint64_t interruptible_en : 1; - uint64_t pc_brk_pt : 48; -#else - uint64_t pc_brk_pt : 48; - uint64_t interruptible_en : 1; - uint64_t pore_done_override : 1; - uint64_t interruptible : 1; - uint64_t narrow_mode_trace : 1; - uint64_t trap_enable : 1; - uint64_t prv_parity : 1; - uint64_t check_parity : 1; - uint64_t freeze_mask : 1; - uint64_t lock_exe_trig : 1; - uint64_t set_tp_scan_clk : 3; - uint64_t set_pc : 1; - uint64_t skip : 1; - uint64_t continue_step : 1; - uint64_t start_stop : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_control_t; - -#endif // __ASSEMBLER__ -#define PORE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PORE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PORE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PORE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PORE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000) -#define PORE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PORE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PORE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define PORE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define PORE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define PORE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define PORE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define PORE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) -#ifndef __ASSEMBLER__ - - -typedef union pore_reset { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t fn_reset : 1; - uint64_t oci_reset : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t oci_reset : 1; - uint64_t fn_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_reset_t; - - - -typedef union pore_error_mask { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_err_handler0 : 1; - uint64_t enable_err_handler1 : 1; - uint64_t enable_err_handler2 : 1; - uint64_t enable_err_handler3 : 1; - uint64_t enable_err_handler4 : 1; - uint64_t enable_err_output0 : 1; - uint64_t enable_err_output1 : 1; - uint64_t enable_err_output2 : 1; - uint64_t enable_err_output3 : 1; - uint64_t enable_err_output4 : 1; - uint64_t enable_fatal_err_output0 : 1; - uint64_t enable_fatal_err_output1 : 1; - uint64_t enable_fatal_err_output2 : 1; - uint64_t enable_fatal_err_output3 : 1; - uint64_t enable_fatal_err_output4 : 1; - uint64_t stop_exe_on_error0 : 1; - uint64_t stop_exe_on_error1 : 1; - uint64_t stop_exe_on_error2 : 1; - uint64_t stop_exe_on_error3 : 1; - uint64_t stop_exe_on_error4 : 1; - uint64_t gate_chiplet_offline_err : 1; - uint64_t i2c_bad_status_0 : 1; - uint64_t i2c_bad_status_1 : 1; - uint64_t i2c_bad_status_2 : 1; - uint64_t i2c_bad_status_3 : 1; - uint64_t group_parity_error_0 : 1; - uint64_t group_parity_error_1 : 1; - uint64_t group_parity_error_2 : 1; - uint64_t group_parity_error_3 : 1; - uint64_t group_parity_error_4 : 1; - uint64_t _reserved0 : 34; -#else - uint64_t _reserved0 : 34; - uint64_t group_parity_error_4 : 1; - uint64_t group_parity_error_3 : 1; - uint64_t group_parity_error_2 : 1; - uint64_t group_parity_error_1 : 1; - uint64_t group_parity_error_0 : 1; - uint64_t i2c_bad_status_3 : 1; - uint64_t i2c_bad_status_2 : 1; - uint64_t i2c_bad_status_1 : 1; - uint64_t i2c_bad_status_0 : 1; - uint64_t gate_chiplet_offline_err : 1; - uint64_t stop_exe_on_error4 : 1; - uint64_t stop_exe_on_error3 : 1; - uint64_t stop_exe_on_error2 : 1; - uint64_t stop_exe_on_error1 : 1; - uint64_t stop_exe_on_error0 : 1; - uint64_t enable_fatal_err_output4 : 1; - uint64_t enable_fatal_err_output3 : 1; - uint64_t enable_fatal_err_output2 : 1; - uint64_t enable_fatal_err_output1 : 1; - uint64_t enable_fatal_err_output0 : 1; - uint64_t enable_err_output4 : 1; - uint64_t enable_err_output3 : 1; - uint64_t enable_err_output2 : 1; - uint64_t enable_err_output1 : 1; - uint64_t enable_err_output0 : 1; - uint64_t enable_err_handler4 : 1; - uint64_t enable_err_handler3 : 1; - uint64_t enable_err_handler2 : 1; - uint64_t enable_err_handler1 : 1; - uint64_t enable_err_handler0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_error_mask_t; - -#endif // __ASSEMBLER__ -#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) -#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) -#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) -#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) -#define PORE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) -#define PORE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) -#define PORE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) -#define PORE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) -#define PORE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) -#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) -#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) -#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) -#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) -#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) -#ifndef __ASSEMBLER__ - - -typedef union pore_prv_base_address0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 25; - uint64_t mc : 1; - uint64_t chiplet_id : 6; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t chiplet_id : 6; - uint64_t mc : 1; - uint64_t spare : 25; -#endif // _BIG_ENDIAN - } fields; -} pore_prv_base_address0_t; - - - -typedef union pore_prv_base_address1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 25; - uint64_t mc : 1; - uint64_t chiplet_id : 6; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t chiplet_id : 6; - uint64_t mc : 1; - uint64_t spare : 25; -#endif // _BIG_ENDIAN - } fields; -} pore_prv_base_address1_t; - - - -typedef union pore_oci_base_address0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 18; - uint64_t oci_mem_route : 14; - uint64_t oci_base_address : 32; -#else - uint64_t oci_base_address : 32; - uint64_t oci_mem_route : 14; - uint64_t spare : 18; -#endif // _BIG_ENDIAN - } fields; -} pore_oci_base_address0_t; - - - -typedef union pore_oci_base_address1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 18; - uint64_t oci_mem_route : 14; - uint64_t oci_base_address : 32; -#else - uint64_t oci_base_address : 32; - uint64_t oci_mem_route : 14; - uint64_t spare : 18; -#endif // _BIG_ENDIAN - } fields; -} pore_oci_base_address1_t; - - - -typedef union pore_table_base_addr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 16; - uint64_t memory_space : 16; - uint64_t table_base_address : 32; -#else - uint64_t table_base_address : 32; - uint64_t memory_space : 16; - uint64_t reserved : 16; -#endif // _BIG_ENDIAN - } fields; -} pore_table_base_addr_t; - - - -typedef union pore_exe_trigger { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 8; - uint64_t start_vector : 4; - uint64_t zeroes : 8; - uint64_t unused : 12; - uint64_t mc_chiplet_select_mask : 32; -#else - uint64_t mc_chiplet_select_mask : 32; - uint64_t unused : 12; - uint64_t zeroes : 8; - uint64_t start_vector : 4; - uint64_t reserved : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_exe_trigger_t; - - - -typedef union pore_scratch0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t zeroes : 8; - uint64_t scratch0 : 24; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t scratch0 : 24; - uint64_t zeroes : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_scratch0_t; - - - -typedef union pore_scratch1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t scratch1 : 64; -#else - uint64_t scratch1 : 64; -#endif // _BIG_ENDIAN - } fields; -} pore_scratch1_t; - - - -typedef union pore_scratch2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t scratch2 : 64; -#else - uint64_t scratch2 : 64; -#endif // _BIG_ENDIAN - } fields; -} pore_scratch2_t; - - - -typedef union pore_ibuf_01 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ibuf0 : 32; - uint64_t ibuf1 : 32; -#else - uint64_t ibuf1 : 32; - uint64_t ibuf0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_ibuf_01_t; - - - -typedef union pore_ibuf_2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ibuf2 : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t ibuf2 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_ibuf_2_t; - - - -typedef union pore_dbg0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t last_completed_address : 32; - uint64_t last_pib_parity_fail : 1; - uint64_t last_ret_code_prv : 3; - uint64_t i2c_bad_status0 : 1; - uint64_t i2c_bad_status1 : 1; - uint64_t i2c_bad_status2 : 1; - uint64_t i2c_bad_status3 : 1; - uint64_t group_parity_error0 : 1; - uint64_t group_parity_error1 : 1; - uint64_t group_parity_error2 : 1; - uint64_t group_parity_error3 : 1; - uint64_t group_parity_error4 : 1; - uint64_t interrupt_counter : 8; - uint64_t _reserved0 : 11; -#else - uint64_t _reserved0 : 11; - uint64_t interrupt_counter : 8; - uint64_t group_parity_error4 : 1; - uint64_t group_parity_error3 : 1; - uint64_t group_parity_error2 : 1; - uint64_t group_parity_error1 : 1; - uint64_t group_parity_error0 : 1; - uint64_t i2c_bad_status3 : 1; - uint64_t i2c_bad_status2 : 1; - uint64_t i2c_bad_status1 : 1; - uint64_t i2c_bad_status0 : 1; - uint64_t last_ret_code_prv : 3; - uint64_t last_pib_parity_fail : 1; - uint64_t last_completed_address : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_dbg0_t; - - - -typedef union pore_dbg1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_last_access : 48; - uint64_t oci_master_rd_parity_err : 1; - uint64_t last_ret_code_oci : 3; - uint64_t bad_instr_parity : 1; - uint64_t invalid_instr_code : 1; - uint64_t pc_overflow_underrun : 1; - uint64_t bad_scan_crc : 1; - uint64_t pc_stack_ovflw_undrn_err : 1; - uint64_t instruction_fetch_error : 1; - uint64_t invalid_instruction_operand : 1; - uint64_t invalid_instruction_path : 1; - uint64_t invalid_start_vector : 1; - uint64_t fast_i2c_protocol_hang : 1; - uint64_t spare : 1; - uint64_t debug_regs_locked : 1; -#else - uint64_t debug_regs_locked : 1; - uint64_t spare : 1; - uint64_t fast_i2c_protocol_hang : 1; - uint64_t invalid_start_vector : 1; - uint64_t invalid_instruction_path : 1; - uint64_t invalid_instruction_operand : 1; - uint64_t instruction_fetch_error : 1; - uint64_t pc_stack_ovflw_undrn_err : 1; - uint64_t bad_scan_crc : 1; - uint64_t pc_overflow_underrun : 1; - uint64_t invalid_instr_code : 1; - uint64_t bad_instr_parity : 1; - uint64_t last_ret_code_oci : 3; - uint64_t oci_master_rd_parity_err : 1; - uint64_t pc_last_access : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_dbg1_t; - - - -typedef union pore_pc_stack0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack0 : 48; - uint64_t _reserved0 : 11; - uint64_t set_new_stack_pointer : 1; - uint64_t new_stack_pointer : 4; -#else - uint64_t new_stack_pointer : 4; - uint64_t set_new_stack_pointer : 1; - uint64_t _reserved0 : 11; - uint64_t pc_stack0 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_pc_stack0_t; - - - -typedef union pore_pc_stack1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack1 : 48; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t pc_stack1 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_pc_stack1_t; - - - -typedef union pore_pc_stack2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack2 : 48; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t pc_stack2 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_pc_stack2_t; - - - -typedef union pore_id_flags { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 32; - uint64_t pib_parity_fail : 1; - uint64_t pib_status : 3; - uint64_t oci_parity_fail : 1; - uint64_t oci_status : 3; - uint64_t reserved1 : 8; - uint64_t ugt : 1; - uint64_t ult : 1; - uint64_t sgt : 1; - uint64_t slt : 1; - uint64_t c : 1; - uint64_t o : 1; - uint64_t n : 1; - uint64_t z : 1; - uint64_t reserved2 : 4; - uint64_t ibuf_id : 4; -#else - uint64_t ibuf_id : 4; - uint64_t reserved2 : 4; - uint64_t z : 1; - uint64_t n : 1; - uint64_t o : 1; - uint64_t c : 1; - uint64_t slt : 1; - uint64_t sgt : 1; - uint64_t ult : 1; - uint64_t ugt : 1; - uint64_t reserved1 : 8; - uint64_t oci_status : 3; - uint64_t oci_parity_fail : 1; - uint64_t pib_status : 3; - uint64_t pib_parity_fail : 1; - uint64_t reserved0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_id_flags_t; - - - -typedef union pore_data0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t data0 : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t data0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_data0_t; - - - -typedef union pore_memory_reloc { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 30; - uint64_t memory_reloc_region : 2; - uint64_t memory_reloc_base : 20; - uint64_t _reserved1 : 12; -#else - uint64_t _reserved1 : 12; - uint64_t memory_reloc_base : 20; - uint64_t memory_reloc_region : 2; - uint64_t _reserved0 : 30; -#endif // _BIG_ENDIAN - } fields; -} pore_memory_reloc_t; - - - -typedef union pore_i2c_en_param { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t i2c_engine_identifier : 4; - uint64_t reserved0 : 1; - uint64_t i2c_engine_address_range : 3; - uint64_t reserved1 : 3; - uint64_t i2c_engine_port : 5; - uint64_t reserved2 : 1; - uint64_t i2c_engine_device_id : 7; - uint64_t reserved3 : 2; - uint64_t i2c_engine_speed : 2; - uint64_t i2c_poll_threshold : 4; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t i2c_poll_threshold : 4; - uint64_t i2c_engine_speed : 2; - uint64_t reserved3 : 2; - uint64_t i2c_engine_device_id : 7; - uint64_t reserved2 : 1; - uint64_t i2c_engine_port : 5; - uint64_t reserved1 : 3; - uint64_t i2c_engine_address_range : 3; - uint64_t reserved0 : 1; - uint64_t i2c_engine_identifier : 4; -#endif // _BIG_ENDIAN - } fields; -} pore_i2c_en_param_t; - - -#endif // __ASSEMBLER__ -#endif // __PORE_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/pore_register_addresses.h b/src/ssx/pgp/registers/pore_register_addresses.h deleted file mode 100755 index 0fc769b..0000000 --- a/src/ssx/pgp/registers/pore_register_addresses.h +++ /dev/null @@ -1,130 +0,0 @@ -#ifndef __PORE_REGISTER_ADDRESSES_H__ -#define __PORE_REGISTER_ADDRESSES_H__ - -// $Id: pore_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file pore_register_addresses.h -/// \brief Symbolic addresses for the PORE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PORE_GPE0_OCI_BASE 0x40000000 -#define PORE_GPE1_OCI_BASE 0x40000100 -#define PORE_SLW_OCI_BASE 0x40040000 -#define PORE_STATUS_OFFSET 0x00000000 -#define PORE_GPE0_STATUS 0x40000000 -#define PORE_GPE1_STATUS 0x40000100 -#define PORE_SLW_STATUS 0x40040000 -#define PORE_CONTROL_OFFSET 0x00000008 -#define PORE_GPE0_CONTROL 0x40000008 -#define PORE_GPE1_CONTROL 0x40000108 -#define PORE_SLW_CONTROL 0x40040008 -#define PORE_RESET_OFFSET 0x00000010 -#define PORE_GPE0_RESET 0x40000010 -#define PORE_GPE1_RESET 0x40000110 -#define PORE_SLW_RESET 0x40040010 -#define PORE_ERROR_MASK_OFFSET 0x00000018 -#define PORE_GPE0_ERROR_MASK 0x40000018 -#define PORE_GPE1_ERROR_MASK 0x40000118 -#define PORE_SLW_ERROR_MASK 0x40040018 -#define PORE_PRV_BASE_ADDRESS0_OFFSET 0x00000020 -#define PORE_GPE0_PRV_BASE_ADDRESS0 0x40000020 -#define PORE_GPE1_PRV_BASE_ADDRESS0 0x40000120 -#define PORE_SLW_PRV_BASE_ADDRESS0 0x40040020 -#define PORE_PRV_BASE_ADDRESS1_OFFSET 0x00000028 -#define PORE_GPE0_PRV_BASE_ADDRESS1 0x40000028 -#define PORE_GPE1_PRV_BASE_ADDRESS1 0x40000128 -#define PORE_SLW_PRV_BASE_ADDRESS1 0x40040028 -#define PORE_OCI_BASE_ADDRESS0_OFFSET 0x00000030 -#define PORE_GPE0_OCI_BASE_ADDRESS0 0x40000030 -#define PORE_GPE1_OCI_BASE_ADDRESS0 0x40000130 -#define PORE_SLW_OCI_BASE_ADDRESS0 0x40040030 -#define PORE_OCI_BASE_ADDRESS1_OFFSET 0x00000038 -#define PORE_GPE0_OCI_BASE_ADDRESS1 0x40000038 -#define PORE_GPE1_OCI_BASE_ADDRESS1 0x40000138 -#define PORE_SLW_OCI_BASE_ADDRESS1 0x40040038 -#define PORE_TABLE_BASE_ADDR_OFFSET 0x00000040 -#define PORE_GPE0_TABLE_BASE_ADDR 0x40000040 -#define PORE_GPE1_TABLE_BASE_ADDR 0x40000140 -#define PORE_SLW_TABLE_BASE_ADDR 0x40040040 -#define PORE_EXE_TRIGGER_OFFSET 0x00000048 -#define PORE_GPE0_EXE_TRIGGER 0x40000048 -#define PORE_GPE1_EXE_TRIGGER 0x40000148 -#define PORE_SLW_EXE_TRIGGER 0x40040048 -#define PORE_SCRATCH0_OFFSET 0x00000050 -#define PORE_GPE0_SCRATCH0 0x40000050 -#define PORE_GPE1_SCRATCH0 0x40000150 -#define PORE_SLW_SCRATCH0 0x40040050 -#define PORE_SCRATCH1_OFFSET 0x00000058 -#define PORE_GPE0_SCRATCH1 0x40000058 -#define PORE_GPE1_SCRATCH1 0x40000158 -#define PORE_SLW_SCRATCH1 0x40040058 -#define PORE_SCRATCH2_OFFSET 0x00000060 -#define PORE_GPE0_SCRATCH2 0x40000060 -#define PORE_GPE1_SCRATCH2 0x40000160 -#define PORE_SLW_SCRATCH2 0x40040060 -#define PORE_IBUF_01_OFFSET 0x00000068 -#define PORE_GPE0_IBUF_01 0x40000068 -#define PORE_GPE1_IBUF_01 0x40000168 -#define PORE_SLW_IBUF_01 0x40040068 -#define PORE_IBUF_2_OFFSET 0x00000070 -#define PORE_GPE0_IBUF_2 0x40000070 -#define PORE_GPE1_IBUF_2 0x40000170 -#define PORE_SLW_IBUF_2 0x40040070 -#define PORE_DBG0_OFFSET 0x00000078 -#define PORE_GPE0_DBG0 0x40000078 -#define PORE_GPE1_DBG0 0x40000178 -#define PORE_SLW_DBG0 0x40040078 -#define PORE_DBG1_OFFSET 0x00000080 -#define PORE_GPE0_DBG1 0x40000080 -#define PORE_GPE1_DBG1 0x40000180 -#define PORE_SLW_DBG1 0x40040080 -#define PORE_PC_STACK0_OFFSET 0x00000088 -#define PORE_GPE0_PC_STACK0 0x40000088 -#define PORE_GPE1_PC_STACK0 0x40000188 -#define PORE_SLW_PC_STACK0 0x40040088 -#define PORE_PC_STACK1_OFFSET 0x00000090 -#define PORE_GPE0_PC_STACK1 0x40000090 -#define PORE_GPE1_PC_STACK1 0x40000190 -#define PORE_SLW_PC_STACK1 0x40040090 -#define PORE_PC_STACK2_OFFSET 0x00000098 -#define PORE_GPE0_PC_STACK2 0x40000098 -#define PORE_GPE1_PC_STACK2 0x40000198 -#define PORE_SLW_PC_STACK2 0x40040098 -#define PORE_ID_FLAGS_OFFSET 0x000000a0 -#define PORE_GPE0_ID_FLAGS 0x400000a0 -#define PORE_GPE1_ID_FLAGS 0x400001a0 -#define PORE_SLW_ID_FLAGS 0x400400a0 -#define PORE_DATA0_OFFSET 0x000000a8 -#define PORE_GPE0_DATA0 0x400000a8 -#define PORE_GPE1_DATA0 0x400001a8 -#define PORE_SLW_DATA0 0x400400a8 -#define PORE_MEMORY_RELOC_OFFSET 0x000000b0 -#define PORE_GPE0_MEMORY_RELOC 0x400000b0 -#define PORE_GPE1_MEMORY_RELOC 0x400001b0 -#define PORE_SLW_MEMORY_RELOC 0x400400b0 -#define PORE_I2C_E0_PARAM_OFFSET 0x000000b8 -#define PORE_I2C_E1_PARAM_OFFSET 0x000000c0 -#define PORE_I2C_E2_PARAM_OFFSET 0x000000c8 -#define PORE_GPE0_I2C_EN_PARAM(n) (PORE_GPE0_I2C_E0_PARAM + ((PORE_GPE0_I2C_E1_PARAM - PORE_GPE0_I2C_E0_PARAM) * (n))) -#define PORE_GPE1_I2C_EN_PARAM(n) (PORE_GPE1_I2C_E0_PARAM + ((PORE_GPE1_I2C_E1_PARAM - PORE_GPE1_I2C_E0_PARAM) * (n))) -#define PORE_SLW_I2C_EN_PARAM(n) (PORE_SLW_I2C_E0_PARAM + ((PORE_SLW_I2C_E1_PARAM - PORE_SLW_I2C_E0_PARAM) * (n))) -#define PORE_GPE0_I2C_E0_PARAM 0x400000b8 -#define PORE_GPE1_I2C_E0_PARAM 0x400001b8 -#define PORE_SLW_I2C_E0_PARAM 0x400400b8 -#define PORE_GPE0_I2C_E1_PARAM 0x400000c0 -#define PORE_GPE1_I2C_E1_PARAM 0x400001c0 -#define PORE_SLW_I2C_E1_PARAM 0x400400c0 -#define PORE_GPE0_I2C_E2_PARAM 0x400000c8 -#define PORE_GPE1_I2C_E2_PARAM 0x400001c8 -#define PORE_SLW_I2C_E2_PARAM 0x400400c8 - -#endif // __PORE_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/sbe_firmware_registers.h b/src/ssx/pgp/registers/sbe_firmware_registers.h deleted file mode 100644 index 8175c11..0000000 --- a/src/ssx/pgp/registers/sbe_firmware_registers.h +++ /dev/null @@ -1,906 +0,0 @@ -#ifndef __SBE_FIRMWARE_REGISTERS_H__ -#define __SBE_FIRMWARE_REGISTERS_H__ - -// $Id: sbe_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sbe_firmware_registers.h -/// \brief C register structs for the SBE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union pore_sbe_status { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cur_state : 8; - uint64_t freeze_action : 1; - uint64_t interrupt_pending : 1; - uint64_t spare : 2; - uint64_t stack_pointer : 4; - uint64_t pc : 48; -#else - uint64_t pc : 48; - uint64_t stack_pointer : 4; - uint64_t spare : 2; - uint64_t interrupt_pending : 1; - uint64_t freeze_action : 1; - uint64_t cur_state : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_status_t; - -#endif // __ASSEMBLER__ -#define PORE_SBE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) -#define PORE_SBE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_SBE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_SBE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000) -#define PORE_SBE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000) -#define PORE_SBE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) -#ifndef __ASSEMBLER__ - - -typedef union pore_sbe_control { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t start_stop : 1; - uint64_t continue_step : 1; - uint64_t skip : 1; - uint64_t set_pc : 1; - uint64_t set_tp_scan_clk : 3; - uint64_t lock_exe_trig : 1; - uint64_t freeze_mask : 1; - uint64_t check_parity : 1; - uint64_t prv_parity : 1; - uint64_t trap_enable : 1; - uint64_t narrow_mode_trace : 1; - uint64_t interruptible : 1; - uint64_t pore_done_override : 1; - uint64_t interruptible_en : 1; - uint64_t pc_brk_pt : 48; -#else - uint64_t pc_brk_pt : 48; - uint64_t interruptible_en : 1; - uint64_t pore_done_override : 1; - uint64_t interruptible : 1; - uint64_t narrow_mode_trace : 1; - uint64_t trap_enable : 1; - uint64_t prv_parity : 1; - uint64_t check_parity : 1; - uint64_t freeze_mask : 1; - uint64_t lock_exe_trig : 1; - uint64_t set_tp_scan_clk : 3; - uint64_t set_pc : 1; - uint64_t skip : 1; - uint64_t continue_step : 1; - uint64_t start_stop : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_control_t; - -#endif // __ASSEMBLER__ -#define PORE_SBE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PORE_SBE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PORE_SBE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PORE_SBE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PORE_SBE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000) -#define PORE_SBE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PORE_SBE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_SBE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_SBE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PORE_SBE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define PORE_SBE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define PORE_SBE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define PORE_SBE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define PORE_SBE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define PORE_SBE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) -#ifndef __ASSEMBLER__ - - -typedef union pore_sbe_reset { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t fn_reset : 1; - uint64_t oci_reset : 1; - uint64_t _reserved0 : 62; -#else - uint64_t _reserved0 : 62; - uint64_t oci_reset : 1; - uint64_t fn_reset : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_reset_t; - - - -typedef union pore_sbe_error_mask { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t enable_err_handler0 : 1; - uint64_t enable_err_handler1 : 1; - uint64_t enable_err_handler2 : 1; - uint64_t enable_err_handler3 : 1; - uint64_t enable_err_handler4 : 1; - uint64_t enable_err_output0 : 1; - uint64_t enable_err_output1 : 1; - uint64_t enable_err_output2 : 1; - uint64_t enable_err_output3 : 1; - uint64_t enable_err_output4 : 1; - uint64_t enable_fatal_err_output0 : 1; - uint64_t enable_fatal_err_output1 : 1; - uint64_t enable_fatal_err_output2 : 1; - uint64_t enable_fatal_err_output3 : 1; - uint64_t enable_fatal_err_output4 : 1; - uint64_t stop_exe_on_error0 : 1; - uint64_t stop_exe_on_error1 : 1; - uint64_t stop_exe_on_error2 : 1; - uint64_t stop_exe_on_error3 : 1; - uint64_t stop_exe_on_error4 : 1; - uint64_t gate_chiplet_offline_err : 1; - uint64_t i2c_bad_status_0 : 1; - uint64_t i2c_bad_status_1 : 1; - uint64_t i2c_bad_status_2 : 1; - uint64_t i2c_bad_status_3 : 1; - uint64_t group_parity_error_0 : 1; - uint64_t group_parity_error_1 : 1; - uint64_t group_parity_error_2 : 1; - uint64_t group_parity_error_3 : 1; - uint64_t group_parity_error_4 : 1; - uint64_t _reserved0 : 34; -#else - uint64_t _reserved0 : 34; - uint64_t group_parity_error_4 : 1; - uint64_t group_parity_error_3 : 1; - uint64_t group_parity_error_2 : 1; - uint64_t group_parity_error_1 : 1; - uint64_t group_parity_error_0 : 1; - uint64_t i2c_bad_status_3 : 1; - uint64_t i2c_bad_status_2 : 1; - uint64_t i2c_bad_status_1 : 1; - uint64_t i2c_bad_status_0 : 1; - uint64_t gate_chiplet_offline_err : 1; - uint64_t stop_exe_on_error4 : 1; - uint64_t stop_exe_on_error3 : 1; - uint64_t stop_exe_on_error2 : 1; - uint64_t stop_exe_on_error1 : 1; - uint64_t stop_exe_on_error0 : 1; - uint64_t enable_fatal_err_output4 : 1; - uint64_t enable_fatal_err_output3 : 1; - uint64_t enable_fatal_err_output2 : 1; - uint64_t enable_fatal_err_output1 : 1; - uint64_t enable_fatal_err_output0 : 1; - uint64_t enable_err_output4 : 1; - uint64_t enable_err_output3 : 1; - uint64_t enable_err_output2 : 1; - uint64_t enable_err_output1 : 1; - uint64_t enable_err_output0 : 1; - uint64_t enable_err_handler4 : 1; - uint64_t enable_err_handler3 : 1; - uint64_t enable_err_handler2 : 1; - uint64_t enable_err_handler1 : 1; - uint64_t enable_err_handler0 : 1; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_error_mask_t; - -#endif // __ASSEMBLER__ -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) -#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) -#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) -#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) -#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) -#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) -#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) -#define PORE_SBE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) -#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) -#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) -#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) -#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) -#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) -#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) -#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) -#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) -#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) -#ifndef __ASSEMBLER__ - - -typedef union pore_sbe_prv_base_address0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 25; - uint64_t mc : 1; - uint64_t chiplet_id : 6; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t chiplet_id : 6; - uint64_t mc : 1; - uint64_t spare : 25; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_prv_base_address0_t; - - - -typedef union pore_sbe_prv_base_address1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 25; - uint64_t mc : 1; - uint64_t chiplet_id : 6; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t chiplet_id : 6; - uint64_t mc : 1; - uint64_t spare : 25; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_prv_base_address1_t; - - - -typedef union pore_sbe_oci_base_address0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 18; - uint64_t oci_mem_route : 14; - uint64_t oci_base_address : 32; -#else - uint64_t oci_base_address : 32; - uint64_t oci_mem_route : 14; - uint64_t spare : 18; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_oci_base_address0_t; - - - -typedef union pore_sbe_oci_base_address1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t spare : 18; - uint64_t oci_mem_route : 14; - uint64_t oci_base_address : 32; -#else - uint64_t oci_base_address : 32; - uint64_t oci_mem_route : 14; - uint64_t spare : 18; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_oci_base_address1_t; - - - -typedef union pore_sbe_table_base_addr { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 16; - uint64_t memory_space : 16; - uint64_t table_base_address : 32; -#else - uint64_t table_base_address : 32; - uint64_t memory_space : 16; - uint64_t reserved : 16; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_table_base_addr_t; - - - -typedef union pore_sbe_exe_trigger { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved : 8; - uint64_t start_vector : 4; - uint64_t zeroes : 8; - uint64_t unused : 12; - uint64_t mc_chiplet_select_mask : 32; -#else - uint64_t mc_chiplet_select_mask : 32; - uint64_t unused : 12; - uint64_t zeroes : 8; - uint64_t start_vector : 4; - uint64_t reserved : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_exe_trigger_t; - - - -typedef union pore_sbe_scratch0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t zeroes : 8; - uint64_t scratch0 : 24; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t scratch0 : 24; - uint64_t zeroes : 8; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_scratch0_t; - - - -typedef union pore_sbe_scratch1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t scratch1 : 64; -#else - uint64_t scratch1 : 64; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_scratch1_t; - - - -typedef union pore_sbe_scratch2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t scratch2 : 64; -#else - uint64_t scratch2 : 64; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_scratch2_t; - - - -typedef union pore_sbe_ibuf_01 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ibuf0 : 32; - uint64_t ibuf1 : 32; -#else - uint64_t ibuf1 : 32; - uint64_t ibuf0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_ibuf_01_t; - - - -typedef union pore_sbe_ibuf_2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t ibuf2 : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t ibuf2 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_ibuf_2_t; - - - -typedef union pore_sbe_dbg0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t last_completed_address : 32; - uint64_t last_pib_parity_fail : 1; - uint64_t last_ret_code_prv : 3; - uint64_t i2c_bad_status0 : 1; - uint64_t i2c_bad_status1 : 1; - uint64_t i2c_bad_status2 : 1; - uint64_t i2c_bad_status3 : 1; - uint64_t group_parity_error0 : 1; - uint64_t group_parity_error1 : 1; - uint64_t group_parity_error2 : 1; - uint64_t group_parity_error3 : 1; - uint64_t group_parity_error4 : 1; - uint64_t interrupt_counter : 8; - uint64_t _reserved0 : 11; -#else - uint64_t _reserved0 : 11; - uint64_t interrupt_counter : 8; - uint64_t group_parity_error4 : 1; - uint64_t group_parity_error3 : 1; - uint64_t group_parity_error2 : 1; - uint64_t group_parity_error1 : 1; - uint64_t group_parity_error0 : 1; - uint64_t i2c_bad_status3 : 1; - uint64_t i2c_bad_status2 : 1; - uint64_t i2c_bad_status1 : 1; - uint64_t i2c_bad_status0 : 1; - uint64_t last_ret_code_prv : 3; - uint64_t last_pib_parity_fail : 1; - uint64_t last_completed_address : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_dbg0_t; - - - -typedef union pore_sbe_dbg1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_last_access : 48; - uint64_t oci_master_rd_parity_err : 1; - uint64_t last_ret_code_oci : 3; - uint64_t bad_instr_parity : 1; - uint64_t invalid_instr_code : 1; - uint64_t pc_overflow_underrun : 1; - uint64_t bad_scan_crc : 1; - uint64_t pc_stack_ovflw_undrn_err : 1; - uint64_t instruction_fetch_error : 1; - uint64_t invalid_instruction_operand : 1; - uint64_t invalid_instruction_path : 1; - uint64_t invalid_start_vector : 1; - uint64_t fast_i2c_protocol_hang : 1; - uint64_t spare : 1; - uint64_t debug_regs_locked : 1; -#else - uint64_t debug_regs_locked : 1; - uint64_t spare : 1; - uint64_t fast_i2c_protocol_hang : 1; - uint64_t invalid_start_vector : 1; - uint64_t invalid_instruction_path : 1; - uint64_t invalid_instruction_operand : 1; - uint64_t instruction_fetch_error : 1; - uint64_t pc_stack_ovflw_undrn_err : 1; - uint64_t bad_scan_crc : 1; - uint64_t pc_overflow_underrun : 1; - uint64_t invalid_instr_code : 1; - uint64_t bad_instr_parity : 1; - uint64_t last_ret_code_oci : 3; - uint64_t oci_master_rd_parity_err : 1; - uint64_t pc_last_access : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_dbg1_t; - - - -typedef union pore_sbe_pc_stack0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack0 : 48; - uint64_t _reserved0 : 11; - uint64_t set_new_stack_pointer : 1; - uint64_t new_stack_pointer : 4; -#else - uint64_t new_stack_pointer : 4; - uint64_t set_new_stack_pointer : 1; - uint64_t _reserved0 : 11; - uint64_t pc_stack0 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_pc_stack0_t; - - - -typedef union pore_sbe_pc_stack1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack1 : 48; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t pc_stack1 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_pc_stack1_t; - - - -typedef union pore_sbe_pc_stack2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t pc_stack2 : 48; - uint64_t _reserved0 : 16; -#else - uint64_t _reserved0 : 16; - uint64_t pc_stack2 : 48; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_pc_stack2_t; - - - -typedef union pore_sbe_id_flags { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t reserved0 : 32; - uint64_t pib_parity_fail : 1; - uint64_t pib_status : 3; - uint64_t oci_parity_fail : 1; - uint64_t oci_status : 3; - uint64_t reserved1 : 8; - uint64_t ugt : 1; - uint64_t ult : 1; - uint64_t sgt : 1; - uint64_t slt : 1; - uint64_t c : 1; - uint64_t o : 1; - uint64_t n : 1; - uint64_t z : 1; - uint64_t reserved2 : 4; - uint64_t ibuf_id : 4; -#else - uint64_t ibuf_id : 4; - uint64_t reserved2 : 4; - uint64_t z : 1; - uint64_t n : 1; - uint64_t o : 1; - uint64_t c : 1; - uint64_t slt : 1; - uint64_t sgt : 1; - uint64_t ult : 1; - uint64_t ugt : 1; - uint64_t reserved1 : 8; - uint64_t oci_status : 3; - uint64_t oci_parity_fail : 1; - uint64_t pib_status : 3; - uint64_t pib_parity_fail : 1; - uint64_t reserved0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_id_flags_t; - - - -typedef union pore_sbe_data0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t data0 : 32; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t data0 : 32; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_data0_t; - - - -typedef union pore_sbe_memory_reloc { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t _reserved0 : 30; - uint64_t memory_reloc_region : 2; - uint64_t memory_reloc_base : 20; - uint64_t _reserved1 : 12; -#else - uint64_t _reserved1 : 12; - uint64_t memory_reloc_base : 20; - uint64_t memory_reloc_region : 2; - uint64_t _reserved0 : 30; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_memory_reloc_t; - - - -typedef union pore_sbe_i2c_en_param { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t i2c_engine_identifier : 4; - uint64_t reserved0 : 1; - uint64_t i2c_engine_address_range : 3; - uint64_t reserved1 : 3; - uint64_t i2c_engine_port : 5; - uint64_t reserved2 : 1; - uint64_t i2c_engine_device_id : 7; - uint64_t reserved3 : 2; - uint64_t i2c_engine_speed : 2; - uint64_t i2c_poll_threshold : 4; - uint64_t _reserved0 : 32; -#else - uint64_t _reserved0 : 32; - uint64_t i2c_poll_threshold : 4; - uint64_t i2c_engine_speed : 2; - uint64_t reserved3 : 2; - uint64_t i2c_engine_device_id : 7; - uint64_t reserved2 : 1; - uint64_t i2c_engine_port : 5; - uint64_t reserved1 : 3; - uint64_t i2c_engine_address_range : 3; - uint64_t reserved0 : 1; - uint64_t i2c_engine_identifier : 4; -#endif // _BIG_ENDIAN - } fields; -} pore_sbe_i2c_en_param_t; - - -#endif // __ASSEMBLER__ -#endif // __SBE_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/sbe_register_addresses.h b/src/ssx/pgp/registers/sbe_register_addresses.h deleted file mode 100644 index 794acea..0000000 --- a/src/ssx/pgp/registers/sbe_register_addresses.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef __SBE_REGISTER_ADDRESSES_H__ -#define __SBE_REGISTER_ADDRESSES_H__ - -// $Id: sbe_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sbe_register_addresses.h -/// \brief Symbolic addresses for the SBE unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define PORE_SBE_PIB_BASE 0x000e0000 -#define PORE_SBE_STATUS 0x000e0000 -#define PORE_SBE_CONTROL 0x000e0001 -#define PORE_SBE_RESET 0x000e0002 -#define PORE_SBE_ERROR_MASK 0x000e0003 -#define PORE_SBE_PRV_BASE_ADDRESS0 0x000e0004 -#define PORE_SBE_PRV_BASE_ADDRESS1 0x000e0005 -#define PORE_SBE_OCI_BASE_ADDRESS0 0x000e0006 -#define PORE_SBE_OCI_BASE_ADDRESS1 0x000e0007 -#define PORE_SBE_TABLE_BASE_ADDR 0x000e0008 -#define PORE_SBE_EXE_TRIGGER 0x000e0009 -#define PORE_SBE_SCRATCH0 0x000e000a -#define PORE_SBE_SCRATCH1 0x000e000b -#define PORE_SBE_SCRATCH2 0x000e000c -#define PORE_SBE_IBUF_01 0x000e000d -#define PORE_SBE_IBUF_2 0x000e000e -#define PORE_SBE_DBG0 0x000e000f -#define PORE_SBE_DBG1 0x000e0010 -#define PORE_SBE_PC_STACK0 0x000e0011 -#define PORE_SBE_PC_STACK1 0x000e0012 -#define PORE_SBE_PC_STACK2 0x000e0013 -#define PORE_SBE_ID_FLAGS 0x000e0014 -#define PORE_SBE_DATA0 0x000e0015 -#define PORE_SBE_MEMORY_RELOC 0x000e0016 -#define PORE_SBE_I2C_EN_PARAM(n) (PORE_SBE_I2C_E0_PARAM + ((PORE_SBE_I2C_E1_PARAM - PORE_SBE_I2C_E0_PARAM) * (n))) -#define PORE_SBE_I2C_E0_PARAM 0x000e0017 -#define PORE_SBE_I2C_E1_PARAM 0x000e0018 -#define PORE_SBE_I2C_E2_PARAM 0x000e0019 - -#endif // __SBE_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/sensors_firmware_registers.h b/src/ssx/pgp/registers/sensors_firmware_registers.h deleted file mode 100755 index 9cb252e..0000000 --- a/src/ssx/pgp/registers/sensors_firmware_registers.h +++ /dev/null @@ -1,668 +0,0 @@ -#ifndef __SENSORS_FIRMWARE_REGISTERS_H__ -#define __SENSORS_FIRMWARE_REGISTERS_H__ - -// $Id: sensors_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sensors_firmware_registers.h -/// \brief C register structs for the SENSORS unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union sensors_v0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts0 : 12; - uint64_t thermal_trip0 : 2; - uint64_t spare0 : 1; - uint64_t valid0 : 1; - uint64_t dts1 : 12; - uint64_t thermal_trip1 : 2; - uint64_t spare1 : 1; - uint64_t valid1 : 1; - uint64_t dts2 : 12; - uint64_t thermal_trip2 : 2; - uint64_t spare2 : 1; - uint64_t valid2 : 1; - uint64_t dts3 : 12; - uint64_t thermal_trip3 : 2; - uint64_t spare3 : 1; - uint64_t valid3 : 1; -#else - uint64_t valid3 : 1; - uint64_t spare3 : 1; - uint64_t thermal_trip3 : 2; - uint64_t dts3 : 12; - uint64_t valid2 : 1; - uint64_t spare2 : 1; - uint64_t thermal_trip2 : 2; - uint64_t dts2 : 12; - uint64_t valid1 : 1; - uint64_t spare1 : 1; - uint64_t thermal_trip1 : 2; - uint64_t dts1 : 12; - uint64_t valid0 : 1; - uint64_t spare0 : 1; - uint64_t thermal_trip0 : 2; - uint64_t dts0 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v0_t; - - - -typedef union sensors_v1 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts4 : 12; - uint64_t thermal_trip4 : 2; - uint64_t spare4 : 1; - uint64_t valid4 : 1; - uint64_t dts5 : 12; - uint64_t thermal_trip5 : 2; - uint64_t spare5 : 1; - uint64_t valid5 : 1; - uint64_t dts6 : 12; - uint64_t thermal_trip6 : 2; - uint64_t spare6 : 1; - uint64_t valid6 : 1; - uint64_t dts7 : 12; - uint64_t thermal_trip7 : 2; - uint64_t spare7 : 1; - uint64_t valid7 : 1; -#else - uint64_t valid7 : 1; - uint64_t spare7 : 1; - uint64_t thermal_trip7 : 2; - uint64_t dts7 : 12; - uint64_t valid6 : 1; - uint64_t spare6 : 1; - uint64_t thermal_trip6 : 2; - uint64_t dts6 : 12; - uint64_t valid5 : 1; - uint64_t spare5 : 1; - uint64_t thermal_trip5 : 2; - uint64_t dts5 : 12; - uint64_t valid4 : 1; - uint64_t spare4 : 1; - uint64_t thermal_trip4 : 2; - uint64_t dts4 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v1_t; - - - -typedef union sensors_v2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts8 : 12; - uint64_t thermal_trip8 : 2; - uint64_t spare8 : 1; - uint64_t valid8 : 1; - uint64_t dts9 : 12; - uint64_t thermal_trip9 : 2; - uint64_t spare9 : 1; - uint64_t valid9 : 1; - uint64_t dts10 : 12; - uint64_t thermal_trip10 : 2; - uint64_t spare10 : 1; - uint64_t valid10 : 1; - uint64_t dts12 : 12; - uint64_t thermal_trip12 : 2; - uint64_t spare12 : 1; - uint64_t valid12 : 1; -#else - uint64_t valid12 : 1; - uint64_t spare12 : 1; - uint64_t thermal_trip12 : 2; - uint64_t dts12 : 12; - uint64_t valid10 : 1; - uint64_t spare10 : 1; - uint64_t thermal_trip10 : 2; - uint64_t dts10 : 12; - uint64_t valid9 : 1; - uint64_t spare9 : 1; - uint64_t thermal_trip9 : 2; - uint64_t dts9 : 12; - uint64_t valid8 : 1; - uint64_t spare8 : 1; - uint64_t thermal_trip8 : 2; - uint64_t dts8 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v2_t; - - - -typedef union sensors_v3 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t unknown : 64; -#else - uint64_t unknown : 64; -#endif // _BIG_ENDIAN - } fields; -} sensors_v3_t; - - - -typedef union sensors_v5 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t raw_cpm0 : 12; - uint64_t spare0 : 4; - uint64_t raw_cpm1 : 12; - uint64_t spare1 : 4; - uint64_t raw_cpm2 : 12; - uint64_t spare2 : 4; - uint64_t raw_cpm3 : 12; - uint64_t spare3 : 4; -#else - uint64_t spare3 : 4; - uint64_t raw_cpm3 : 12; - uint64_t spare2 : 4; - uint64_t raw_cpm2 : 12; - uint64_t spare1 : 4; - uint64_t raw_cpm1 : 12; - uint64_t spare0 : 4; - uint64_t raw_cpm0 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v5_t; - - - -typedef union sensors_v6 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t raw_cpm4 : 12; - uint64_t spare4 : 4; - uint64_t raw_cpm5 : 12; - uint64_t spare5 : 4; - uint64_t raw_cpm6 : 12; - uint64_t spare6 : 4; - uint64_t raw_cpm7 : 12; - uint64_t spare7 : 4; -#else - uint64_t spare7 : 4; - uint64_t raw_cpm7 : 12; - uint64_t spare6 : 4; - uint64_t raw_cpm6 : 12; - uint64_t spare5 : 4; - uint64_t raw_cpm5 : 12; - uint64_t spare4 : 4; - uint64_t raw_cpm4 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v6_t; - - - -typedef union sensors_v7 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t raw_cpm8 : 12; - uint64_t spare8 : 4; - uint64_t raw_cpm9 : 12; - uint64_t spare9 : 4; - uint64_t raw_cpm10 : 12; - uint64_t spare10 : 4; - uint64_t raw_cpm11 : 12; - uint64_t spare11 : 4; -#else - uint64_t spare11 : 4; - uint64_t raw_cpm11 : 12; - uint64_t spare10 : 4; - uint64_t raw_cpm10 : 12; - uint64_t spare9 : 4; - uint64_t raw_cpm9 : 12; - uint64_t spare8 : 4; - uint64_t raw_cpm8 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v7_t; - - - -typedef union sensors_v8 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts0 : 12; - uint64_t thermal_trip0 : 2; - uint64_t spare0 : 1; - uint64_t valid0 : 1; - uint64_t dts1 : 12; - uint64_t thermal_trip1 : 2; - uint64_t spare1 : 1; - uint64_t valid1 : 1; - uint64_t dts2 : 12; - uint64_t thermal_trip2 : 2; - uint64_t spare2 : 1; - uint64_t valid2 : 1; - uint64_t encoded_cpm0 : 4; - uint64_t encoded_cpm1 : 4; - uint64_t encoded_cpm2 : 4; - uint64_t encoded_cpm3 : 4; -#else - uint64_t encoded_cpm3 : 4; - uint64_t encoded_cpm2 : 4; - uint64_t encoded_cpm1 : 4; - uint64_t encoded_cpm0 : 4; - uint64_t valid2 : 1; - uint64_t spare2 : 1; - uint64_t thermal_trip2 : 2; - uint64_t dts2 : 12; - uint64_t valid1 : 1; - uint64_t spare1 : 1; - uint64_t thermal_trip1 : 2; - uint64_t dts1 : 12; - uint64_t valid0 : 1; - uint64_t spare0 : 1; - uint64_t thermal_trip0 : 2; - uint64_t dts0 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v8_t; - - - -typedef union sensors_v9 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts4 : 12; - uint64_t thermal_trip4 : 2; - uint64_t spare4 : 1; - uint64_t valid4 : 1; - uint64_t dts5 : 12; - uint64_t thermal_trip5 : 2; - uint64_t spare5 : 1; - uint64_t valid5 : 1; - uint64_t dts6 : 12; - uint64_t thermal_trip6 : 2; - uint64_t spare6 : 1; - uint64_t valid6 : 1; - uint64_t encoded_cpm4 : 4; - uint64_t encoded_cpm5 : 4; - uint64_t encoded_cpm6 : 4; - uint64_t encoded_cpm7 : 4; -#else - uint64_t encoded_cpm7 : 4; - uint64_t encoded_cpm6 : 4; - uint64_t encoded_cpm5 : 4; - uint64_t encoded_cpm4 : 4; - uint64_t valid6 : 1; - uint64_t spare6 : 1; - uint64_t thermal_trip6 : 2; - uint64_t dts6 : 12; - uint64_t valid5 : 1; - uint64_t spare5 : 1; - uint64_t thermal_trip5 : 2; - uint64_t dts5 : 12; - uint64_t valid4 : 1; - uint64_t spare4 : 1; - uint64_t thermal_trip4 : 2; - uint64_t dts4 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v9_t; - - - -typedef union sensors_v10 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dts8 : 12; - uint64_t thermal_trip8 : 2; - uint64_t spare8 : 1; - uint64_t valid8 : 1; - uint64_t dts9 : 12; - uint64_t thermal_trip9 : 2; - uint64_t spare9 : 1; - uint64_t valid9 : 1; - uint64_t dts10 : 12; - uint64_t thermal_trip10 : 2; - uint64_t spare10 : 1; - uint64_t valid10 : 1; - uint64_t encoded_cpm8 : 4; - uint64_t encoded_cpm9 : 4; - uint64_t encoded_cpm10 : 4; - uint64_t encoded_cpm11 : 4; -#else - uint64_t encoded_cpm11 : 4; - uint64_t encoded_cpm10 : 4; - uint64_t encoded_cpm9 : 4; - uint64_t encoded_cpm8 : 4; - uint64_t valid10 : 1; - uint64_t spare10 : 1; - uint64_t thermal_trip10 : 2; - uint64_t dts10 : 12; - uint64_t valid9 : 1; - uint64_t spare9 : 1; - uint64_t thermal_trip9 : 2; - uint64_t dts9 : 12; - uint64_t valid8 : 1; - uint64_t spare8 : 1; - uint64_t thermal_trip8 : 2; - uint64_t dts8 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v10_t; - - - -typedef union sensors_v11 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dvs0 : 12; - uint64_t spare00 : 1; - uint64_t trip0 : 1; - uint64_t spare01 : 1; - uint64_t valid0 : 1; - uint64_t dvs1 : 12; - uint64_t spare10 : 1; - uint64_t trip1 : 1; - uint64_t spare11 : 1; - uint64_t valid1 : 1; - uint64_t dvs2 : 12; - uint64_t spare20 : 1; - uint64_t trip2 : 1; - uint64_t spare21 : 1; - uint64_t valid2 : 1; - uint64_t dvs3 : 12; - uint64_t spare30 : 1; - uint64_t trip3 : 1; - uint64_t spare31 : 1; - uint64_t valid3 : 1; -#else - uint64_t valid3 : 1; - uint64_t spare31 : 1; - uint64_t trip3 : 1; - uint64_t spare30 : 1; - uint64_t dvs3 : 12; - uint64_t valid2 : 1; - uint64_t spare21 : 1; - uint64_t trip2 : 1; - uint64_t spare20 : 1; - uint64_t dvs2 : 12; - uint64_t valid1 : 1; - uint64_t spare11 : 1; - uint64_t trip1 : 1; - uint64_t spare10 : 1; - uint64_t dvs1 : 12; - uint64_t valid0 : 1; - uint64_t spare01 : 1; - uint64_t trip0 : 1; - uint64_t spare00 : 1; - uint64_t dvs0 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v11_t; - - - -typedef union sensors_v12 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dvs4 : 12; - uint64_t spare40 : 1; - uint64_t trip4 : 1; - uint64_t spare41 : 1; - uint64_t valid4 : 1; - uint64_t dvs5 : 12; - uint64_t spare50 : 1; - uint64_t trip5 : 1; - uint64_t spare51 : 1; - uint64_t valid5 : 1; - uint64_t dvs6 : 12; - uint64_t spare60 : 1; - uint64_t trip6 : 1; - uint64_t spare61 : 1; - uint64_t valid6 : 1; - uint64_t dvs7 : 12; - uint64_t spare70 : 1; - uint64_t trip7 : 1; - uint64_t spare71 : 1; - uint64_t valid7 : 1; -#else - uint64_t valid7 : 1; - uint64_t spare71 : 1; - uint64_t trip7 : 1; - uint64_t spare70 : 1; - uint64_t dvs7 : 12; - uint64_t valid6 : 1; - uint64_t spare61 : 1; - uint64_t trip6 : 1; - uint64_t spare60 : 1; - uint64_t dvs6 : 12; - uint64_t valid5 : 1; - uint64_t spare51 : 1; - uint64_t trip5 : 1; - uint64_t spare50 : 1; - uint64_t dvs5 : 12; - uint64_t valid4 : 1; - uint64_t spare41 : 1; - uint64_t trip4 : 1; - uint64_t spare40 : 1; - uint64_t dvs4 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v12_t; - - - -typedef union sensors_v13 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t dvs8 : 12; - uint64_t spare80 : 1; - uint64_t trip8 : 1; - uint64_t spare81 : 1; - uint64_t valid8 : 1; - uint64_t dvs9 : 12; - uint64_t spare90 : 1; - uint64_t trip9 : 1; - uint64_t spare91 : 1; - uint64_t valid9 : 1; - uint64_t dvs10 : 12; - uint64_t spare100 : 1; - uint64_t trip10 : 1; - uint64_t spare101 : 1; - uint64_t valid10 : 1; - uint64_t dvs11 : 12; - uint64_t spare110 : 1; - uint64_t trip11 : 1; - uint64_t spare111 : 1; - uint64_t valid11 : 1; -#else - uint64_t valid11 : 1; - uint64_t spare111 : 1; - uint64_t trip11 : 1; - uint64_t spare110 : 1; - uint64_t dvs11 : 12; - uint64_t valid10 : 1; - uint64_t spare101 : 1; - uint64_t trip10 : 1; - uint64_t spare100 : 1; - uint64_t dvs10 : 12; - uint64_t valid9 : 1; - uint64_t spare91 : 1; - uint64_t trip9 : 1; - uint64_t spare90 : 1; - uint64_t dvs9 : 12; - uint64_t valid8 : 1; - uint64_t spare81 : 1; - uint64_t trip8 : 1; - uint64_t spare80 : 1; - uint64_t dvs8 : 12; -#endif // _BIG_ENDIAN - } fields; -} sensors_v13_t; - - -#endif // __ASSEMBLER__ -#endif // __SENSORS_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/sensors_register_addresses.h b/src/ssx/pgp/registers/sensors_register_addresses.h deleted file mode 100755 index c815ace..0000000 --- a/src/ssx/pgp/registers/sensors_register_addresses.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __SENSORS_REGISTER_ADDRESSES_H__ -#define __SENSORS_REGISTER_ADDRESSES_H__ - -// $Id: sensors_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sensors_register_addresses.h -/// \brief Symbolic addresses for the SENSORS unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define SENSORS_CORE_PCB_BASE 0x10050000 -#define SENSORS_V0_OFFSET 0x00000000 -#define SENSORS_CORE_V0 0x10050000 -#define SENSORS_V1_OFFSET 0x00000001 -#define SENSORS_CORE_V1 0x10050001 -#define SENSORS_V2_OFFSET 0x00000002 -#define SENSORS_CORE_V2 0x10050002 -#define SENSORS_V3_OFFSET 0x00000003 -#define SENSORS_CORE_V3 0x10050003 -#define SENSORS_V5_OFFSET 0x00000005 -#define SENSORS_CORE_V5 0x10050005 -#define SENSORS_V6_OFFSET 0x00000006 -#define SENSORS_CORE_V6 0x10050006 -#define SENSORS_V7_OFFSET 0x00000007 -#define SENSORS_CORE_V7 0x10050007 -#define SENSORS_V8_OFFSET 0x00000008 -#define SENSORS_CORE_V8 0x10050008 -#define SENSORS_V9_OFFSET 0x00000009 -#define SENSORS_CORE_V9 0x10050009 -#define SENSORS_V10_OFFSET 0x0000000a -#define SENSORS_CORE_V10 0x1005000a -#define SENSORS_V11_OFFSET 0x0000000b -#define SENSORS_CORE_V11 0x1005000b -#define SENSORS_V12_OFFSET 0x0000000c -#define SENSORS_CORE_V12 0x1005000c -#define SENSORS_V13_OFFSET 0x0000000d -#define SENSORS_CORE_V13 0x1005000d - -#endif // __SENSORS_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/sramctl_firmware_registers.h b/src/ssx/pgp/registers/sramctl_firmware_registers.h deleted file mode 100755 index c8a7c26..0000000 --- a/src/ssx/pgp/registers/sramctl_firmware_registers.h +++ /dev/null @@ -1,211 +0,0 @@ -#ifndef __SRAMCTL_FIRMWARE_REGISTERS_H__ -#define __SRAMCTL_FIRMWARE_REGISTERS_H__ - -// $Id: sramctl_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sramctl_firmware_registers.h -/// \brief C register structs for the SRAMCTL unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union sramctl_srbar { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t sram_region_qualifier : 2; - uint32_t reserved : 3; - uint32_t sram_bar_region : 8; - uint32_t _reserved0 : 19; -#else - uint32_t _reserved0 : 19; - uint32_t sram_bar_region : 8; - uint32_t reserved : 3; - uint32_t sram_region_qualifier : 2; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srbar_t; - - - -typedef union sramctl_srmr { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t sram_enable_remap : 1; - uint32_t sram_arb_en_send_all_writes : 1; - uint32_t sram_disable_lfsr : 1; - uint32_t sram_lfsr_fairness_mask : 5; - uint32_t sram_error_inject_enable : 1; - uint32_t sram_ctl_trace_en : 1; - uint32_t sram_ctl_trace_sel : 1; - uint32_t reserved : 5; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t reserved : 5; - uint32_t sram_ctl_trace_sel : 1; - uint32_t sram_ctl_trace_en : 1; - uint32_t sram_error_inject_enable : 1; - uint32_t sram_lfsr_fairness_mask : 5; - uint32_t sram_disable_lfsr : 1; - uint32_t sram_arb_en_send_all_writes : 1; - uint32_t sram_enable_remap : 1; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srmr_t; - - - -typedef union sramctl_srmap { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t reserved : 1; - uint32_t sram_remap_source : 12; - uint32_t _reserved0 : 1; - uint32_t reserved1 : 3; - uint32_t sram_remap_dest : 13; - uint32_t reserved2 : 2; -#else - uint32_t reserved2 : 2; - uint32_t sram_remap_dest : 13; - uint32_t reserved1 : 3; - uint32_t _reserved0 : 1; - uint32_t sram_remap_source : 12; - uint32_t reserved : 1; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srmap_t; - - - -typedef union sramctl_srear { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t sram_error_address : 16; - uint32_t _reserved0 : 16; -#else - uint32_t _reserved0 : 16; - uint32_t sram_error_address : 16; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srear_t; - - - -typedef union sramctl_srbv0 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t boot_vector_word0 : 32; -#else - uint32_t boot_vector_word0 : 32; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srbv0_t; - - - -typedef union sramctl_srbv1 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t boot_vector_word1 : 32; -#else - uint32_t boot_vector_word1 : 32; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srbv1_t; - - - -typedef union sramctl_srbv2 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t boot_vector_word2 : 32; -#else - uint32_t boot_vector_word2 : 32; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srbv2_t; - - - -typedef union sramctl_srbv3 { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t boot_vector_word3 : 32; -#else - uint32_t boot_vector_word3 : 32; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srbv3_t; - - - -typedef union sramctl_srchsw { - - uint32_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t chksw_wrfsm_dly_dis : 1; - uint32_t chksw_allow1_rd : 1; - uint32_t chksw_allow1_wr : 1; - uint32_t chksw_allow1_rdwr : 1; - uint32_t chksw_oci_parchk_dis : 1; - uint32_t chksw_tank_rddata_parchk_dis : 1; - uint32_t chksw_tank_sr_rderr_dis : 1; - uint32_t chksw_val_be_addr_chk_dis : 1; - uint32_t chksw_so_spare : 2; - uint32_t _reserved0 : 22; -#else - uint32_t _reserved0 : 22; - uint32_t chksw_so_spare : 2; - uint32_t chksw_val_be_addr_chk_dis : 1; - uint32_t chksw_tank_sr_rderr_dis : 1; - uint32_t chksw_tank_rddata_parchk_dis : 1; - uint32_t chksw_oci_parchk_dis : 1; - uint32_t chksw_allow1_rdwr : 1; - uint32_t chksw_allow1_wr : 1; - uint32_t chksw_allow1_rd : 1; - uint32_t chksw_wrfsm_dly_dis : 1; -#endif // _BIG_ENDIAN - } fields; -} sramctl_srchsw_t; - - -#endif // __ASSEMBLER__ -#endif // __SRAMCTL_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/sramctl_register_addresses.h b/src/ssx/pgp/registers/sramctl_register_addresses.h deleted file mode 100755 index baec5d5..0000000 --- a/src/ssx/pgp/registers/sramctl_register_addresses.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __SRAMCTL_REGISTER_ADDRESSES_H__ -#define __SRAMCTL_REGISTER_ADDRESSES_H__ - -// $Id: sramctl_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file sramctl_register_addresses.h -/// \brief Symbolic addresses for the SRAMCTL unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define SRAMCTL_OCI_BASE 0x40030000 -#define SRAMCTL_SRBAR 0x40030000 -#define SRAMCTL_SRMR 0x40030008 -#define SRAMCTL_SRMAP 0x40030010 -#define SRAMCTL_SREAR 0x40030018 -#define SRAMCTL_SRBV0 0x40030020 -#define SRAMCTL_SRBV1 0x40030028 -#define SRAMCTL_SRBV2 0x40030030 -#define SRAMCTL_SRBV3 0x40030038 -#define SRAMCTL_SRCHSW 0x40030040 - -#endif // __SRAMCTL_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/tod_firmware_registers.h b/src/ssx/pgp/registers/tod_firmware_registers.h deleted file mode 100755 index 7a700d7..0000000 --- a/src/ssx/pgp/registers/tod_firmware_registers.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef __TOD_FIRMWARE_REGISTERS_H__ -#define __TOD_FIRMWARE_REGISTERS_H__ - -// $Id: tod_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file tod_firmware_registers.h -/// \brief C register structs for the TOD unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union tod_value_reg { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t tod_incrementer : 60; - uint64_t tod_wof : 4; -#else - uint64_t tod_wof : 4; - uint64_t tod_incrementer : 60; -#endif // _BIG_ENDIAN - } fields; -} tod_value_reg_t; - - -#endif // __ASSEMBLER__ -#endif // __TOD_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/tod_register_addresses.h b/src/ssx/pgp/registers/tod_register_addresses.h deleted file mode 100755 index ac7d136..0000000 --- a/src/ssx/pgp/registers/tod_register_addresses.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __TOD_REGISTER_ADDRESSES_H__ -#define __TOD_REGISTER_ADDRESSES_H__ - -// $Id: tod_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file tod_register_addresses.h -/// \brief Symbolic addresses for the TOD unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define TOD_PIB_BASE 0x00040000 -#define TOD_VALUE_REG 0x00040020 - -#endif // __TOD_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/registers/tpc_firmware_registers.h b/src/ssx/pgp/registers/tpc_firmware_registers.h deleted file mode 100644 index 62f1c42..0000000 --- a/src/ssx/pgp/registers/tpc_firmware_registers.h +++ /dev/null @@ -1,213 +0,0 @@ -#ifndef __TPC_FIRMWARE_REGISTERS_H__ -#define __TPC_FIRMWARE_REGISTERS_H__ - -// $Id: tpc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_firmware_registers.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file tpc_firmware_registers.h -/// \brief C register structs for the TPC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - -#ifndef SIXTYFOUR_BIT_CONSTANT -#ifdef __ASSEMBLER__ -#define SIXTYFOUR_BIT_CONSTANT(x) x -#else -#define SIXTYFOUR_BIT_CONSTANT(x) x##ull -#endif -#endif - -#ifndef __ASSEMBLER__ - -#include <stdint.h> - - - - -typedef union tpc_perv_gp3 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t tp_chiplet_chiplet_en_dc : 1; - uint64_t put_in_later0 : 25; - uint64_t tp_chiplet_fence_pcb_dc : 1; - uint64_t put_in_later1 : 37; -#else - uint64_t put_in_later1 : 37; - uint64_t tp_chiplet_fence_pcb_dc : 1; - uint64_t put_in_later0 : 25; - uint64_t tp_chiplet_chiplet_en_dc : 1; -#endif // _BIG_ENDIAN - } fields; -} tpc_perv_gp3_t; - - - -typedef union tpc_gp0 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t put_in_later0 : 40; - uint64_t tc_node_id_dc : 3; - uint64_t tc_chip_id_dc : 3; - uint64_t put_in_later1 : 18; -#else - uint64_t put_in_later1 : 18; - uint64_t tc_chip_id_dc : 3; - uint64_t tc_node_id_dc : 3; - uint64_t put_in_later0 : 40; -#endif // _BIG_ENDIAN - } fields; -} tpc_gp0_t; - - - -typedef union tpc_gp0_and { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t put_in_later0 : 40; - uint64_t tc_node_id_dc : 3; - uint64_t tc_chip_id_dc : 3; - uint64_t put_in_later1 : 18; -#else - uint64_t put_in_later1 : 18; - uint64_t tc_chip_id_dc : 3; - uint64_t tc_node_id_dc : 3; - uint64_t put_in_later0 : 40; -#endif // _BIG_ENDIAN - } fields; -} tpc_gp0_and_t; - - - -typedef union tpc_gp0_or { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t put_in_later0 : 40; - uint64_t tc_node_id_dc : 3; - uint64_t tc_chip_id_dc : 3; - uint64_t put_in_later1 : 18; -#else - uint64_t put_in_later1 : 18; - uint64_t tc_chip_id_dc : 3; - uint64_t tc_node_id_dc : 3; - uint64_t put_in_later0 : 40; -#endif // _BIG_ENDIAN - } fields; -} tpc_gp0_or_t; - - - -typedef union tpc_hpr2 { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t hang_pulse_reg : 6; - uint64_t suppress_hang : 1; - uint64_t _reserved0 : 57; -#else - uint64_t _reserved0 : 57; - uint64_t suppress_hang : 1; - uint64_t hang_pulse_reg : 6; -#endif // _BIG_ENDIAN - } fields; -} tpc_hpr2_t; - - - -typedef union tpc_device_id { - - uint64_t value; - struct { -#ifdef _BIG_ENDIAN - uint32_t high_order; - uint32_t low_order; -#else - uint32_t low_order; - uint32_t high_order; -#endif // _BIG_ENDIAN - } words; - struct { -#ifdef _BIG_ENDIAN - uint64_t cfam_id : 32; - uint64_t fuse_nx_allow_crypto : 1; - uint64_t fuse_vmx_crypto_dis : 1; - uint64_t fuse_fp_throttle_en : 1; - uint64_t reserved32 : 1; - uint64_t socket_id : 3; - uint64_t chippos_id : 1; - uint64_t _reserved0 : 24; -#else - uint64_t _reserved0 : 24; - uint64_t chippos_id : 1; - uint64_t socket_id : 3; - uint64_t reserved32 : 1; - uint64_t fuse_fp_throttle_en : 1; - uint64_t fuse_vmx_crypto_dis : 1; - uint64_t fuse_nx_allow_crypto : 1; - uint64_t cfam_id : 32; -#endif // _BIG_ENDIAN - } fields; -} tpc_device_id_t; - - -#endif // __ASSEMBLER__ -#endif // __TPC_FIRMWARE_REGISTERS_H__ - diff --git a/src/ssx/pgp/registers/tpc_register_addresses.h b/src/ssx/pgp/registers/tpc_register_addresses.h deleted file mode 100644 index 50c7e97..0000000 --- a/src/ssx/pgp/registers/tpc_register_addresses.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __TPC_REGISTER_ADDRESSES_H__ -#define __TPC_REGISTER_ADDRESSES_H__ - -// $Id: tpc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_register_addresses.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file tpc_register_addresses.h -/// \brief Symbolic addresses for the TPC unit - -// *** WARNING *** - This file is generated automatically, do not edit. - - -#define TPC_PERVPIB_BASE 0x00050000 -#define TPC_PERV_GP3 0x0005001b -#define TPC_PIB_BASE 0x01000000 -#define TPC_GP0 0x01000000 -#define TPC_GP0_AND 0x01000004 -#define TPC_GP0_OR 0x01000005 -#define TPC_MISCPIB_BASE 0x010f0000 -#define TPC_HPR2 0x010f0022 -#define TPC_TPCHIP_BASE 0x000f0000 -#define TPC_DEVICE_ID 0x000f000f - -#endif // __TPC_REGISTER_ADDRESSES_H__ - diff --git a/src/ssx/pgp/ssx.mk b/src/ssx/pgp/ssx.mk deleted file mode 100755 index 402f153..0000000 --- a/src/ssx/pgp/ssx.mk +++ /dev/null @@ -1,442 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/ssx/pgp/ssx.mk $ -# -# OpenPOWER OnChipController Project -# -# Contributors Listed Below - COPYRIGHT 2014,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -# $Id: ssx.mk,v 1.2 2014/06/26 12:55:39 cmolsen Exp $ -# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssx.mk,v $ -# Make header for PgP SSX builds -# -# The application may define the following variables to control the -# build process: -# -# APP_INCLUDES : Aplication-specific header search paths -# -# DEFS : A string of -D<symbol>[=<value>] to control compilation -# -# SSX : Default ..; The path to the SSX source code. -# The default is set for building the SSX -# subdirectories. -# -# SSX_THREAD_SUPPORT : (0/1, default 1); Compile SSX thread and -# semaphore suppprt -# -# SSX_TIMER_SUPPORT : (0/1, default 1); Compile SSX timer suppprt -# -# PPC405_MMU_SUPPORT : (0/1, default 1); Compile for PPC405 simple MMU protection -# -# SIMICS_ENVIRONMENT : (0/1, current default 0); Compile for Simics -# -# SIMICS_MAGIC_PANIC : (0/1, current default 0); Use Simics Magic -# breakpoint for SSX_PANIC() instead of PowerPC trap. -# Note that Simics does not model trap correctly in -# external debug mode. -# -# GCC-O-LEVEL : The optimization level passed to GCC (default -Os). May -# also be defined empty (GCC-O-LEVEL=) to disable -# optimization. This variable can also be used to pass -# any other non-default setting to GCC, e.g. -# make GCC-O-LEVEL="-Os -fno-branch-count-reg" -# -# GCC-TOOL-PREFIX : The full path (including executable file prefixes) to -# the GCC cross-development tools to use. The default is -# "ppcnf-mcp5-" -# -# POREPATH : Overrideable path to the PORE binutils - -export OCCROOT = $(dir $(lastword $(MAKEFILE_LIST)))../../ - -ifndef SIMICS_ENVIRONMENT -SIMICS_ENVIRONMENT=0 -endif - -ifndef GCC-TOOL-PREFIX - -# CROSS_PREFIX may be set by -# op-build/openpower/package/occ/occ.mk - -ifdef CROSS_PREFIX -GCC-TOOL-PREFIX = $(CROSS_PREFIX) -else -GCC-TOOL-PREFIX = powerpc64-unknown-linux-gnu- -endif - -endif - -ifndef HOST-PREFIX -HOST-PREFIX = x86_64-pc-linux-gnu- -endif - -CC_ASM = $(GCC-TOOL-PREFIX)gcc -CC = $(TRACEPP) $(GCC-TOOL-PREFIX)gcc -LD = $(GCC-TOOL-PREFIX)ld -OBJDUMP = $(GCC-TOOL-PREFIX)objdump - -JAIL = $(HOST-PREFIX)jail - -ifndef OCC_OP_BUILD -AS = $(JAIL) /usr/bin/as -AR = $(JAIL) /usr/bin/ar -OBJCOPY = $(JAIL) /usr/bin/objcopy -CPP = $(JAIL) /usr/bin/cpp -else -AS = $(GCC-TOOL-PREFIX)as -AR = $(GCC-TOOL-PREFIX)ar -OBJCOPY = $(GCC-TOOL-PREFIX)objcopy -CPP = $(GCC-TOOL-PREFIX)cpp -endif - -ifndef POREPATH -$(warning The POREPATH variable is not defined; Defaulting to current PATH) -endif - -PORE-AS = $(POREPATH)pore-elf64-as -PORE-AS = $(POREPATH)pore-elf64-as -PORE-LD = $(POREPATH)pore-elf64-ld -PORE-OBJCOPY = $(POREPATH)pore-elf64-objcopy - -ifeq "$(SSX)" "" -SSX = .. -endif - -ifeq "$(LIB)" "" -LIB = ../../lib -endif - -ifeq "$(SSX_TIMER_SUPPORT)" "" -SSX_TIMER_SUPPORT = 1 -endif - -ifeq "$(SSX_THREAD_SUPPORT)" "" -SSX_THREAD_SUPPORT = 1 -endif - -ifeq "$(PPC405_MMU_SUPPORT)" "" -PPC405_MMU_SUPPORT = 1 -endif - -ifeq "$(PGP_ASYNC_SUPPORT)" "" -PGP_ASYNC_SUPPORT = 1 -endif - -ifndef GCC-O-LEVEL -GCC-O-LEVEL = -Os -endif - -GCC-DEFS += -DSIMICS_ENVIRONMENT=$(SIMICS_ENVIRONMENT) -GCC-DEFS += -DSSX_TIMER_SUPPORT=$(SSX_TIMER_SUPPORT) -GCC-DEFS += -DSSX_THREAD_SUPPORT=$(SSX_THREAD_SUPPORT) -GCC-DEFS += -DPPC405_MMU_SUPPORT=$(PPC405_MMU_SUPPORT) -DEFS += $(GCC-DEFS) -DPGAS_PPC=1 -DCONFIGURE_PTS_SLW=0 -PORE-DEFS += $(GCC-DEFS) - -############################################################################ - -INCLUDES += $(APP_INCLUDES) \ - -I$(SSX)/ssx -I$(SSX)/ppc32 -I$(SSX)/ppc405 \ - -I$(SSX)/pgp -I$(SSX)/pgp/registers \ - -I$(LIB) - -PIPE-CFLAGS = -pipe -Wa,-m405 - -GCC-CFLAGS += -g -Wall -fsigned-char -msoft-float \ - -m32 -mbig-endian -mcpu=405 -mmultiple -mstring \ - -meabi -msdata=eabi -ffreestanding -fno-common \ - -fno-inline-functions-called-once - -CFLAGS = -c $(GCC-CFLAGS) $(PIPE-CFLAGS) $(GCC-O-LEVEL) $(INCLUDES) -PORE-CFLAGS = -E $(GCC-CFLAGS) $(OPT) $(INCLUDES) -CPPFLAGS += -m32 -mcpu=405 -msdata=eabi -meabi -mstring -mmultiple - -############################################################################ - -# Build object code -# -# %.o: %.c - Compile C code -# -# %.o: %.S - Compile PowerPC assembler (including PGAS-PPC assembly) - -%.o: %.c - $(CC) $(CFLAGS) $(DEFS) -o $@ $< - -%.o: %.S - $(CC_ASM) $(CFLAGS) $(DEFS) -o $@ $< - -#Temporary always use PGAS PPC Assembler for compiling .pS files. -#relocatable symbols are being added to the GPE (.pS) files and -#so need new way to compile using GNU assembler. -PGAS_PPC=1 - -# use "make PGAS_PPC=1" to compile .pS file using PGAS PPC assembler. -# If PGAS_PPC=1 is not part of the make command, then GNU assembler is -# used for compiling .pS files. -ifdef PGAS_PPC - -ifneq ($(MAKE_PORE_HOOKS),) - -# This Makefile included here defines how to convert *.pS into both the object -# file and the hooks object file. - -include $(MAKE_PORE_HOOKS) - -else - -%.o: %.pS - $(CC_ASM) -x assembler-with-cpp $(PORE-CFLAGS) $(PORE-DEFS) $< | $(PORE-AS) - -o $@ -endif - -%.lst: %.pS - $(CC_ASM) -x assembler-with-cpp $(CFLAGS) $(DEFS) \ - -Wa,-al -Wa,--listing-cont-lines=20 $< > $@ - -else -%.o: %.pS - $(CPP_ASM) -x assembler-with-cpp $(PORE-CFLAGS) $(PORE-DEFS) $< | $(PORE-AS) - -o $@ -endif - -# Other useful targets -# -# %.S: %.c - See what the assembler produces from the C code, however you can -# also just look at the final disassembly. -# -# %.lst: %.S - Get an assembler listing -# -# %.cpp: %.S - Preprocess PowerPC assembler source to stdout -# -# %.cpp: %.pS - Preprocess PORE assembler source to stdout -# -# %.cpp: %.c - Preprocess C source to stdout - -%.S: %.c - $(CC) $(CFLAGS) $(DEFS) -S -o $@ $< - -%.lst: %.S - $(CC_ASM) $(CFLAGS) $(DEFS) -Wa,-al -Wa,--listing-cont-lines=20 $< > $@ - -%.cpp: %.S - $(CC_ASM) $(CFLAGS) $(DEFS) -E $< - -%.cpp: %.pS - $(CC) -x assembler-with-cpp $(CFLAGS) $(DEFS) -E $< - -%.cpp: %.c - $(CC) $(CFLAGS) $(DEFS) -E $< - -# From the GNU 'Make' manual - these scripts uses the preprocessor to -# create dependency files (*.d), then mungs them slightly to make them -# work as Make targets. The *.d files are include-ed in the -# subdirectory Makefiles. - -%.d: %.c - @set -e; rm -f $@; \ - $(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< > $@.$$$$; \ - sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \ - rm -f $@.$$$$ - -%.d: %.S - @set -e; rm -f $@; \ - $(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) $(DEFS) $< > $@.$$$$; \ - sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \ - rm -f $@.$$$$ - -%.d: %.pS - @set -e; rm -f $@; \ - $(CC_ASM) -MM $(INCLUDES) $(CPPFLAGS) -x assembler-with-cpp $(DEFS) $< > $@.$$$$; \ - sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \ - rm -f $@.$$$$ - -############################################################################ -# -# GCC Compiler flags used in these builds. Comments, or reasons for -# non-obvious choices appear in [] after the GCC documentation. -# -#`-Os' -# Optimize for size. `-Os' enables all `-O2' optimizations that do -# not typically increase code size. It also performs further -# optimizations designed to reduce code size. -# -# `-Os' disables the following optimization flags: -# -falign-functions -falign-jumps -falign-loops -# -falign-labels -freorder-blocks -freorder-blocks-and-partition -# -fprefetch-loop-arrays -ftree-vect-loop-version -# -# If you use multiple `-O' options, with or without level numbers, -# the last such option is the one that is effective. -# -#`-g' -# Produce debugging information in the operating system's native -# format (stabs, COFF, XCOFF, or DWARF 2). GDB can work with this -# debugging information. -# -# On most systems that use stabs format, `-g' enables use of extra -# debugging information that only GDB can use; this extra information -# makes debugging work better in GDB but will probably make other -# debuggers crash or refuse to read the program. If you want to -# control for certain whether to generate the extra information, use -# `-gstabs+', `-gstabs', `-gxcoff+', `-gxcoff', or `-gvms' (see -# below). -# -# GCC allows you to use `-g' with `-O'. The shortcuts taken by -# optimized code may occasionally produce surprising results: some -# variables you declared may not exist at all; flow of control may -# briefly move where you did not expect it; some statements may not -# be executed because they compute constant results or their values -# were already at hand; some statements may execute in different -# places because they were moved out of loops. -# -# Nevertheless it proves possible to debug optimized output. This -# makes it reasonable to use the optimizer for programs that might -# have bugs. -# -#`-Wall' -# Turns on all optional warnings which are desirable for normal code. -# At present this is `-Wcomment', `-Wtrigraphs', `-Wmultichar' and a -# warning about integer promotion causing a change of sign in `#if' -# expressions. Note that many of the preprocessor's warnings are on -# by default and have no options to control them. -# -#`-Werror' -# Make all warnings into errors. -# -#`-fsigned-char' -# Let the type `char' be signed, like `signed char'. -# -# Note that this is equivalent to `-fno-unsigned-char', which is the -# negative form of `-funsigned-char'. Likewise, the option -# `-fno-signed-char' is equivalent to `-funsigned-char'. -# -#`-msoft-float' -# Generate output containing library calls for floating point. -# *Warning:* the requisite libraries are not available for all ARM -# targets. Normally the facilities of the machine's usual C -# compiler are used, but this cannot be done directly in -# cross-compilation. You must make your own arrangements to provide -# suitable library functions for cross-compilation. -# -# `-msoft-float' changes the calling convention in the output file; -# therefore, it is only useful if you compile _all_ of a program with -# this option. In particular, you need to compile `libgcc.a', the -# library that comes with GCC, with `-msoft-float' in order for this -# to work. -# -#`-pipe' -# Use pipes rather than temporary files for communication between the -# various stages of compilation. This fails to work on some systems -# where the assembler is unable to read from a pipe; but the GNU -# assembler has no trouble. -# -#`-mmultiple' -#`-mno-multiple' -# Generate code that uses (does not use) the load multiple word -# instructions and the store multiple word instructions. These -# instructions are generated by default on POWER systems, and not -# generated on PowerPC systems. Do not use `-mmultiple' on little -# endian PowerPC systems, since those instructions do not work when -# the processor is in little endian mode. The exceptions are PPC740 -# and PPC750 which permit the instructions usage in little endian -# mode. -# -#`-mstring' -#`-mno-string' -# Generate code that uses (does not use) the load string instructions -# and the store string word instructions to save multiple registers -# and do small block moves. These instructions are generated by -# default on POWER systems, and not generated on PowerPC systems. -# Do not use `-mstring' on little endian PowerPC systems, since those -# instructions do not work when the processor is in little endian -# mode. The exceptions are PPC740 and PPC750 which permit the -# instructions usage in little endian mode. -# -#`-meabi' -#`-mno-eabi' -# On System V.4 and embedded PowerPC systems do (do not) adhere to -# the Embedded Applications Binary Interface (eabi) which is a set of -# modifications to the System V.4 specifications. Selecting `-meabi' -# means that the stack is aligned to an 8 byte boundary, a function -# `__eabi' is called to from `main' to set up the eabi environment, -# and the `-msdata' option can use both `r2' and `r13' to point to -# two separate small data areas. Selecting `-mno-eabi' means that -# the stack is aligned to a 16 byte boundary, do not call an -# initialization function from `main', and the `-msdata' option will -# only use `r13' to point to a single small data area. The `-meabi' -# option is on by default if you configured GCC using one of the -# `powerpc*-*-eabi*' options. -# -# [We elected to use the EABI to reduce stack requirements and possibly reduce -# code size and improve performance. In practice it probably has little real -# effect since the code size and performance improvements only apply to global -# variables <= 8 bytes, and our applications will not have deeply nested call -# trees. Still, much of the assembler code requires/assumes the EABI is in -# place, and it certainly doesn't hurt anything to use it.] -# -#`-msdata=eabi' -# On System V.4 and embedded PowerPC systems, put small initialized -# `const' global and static data in the `.sdata2' section, which is -# pointed to by register `r2'. Put small initialized non-`const' -# global and static data in the `.sdata' section, which is pointed -# to by register `r13'. Put small uninitialized global and static -# data in the `.sbss' section, which is adjacent to the `.sdata' -# section. The `-msdata=eabi' option is incompatible with the -# `-mrelocatable' option. The `-msdata=eabi' option also sets the -# `-memb' option. -# -#`-memb' -# On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags -# header to indicate that `eabi' extended relocations are used. -# -#`-ffreestanding' -# Assert that compilation takes place in a freestanding environment. -# This implies `-fno-builtin'. A freestanding environment is one -# in which the standard library may not exist, and program startup -# may not necessarily be at `main'. The most obvious example is an -# OS kernel. This is equivalent to `-fno-hosted'. -# -#`-fno-common' -# In C, allocate even uninitialized global variables in the data -# section of the object file, rather than generating them as common -# blocks. This has the effect that if the same variable is declared -# (without `extern') in two different compilations, you will get an -# error when you link them. The only reason this might be useful is -# if you wish to verify that the program will work on other systems -# which always work this way. -# -# [It is always assumed to be an error if two C source files declare global -# variables of the same name, since it is not clear whether this was intended -# or not.] -# -#`-finline-functions-called-once' -#`-fno-inline-functions-called-once' -# Consider all `static' functions called once for inlining into their -# caller even if they are not marked `inline'. If a call to a given -# function is integrated, then the function is not output as -# assembler code in its own right. -# -# Enabled if `-funit-at-a-time' is enabled. -# -# [There is a 'bug' in GCC related to inlining static, called-once -# functions. GCC allocates stack space in the caller for the stacks of ALL -# inlined functions of this type, even if they are called sequentially, -# leading in some cases to kilobytes of wasted stack space. If you want to -# inline a static called-once function you will need to explicity declare it -# as 'inline'.] - - diff --git a/src/ssx/pgp/ssx_port.h b/src/ssx/pgp/ssx_port.h deleted file mode 100755 index 613ac43..0000000 --- a/src/ssx/pgp/ssx_port.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __SSX_PORT_H__ -#define __SSX_PORT_H__ - -// $Id: ssx_port.h,v 1.1.1.1 2013/12/11 21:03:22 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssx_port.h,v $ -//----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//----------------------------------------------------------------------------- - -/// \file ssx_port.h -/// \brief The top-level PGP environment header for SSX. - -#define CHIP_PGP - -#include "ppc405.h" - -#endif /* __SSX_PORT_H__ */ diff --git a/src/ssx/pgp/ssxpgpfiles.mk b/src/ssx/pgp/ssxpgpfiles.mk deleted file mode 100755 index dd12da1..0000000 --- a/src/ssx/pgp/ssxpgpfiles.mk +++ /dev/null @@ -1,37 +0,0 @@ -# $Id: ssxpgpfiles.mk,v 1.4 2014/06/26 12:56:28 cmolsen Exp $ -# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/ssxpgpfiles.mk,v $ -# @file ssxpgpfiles.mk -# -# @brief mk for including pgp object files -# -# @page ChangeLogs Change Logs -# @section ssxpgpfiles.mk -# @verbatim -# -# -# Change Log ****************************************************************** -# Flag Defect/Feature User Date Description -# ------ -------------- ---------- ------------ ----------- -# @pb00E pbavari 03/11/2012 Makefile ODE support -# -# @endverbatim -# -########################################################################## -# Object Files -########################################################################## -PGP-C-SOURCES = pgp_init.c pgp_irq_init.c pgp_pmc.c pgp_ocb.c pgp_pba.c \ - pgp_id.c pgp_centaur.c -PGP-S-SOURCES = pgp_cache.S - -PGP-TIMER-C-SOURCES = -PGP-TIMER-S-SOURCES = - -PGP-THREAD-C-SOURCES = -PGP-THREAD-S-SOURCES = - -PGP-ASYNC-C-SOURCES = pgp_async.c pgp_async_pore.c pgp_async_ocb.c \ - pgp_async_pba.c -PGP-ASYNC-S-SOURCES = - -PGP_OBJECTS += $(PGP-C-SOURCES:.c=.o) $(PGP-S-SOURCES:.S=.o) - diff --git a/src/ssx/ppc32/Makefile b/src/ssx/ppc32/Makefile index 81776dd..67541ac 100755..100644 --- a/src/ssx/ppc32/Makefile +++ b/src/ssx/ppc32/Makefile @@ -1,30 +1,44 @@ -# $Id: Makefile,v 1.2 2013/12/12 16:12:37 bcbrock Exp $ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ppc32/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG # This Makefile is designed to be invoked with the -I argument set to -# the location of the "ssx.mk" for the build. +# the location of the "img_defs.mk" for the build. # -# This makefile creates the libppc32.a library. - -SSX = .. -PGP = $(SSX)/pgp - -include $(PGP)/ssx.mk +include img_defs.mk include ssxppc32files.mk +OBJS := $(addprefix $(OBJDIR)/, $(PPC32_OBJECTS)) +all: $(OBJS) -libppc32.a: ${PPC32_OBJECTS} - $(AR) crs libppc32.a ${PPC32_OBJECTS} +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) -.PHONY : clean -clean: - rm -f *.o *.a *.d *.d.* - - -# This clause prevents the dependencies from creating errors during a clean. -# Whenever a header file is added or deleted it will likely be necessary to -# 'make clean' to force recomputation of dependencies. +$(OBJDIR): + mkdir -p $(OBJDIR) ifneq ($(MAKECMDGOALS),clean) -include $(PPC32_OBJECTS:.o=.d) -endif
\ No newline at end of file +include $(OBJS:.o=.d) +endif + diff --git a/src/ssx/ppc32/div64.S b/src/ssx/ppc32/div64.S index 04ee008..cc6309b 100755..100644 --- a/src/ssx/ppc32/div64.S +++ b/src/ssx/ppc32/div64.S @@ -1,7 +1,29 @@ -// $Id: div64.S,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/div64.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/div64.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/gnu/stubs-32.h b/src/ssx/ppc32/gnu/stubs-32.h deleted file mode 100644 index 3da2fb2..0000000 --- a/src/ssx/ppc32/gnu/stubs-32.h +++ /dev/null @@ -1,21 +0,0 @@ -/* This file is automatically generated. - It defines a symbol `__stub_FUNCTION' for each function - in the C library which is a stub, meaning it will fail - every time called, usually setting errno to ENOSYS. */ - -#ifdef _LIBC - #error Applications may not define the macro _LIBC -#endif - -#define __stub___kernel_rem_pio2l -#define __stub_chflags -#define __stub_fattach -#define __stub_fchflags -#define __stub_fdetach -#define __stub_gtty -#define __stub_lchmod -#define __stub_revoke -#define __stub_setlogin -#define __stub_sigreturn -#define __stub_sstk -#define __stub_stty diff --git a/src/ssx/ppc32/ppc32.h b/src/ssx/ppc32/ppc32.h index e7f7bf8..0ba8a46 100755..100644 --- a/src/ssx/ppc32/ppc32.h +++ b/src/ssx/ppc32/ppc32.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/ppc32.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC32_H__ #define __PPC32_H__ -// $Id: ppc32.h,v 1.2 2014/03/14 15:11:46 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/ppc32_asm.h b/src/ssx/ppc32/ppc32_asm.h index 0207c22..b681e88 100755..100644 --- a/src/ssx/ppc32/ppc32_asm.h +++ b/src/ssx/ppc32/ppc32_asm.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/ppc32_asm.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC32_ASM_H__ #define __PPC32_ASM_H__ -// $Id: ppc32_asm.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_asm.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/ppc32_gcc.c b/src/ssx/ppc32/ppc32_gcc.c index a00ab48..8fe9bf5 100755..100644 --- a/src/ssx/ppc32/ppc32_gcc.c +++ b/src/ssx/ppc32/ppc32_gcc.c @@ -1,7 +1,29 @@ -// $Id: ppc32_gcc.c,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_gcc.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/ppc32_gcc.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/ppc32_gcc.h b/src/ssx/ppc32/ppc32_gcc.h index 1925107..7931fcd 100755..100644 --- a/src/ssx/ppc32/ppc32_gcc.h +++ b/src/ssx/ppc32/ppc32_gcc.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/ppc32_gcc.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC32_GCC_H__ #define __PPC32_GCC_H__ -// $Id: ppc32_gcc.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ppc32_gcc.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/savegpr.S b/src/ssx/ppc32/savegpr.S index 854f22b..4dbfef0 100755..100644 --- a/src/ssx/ppc32/savegpr.S +++ b/src/ssx/ppc32/savegpr.S @@ -1,7 +1,29 @@ -// $Id: savegpr.S,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/savegpr.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc32/savegpr.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc32/ssxppc32files.mk b/src/ssx/ppc32/ssxppc32files.mk index 8697550..7987265 100755..100644 --- a/src/ssx/ppc32/ssxppc32files.mk +++ b/src/ssx/ppc32/ssxppc32files.mk @@ -1,5 +1,27 @@ -# $Id: ssxppc32files.mk,v 1.2 2014/06/26 12:58:31 cmolsen Exp $ -# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc32/ssxppc32files.mk,v $ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ppc32/ssxppc32files.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG # @file ssxppc32files.mk # # @brief mk for including ppc32 object files diff --git a/src/ssx/ppc405/Makefile b/src/ssx/ppc405/Makefile index 0391504..82391e2 100755..100644 --- a/src/ssx/ppc405/Makefile +++ b/src/ssx/ppc405/Makefile @@ -1,12 +1,30 @@ -# $Id: Makefile,v 1.2 2013/12/12 16:12:38 bcbrock Exp $ - +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ppc405/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG # This Makefile is designed to be invoked with the -I argument set to -# the location of the "ssx.mk" for the build - -SSX = .. -PGP = $(SSX)/pgp - -include $(PGP)/ssx.mk +# the location of the "img_defs.mk" for the build +include img_defs.mk include ssxppc405files.mk ifeq "$(SSX_TIMER_SUPPORT)" "1" @@ -21,17 +39,16 @@ ifeq "$(PPC405_MMU_SUPPORT)" "1" PPC405_OBJECTS += ${PPC405-MMU-C-SOURCES:.c=.o} ${PPC405-MMU-S-SOURCES:.S=.o} endif +OBJS := $(addprefix $(OBJDIR)/, $(PPC405_OBJECTS)) -all: local - $(MAKE) -I ../pgp -C ../ppc32 +all: $(OBJS) -local: $(PPC405_OBJECTS) +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) -.PHONY : clean -clean: - rm -f *.o *.d *.d.* - $(MAKE) -I ../pgp -C ../ppc32 clean +$(OBJDIR): + mkdir -p $(OBJDIR) ifneq ($(MAKECMDGOALS),clean) -include $(PPC405_OBJECTS:.o=.d) -endif
\ No newline at end of file +include $(OBJS:.o=.d) +endif + diff --git a/src/ssx/ppc405/ppc405.h b/src/ssx/ppc405/ppc405.h index 18b0c53..079831d 100755..100644 --- a/src/ssx/ppc405/ppc405.h +++ b/src/ssx/ppc405/ppc405.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_H__ #define __PPC405_H__ -// $Id: ppc405.h,v 1.3 2014/02/03 01:30:42 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -19,7 +41,7 @@ // documentation on the D-cache tag sizes doesn't make any sense to me - it // claims the tag size is constant regardless of the size of the cache. // However the Xilinx documentation for their 405 core (which has the same -// 16KB cache as PgP) is consistent with the way the DCACHE_TAG_MASK is +// 16KB cache as OCCHW) is consistent with the way the DCACHE_TAG_MASK is // defined here. #define CACHE_LINE_SIZE 32 @@ -37,7 +59,7 @@ #define DCACHE_TAG_MASK \ ((0xffffffff << (LOG_DCACHE_SIZE - LOG_DCACHE_WAYS)) & 0xffffffff) -#ifdef CHIP_PGP +#ifdef HWMACRO_OCC #define ICACHE_SIZE (16 * 1024) #define DCACHE_SIZE (16 * 1024) @@ -68,8 +90,8 @@ #endif -#ifdef CHIP_PGP -#include "pgp.h" +#ifdef HWMACRO_OCC +#include "occhw.h" #endif #include "ppc32.h" diff --git a/src/ssx/ppc405/ppc405_boot.S b/src/ssx/ppc405/ppc405_boot.S index 1f4a4f9..7ffe7dd 100755..100644 --- a/src/ssx/ppc405/ppc405_boot.S +++ b/src/ssx/ppc405/ppc405_boot.S @@ -1,7 +1,29 @@ -// $Id: ppc405_boot.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_boot.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_boot.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_breakpoint.S b/src/ssx/ppc405/ppc405_breakpoint.S index 3adbd13..ce3aef2 100644 --- a/src/ssx/ppc405/ppc405_breakpoint.S +++ b/src/ssx/ppc405/ppc405_breakpoint.S @@ -1,7 +1,29 @@ -// $Id: ppc405_breakpoint.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_breakpoint.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_breakpoint.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_cache.h b/src/ssx/ppc405/ppc405_cache.h index 02bd4f5..2d78425 100755..100644 --- a/src/ssx/ppc405/ppc405_cache.h +++ b/src/ssx/ppc405/ppc405_cache.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_cache.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_CACHE_H__ #define __PPC405_CACHE_H__ -// $Id: ppc405_cache.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_cache_core.c b/src/ssx/ppc405/ppc405_cache_core.c index a03f5e2..36056e2 100755..100644 --- a/src/ssx/ppc405/ppc405_cache_core.c +++ b/src/ssx/ppc405/ppc405_cache_core.c @@ -1,7 +1,29 @@ -// $Id: ppc405_cache_core.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_cache_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_cache_init.S b/src/ssx/ppc405/ppc405_cache_init.S index c4bed0e..a8ef79c 100755..100644 --- a/src/ssx/ppc405/ppc405_cache_init.S +++ b/src/ssx/ppc405/ppc405_cache_init.S @@ -1,7 +1,29 @@ -// $Id: ppc405_cache_init.S,v 1.3 2014/06/26 12:59:35 cmolsen Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_cache_init.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_cache_init.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_context.h b/src/ssx/ppc405/ppc405_context.h index 3019358..a820a99 100755..100644 --- a/src/ssx/ppc405/ppc405_context.h +++ b/src/ssx/ppc405/ppc405_context.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_context.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_CONTEXT_H__ #define __PPC405_CONTEXT_H__ -// $Id: ppc405_context.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_context.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -105,7 +127,7 @@ // // When SSX is initialized USPRG0 is initialized to 0. When thread-mode is // entered (by ssx_start_threads()) bit 24 is set to 1. In order to support -// PgP/OCC firmware, once initialized (with ssx_initialize()) SSX can simply +// OCC firmware, once initialized (with ssx_initialize()) SSX can simply // handle interrupts, reverting back to the non-thread-mode idle loop when // there's nothing to do. // @@ -337,11 +359,11 @@ .macro _save_update_kernel_context critical, irqreg, ctxreg - .if \critical - SSX_TRACE_CRITICAL_IRQ_ENTRY \irqreg, \ctxreg - .else - SSX_TRACE_NONCRITICAL_IRQ_ENTRY \irqreg, \ctxreg - .endif + //.if \critical + //SSX_TRACE_CRITICAL_IRQ_ENTRY \irqreg, \ctxreg + //.else + //SSX_TRACE_NONCRITICAL_IRQ_ENTRY \irqreg, \ctxreg + //.endif mfusprg0 \ctxreg stw \ctxreg, SSX_FAST_CTX_KERNEL_CTX(%r1) @@ -363,13 +385,13 @@ .macro _ssx_fast_ctx_pop_exit critical - .if SSX_KERNEL_TRACE_ENABLE - .if \critical - bl __ssx_trace_critical_irq_exit - .else - bl __ssx_trace_noncritical_irq_exit - .endif - .endif + //.if SSX_KERNEL_TRACE_ENABLE + //.if \critical + //bl __ssx_trace_critical_irq_exit + //.else + //bl __ssx_trace_noncritical_irq_exit + //.endif + //.endif lwz %r3, SSX_FAST_CTX_KERNEL_CTX(%r1) mtusprg0 %r3 diff --git a/src/ssx/ppc405/ppc405_core.c b/src/ssx/ppc405/ppc405_core.c index 5df0967..c3a82d3 100755..100644 --- a/src/ssx/ppc405/ppc405_core.c +++ b/src/ssx/ppc405/ppc405_core.c @@ -1,7 +1,29 @@ -// $Id: ppc405_core.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -17,6 +39,57 @@ #include "ssx.h" +// Even though the external timebase is only a 32 bit register, we emulate +// a 64 bit timebase by keeping the upper 32 bits in SRAM. +volatile SsxTimebase ppc405_64bit_ext_timebase = 0; + +#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE +typedef union +{ + struct + { + uint32_t tbu; + uint32_t tbl; + }; + SsxTimebase tb64; +} SsxExtTimebase; + + +SsxTimebase ssx_ext_timebase_get(void) +{ + SsxExtTimebase snapshot; + volatile SsxExtTimebase *cur_tb = (SsxExtTimebase*)&ppc405_64bit_ext_timebase; + uint32_t tbr; + uint32_t high; + + //read our in-memory timebase accumulator. + //NOTE: 64 bit reads are not atomic on the ppc405. This means that the + //accumulator can be updated between reading the upper 32 bits and lower + //32 bits. It's ok if only the lower 32 bits changed, but if the upper + //32 bits changed, then we will report the wrong time stamp. Therefore, + //we check the upper 32 bits after reading the lower 32 bits to make sure + //it hasn't changed. + do + { + snapshot.tbu = cur_tb->tbu; + snapshot.tbl = cur_tb->tbl; + high = cur_tb->tbu; + }while(snapshot.tbu != high); + + //Now read the external timebase register + tbr = in32(OCB_OTBR); + + //Check if we need to increment the upper 32 bits + if(tbr < snapshot.tbl) + { + snapshot.tbu++; + } + snapshot.tbl = tbr; + return snapshot.tb64; +} + +#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */ + /// Get the 64-bit timebase following the PowerPC protocol /// /// Note that the only way to guarantee that the value returned is the value @@ -161,6 +234,10 @@ __ssx_schedule_hardware_timeout(SsxTimebase timeout) } mtspr(SPRN_PIT, pit); + +#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE + ppc405_64bit_ext_timebase = ssx_ext_timebase_get(); +#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */ } } diff --git a/src/ssx/ppc405/ppc405_dcr.h b/src/ssx/ppc405/ppc405_dcr.h index 1f389bf..b7e6207 100755..100644 --- a/src/ssx/ppc405/ppc405_dcr.h +++ b/src/ssx/ppc405/ppc405_dcr.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_dcr.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_DCR_H__ #define __PPC405_DCR_H__ -// $Id: ppc405_dcr.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_dcr.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_exceptions.S b/src/ssx/ppc405/ppc405_exceptions.S index c8be2e3..b4a1419 100755..100644 --- a/src/ssx/ppc405/ppc405_exceptions.S +++ b/src/ssx/ppc405/ppc405_exceptions.S @@ -1,7 +1,29 @@ -// $Id: ppc405_exceptions.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_exceptions.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_exceptions.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -24,7 +46,7 @@ /// /// .vectors_0000 - Empty section for adding image header /// -/// .vectors_0100 - From 0x0100 to 0x0bff. The beginning of the table through +/// .vectors_0100 - From 0x0100 to 0x081f. The beginning of the table through /// the large space prior to the system call vector. /// /// .vectors_0c00 - From 0x0c00 to 0x0eff. This is a moderately large area @@ -47,6 +69,9 @@ .nolist #include "ssx.h" .list + +## declare and initializes global variables that hold external irq config data + .occhw_irq_cfg_bitmaps ### **************************************************************************** ### .vectors_0000 - Empty section ( Image header will be placed in this section @@ -59,6 +84,10 @@ __vectors: __vectors_0000: + // FIXME: This is just a quick hack to get SSX running on simics -- grm + .global __ssx_boot + b __ssx_boot + ### **************************************************************************** ### .vectors_0100 ### **************************************************************************** @@ -341,7 +370,7 @@ __ssx_idle_thread: __ssx_idle_thread_from_bootloader: li %r3, SSX_THREADS - SSX_TRACE_THREAD_SWITCH %r3, %r4 + //SSX_TRACE_THREAD_SWITCH %r3, %r4 _lwzsd %r3, __ssx_thread_machine_context_default _oriwa %r3, %r3, MSR_WE mtmsr %r3 @@ -587,6 +616,11 @@ __fpu_unavailable: .org __fpu_unavailable + 0x20 +### **************************************************************************** +### .irq_exit_traces +### **************************************************************************** + + .section .irq_exit_traces, "ax", @progbits ## Exit traces are moved here because the code area (0x100 bytes) ## reserved for individual interrupts is overflowing when tracing is @@ -595,11 +629,11 @@ __fpu_unavailable: ## where we can use any of the fast registers. __ssx_trace_critical_irq_exit: - SSX_TRACE_CRITICAL_IRQ_EXIT %r3, %r4 + //SSX_TRACE_CRITICAL_IRQ_EXIT %r3, %r4 blr __ssx_trace_noncritical_irq_exit: - SSX_TRACE_NONCRITICAL_IRQ_EXIT %r3, %r4 + //SSX_TRACE_NONCRITICAL_IRQ_EXIT %r3, %r4 blr ## >>>>>>>>>> Pack .vectors_0100 here. Room for ~900 bytes. <<<<<<<<<< @@ -673,7 +707,7 @@ __ssx_next_thread_resume: _ssx_vol_fast_ctx_pop SSX_THREAD_CONTEXT, SSX_NONCRITICAL _lbzsd %r3, __ssx_next_priority - SSX_TRACE_THREAD_SWITCH %r3, %r4 + //SSX_TRACE_THREAD_SWITCH %r3, %r4 ori %r3, %r3, PPC405_THREAD_MODE mtusprg0 %r3 diff --git a/src/ssx/ppc405/ppc405_init.c b/src/ssx/ppc405/ppc405_init.c index e818737..8405a4a 100755..100644 --- a/src/ssx/ppc405/ppc405_init.c +++ b/src/ssx/ppc405/ppc405_init.c @@ -1,7 +1,29 @@ -// $Id: ppc405_init.c,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -14,6 +36,7 @@ /// no longer needed by the application after initialization. #include "ssx.h" +#include "ssx_trace.h" // Note that __ppc405_system_setup() is called from the SSX bootloader early // in the initialization, at a point before the aplication has enabled @@ -26,7 +49,7 @@ __ppc405_system_setup() // Initialize the interrupt vectors. - for (irq = 0; irq < PPC405_IRQS; irq++) { + for (irq = 0; irq < EXTERNAL_IRQS; irq++) { __ppc405_irq_handlers[irq].handler = __ppc405_default_irq_handler; __ppc405_irq_handlers[irq].arg = 0; } @@ -53,11 +76,18 @@ __ppc405_system_setup() or_spr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS); - // Call system-specific setup +#if SSX_TIMER_SUPPORT +#if SSX_TRACE_SUPPORT +extern SsxTraceBuffer g_ssx_trace_buf; + //set the instance id + g_ssx_trace_buf.instance_id = OCCHW_INST_ID_PPC; +#endif /* SSX_TRACE_SUPPORT */ +#endif /* SSX_TIMER_SUPPORT */ -#ifdef CHIP_PGP - void __pgp_setup(); - __pgp_setup(); +#ifdef HWMACRO_OCC + // Call system-specific setup + void __occhw_setup(); + __occhw_setup(); #endif } diff --git a/src/ssx/ppc405/ppc405_irq.h b/src/ssx/ppc405/ppc405_irq.h index d85e9ce..0ffd2c1 100755..100644 --- a/src/ssx/ppc405/ppc405_irq.h +++ b/src/ssx/ppc405/ppc405_irq.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_irq.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_IRQ_H__ #define __PPC405_IRQ_H__ -// $Id: ppc405_irq.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -16,7 +38,7 @@ /// inherently non-portable, however SSX defines APIs that may be useful among /// different machines. /// -/// The interrupt controllers in PPC405 ASICS and PGP allow interrupts to be +/// The interrupt controllers in PPC405 ASICS and OCCHW allow interrupts to be /// programmed as critical or non-critical, with programmable polarity and /// edge or level sensitivity. @@ -259,8 +281,8 @@ asm("b __ssx_irq_full_mode_exit"); // It's hard to be portable and get all of the definitions and headers in the // correct order. We need to bring in the system IRQ header here. -#ifdef CHIP_PGP -#include "pgp_irq.h" +#ifdef HWMACRO_OCC +#include "occhw_irq.h" #endif /// \page ppc405_irq_macros_page PPC405 SSX IRQ Assembler Macros @@ -323,7 +345,7 @@ typedef struct { /// Interrupt handlers for real (implemented interrupts) UNLESS__PPC405_IRQ_CORE_C__(extern) -Ppc405IrqHandler __ppc405_irq_handlers[PPC405_IRQS]; +Ppc405IrqHandler __ppc405_irq_handlers[EXTERNAL_IRQS]; /// The 'phantom interrupt' handler diff --git a/src/ssx/ppc405/ppc405_irq_core.c b/src/ssx/ppc405/ppc405_irq_core.c index 3cd7469..ce1c924 100755..100644 --- a/src/ssx/ppc405/ppc405_irq_core.c +++ b/src/ssx/ppc405/ppc405_irq_core.c @@ -1,7 +1,29 @@ -// $Id: ppc405_irq_core.c,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_irq_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_irq_init.c b/src/ssx/ppc405/ppc405_irq_init.c index da33947..321d238 100755..100644 --- a/src/ssx/ppc405/ppc405_irq_init.c +++ b/src/ssx/ppc405/ppc405_irq_init.c @@ -1,7 +1,29 @@ -// $Id: ppc405_irq_init.c,v 1.2 2014/02/03 01:30:42 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_irq_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_irq_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_lib_core.c b/src/ssx/ppc405/ppc405_lib_core.c index 3086efb..334f08b 100755..100644 --- a/src/ssx/ppc405/ppc405_lib_core.c +++ b/src/ssx/ppc405/ppc405_lib_core.c @@ -1,7 +1,29 @@ -// $Id: ppc405_lib_core.c,v 1.2 2014/06/26 13:00:11 cmolsen Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_lib_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_lib_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_mmu.c b/src/ssx/ppc405/ppc405_mmu.c index 1affc67..3509c36 100755..100644 --- a/src/ssx/ppc405/ppc405_mmu.c +++ b/src/ssx/ppc405/ppc405_mmu.c @@ -1,7 +1,29 @@ -// $Id: ppc405_mmu.c,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_mmu.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -349,7 +371,7 @@ ppc405_mmu_unmap(Ppc405MmuMap *map) /// \param[in] i_map An optional pointer. If NULL (0) then a full report is /// printed. If non-null then only the entries recorded in the \a i_map are /// printed. - +#if 0 void ppc405_mmu_report(FILE* i_stream, Ppc405MmuMap* i_map) { @@ -418,7 +440,7 @@ ppc405_mmu_report(FILE* i_stream, Ppc405MmuMap* i_map) fprintf(i_stream, "------------------------------------------------------------------------------\n"); } - +#endif /// Perform a memcpy() without address translation (protection) /// diff --git a/src/ssx/ppc405/ppc405_mmu.h b/src/ssx/ppc405/ppc405_mmu.h index cd7e249..058143c 100755..100644 --- a/src/ssx/ppc405/ppc405_mmu.h +++ b/src/ssx/ppc405/ppc405_mmu.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_mmu.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_MMU_H__ #define __PPC405_MMU_H__ -// $Id: ppc405_mmu.h,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_mmu_asm.S b/src/ssx/ppc405/ppc405_mmu_asm.S index 1118779..d5fefd3 100755..100644 --- a/src/ssx/ppc405/ppc405_mmu_asm.S +++ b/src/ssx/ppc405/ppc405_mmu_asm.S @@ -1,7 +1,29 @@ -// $Id: ppc405_mmu_asm.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_mmu_asm.S,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_mmu_asm.S $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_msr.h b/src/ssx/ppc405/ppc405_msr.h index 645a052..213058f 100755..100644 --- a/src/ssx/ppc405/ppc405_msr.h +++ b/src/ssx/ppc405/ppc405_msr.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_msr.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_MSR_H__ #define __PPC405_MSR_H__ -// $Id: ppc405_msr.h,v 1.1.1.1 2013/12/11 21:03:26 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_msr.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_spr.h b/src/ssx/ppc405/ppc405_spr.h index ede91cb..b73eb90 100755..100644 --- a/src/ssx/ppc405/ppc405_spr.h +++ b/src/ssx/ppc405/ppc405_spr.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ppc405_spr.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PPC405_SPR_H__ #define __PPC405_SPR_H__ -// $Id: ppc405_spr.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_spr.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ppc405_thread_init.S b/src/ssx/ppc405/ppc405_thread_init.S index 47f5813..dca6184 100755..100644 --- a/src/ssx/ppc405/ppc405_thread_init.S +++ b/src/ssx/ppc405/ppc405_thread_init.S @@ -1,4 +1,27 @@ -// $Id: ppc405_thread_init.S,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ppc405/ppc405_thread_init.S $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG /// \file ppc405_thread_init.S /// \brief PPC405-specific thread initialization @@ -26,9 +49,9 @@ void __ssx_thread_context_initialize(SsxThread *thread, SsxThreadRoutine thread_routine, void *private); -#endif// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ppc405_thread_init.S,v $ +#endif //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ssx_port_types.h b/src/ssx/ppc405/ssx_port_types.h index f57951d..4040b4a 100755..100644 --- a/src/ssx/ppc405/ssx_port_types.h +++ b/src/ssx/ppc405/ssx_port_types.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ppc405/ssx_port_types.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __SSX_PORT_TYPES_H__ #define __SSX_PORT_TYPES_H__ -// $Id: ssx_port_types.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ssx_port_types.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ppc405/ssxppc405files.mk b/src/ssx/ppc405/ssxppc405files.mk index 72d5ecb..c91560e 100755..100644 --- a/src/ssx/ppc405/ssxppc405files.mk +++ b/src/ssx/ppc405/ssxppc405files.mk @@ -1,5 +1,27 @@ -# $Id: ssxppc405files.mk,v 1.2 2014/06/26 13:00:55 cmolsen Exp $ -# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ppc405/ssxppc405files.mk,v $ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ppc405/ssxppc405files.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG # @file ssxppc405files.mk # # @brief mk for including ppc405 object files diff --git a/src/ssx/ssx/Makefile b/src/ssx/ssx/Makefile index ce1116f..e149e7f 100755..100644 --- a/src/ssx/ssx/Makefile +++ b/src/ssx/ssx/Makefile @@ -1,9 +1,32 @@ -# $Id: Makefile,v 1.2 2013/12/12 16:12:38 bcbrock Exp $ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/ssx/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG # This Makefile is designed to be invoked with the -I argument set to -# the location of the "ssx.mk" for the build +# the location of the "img_defs.mk" file for the build -include ../pgp/ssx.mk +include img_defs.mk include ssxssxfiles.mk ifeq "$(SSX_TIMER_SUPPORT)" "1" @@ -14,12 +37,15 @@ ifeq "$(SSX_THREAD_SUPPORT)" "1" SSX_OBJECTS += ${SSX-THREAD-C-SOURCES:.c=.o} endif -all: $(SSX_OBJECTS) +OBJS := $(addprefix $(OBJDIR)/, $(SSX_OBJECTS)) -.PHONY : clean -clean: - rm -f *.o *.d *.d.* +all: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) ifneq ($(MAKECMDGOALS),clean) -include $(SSX_OBJECTS:.o=.d) +include $(OBJS:.o=.d) endif diff --git a/src/ssx/ssx/ssx.h b/src/ssx/ssx/ssx.h index 5470968..ff6c947 100755..100644 --- a/src/ssx/ssx/ssx.h +++ b/src/ssx/ssx/ssx.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __SSX_H__ #define __SSX_H__ -// $Id: ssx.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -22,7 +44,9 @@ #include <stddef.h> #endif /* __ASSEMBLER__ */ -#define __SSX__ +#ifndef __SSX__ +#define __SSX__ 1 +#endif /// The application environment specifies whether or not it will provide an /// application configuration file, which must be named "ssx_app_cfg.h". diff --git a/src/ssx/ssx/ssx_api.h b/src/ssx/ssx/ssx_api.h index c9657e4..e4f6a10 100755..100644 --- a/src/ssx/ssx/ssx_api.h +++ b/src/ssx/ssx/ssx_api.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_api.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __SSX_API_H__ #define __SSX_API_H__ -// $Id: ssx_api.h,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_api.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -341,39 +363,79 @@ #endif -// Application and kernel tracing. Tracing can only be enabled if the port -// defines the trace macros in that case. - -/// Enable SSX application tracing +/// Enable SSX application tracing (enabled by default) #ifndef SSX_TRACE_ENABLE -#define SSX_TRACE_ENABLE 0 +#define SSX_TRACE_ENABLE 1 #endif -/// Enable SSX kernel tracing +/// Enable SSX kernel tracing (disabled by default) #ifndef SSX_KERNEL_TRACE_ENABLE #define SSX_KERNEL_TRACE_ENABLE 0 #endif #if !SSX_TRACE_ENABLE -#define SSX_TRACE(event) +#define SSX_TRACE(...) +#define SSX_TRACE_BIN(str, bufp, buf_size) +#else +#define SSX_TRACE(...) SSXTRACE(__VA_ARGS__) +#define SSX_TRACE_BIN(str, bufp, buf_size) SSXTRACE_BIN(str, bufp, buf_size) #endif +//Kernel trace macros #if !SSX_KERNEL_TRACE_ENABLE +#define SSX_KERN_TRACE(...) +#define SSX_KERN_TRACE_ASM16(...) +#else +#define SSX_KERN_TRACE(...) SSX_TRACE(__VA_ARGS__) +#define SSX_KERN_TRACE_ASM16(...) SSX_TRACE_ASM16(__VA_ARGS__) +#endif /* SSX_KERNEL_TRACE_ENABLE */ -#define SSX_TRACE_THREAD_SLEEP(priority) -#define SSX_TRACE_THREAD_WAKEUP(priority) -#define SSX_TRACE_THREAD_SEMAPHORE_PEND(priority) -#define SSX_TRACE_THREAD_SEMAPHORE_POST(priority) -#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT(priority) -#define SSX_TRACE_THREAD_SUSPENDED(priority) -#define SSX_TRACE_THREAD_DELETED(priority) -#define SSX_TRACE_THREAD_COMPLETED(priority) -#define SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority) -#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority) -#define SSX_TRACE_THREAD_MAPPED_SLEEPING(priority) +/// Add a string to the trace buffer with an optional register holding a 16bit value +/// WARNING: This calls a c function which may clobber any of the volatile registers +#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +#define SSX_TRACE_ASM16(...) TRACE_ASM_HELPER16(VARG_COUNT(__VA_ARGS__), __VA_ARGS__) +#else +#define SSX_TRACE_ASM16(...) +#endif /* SSX_TRACE_SUPPORT */ + +/// The following macros are helper macros for tracing. They should not be called +/// directly. +#define VARG_COUNT_HELPER(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N +#define VARG_COUNT(...) VARG_COUNT_HELPER(, ##__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#ifdef __ASSEMBLER__ +#define TRACE_ASM_HELPER16_CALL(count, ...) TINY_TRACE_ASM ## count (__VA_ARGS__) +#define TRACE_ASM_HELPER16(count, ...) TRACE_ASM_HELPER16_CALL(count, __VA_ARGS__) + +#define TINY_TRACE_ASM0() .error "format string required" +#define TINY_TRACE_ASM1(str) \ + .tiny_trace_asm1 trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX) +#define TINY_TRACE_ASM2(str, reg) \ + .tiny_trace_asm2 trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX), reg +#define TINY_TRACE_ASM3() .error "too many parameters" +#define TINY_TRACE_ASM4() .error "too many parameters" +#define TINY_TRACE_ASM5() .error "too many parameters" +#define TINY_TRACE_ASM6() .error "too many parameters" +#define TINY_TRACE_ASM7() .error "too many parameters" + +//TODO: add support for tracing more than 1 parameter and binary data in assembly + + .global ssx_trace_tiny + + .macro .tiny_trace_asm1 hash16 + lis %r3, \hash16 + bl ssx_trace_tiny + .endm + + .macro .tiny_trace_asm2 hash16, parm16 + clrlwi %r3, \parm16, 16 + oris %r3, %r3, \hash16 + bl ssx_trace_tiny + .endm + +#endif /*__ASSEMBLER__*/ -#endif /* SSX_KERNEL_TRACE_ENABLE */ #ifndef __ASSEMBLER__ @@ -436,6 +498,45 @@ typedef struct { #define SSX_SEMAPHORE(sem, initial_count, max_count) \ SsxSemaphore sem = SSX_SEMAPHORE_INITIALIZATION(initial_count, max_count) +/// Trace macros for C functions +#define HASH_ARG_COMBO(str, arg) \ + ((((uint32_t)trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX)) << 16) | ((uint32_t)(arg) & 0x0000ffff)) + +#define SSXTRACE0(...) ssx_trace_tiny() //will fail at compile time + +#define SSXTRACE1(str) \ + ssx_trace_tiny((trace_ppe_hash(str, SSX_TRACE_HASH_PREFIX) << 16)) + +#define SSXTRACE2(str, parm0) \ + ((sizeof(parm0) <= 2)? \ + ssx_trace_tiny(HASH_ARG_COMBO(str, parm0)): \ + ssx_trace_big(HASH_ARG_COMBO(str, 1), ((uint64_t)parm0) << 32, 0)) + +#define SSXTRACE3(str, parm0, parm1) \ + ssx_trace_big(HASH_ARG_COMBO(str, 2), ((((uint64_t)parm0) << 32) | parm1), 0) + +#define SSXTRACE4(str, parm0, parm1, parm2) \ + ssx_trace_big(HASH_ARG_COMBO(str, 3), ((((uint64_t)parm0) << 32) | parm1),\ + ((uint64_t)parm2) << 32 ) + +#define SSXTRACE5(str, parm0, parm1, parm2, parm3) \ + ssx_trace_big(HASH_ARG_COMBO(str, 4), ((((uint64_t)parm0) << 32) | parm1),\ + ((((uint64_t)parm2) << 32) | parm3) ) + +#define SSXTRACE6(...) ssx_trace_tiny() //will fail at compile time +#define SSXTRACE7(...) ssx_trace_tiny() //will fail at compile time + +#define SSXTRACE_HELPER2(count, ...) SSXTRACE ## count (__VA_ARGS__) +#define SSXTRACE_HELPER(count, ...) SSXTRACE_HELPER2(count, __VA_ARGS__) + +#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +#define SSXTRACE(...) SSXTRACE_HELPER(VARG_COUNT(__VA_ARGS__), __VA_ARGS__) +#define SSXTRACE_BIN(str, bufp, buf_size) \ + ssx_trace_binary(((buf_size < 255)? HASH_ARG_COMBO(str, buf_size): HASH_ARG_COMBO(str, 255)), bufp) +#else +#define SSXTRACE(...) +#define SSXTRACE_BIN(str, bufp, buf_size) +#endif //SSX_TRACE_SUPPORT /// A generic doubly-linked list object /// @@ -578,6 +679,18 @@ ssx_initialize(SsxAddress noncritical_stack, SsxTimebase ssx_timebase_get(void); +#if APPCFG_USE_EXT_TIMEBASE_FOR_TRACE +// Retrieve an external timebase +SsxTimebase +ssx_ext_timebase_get(void); +#else +static inline SsxTimebase +ssx_ext_timebase_get(void) +{ + return ssx_timebase_get(); +} +#endif /* APPCFG_USE_EXT_TIMEBASE_FOR_TRACE */ + void ssx_timebase_set(SsxTimebase timebase); @@ -707,9 +820,27 @@ ssx_halt() __attribute__ ((noreturn)); int ssx_deque_sentinel_create(SsxDeque *deque); +#define SSX_DEQUE_SENTINEL_INIT(dq_addr) \ +{\ + .next = dq_addr, \ + .previous = dq_addr \ +} + +#define SSX_DEQUE_SENTINEL_STATIC_CREATE(deque) \ + SsxDeque deque = SSX_DEQUE_SENTINEL_INIT(&deque) + int ssx_deque_element_create(SsxDeque *element); +#define SSX_DEQUE_ELEMENT_INIT() \ +{\ + .next = 0, \ + .previous = 0 \ +} + +#define SSX_DEQUE_ELEMENT_STATIC_CREATE(deque) \ + SsxDeque deque = SSX_DEQUE_ELEMENT_INIT() + /// Check for an empty SsxDeque /// @@ -822,10 +953,29 @@ ssx_deque_delete(SsxDeque *element) } +//Trace function prototypes +void ssx_trace_tiny(uint32_t i_parm); +void ssx_trace_big(uint32_t i_hash_and_count, + uint64_t i_parm1, uint64_t i_parm2); +void ssx_trace_binary(uint32_t i_hash_and_size, void* bufp); +void ssx_trace_set_timebase(SsxTimebase timebase); +void ssx_trace_init(uint32_t timebase_frequency_hz, + SsxTimebase initial_timebase); + + + /// Cast a pointer to another type, in a way that won't cause warnings #define SSX_CAST_POINTER(t, p) ((t)((SsxAddress)(p))) +// Static Assert Macro for Compile time assertions. +// - This macro can be used both inside and outside of a function. +// - A value of false will cause the ASSERT to produce this error +// - This will show up on a compile fail as: +// <file>:<line> error: size of array '_static_assert' is negative +// - It would be trivial to use the macro to paste a more descriptive +// array name for each assert, but we will leave it like this for now. +#define SSX_STATIC_ASSERT(cond) extern uint8_t _static_assert[(cond) ? 1 : -1] __attribute__ ((unused)) /// \page ssx_errors SSX API and Kernel Error Handling /// diff --git a/src/ssx/ssx/ssx_core.c b/src/ssx/ssx/ssx_core.c index 7fa484a..78fffbc 100755..100644 --- a/src/ssx/ssx/ssx_core.c +++ b/src/ssx/ssx/ssx_core.c @@ -1,7 +1,29 @@ -// $Id: ssx_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/pgp/registers/mcs_register_addresses.h b/src/ssx/ssx/ssx_debug_ptrs.c index 197ecfb..9247273 100755..100644 --- a/src/ssx/pgp/registers/mcs_register_addresses.h +++ b/src/ssx/ssx/ssx_debug_ptrs.c @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/ssx/pgp/registers/mcs_register_addresses.h $ */ +/* $Source: src/ssx/ssx/ssx_debug_ptrs.c $ */ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* Contributors Listed Below - COPYRIGHT 2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,57 +22,57 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -#ifndef __MCS_REGISTER_ADDRESSES_H__ -#define __MCS_REGISTER_ADDRESSES_H__ - -// $Id: mcs_register_addresses.h,v 1.4 2015/01/27 17:56:30 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_register_addresses.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2015 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- -/// \file mcs_register_addresses.h -/// \brief Symbolic addresses for the MCS unit +/// \file ssx_debug_ptrs.c +/// \brief Defines a table of pointers to important kernel debug data. +/// +/// This table is placed in a special section named .debug_ptrs which can be +/// placed at a well-known memory location for tools to find. +/// + +#include "ssx.h" +#include "ssx_trace.h" +#include "ssx_debug_ptrs.h" + + +extern SsxTimebase ppc405_64bit_ext_timebase; + +#if SSX_TRACE_SUPPORT +extern SsxTraceBuffer g_ssx_trace_buf; +#endif + +ssx_debug_ptrs_t ssx_debug_ptrs SECTION_ATTRIBUTE(".debug_ptrs") = +{ + .debug_ptrs_size = sizeof(ssx_debug_ptrs), + .debug_ptrs_version = SSX_DEBUG_PTRS_VERSION, -// *** WARNING *** - This file is generated automatically, do not edit. +#if SSX_TRACE_SUPPORT + .debug_trace_ptr = &g_ssx_trace_buf, + .debug_trace_size = sizeof(g_ssx_trace_buf), +#else + .debug_trace_ptr = 0, + .debug_trace_size = 0, +#endif /* SSX_TRACE_SUPPORT */ +#if SSX_THREAD_SUPPORT + .debug_thread_table_ptr = &__ssx_priority_map, + .debug_thread_table_size = sizeof(__ssx_priority_map), + .debug_thread_runq_ptr = (void*)&__ssx_run_queue, + .debug_thread_runq_size = sizeof(__ssx_run_queue), +#else + .debug_thread_table_ptr = 0, + .debug_thread_table_size = 0, + .debug_thread_runq_ptr = 0, + .debug_thread_runq_size = 0, +#endif /* SSX_THREAD_SUPPORT */ -#define MCS0_PIB_BASE 0x02011800 -#define MCS1_PIB_BASE 0x02011880 -#define MCS2_PIB_BASE 0x02011900 -#define MCS3_PIB_BASE 0x02011980 -#define MCS4_PIB_BASE 0x02011C00 -#define MCS5_PIB_BASE 0x02011C80 -#define MCS6_PIB_BASE 0x02011D00 -#define MCS7_PIB_BASE 0x02011D80 -#define MCFGPR_OFFSET 0x00000002 -#define MCS0_MCFGPR 0x02011802 -#define MCS1_MCFGPR 0x02011882 -#define MCS2_MCFGPR 0x02011902 -#define MCS3_MCFGPR 0x02011982 -#define MCS4_MCFGPR 0x02011c02 -#define MCS5_MCFGPR 0x02011c82 -#define MCS6_MCFGPR 0x02011d02 -#define MCS7_MCFGPR 0x02011d82 -#define MCSMODE0_OFFSET 0x00000007 -#define MCS0_MCSMODE0 0x02011807 -#define MCS1_MCSMODE0 0x02011887 -#define MCS2_MCSMODE0 0x02011907 -#define MCS3_MCSMODE0 0x02011987 -#define MCS4_MCSMODE0 0x02011c07 -#define MCS5_MCSMODE0 0x02011c87 -#define MCS6_MCSMODE0 0x02011d07 -#define MCS7_MCSMODE0 0x02011d87 -#define MCS0_MCIFIR 0x02011840 -#define MCS1_MCIFIR 0x020118C0 -#define MCS2_MCIFIR 0x02011940 -#define MCS3_MCIFIR 0x020119C0 -#define MCS4_MCIFIR 0x02011C40 -#define MCS5_MCIFIR 0x02011CC0 -#define MCS6_MCIFIR 0x02011D40 -#define MCS7_MCIFIR 0x02011DC0 + .debug_timebase_ptr = &ppc405_64bit_ext_timebase, + .debug_timebase_size = sizeof(ppc405_64bit_ext_timebase), -#endif // __MCS_REGISTER_ADDRESSES_H__ +}; diff --git a/src/ssx/ssx/ssx_debug_ptrs.h b/src/ssx/ssx/ssx_debug_ptrs.h new file mode 100644 index 0000000..0ff8097 --- /dev/null +++ b/src/ssx/ssx/ssx_debug_ptrs.h @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_debug_ptrs.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __SSX_DEBUG_PTRS_H__ +#define __SSX_DEBUG_PTRS_H__ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2015 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_debug_ptrs.h +/// \brief Structure for a table of pointers to kernel debug data +/// + +#define SSX_DEBUG_PTRS_VERSION 1 + +typedef struct +{ + // The size and version of this structure + unsigned short debug_ptrs_size; + unsigned short debug_ptrs_version; + + // Trace buffer location and size + void* debug_trace_ptr; + unsigned long debug_trace_size; + + // Thread table location and size + void* debug_thread_table_ptr; + unsigned long debug_thread_table_size; + + // Thread run queue location and size + void* debug_thread_runq_ptr; + unsigned long debug_thread_runq_size; + + // Emulated timebase location and size + void* debug_timebase_ptr; + unsigned long debug_timebase_size; + +} ssx_debug_ptrs_t; + +#endif /*__SSX_DEBUG_PTRS_H__*/ diff --git a/src/ssx/ssx/ssx_init.c b/src/ssx/ssx/ssx_init.c index fc12a9b..e2212da 100755..100644 --- a/src/ssx/ssx/ssx_init.c +++ b/src/ssx/ssx/ssx_init.c @@ -1,7 +1,29 @@ -// $Id: ssx_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_kernel.h b/src/ssx/ssx/ssx_kernel.h index c6a70ca..940fd31 100755..100644 --- a/src/ssx/ssx/ssx_kernel.h +++ b/src/ssx/ssx/ssx_kernel.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_kernel.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __SSX_KERNEL_H__ #define __SSX_KERNEL_H__ -// $Id: ssx_kernel.h,v 1.1.1.1 2013/12/11 21:03:27 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_kernel.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_macros.h b/src/ssx/ssx/ssx_macros.h index 76d3ba7..b20ac83 100755..100644 --- a/src/ssx/ssx/ssx_macros.h +++ b/src/ssx/ssx/ssx_macros.h @@ -1,10 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_macros.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __SSX_MACROS_H__ #define __SSX_MACROS_H__ -// $Id: ssx_macros.h,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_macros.h,v $ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_semaphore_core.c b/src/ssx/ssx/ssx_semaphore_core.c index f1f64e8..300628e 100755..100644 --- a/src/ssx/ssx/ssx_semaphore_core.c +++ b/src/ssx/ssx/ssx_semaphore_core.c @@ -1,7 +1,29 @@ -// $Id: ssx_semaphore_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_semaphore_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_semaphore_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -61,7 +83,7 @@ ssx_semaphore_post(SsxSemaphore *semaphore) __ssx_thread_queue_delete(&(semaphore->pending_threads), priority); __ssx_thread_queue_insert(&__ssx_run_queue, priority); - SSX_TRACE_THREAD_SEMAPHORE_POST(priority); + SSX_KERN_TRACE("THREAD_SEMAPHORE_POST(%d)", priority); __ssx_schedule(); @@ -183,7 +205,7 @@ ssx_semaphore_pend(SsxSemaphore *semaphore, thread->semaphore = semaphore; thread->flags |= SSX_THREAD_FLAG_SEMAPHORE_PEND; - SSX_TRACE_THREAD_SEMAPHORE_PEND(priority); + SSX_KERN_TRACE("THREAD_SEMAPHORE_PEND(%d)", priority); if (timeout != SSX_WAIT_FOREVER) { timer = &(thread->timer); @@ -200,6 +222,7 @@ ssx_semaphore_pend(SsxSemaphore *semaphore, if (thread->flags & SSX_THREAD_FLAG_TIMER_PEND) { if (thread->flags & SSX_THREAD_FLAG_TIMED_OUT) { rc = -SSX_SEMAPHORE_PEND_TIMED_OUT; + __ssx_thread_queue_delete(&(semaphore->pending_threads), thread->priority); } else { __ssx_timer_cancel(timer); } diff --git a/src/ssx/ssx/ssx_semaphore_init.c b/src/ssx/ssx/ssx_semaphore_init.c index 98bba89..9d0c099 100755..100644 --- a/src/ssx/ssx/ssx_semaphore_init.c +++ b/src/ssx/ssx/ssx_semaphore_init.c @@ -1,7 +1,29 @@ -// $Id: ssx_semaphore_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_semaphore_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_semaphore_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_stack_init.c b/src/ssx/ssx/ssx_stack_init.c index 9d6331a..ef81fb1 100755..100644 --- a/src/ssx/ssx/ssx_stack_init.c +++ b/src/ssx/ssx/ssx_stack_init.c @@ -1,7 +1,29 @@ -// $Id: ssx_stack_init.c,v 1.1.1.1 2013/12/11 21:03:28 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_stack_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_stack_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_thread_core.c b/src/ssx/ssx/ssx_thread_core.c index d6124e8..f6d8a62 100755..100644 --- a/src/ssx/ssx/ssx_thread_core.c +++ b/src/ssx/ssx/ssx_thread_core.c @@ -1,7 +1,29 @@ -// $Id: ssx_thread_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_thread_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_thread_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- @@ -98,11 +120,11 @@ __ssx_thread_map(SsxThread* thread) if (SSX_KERNEL_TRACE_ENABLE) { if (__ssx_thread_is_runnable(thread)) { - SSX_TRACE_THREAD_MAPPED_RUNNABLE(priority); + SSX_KERN_TRACE("THREAD_MAPPED_RUNNABLE(%d)", priority); } else if (thread->flags & SSX_THREAD_FLAG_SEMAPHORE_PEND) { - SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND(priority); + SSX_KERN_TRACE("THREAD_MAPPED_SEMAPHORE_PEND(%d)", priority); } else { - SSX_TRACE_THREAD_MAPPED_SLEEPING(priority); + SSX_KERN_TRACE("THREAD_MAPPED_SLEEPING(%d)", priority); } } } @@ -216,9 +238,9 @@ __ssx_thread_delete(SsxThread *thread, SsxThreadState final_state) if (SSX_KERNEL_TRACE_ENABLE) { if (final_state == SSX_THREAD_STATE_DELETED) { - SSX_TRACE_THREAD_DELETED(thread->priority); + SSX_KERN_TRACE("THREAD_DELETED(%d)", thread->priority); } else { - SSX_TRACE_THREAD_COMPLETED(thread->priority); + SSX_KERN_TRACE("THREAD_COMPLETED(%d)", thread->priority); } } @@ -471,7 +493,7 @@ ssx_thread_suspend(SsxThread *thread) if (__ssx_thread_is_mapped(thread)) { - SSX_TRACE_THREAD_SUSPENDED(thread->priority); + SSX_KERN_TRACE("THREAD_SUSPENDED(%d)", thread->priority); __ssx_thread_unmap(thread); __ssx_schedule(); } @@ -606,7 +628,7 @@ ssx_sleep_absolute(SsxTimebase time) current->flags |= SSX_THREAD_FLAG_TIMER_PEND; - SSX_TRACE_THREAD_SLEEP(current->priority); + SSX_KERN_TRACE("THREAD_SLEEP(%d)", current->priority); __ssx_thread_queue_delete(&__ssx_run_queue, current->priority); __ssx_schedule(); diff --git a/src/ssx/ssx/ssx_thread_init.c b/src/ssx/ssx/ssx_thread_init.c index c1a71b5..3fca442 100755..100644 --- a/src/ssx/ssx/ssx_thread_init.c +++ b/src/ssx/ssx/ssx_thread_init.c @@ -1,7 +1,29 @@ -// $Id: ssx_thread_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_thread_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_thread_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_timer_core.c b/src/ssx/ssx/ssx_timer_core.c index 8153acf..d51c166 100755..100644 --- a/src/ssx/ssx/ssx_timer_core.c +++ b/src/ssx/ssx/ssx_timer_core.c @@ -1,7 +1,29 @@ -// $Id: ssx_timer_core.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_timer_core.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_timer_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssx_timer_init.c b/src/ssx/ssx/ssx_timer_init.c index 6c35ea6..e944fd1 100755..100644 --- a/src/ssx/ssx/ssx_timer_init.c +++ b/src/ssx/ssx/ssx_timer_init.c @@ -1,7 +1,29 @@ -// $Id: ssx_timer_init.c,v 1.2 2014/02/03 01:30:44 daviddu Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssx_timer_init.c,v $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/ssx/ssx_timer_init.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ //----------------------------------------------------------------------------- -// *! (C) Copyright International Business Machines Corp. 2013 +// *! (C) Copyright International Business Machines Corp. 2014 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //----------------------------------------------------------------------------- diff --git a/src/ssx/ssx/ssxssxfiles.mk b/src/ssx/ssx/ssxssxfiles.mk index e78e986..fc5db57 100755..100644 --- a/src/ssx/ssx/ssxssxfiles.mk +++ b/src/ssx/ssx/ssxssxfiles.mk @@ -1,11 +1,33 @@ -# $Id: ssxssxfiles.mk,v 1.2 2014/06/26 13:02:00 cmolsen Exp $ -# $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/ssx/ssxssxfiles.mk,v $ -# @file ssxpgpfiles.mk +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# @brief mk for including pgp object files +# $Source: src/ssx/ssx/ssxssxfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2014,2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file ssxssxfiles.mk +# +# @brief mk for including ssx object files # # @page ChangeLogs Change Logs -# @section ssxpgpfiles.mk +# @section ssxssxfiles.mk # @verbatim # # @@ -24,7 +46,7 @@ ########################################################################## # Object Files ########################################################################## -SSX-C-SOURCES = ssx_core.c ssx_init.c ssx_stack_init.c +SSX-C-SOURCES = ssx_core.c ssx_init.c ssx_stack_init.c ssx_debug_ptrs.c SSX-TIMER-C-SOURCES += ssx_timer_core.c ssx_timer_init.c diff --git a/src/ssx/trace/Makefile b/src/ssx/trace/Makefile new file mode 100644 index 0000000..5506b32 --- /dev/null +++ b/src/ssx/trace/Makefile @@ -0,0 +1,50 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/trace/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# This Makefile is designed to be invoked with the -I argument set to +# the location of the "ssx.mk" for the build + +include img_defs.mk +include ssxtracefiles.mk + +ifeq "$(SSX_TIMER_SUPPORT)" "1" +SSXTRACE_OBJECTS += ${SSXTRACE-TIMER-C-SOURCES:.c=.o} ${SSXTRACE-TIMER-S-SOURCES:.S=.o} +endif + +ifeq "$(SSX_THREAD_SUPPORT)" "1" +SSXTRACE_OBJECTS += ${SSXTRACE-THREAD-C-SOURCES:.c=.o} ${SSXTRACE-THREAD-S-SOURCES:.S=.o} +endif + +OBJS := $(addprefix $(OBJDIR)/, $(SSXTRACE_OBJECTS)) + +all: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ssx/trace/ssx_trace.h b/src/ssx/trace/ssx_trace.h new file mode 100644 index 0000000..c79452b --- /dev/null +++ b/src/ssx/trace/ssx_trace.h @@ -0,0 +1,303 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/trace/ssx_trace.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __SSX_TRACE_H__ +#define __SSX_TRACE_H__ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_trace.h +/// \brief Macros and declarations for the SSX Firmware Tracing Facility. +/// + +#include <stdint.h> + +#define SSX_TRACE_VERSION 2 + +#ifndef SSX_TRACE_SZ +#define SSX_TRACE_SZ 256 +#endif + +//Fail compilation if size is not a power of 2 +#if ((SSX_TRACE_SZ - 1) & SSX_TRACE_SZ) +#error "SSX_TRACE_SZ is not a power of two!!!" +#endif + +//Fail compilation if size is smaller than 64 bytes +#if (SSX_TRACE_SZ < 64) +#error "SSX_TRACE_SZ must be at least 64 bytes!!!" +#endif + +//Mask for calculating offsets into the trace circular buffer +#define SSX_TRACE_CB_MASK (SSX_TRACE_SZ - 1) + +#define STRINGIFY_HELPER(x) #x +#define STRINGIFY(x) STRINGIFY_HELPER(x) + +#define PPC_IMG_STRING STRINGIFY(IMAGE_NAME) + +#ifdef SSX_TRACE_HASH_PREFIX +#if (SSX_TRACE_HASH_PREFIX > 0xffff) +#error SSX_TRACE_HASH_PREFIX must be defined as a 16 bit constant value +#endif +#endif //SSX_TRACE_HASH_PREFIX + +//This provides a 128ns tick (assuming a 32ns clock period) +//and 4 different format values +#define SSX_TRACE_TS_BITS 30 + +#define SSX_TRACE_FORMAT_BITS (32 - SSX_TRACE_TS_BITS) + +#define SSX_TRACE_TS_MASK (0xfffffffful << SSX_TRACE_FORMAT_BITS) +#define SSX_TRACE_FORMAT_MASK (~SSX_TRACE_TS_MASK) + +#define SSX_GET_TRACE_FORMAT(w32) (SSX_TRACE_FORMAT_MASK & w32) +#define SSX_GET_TRACE_TIME(w32) (SSX_TRACE_TS_MASK & w32) + +//Set the trace timer period to be the maximum +//32 bit time minus 2 seconds (assuming a 32ns tick) +//This allows for up to 1 second of interrupt latency + +//1 second for SSX_TRACE_MTBT while only requiring a trace +//every 135 seconds in order to maintain the 64bit timebase. +#define SSX_TRACE_TIMER_PERIOD (0xfffffffful - 62500000) + +//The Maximum Time Between Traces. In order to reduce the time that interrupts +//are disabled for tracing, reading of the time stamp is not done atomically +//with alocating an entry in the circular buffer. This means that the +//timestamps might not appear in order in the trace buffer. This is a +//problem because our calculation of the 64 bit timebase uses the unsigned +//difference of the current 32bit timestamp and the previous one and if they +//are out of order it will result in a very large difference. To solve this +//problem, any time that the parser code sees a very large difference (larger +//than SSX_TRACE_MTBT) it will treat it as a negative number. +#define SSX_TRACE_MTBT (0xfffffffful - 31250000) + +#define SSX_TRACE_MAX_PARMS 4 + +//This is the maximum number of bytes allowed to be traced in a binary trace +//entry. +//The trace version needs to change if this changes. +#define SSX_TRACE_MAX_BINARY 256 + +//clip the largest binary trace according to the trace buffer size. +//(The trace version does not need to change if this changes as long +// as it remains less than SSX_TRACE_MAX_BINARY) +#if (SSX_TRACE_SZ <= 256) +#define SSX_TRACE_CLIPPED_BINARY_SZ SSX_TRACE_SZ / 2 +#else +#define SSX_TRACE_CLIPPED_BINARY_SZ SSX_TRACE_MAX_BINARY +#endif + +//Trace formats that are supported +typedef enum +{ + SSX_TRACE_FORMAT_EMPTY, + SSX_TRACE_FORMAT_TINY, + SSX_TRACE_FORMAT_BIG, + SSX_TRACE_FORMAT_BINARY, +}SsxTraceFormat; + +//This combines the timestamp and the format bits into a +//single 32 bit word. +typedef union +{ + struct + { + uint32_t timestamp : SSX_TRACE_TS_BITS; + uint32_t format : SSX_TRACE_FORMAT_BITS; + }; + uint32_t word32; +}SsxTraceTime; + +//SSX trace uses a 16 bit string format hash value +typedef uint16_t SsxTraceHash; + +//The constant 16 bit hash value is combined with a +//16 bit parameter value when doing a tiny trace +typedef union +{ + struct + { + SsxTraceHash string_id; + uint16_t parm; + }; + uint32_t word32; +}SsxTraceTinyParms; + +//A tiny trace fits within a single 8 byte word. This includes +//the timestamp, format bits, hash id, and a 16 bit parameter. +typedef union +{ + struct + { + SsxTraceTinyParms parms; + SsxTraceTime time_format; + }; + uint64_t word64; +}SsxTraceTiny; + +//Larger traces that require a 32 bit parameter or more than one +//parameter use the big trace format. The number of parms and +//the 'complete' flag are combined with the hash id. 'complete' +//is set to 0 initially and set to one only after all of the trace +//data has been written. +typedef union +{ + struct + { + SsxTraceHash string_id; + uint8_t complete; + uint8_t num_parms; + }; + uint32_t word32; +}SsxTraceBigParms; + +typedef union +{ + struct + { + SsxTraceBigParms parms; + SsxTraceTime time_format; + }; + uint64_t word64; +}SsxTraceBig; + +//Binary traces are handled in a similar fashion to big traces, except +//that instead of having a number of parameters, we have number of bytes. +typedef union +{ + struct + { + SsxTraceHash string_id; + uint8_t complete; + uint8_t num_bytes; + }; + uint32_t word32; +}SsxTraceBinaryParms; + +typedef union +{ + struct + { + SsxTraceBinaryParms parms; + SsxTraceTime time_format; + }; + uint64_t word64; +}SsxTraceBinary; + +//This is a generic structure that can be used to retrieve data +//for tiny, big, and binary formatted entries. +typedef union +{ + struct + { + SsxTraceHash string_id; + union + { + uint16_t parm16; + struct + { + uint8_t complete; + uint8_t bytes_or_parms_count; + }; + }; + SsxTraceTime time_format; + }; + uint64_t word64; +}SsxTraceGeneric; + +//This is a format that might be used in the future for tracing +//a 64 bit timestamp so that we don't fill up the buffer with periodic +//timer traces. It is not currently used. +#if 0 +typedef union +{ + struct + { + uint32_t upper32; + SsxTraceTime time_format; + }; + uint64_t word64; +}SsxTraceTime64; +#endif + +//It would probably be more accurate to call this a footer since it +//actually resides at the highest address of each trace entry. These eight +//bytes contain information that allow us to walk the trace buffer from the +//most recent entry to the oldest entry. +typedef union +{ + SsxTraceGeneric generic; + SsxTraceBinary binary; + SsxTraceBig big; + SsxTraceTiny small; +}SsxTraceEntryFooter; + + +//This is the data that is updated (in the buffer header) every time we add +//a new entry to the buffer. +typedef union +{ + struct + { + uint32_t tbu32; + uint32_t offset; + }; + uint64_t word64; +}SsxTraceState; + +#define SSX_TRACE_IMG_STR_SZ 16 + +//Header data for the trace buffer that is used for parsing the data. +//Note: SsxTraceState contains a uint64_t which is required to be +//placed on an 8-byte boundary according to the EABI Spec. This also +//causes cb to start on an 8-byte boundary. +typedef struct +{ + //these values are needed by the parser + uint16_t version; + uint16_t rsvd; + char image_str[SSX_TRACE_IMG_STR_SZ]; + uint16_t instance_id; + uint16_t partial_trace_hash; + uint16_t hash_prefix; + uint16_t size; + uint32_t max_time_change; + uint32_t hz; + uint32_t pad; + uint64_t time_adj64; + + //updated with each new trace entry + SsxTraceState state; + + //circular trace buffer + uint8_t cb[SSX_TRACE_SZ]; +}SsxTraceBuffer; + +extern SsxTraceBuffer g_ssx_trace_buf; + +#endif /* __SSX_TRACE_H__ */ diff --git a/src/ssx/trace/ssx_trace_big.c b/src/ssx/trace/ssx_trace_big.c new file mode 100644 index 0000000..4a9bdb5 --- /dev/null +++ b/src/ssx/trace/ssx_trace_big.c @@ -0,0 +1,116 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/trace/ssx_trace_big.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_trace_big.c +/// \brief SSX Trace function that supports up to four 32-bit parameters +/// +/// The ssx_trace_big function is only called (via some macro magic) if the +/// caller passes in a single parameter (not including the format string) +/// that is larger than 16 bits to the SSX_TRACE(...) macro. +/// + +#include "ssx.h" +#include "ssx_trace.h" + +#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +void ssx_trace_big(uint32_t i_hash_and_count, + uint64_t i_parm1, uint64_t i_parm2) +{ + SsxTraceBig footer; + SsxTraceBig* footer_ptr; + SsxTraceState state; + uint64_t* ptr64; + uint64_t tb64; + SsxMachineContext ctx; + uint32_t parm_size; + uint32_t cur_offset; + uint32_t footer_offset; + + //fill in the footer data + tb64 = ssx_ext_timebase_get(); + footer.parms.word32 = i_hash_and_count; //this has the parm count and hash + state.tbu32 = tb64 >> 32; + footer.time_format.word32 = tb64 & 0x00000000ffffffffull; + footer.time_format.format = SSX_TRACE_FORMAT_BIG; + + //round up to 8 byte boundary + if(footer.parms.num_parms <= 2) + { + parm_size = 8; + } + else + { + parm_size = 16; + } + + //*****The following operations must be done atomically***** + ssx_critical_section_enter(SSX_NONCRITICAL, &ctx); + + //load in the offset in the cb for the entry we are adding + cur_offset = g_ssx_trace_buf.state.offset; + + //Find the offset for the footer (at the end of the entry) + footer_offset = cur_offset + parm_size; + + //calculate the address of the footer + ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[footer_offset & SSX_TRACE_CB_MASK]; + + //calculate the offset for the next entry in the cb + state.offset = footer_offset + sizeof(SsxTraceBig); + + //update the cb state (tbu and offset) + g_ssx_trace_buf.state.word64 = state.word64; + + //write the data to the circular buffer including the + //timesamp, string hash, and 16bit parameter + *ptr64 = footer.word64; + + //*******************exit the critical section*************** + ssx_critical_section_exit(&ctx); + + + //write parm values to the circular buffer + footer_ptr = (SsxTraceBig*)ptr64; + ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[cur_offset & SSX_TRACE_CB_MASK]; + *ptr64 = i_parm1; + if(parm_size > 8) + { + ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[(cur_offset + 8) & SSX_TRACE_CB_MASK]; + *ptr64 = i_parm2; + } + + //Mark the trace entry update as being completed + footer_ptr->parms.complete = 1; + +} + +#endif + + diff --git a/src/ssx/trace/ssx_trace_binary.c b/src/ssx/trace/ssx_trace_binary.c new file mode 100644 index 0000000..f1d1db6 --- /dev/null +++ b/src/ssx/trace/ssx_trace_binary.c @@ -0,0 +1,115 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/trace/ssx_trace_binary.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_trace_binary.c +/// \brief SSX Trace function for dumping memory contents +/// +/// The ssx_trace_binary function is called by the SSX_TRACE_BINARY() macro. +/// + + +#include "ssx.h" +#include "ssx_trace.h" + +#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +void ssx_trace_binary(uint32_t i_hash_and_size, void* bufp) +{ + SsxTraceBinary footer; + SsxTraceBinary* footer_ptr; + SsxTraceState state; + uint64_t* ptr64; + uint64_t tb64; + SsxMachineContext ctx; + uint32_t data_size; + uint32_t cb_offset; + uint32_t footer_offset; + uint8_t* dest; + uint8_t* src; + uint32_t index; + + //fill in the footer data + tb64 = ssx_ext_timebase_get(); + footer.parms.word32 = i_hash_and_size; //this has the size and hash + state.tbu32 = tb64 >> 32; + footer.time_format.word32 = tb64 & 0x00000000ffffffffull; + footer.time_format.format = SSX_TRACE_FORMAT_BINARY; + + //round up to 8 byte boundary + data_size = (footer.parms.num_bytes + 7) & ~0x00000007ul; + + //limit data size + if(data_size > SSX_TRACE_CLIPPED_BINARY_SZ) + { + data_size = SSX_TRACE_CLIPPED_BINARY_SZ; + } + + //*****The following operations must be done atomically***** + ssx_critical_section_enter(SSX_NONCRITICAL, &ctx); + + //load in the offset in the cb for the entry we are adding + cb_offset = g_ssx_trace_buf.state.offset; + + //Find the offset for the footer (at the end of the entry) + footer_offset = cb_offset + data_size; + + //calculate the address of the footer + ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[footer_offset & SSX_TRACE_CB_MASK]; + + //calculate the offset for the next entry in the cb + state.offset = footer_offset + sizeof(SsxTraceBinary); + + //update the cb state (tbu and offset) + g_ssx_trace_buf.state.word64 = state.word64; + + //write the footer data to the circular buffer including the + //timesamp, string hash and data size + *ptr64 = footer.word64; + + //*******************exit the critical section*************** + ssx_critical_section_exit(&ctx); + + //write data to the circular buffer + for(src = bufp, index = 0; + index < data_size; + index++) + { + dest = &g_ssx_trace_buf.cb[(cb_offset + index) & SSX_TRACE_CB_MASK]; + *dest = *(src++); + } + + //Mark the trace entry update as being completed + footer_ptr = (SsxTraceBinary*)ptr64; + footer_ptr->parms.complete = 1; + +} + +#endif + + diff --git a/src/ssx/trace/ssx_trace_core.c b/src/ssx/trace/ssx_trace_core.c new file mode 100644 index 0000000..a2db4b8 --- /dev/null +++ b/src/ssx/trace/ssx_trace_core.c @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ssx/trace/ssx_trace_core.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ssx_trace_core.c +/// \brief SSX Trace core data and code. +/// +/// This file includes the minimal code/data required to do minimal tracing. +/// This includes the periodic timer initialization and the ssx_trace_tiny +/// function. The ssx_trace_tiny function is called by the SSX_TRACE() macro +/// when there is one or less parameters (not including the format string) +/// and the parameter size is 16 bits or smaller. +/// + +#include "ssx.h" +#include "ssx_trace.h" + +void ssx_trace_timer_callback(void* arg); + +#if (SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) + +//Static initialization of the trace timer +SsxTimer g_ssx_trace_timer = { + .deque = SSX_DEQUE_ELEMENT_INIT(), + .timeout = 0, + .callback = ssx_trace_timer_callback, + .arg = 0, + .options = SSX_TIMER_CALLBACK_PREEMPTIBLE, +}; + +//Static initialization of the ssx trace buffer +SsxTraceBuffer g_ssx_trace_buf = +{ + .version = SSX_TRACE_VERSION, + .image_str = PPC_IMG_STRING, + .hash_prefix = SSX_TRACE_HASH_PREFIX, + .partial_trace_hash = trace_ppe_hash("PARTIAL TRACE ENTRY. HASH_ID = %d", SSX_TRACE_HASH_PREFIX), + .size = SSX_TRACE_SZ, + .max_time_change = SSX_TRACE_MTBT, + .hz = 500000000, //default value. Actual value is set in ssx_init.c + .time_adj64 = 0, + .state.word64 = 0, + .cb = {0} +}; + +//Needed for buffer extraction in simics for now +SsxTraceBuffer* g_ssx_trace_buf_ptr = &g_ssx_trace_buf; + +// Creates an 8 byte entry in the trace buffer that includes a timestamp, +// a format string hash value and a 16 bit parameter. +// +// i_parm has the hash value combined with the 16 bit parameter +void ssx_trace_tiny(uint32_t i_parm) +{ + SsxTraceTiny footer; + SsxTraceState state; + uint64_t* ptr64; + uint64_t tb64; + SsxMachineContext ctx; + + //fill in the footer data + footer.parms.word32 = i_parm; + tb64 = ssx_ext_timebase_get(); + state.tbu32 = tb64 >> 32; + footer.time_format.word32 = tb64 & 0x00000000ffffffffull; + + footer.time_format.format = SSX_TRACE_FORMAT_TINY; + + //The following operations must be done atomically + ssx_critical_section_enter(SSX_NONCRITICAL, &ctx); + + //load the current byte count and calculate the address for this + //entry in the cb + ptr64 = (uint64_t*)&g_ssx_trace_buf.cb[g_ssx_trace_buf.state.offset & SSX_TRACE_CB_MASK]; + + //calculate the offset for the next entry in the cb + state.offset = g_ssx_trace_buf.state.offset + sizeof(SsxTraceTiny); + + //update the cb state (tbu and offset) + g_ssx_trace_buf.state.word64 = state.word64; + + //write the data to the circular buffer including the + //timesamp, string hash, and 16bit parameter + *ptr64 = footer.word64; + + //exit the critical section + ssx_critical_section_exit(&ctx); +} + + +// This function is called periodically in order to ensure that the max ticks +// between trace entries is no more than what will fit inside a 32bit value. +void ssx_trace_timer_callback(void* arg) +{ + + // guarantee at least one trace before the lower 32bit timebase flips + SSX_TRACE("PERIODIC TIMESTAMPING TRACE"); + + // restart the timer + ssx_timer_schedule(&g_ssx_trace_timer, + SSX_TRACE_TIMER_PERIOD, + 0); +} + +// Use this function to synchronize the timebase between multiple Processors. +// proc A can send proc B it's current timebase and then proc B can set that +// as the current timebase for tracing purposes. It can also be used +// to set the current time to 0. This function changes the timebase for +// all entries that are currently in the trace buffer. Setting the current +// timebase to 0 will cause previous traces to have very large timestamps. +void ssx_trace_set_timebase(SsxTimebase timebase) +{ + g_ssx_trace_buf.time_adj64 = timebase - ssx_ext_timebase_get(); +} + +void ssx_trace_init(uint32_t timebase_frequency_hz, + SsxTimebase initial_timebase) +{ + //set the trace timebase HZ (used by parsing tools) + g_ssx_trace_buf.hz = timebase_frequency_hz; + + if(initial_timebase != SSX_TIMEBASE_CONTINUES) + { + //Set the timebase adjustment. The external timebase + //is not adjustable so we use a software adjustment instead. + //Typically, this should only be used by the first processor to come + //up in order to set the timebase to 0. Other processors + //will want to synchronize with the first processor's timebase. + ssx_trace_set_timebase(initial_timebase); + } + + // Schedule the timer that puts a timestamp in the trace buffer + // periodically. This allows us to use 32bit timestamps. + ssx_timer_schedule(&g_ssx_trace_timer, + SSX_TRACE_TIMER_PERIOD, + 0); +} + +#endif diff --git a/src/ssx/trace/ssxtracefiles.mk b/src/ssx/trace/ssxtracefiles.mk new file mode 100644 index 0000000..dc3d058 --- /dev/null +++ b/src/ssx/trace/ssxtracefiles.mk @@ -0,0 +1,63 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ssx/trace/ssxtracefiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file ssxtracefiles.mk +# +# @brief mk for including SSX trace object files +# +# @page ChangeLogs Change Logs +# @section ssxtracefiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Include Files +########################################################################## + + + +########################################################################## +# Object Files +########################################################################## +SSXTRACE-C-SOURCES = ssx_trace_core.c ssx_trace_big.c ssx_trace_binary.c + +SSXTRACE-S-SOURCES = + +SSXTRACE-TIMER-C-SOURCES = +SSXTRACE-TIMER-S-SOURCES = + +SSXTRACE-THREAD-C-SOURCES += +SSXTRACE-THREAD-S-SOURCES += + + +SSXTRACE_OBJECTS += $(SSXTRACE-C-SOURCES:.c=.o) $(SSXTRACE-S-SOURCES:.S=.o) + + + |
