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author | Doug Gilbert <dgilbert@us.ibm.com> | 2017-09-20 14:56:59 -0500 |
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committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-10-10 13:02:41 -0400 |
commit | 9c63762e00a20f22fc8a4509071d90786513e16a (patch) | |
tree | 5e2484abcfeae088d6b20f562535881978800d5e /src/occ_gpe1 | |
parent | ba4e81e804275ced6c1793f818e5fc1fd8d1ecae (diff) | |
download | talos-occ-9c63762e00a20f22fc8a4509071d90786513e16a.tar.gz talos-occ-9c63762e00a20f22fc8a4509071d90786513e16a.zip |
Enable hardware GPU power brake
Change-Id: I39ae6205cef6ae06cacc0eb2c8a0a4288b8081c8
RTC: 179617
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46800
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
-rw-r--r-- | src/occ_gpe1/gpe_gpu_init.c | 69 | ||||
-rw-r--r-- | src/occ_gpe1/ipc_func_tables.c | 3 | ||||
-rw-r--r-- | src/occ_gpe1/topfiles.mk | 2 |
3 files changed, 72 insertions, 2 deletions
diff --git a/src/occ_gpe1/gpe_gpu_init.c b/src/occ_gpe1/gpe_gpu_init.c new file mode 100644 index 0000000..a293905 --- /dev/null +++ b/src/occ_gpe1/gpe_gpu_init.c @@ -0,0 +1,69 @@ +#include "pk.h" +#include "ppe42_scom.h" +#include "gpu_structs.h" +#include "ipc_async_cmd.h" +#include "gpe_err.h" +#include "gpe_util.h" +#include "p9_misc_scom_addresses.h" + +gpu_i2c_info_t G_gpu_i2c __attribute__((section(".sbss.G_gpu_i2c"))); + +void gpe_gpu_init(ipc_msg_t* cmd, void* arg) +{ + int rc = 0; + int i; + ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd; + gpu_init_args_t *args = (gpu_init_args_t*)async_cmd->cmd_data; + + args->error.ffdc = 0; + + // Prevent MCK attention on scom failes (PK kernel fix?) + mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM); + + // According to Jordan Keuseman, Setting PV_CP0_P_PRV_GPIO0 pin on the + // processor chip to low enables HW to automatically apply GPU power brake. + // GPIO1 (GPU_PWR_BRAKE_FORCE_N) will not be controlled by FW, so needs to + // be configured as input. + uint64_t data64 = 0x8000000000000000ull; + rc = putscom_abs(PU_GPIO_OUTPUT_CLR,data64); + if(rc) + { + PK_TRACE("gpe_gpu_init: PU_GPIO0_OUTPUT failed. rc:0x%08x",rc); + gpe_set_ffdc(&(args->error), 0, GPE_RC_GPU_INIT_FAILED, rc); + } + + rc = getscom_abs(PU_GPIO_OUTPUT_EN, &data64); + if(rc) + { + PK_TRACE("gpe_gpu_init: Read PU_GPIO0_OUTPUT_EN failed. rc:0x%08x",rc); + gpe_set_ffdc(&(args->error), 0, GPE_RC_GPU_INIT_FAILED, rc); + } + + // pin0 as output, pin1 as input, pin3 unchanged + data64 &= 0xBfffffffffffffffull; + data64 |= 0x8000000000000000ull; + + rc = putscom_abs(PU_GPIO_OUTPUT_EN, data64); + + if(rc) + { + PK_TRACE("gpe_gpu_init: PU_GPIO0_OUTPUT_EN failed. rc:0x%08x",rc); + gpe_set_ffdc(&(args->error), 0, GPE_RC_GPU_INIT_FAILED, rc); + } + + // Get i2c data + G_gpu_i2c.pib_master = args->gpu_i2c.pib_master; + G_gpu_i2c.bus_voltage = args->gpu_i2c.bus_voltage; + for(i = 0; i < MAX_GPUS; ++i) + { + G_gpu_i2c.port[i] = args->gpu_i2c.port[i]; + G_gpu_i2c.addr[i] = args->gpu_i2c.addr[i]; + } + + rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS); + if(rc) + { + PK_TRACE("E>gpu_init: Failed to send response back. Halting GPE1", rc); + pk_halt(); + } +} diff --git a/src/occ_gpe1/ipc_func_tables.c b/src/occ_gpe1/ipc_func_tables.c index ea1d6f8..a7fe5ea 100644 --- a/src/occ_gpe1/ipc_func_tables.c +++ b/src/occ_gpe1/ipc_func_tables.c @@ -32,6 +32,7 @@ void gpe1_nop(ipc_msg_t* cmd, void* arg); void gpe_reset_mem_deadman(ipc_msg_t* cmd, void* arg); void gpe_24x7(ipc_msg_t* cmd, void* arg); void gpe_mem_power_control(ipc_msg_t* cmd, void* arg); +void gpe_gpu_init(ipc_msg_t* cmd, void* arg); #ifdef OCC_GPU_SUPPORT void gpe_gpu_sm(ipc_msg_t* cmd, void* arg); @@ -82,7 +83,7 @@ IPC_HANDLER(gpe_reset_mem_deadman, 0) // 3 - IPC_ST_RESET_MEM_DEADMAN IPC_HANDLER(gpe_24x7, 0) // 4 - IPC_ST_24_X_7_FUNCID IPC_HANDLER(gpe_mem_power_control, 0) // 5 - IPC_ST_MEM_POWER_CONTROL_FUNCID IPC_HANDLER(gpe_gpu_sm, 0) // 6 - IPC_ST_GPU_SM_FUNCID -IPC_HANDLER_DEFAULT // 7 +IPC_HANDLER(gpe_gpu_init, 0) // 7 - IPC_ST_GPE_GPU_INIT_FUNCID IPC_HANDLER_DEFAULT // 8 IPC_HANDLER_DEFAULT // 9 IPC_HANDLER_DEFAULT // 10 diff --git a/src/occ_gpe1/topfiles.mk b/src/occ_gpe1/topfiles.mk index 6dbae16..d0c2c2f 100644 --- a/src/occ_gpe1/topfiles.mk +++ b/src/occ_gpe1/topfiles.mk @@ -25,7 +25,7 @@ TOP-C-SOURCES = gpe1_main.c gpe1_dimm_read.c gpe1_dimm_reset.c nop.c \ pk_app_irq_table.c ipc_func_tables.c gpe1_dimm_control.c \ - gpe1_24x7.c gpe1_memory_power_control.c + gpe1_24x7.c gpe1_memory_power_control.c gpe_gpu_init.c TOP-S-SOURCES = |