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| author | Wael El-Essawy <welessa@us.ibm.com> | 2017-03-22 10:30:48 -0500 |
|---|---|---|
| committer | Wael El-Essawy <welessa@us.ibm.com> | 2017-05-10 13:53:16 -0400 |
| commit | cf2258322bb72a2cd868f8eaef25e9a665077f4f (patch) | |
| tree | f7a9b13ef36943246377ff623ed917fa4fd08ada /src/occ_gpe1/gpe1_memory_power_control.h | |
| parent | ff3b5a1c08389bf766de21adcd033e3c7b86af87 (diff) | |
| download | talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.tar.gz talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.zip | |
Memory Power Control when entering and exiting IPS (Idle Power Save)
memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.
Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1/gpe1_memory_power_control.h')
| -rw-r--r-- | src/occ_gpe1/gpe1_memory_power_control.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/occ_gpe1/gpe1_memory_power_control.h b/src/occ_gpe1/gpe1_memory_power_control.h new file mode 100644 index 0000000..e5f704f --- /dev/null +++ b/src/occ_gpe1/gpe1_memory_power_control.h @@ -0,0 +1,47 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ_gpe1/gpe1_memory_power_control.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef _GPE1_MEMORY_POWER_CONTROL_H +#define _GPE1_MEMORY_POWER_CONTROL_H + +#define PCR0_MASTER_ENABLE_BIT 2 +#define PCR0_POWERDOWN_ENABLE_BIT 22 + +#define STR0_STR_ENABLE_BIT 0 +#define STR0_DISABLE_MEMORY_CLOCKS_BIT 1 + +// Big Endian set/clear bit MACROS +#define SET_BIT(var, bit) (var | (0x8000000000000000 >> bit) ) + +#define CLR_BIT(var, bit) (var & ~(0x8000000000000000 >> bit) ) + + +// Big Endian set/clear 2 different bits MACROS +#define SET_2BITS(var, bit1, bit2) SET_BIT(SET_BIT(var, bit1), bit2) + +#define CLR_2BITS(var, bit1, bit2) CLR_BIT(CLR_BIT(var, bit1), bit2) + + +#endif // _GPE1_MEMORY_POWER_CONTROL_H |
