Enable APSS Composite Mode

RTC:132559

Change-Id: Id66a6ee7083031f0a6a3364f4f01bdc9886ca638
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29070
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

4 files changed, 48 insertions, 71 deletions

diff --git a/src/occ_gpe0/apss_constants.h b/src/occ_gpe0/apss_constants.h
deleted file mode 100755
index 8d6d156..0000000
--- a/src/occ_gpe0/apss_constants.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/occ_405/gpe/apss_constants.h $                            */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-#ifndef _APSS_CONSTANTS_H
-#define _APSS_CONSTANTS_H
-
-#define SPIPSS_REGISTER_BASE          0x00070000
-#define SPIPSS_ADC_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x00)
-#define SPIPSS_ADC_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x01)
-#define SPIPSS_ADC_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x02)
-#define SPIPSS_ADC_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x03)
-#define SPIPSS_ADC_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x04)
-#define SPIPSS_ADC_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x10)
-#define SPIPSS_ADC_RDATA_REG0         (SPIPSS_REGISTER_BASE + 0x20)
-#define SPIPSS_ADC_RDATA_REG1         (SPIPSS_REGISTER_BASE + 0x21)
-#define SPIPSS_ADC_RDATA_REG2         (SPIPSS_REGISTER_BASE + 0x22)
-#define SPIPSS_ADC_RDATA_REG3         (SPIPSS_REGISTER_BASE + 0x23)
-#define SPIPSS_P2S_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x40)
-#define SPIPSS_P2S_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x41)
-#define SPIPSS_P2S_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x42)
-#define SPIPSS_P2S_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x43)
-#define SPIPSS_P2S_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x44)
-#define SPIPSS_P2S_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x50)
-#define SPIPSS_P2S_RDATA_REG          (SPIPSS_REGISTER_BASE + 0x60)
-
-#define TOD_VALUE_REG 0x00040020
-
-// Constant for use in wait statments: waits (5 * MICROSECONDS)
-#define MICROSECONDS 600
-
-
-#endif //_APSS_CONSTANTS_H
diff --git a/src/occ_gpe0/apss_init.c b/src/occ_gpe0/apss_init.c
index ec232fd..678dad3 100644
--- a/src/occ_gpe0/apss_init.c
+++ b/src/occ_gpe0/apss_init.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -30,6 +30,10 @@
 #include <apss_structs.h>       //H file common with occ_405
 #include "gpe_util.h"
 
+// Default to Auto-2 for now, should get set when the mode
+// is initialized, and before any APSS data is gathered.
+uint8_t G_apss_mode = APSS_MODE_AUTO2;
+
 /*
  * Function Specification
  *
@@ -56,7 +60,7 @@ uint32_t apss_start_spi_command(initGpioArgs_t * args, uint8_t i_noWait)
     else
     {
 
-         busy_wait(5);
+        busy_wait(5);
 
         if (!i_noWait)
         {
@@ -116,7 +120,7 @@ void apss_init_gpio(ipc_msg_t* cmd, void* arg)
             gpe_set_ffdc(&(args->error), SPIPSS_P2S_CTRL_REG0, rc, regValue);
             break;
         }
-        // bridge_enable, clock_divider=7, 2 frames
+        // bridge_enable, clock_divider=36, 2 frames
         regValue = 0x8090400000000000;
         rc = putscom_abs(SPIPSS_P2S_CTRL_REG1, regValue);
         if (rc)
@@ -276,7 +280,7 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
 
         ////////////////////////////
         // Setup the control regs
-        // frame_size=16, out_count1=16, in_delay1=never, in_count2=16
+        // frame_size=16, out_count1=16
         regValue = 0x4100000000000000;
         rc = putscom_abs(SPIPSS_P2S_CTRL_REG0, regValue);
         if (rc)
@@ -286,7 +290,7 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
             break;
         }
 
-        // bridge_enable, clock_divider=7, 1 frames
+        // bridge_enable, clock_divider=36, 1 frames
         regValue = 0x8090000000000000;
         rc = putscom_abs(SPIPSS_P2S_CTRL_REG1, regValue);
         if (rc)
@@ -295,7 +299,7 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
             gpe_set_ffdc(&(args->error), SPIPSS_P2S_CTRL_REG1, rc, regValue);
             break;
         }
-        // inter_frame_delay=25 (2.5usec)
+        // inter_frame_delay=50 (5usec)
         regValue = 0x0019000000000000;
         rc = putscom_abs(SPIPSS_P2S_CTRL_REG2, regValue);
         if (rc)
@@ -313,12 +317,14 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
             regValue = args->config.numAdcChannelsToRead - 1;  //aaaa => Address of last ADC channel (countOfADCChannels - 1)
             regValue = regValue << 6;                   //Make space for GPIO port count
             regValue |= (args->config.numGpioPortsToRead) & 0x03;   //gg => Num of GPIO ports
-            regValue = (regValue << 51) | 0x8C00000000000000; //Add Command at D15-D12
+            regValue = (regValue << 48) | 0x8C00000000000000; //Add Command at D15-D12
+            G_apss_mode = APSS_MODE_COMPOSITE;
         }
         else if (args->config.mode == APSS_MODE_AUTO2)
         {
-            // Set Auto2 mode
+            // Set Auto2 mode to scan all 16 ADC channels
             regValue = 0x3FC0000000000000;
+            G_apss_mode = APSS_MODE_AUTO2;
         }
         else
         {
diff --git a/src/occ_gpe0/apss_read.c b/src/occ_gpe0/apss_read.c
index bcc602c..12e7102 100644
--- a/src/occ_gpe0/apss_read.c
+++ b/src/occ_gpe0/apss_read.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -32,6 +32,8 @@
 #include <apss_structs.h>
 #include "gpe_util.h"
 
+extern uint8_t G_apss_mode;
+
 /*
  * Function Specifications:
  *
@@ -82,7 +84,7 @@ void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg)
         // Setup control regs:
 
         // SPIPSS_ADC_CTRL_REG0:
-        // frame_size=16, out_count=16, in_count=16
+        // frame_size=16, out_count=0, in_count=16
         //    rc = putscom(0, SPIPSS_ADC_CTRL_REG0, uint64_t 0x4000100000000000);
         regValue = 0x4000100000000000;
         rc = putscom_abs(SPIPSS_ADC_CTRL_REG0, regValue);
@@ -95,9 +97,16 @@ void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg)
         }
 
         // SPIPSS_ADC_CTRL_REG1: ADC FSM
-        // clock_divider=7, frames=16
-        // rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000);
-        regValue = 0x8093c00000000000;
+        if (APSS_MODE_COMPOSITE == G_apss_mode)
+        {
+            // clock_divider=36, frames=17 (i.e. 18)
+            regValue = 0x8092200000000000;
+        }
+        else
+        {
+            // clock_divider=36, frames=15 (i.e. 16)
+            regValue = 0x8091E00000000000;
+        }
         rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, regValue);
         if(rc)
         {
@@ -186,7 +195,6 @@ void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     apss_continue_args_t *args = (apss_continue_args_t*)async_cmd->cmd_data;
 
-
     // Clear error, ffdc, and rc (feedback to 405)
     // These may be overwritten by error codes if errors occur
     // REVIEW: Since the OCC clears these fields, do we really have to repeat this here?
@@ -289,7 +297,6 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     apss_complete_args_t *args = (apss_complete_args_t*)async_cmd->cmd_data;
 
-
     // clear error, ffdc, and rc (feedback to 405)
     // These may be overwritten by error codes if errors occur
     // REVIEW: Since the OCC clears these fields, do we really have to repeat this here?
@@ -310,6 +317,7 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
             break;
         }
 
+        // Get Time of Day
         rc = getscom_abs(TOD_VALUE_REG, &args->meas_data[3]);
         if(rc)
         {
@@ -319,6 +327,19 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
             break;
         }
 
+        // If we're in composite mode, collect the GPIO data
+        if (APSS_MODE_COMPOSITE == G_apss_mode)
+        {
+            // Read first 8 bytes of data (GPIO frames) into meas_data[0]
+            rc = getscom_abs(SPIPSS_ADC_RDATA_REG4, &args->meas_data[0]);
+            if(rc)
+            {
+                PK_TRACE("apss_complete_pwr_meas_read: SPIPSS_ADC_RDATA_REG4 getscom failed. rc = 0x%08x",
+                         rc);
+                gpe_set_ffdc(&(args->error), SPIPSS_ADC_RDATA_REG4, GPE_RC_SCOM_GET_FAILED, rc);
+                break;
+            }
+        }
     } while(0);
 
     // send back a response, IPC success (even if ffdc/rc are non zeros)
diff --git a/src/occ_gpe0/pss_constants.h b/src/occ_gpe0/pss_constants.h
index fa7e46b..08a7d90 100755
--- a/src/occ_gpe0/pss_constants.h
+++ b/src/occ_gpe0/pss_constants.h
@@ -1,11 +1,11 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/occ_405/gpe/pss_constants.h $                             */
+/* $Source: src/occ_gpe0/pss_constants.h $                                */
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -39,6 +39,10 @@
 #define SPIPSS_ADC_RDATA_REG1         (SPIPSS_REGISTER_BASE + 0x21)
 #define SPIPSS_ADC_RDATA_REG2         (SPIPSS_REGISTER_BASE + 0x22)
 #define SPIPSS_ADC_RDATA_REG3         (SPIPSS_REGISTER_BASE + 0x23)
+#define SPIPSS_ADC_RDATA_REG4         (SPIPSS_REGISTER_BASE + 0x24)
+#define SPIPSS_ADC_RDATA_REG5         (SPIPSS_REGISTER_BASE + 0x25)
+#define SPIPSS_ADC_RDATA_REG6         (SPIPSS_REGISTER_BASE + 0x26)
+#define SPIPSS_ADC_RDATA_REG7         (SPIPSS_REGISTER_BASE + 0x27)
 #define SPIPSS_100NS_REG              (SPIPSS_REGISTER_BASE + 0x28)
 #define SPIPSS_P2S_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x40)
 #define SPIPSS_P2S_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x41)