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author | Prachi Gupta <pragupta@us.ibm.com> | 2017-07-17 17:43:01 -0500 |
---|---|---|
committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-07-21 17:51:40 -0400 |
commit | b796b12052f5542945bf6d1a831f8d67a502a0ef (patch) | |
tree | c3eb6825606ce714b5d020b1092c5d6c05d06027 /src/occ_gpe0/firdata | |
parent | 3d71bd95e10f82ae2a96e6ebc929dc2ca7b1b63c (diff) | |
download | talos-occ-b796b12052f5542945bf6d1a831f8d67a502a0ef.tar.gz talos-occ-b796b12052f5542945bf6d1a831f8d67a502a0ef.zip |
rt_xstop_analysis: single proc fir collection is working, without pnor writes
Change-Id: Ib49d3b9d52c8f4e1054e9b0c0d609a6e13908ddb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43245
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_gpe0/firdata')
-rw-r--r-- | src/occ_gpe0/firdata/firData.c | 154 | ||||
-rw-r--r-- | src/occ_gpe0/firdata/fir_data_collect.c | 2 | ||||
-rw-r--r-- | src/occ_gpe0/firdata/homerData_common.h | 1 | ||||
-rw-r--r-- | src/occ_gpe0/firdata/native.c | 4 | ||||
-rw-r--r-- | src/occ_gpe0/firdata/pnorData_common.h | 2 | ||||
-rw-r--r-- | src/occ_gpe0/firdata/scom_util.c | 83 |
6 files changed, 140 insertions, 106 deletions
diff --git a/src/occ_gpe0/firdata/firData.c b/src/occ_gpe0/firdata/firData.c index f124ad3..04ae81d 100644 --- a/src/occ_gpe0/firdata/firData.c +++ b/src/occ_gpe0/firdata/firData.c @@ -81,6 +81,7 @@ typedef struct } FirData_existBits_t; + /* Uncomment for additional debug traces */ #if 0 #define DEBUG_PRD_CHKSTOP_ANALYSIS @@ -98,7 +99,6 @@ bool FirData_addDataToPnor( FirData_t * io_fd, void * i_data, uint32_t i_dataSize ) { bool full = (io_fd->maxPBufSize < io_fd->pBufSize + i_dataSize); - if ( full ) { /* Indicate the PNOR data is full. */ @@ -107,7 +107,13 @@ bool FirData_addDataToPnor( FirData_t * io_fd, void * i_data, else { /* Copy data to PNOR buffer. */ - memcpy( &io_fd->pBuf[io_fd->pBufSize], i_data, i_dataSize ); + uint8_t* l_destPtr = (uint8_t*)(&io_fd->pBuf[io_fd->pBufSize]); + uint8_t* l_srcPtr = (uint8_t*)(i_data); + int i; + for (i = 0; i < i_dataSize; i++) + { + l_destPtr[i] = l_srcPtr[i]; + } io_fd->pBufSize += i_dataSize; } @@ -132,12 +138,17 @@ bool FirData_addRegToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, bool full = false; int32_t rc = 0; - PNOR_Reg_t reg = { i_addr, 0 }; + PNOR_Reg_t reg = { 0, i_addr }; *o_nonZero = false; do { +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_ERR( "[FirData_addRegToPnor] t=0x%x p=0x%x u=0x%x scom addr=0x%08x", + (uint32_t)i_sTrgt.type, (uint32_t)i_sTrgt.procPos, + (uint32_t)i_sTrgt.procUnitPos, (uint32_t)i_addr); +#endif rc = SCOM_getScom( i_sTrgt, i_addr, &(reg.val) ); if ( SUCCESS != rc ) { @@ -152,8 +163,14 @@ bool FirData_addRegToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, break; } + if ( 0 == reg.val ) break; // Skip zero value registers. +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_IMP("addRegToPnor: got scom value, addr=0x%08X value=0x%08X %08X", + i_addr, (uint32_t)(reg.val>>32), reg.val); +#endif + full = FirData_addDataToPnor( io_fd, ®, sizeof(reg) ); if ( full ) break; @@ -165,9 +182,7 @@ bool FirData_addRegToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, } while (0); #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_INFO(" addToPnor: Type:%d Pos:%d Unit:%d Addr:%X Full:%d", - i_sTrgt.type, i_sTrgt.procPos, i_sTrgt.procUnitPos, - i_addr, full ); + TRAC_IMP(" FirData_addRegToPnor completed for some target "); #endif return full; @@ -198,6 +213,11 @@ bool FirData_addIdRegToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, do { +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_ERR( "[FirData_addIdRegToPnor] t=0x%x p=0x%x u=0x%x scom addr=0x%08x", + (uint32_t)i_sTrgt.type, (uint32_t)i_sTrgt.procPos, + (uint32_t)i_sTrgt.procUnitPos, (uint32_t)i_addr); +#endif rc = SCOM_getIdScom( i_sTrgt, i_addr, &(reg.val) ); if ( SUCCESS != rc ) { @@ -206,8 +226,14 @@ bool FirData_addIdRegToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, break; } + if ( 0 == reg.val ) break; // Skip zero value registers. +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_IMP("addRegToPnor: got scom value, addr=0x%08X %08X value=0x%08X", + (uint32_t)(i_addr>>32), i_addr, (uint32_t)reg.val); +#endif + full = FirData_addDataToPnor( io_fd, ®, sizeof(reg) ); if ( full ) break; @@ -264,6 +290,7 @@ bool FirData_addGlblsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, full = FirData_addRegToPnor( io_fd, io_pTrgt, i_sTrgt, addr, &nonZero ); + if ( full ) break; if ( nonZero ) l_isAnyNonZero = true; @@ -281,12 +308,12 @@ bool FirData_addGlblsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, for ( i = 0; i < cnt; i++ ) { #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_INFO(" addGlblsToPnor In/Array: chipType:%X::%X trgType:%X::%X" - " regType:%X::%X ecLevel %X::%X", - i_chipStruct->chipType, l_ecAddrtPtr->chipType, - t, l_ecAddrtPtr->trgtType, - REG_GLBL, l_ecAddrtPtr->regType, - i_chipStruct->chipEcLevel, l_ecAddrtPtr->ddLevel ); + TRAC_IMP(" addGlblsToPnor In/Array: chipType:%X::%X trgType:%X::%X", + (uint32_t)i_chipStruct->chipType, (uint32_t)l_ecAddrtPtr->chipType, + (uint32_t)t, (uint32_t)l_ecAddrtPtr->trgtType); + TRAC_IMP("addGlblsToPnor: regType:%X::%X ecLevel %X::%X", + (uint32_t)REG_GLBL, (uint32_t)l_ecAddrtPtr->regType, + (uint32_t)i_chipStruct->chipEcLevel, (uint32_t)l_ecAddrtPtr->ddLevel); #endif /** Need same chipType (nimbus,cumulus,etc..), same target type, */ @@ -393,12 +420,12 @@ bool FirData_addFirsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, for ( i = 0; i < cnt; i++ ) { #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_INFO(" addFirsToPnor In/Array: chipType:%X::%X trgType:%X::%X" - " regType:%X::%X ecLevel %X::%X", - i_chipStruct->chipType, l_ecAddrtPtr->chipType, - t, l_ecAddrtPtr->trgtType, - REG_GLBL, l_ecAddrtPtr->regType, - i_chipStruct->chipEcLevel, l_ecAddrtPtr->ddLevel ); + TRAC_IMP(" addFirsToPnor In/Array: chipType:%X::%X trgType:%X::%X", + (uint32_t)i_chipStruct->chipType, (uint32_t)l_ecAddrtPtr->chipType, + (uint32_t)t, (uint32_t)l_ecAddrtPtr->trgtType); + TRAC_IMP("regType:%X::%X ecLevel %X::%X", + (uint32_t)REG_FIR, (uint32_t)l_ecAddrtPtr->regType, + (uint32_t)i_chipStruct->chipEcLevel, (uint32_t)l_ecAddrtPtr->ddLevel); #endif /** Need same chipType (nimbus,cumulus,etc..), same target type, */ @@ -408,6 +435,7 @@ bool FirData_addFirsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, (l_ecAddrtPtr->regType == REG_FIR) && (l_ecAddrtPtr->ddLevel == i_chipStruct->chipEcLevel) ) + { /* address is right justified in 64 bits */ addr = (uint32_t)(l_ecAddrtPtr->address); nonZero = false; @@ -487,10 +515,10 @@ bool FirData_addRegsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, for ( i = 0; i < cnt; i++ ) { #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_INFO(" addRegsToPnor In/Array: chipType:%X::%X trgType:%X::%X" - " regType:%X::%X ecLevel %X::%X", + TRAC_IMP(" addRegsToPnor In/Array: chipType:%X::%X trgType:%X::%X", i_chipStruct->chipType, l_ecAddrtPtr->chipType, - t, l_ecAddrtPtr->trgtType, + t, l_ecAddrtPtr->trgtType); + TRAC_IMP(" regType:%X::%X ecLevel %X::%X", REG_GLBL, l_ecAddrtPtr->regType, i_chipStruct->chipEcLevel, l_ecAddrtPtr->ddLevel ); #endif @@ -584,10 +612,10 @@ bool FirData_addIdFirsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, for ( i = 0; i < cnt; i++ ) { #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_INFO(" addIdFirsToPnor In/Array: chipType:%X::%X trgType:%X::%X" - " regType:%X::%X ecLevel %X::%X", + TRAC_IMP(" addIdFirsToPnor In/Array: chipType:%X::%X trgType:%X::%X", i_chipStruct->chipType, l_ecAddrtPtr->chipType, - t, l_ecAddrtPtr->trgtType, + t, l_ecAddrtPtr->trgtType); + TRAC_IMP(" regType:%X::%X ecLevel %X::%X", REG_GLBL, l_ecAddrtPtr->regType, i_chipStruct->chipEcLevel, l_ecAddrtPtr->ddLevel ); #endif @@ -680,10 +708,10 @@ bool FirData_addIdRegsToPnor( FirData_t * io_fd, PNOR_Trgt_t * io_pTrgt, for ( i = 0; i < cnt; i++ ) { #ifdef DEBUG_PRD_CHKSTOP_ANALYSIS - TRAC_IMP(" addIdRegsToPnor In/Array: chipType:%X::%X trgType:%X::%X" - " regType:%X::%X ecLevel %X::%X", + TRAC_IMP(" addIdRegsToPnor In/Array: chipType:%X::%X trgType:%X::%X", i_chipStruct->chipType, l_ecAddrtPtr->chipType, - t, l_ecAddrtPtr->trgtType, + t, l_ecAddrtPtr->trgtType); + TRAC_IMP(" regType:%X::%X ecLevel %X::%X", REG_GLBL, l_ecAddrtPtr->regType, i_chipStruct->chipEcLevel, l_ecAddrtPtr->ddLevel ); #endif @@ -728,11 +756,17 @@ bool FirData_addTrgtToPnor( FirData_t * io_fd, SCOM_Trgt_t i_sTrgt, bool * o_noAttn, HOMER_Chip_t *i_chipStruct ) { bool full = false; - PNOR_Trgt_t * pTrgt = (PNOR_Trgt_t *)(&io_fd->pBuf[io_fd->pBufSize]); - PNOR_Trgt_t tmp_pTrgt = PNOR_getTrgt( i_sTrgt.type, i_sTrgt.procPos, - i_sTrgt.procUnitPos ); + + /* may be able to remove PNOR_getTrgt function */ + /* had some issue with local var return in diff function so take out */ + /* init to zero */ + PNOR_Trgt_t tmp_pTrgt; memset( &tmp_pTrgt, 0x00, sizeof(tmp_pTrgt) ); + + tmp_pTrgt.trgtType = i_sTrgt.type; + tmp_pTrgt.chipPos = i_sTrgt.procPos, + tmp_pTrgt.unitPos = i_sTrgt.procUnitPos; *o_noAttn = false; /* Must be false if there are no global regs. */ @@ -743,6 +777,7 @@ bool FirData_addTrgtToPnor( FirData_t * io_fd, SCOM_Trgt_t i_sTrgt, { /* Add the target info to PNOR. */ full = FirData_addDataToPnor( io_fd, &tmp_pTrgt, sizeof(tmp_pTrgt) ); + if ( full ) break; /* Update the number of targets in the PNOR data. */ @@ -804,15 +839,13 @@ void FirData_addTrgtsToPnor( FirData_t * io_fd ) memset(&l_existBits, 0x00, sizeof(FirData_existBits_t) ); /* Point past HOMER header to first chiplet info */ - /* The HOMER_Data_t struct may have some padding added after the struct - * to ensure the HOMER_Chip_t structs are 4-byte word aligned. */ + /* The HOMER_Data_t struct may have some padding added after the struct */ + /* to ensure the HOMER_Chip_t structs are 4-byte word aligned. */ uint32_t sz_word = sizeof(uint32_t); uint32_t pad = (sz_word - (sizeof(HOMER_Data_t) % sz_word)) % sz_word; uint8_t *l_bytePtr = io_fd->hBuf + sizeof(HOMER_Data_t) + pad; HOMER_Chip_t *l_chipPtr = NULL; - TRAC_IMP("AddTgtsMain:numChips:%d", (uint32_t)io_fd->hData->chipCount); - /* Iterate ALL CHIPs */ for ( p = 0; p < io_fd->hData->chipCount; p++ ) { @@ -822,9 +855,6 @@ void FirData_addTrgtsToPnor( FirData_t * io_fd ) fsi = l_chipPtr->fsiBaseAddr; p = l_chipPtr->chipPos; - TRAC_IMP( " AddTgtsMain:ChipType:%d ChipNumber:%d", - l_chipPtr->chipType, p ); - /* Is this a PROC or Centaur chip ? */ if ( (HOMER_CHIP_NIMBUS == l_chipPtr->chipType) || (HOMER_CHIP_CUMULUS == l_chipPtr->chipType) ) @@ -907,13 +937,18 @@ void FirData_addTrgtsToPnor( FirData_t * io_fd ) l_bytePtr += sizeof(HOMER_ChipCumulus_t); } /* else if cumulus */ -// TRAC_IMP("Masks XBUS:%X OBUS:%X EC:%X EQ:%X EX:%X CAPP:%X PEC:%X PHB:%X", -// (uint32_t)l_existBits.xbusMask, (uint32_t)l_existBits.obusMask, (uint32_t)l_existBits.ecMask, -// (uint32_t)l_existBits.eqMask, (uint32_t)l_existBits.exMask, (uint32_t)l_existBits.cappMask, -// (uint32_t)l_existBits.pecMask, (uint32_t)l_existBits.phbMask); -// TRAC_IMP("Masks MCBIST:%X MCS:%X MCA:%X", -// (uint32_t)l_existBits.mcbist_mc_Mask, (uint32_t) l_existBits.mcs_mi_Mask, -// (uint32_t)l_existBits.mca_dmi_Mask); + +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_IMP(" Masks XBUS:%X OBUS:%X ", + l_existBits.xbusMask, l_existBits.obusMask); + TRAC_IMP(" Masks EC:%X EQ:%X EX:%X", + l_existBits.ecMask, l_existBits.eqMask, l_existBits.exMask); + TRAC_IMP(" Masks CAPP:%X PEC:%X PHB:%X",l_existBits.cappMask, + l_existBits.pecMask, l_existBits.phbMask ); + TRAC_IMP(" Masks MCBIST:%X MCS:%X MCA:%X", + l_existBits.mcbist_mc_Mask, l_existBits.mcs_mi_Mask, + l_existBits.mca_dmi_Mask ); +#endif /* Add this PROC to the PNOR. */ sTrgt = SCOM_Trgt_getTrgt(TRGT_PROC, p, 0, fsi, isM); @@ -1124,7 +1159,7 @@ void FirData_addTrgtsToPnor( FirData_t * io_fd ) } if ( full ) break; - + break; //@TODO remove when 2 proc support is in place } /* if processor chip type */ else if (HOMER_CHIP_CENTAUR == l_chipPtr->chipType) { @@ -1197,8 +1232,6 @@ int32_t FirData_init( FirData_t * io_fd, uint8_t * reglist = NULL; - PNOR_Data_t pData = PNOR_getData(); - do { /* Init the struct. */ @@ -1235,6 +1268,10 @@ int32_t FirData_init( FirData_t * io_fd, io_fd->maxPBufSize = sz_pnoNoEcc; /* Initialize the PNOR header data. */ + PNOR_Data_t pData; + memset( &pData, 0x00, sizeof(pData) ); /* init to zero */ + pData.header = PNOR_FIR2; + full = FirData_addDataToPnor( io_fd, &pData, sizeof(pData) ); if ( full ) { @@ -1262,8 +1299,8 @@ int32_t FirData_init( FirData_t * io_fd, /* Homer buffer. */ if ( io_fd->maxHBufSize - sz_hData < curIdx ) { - TRAC_ERR( FUNC"HOMER list size %d is larger than HOMER data " - "buffer %d", (uint32_t)curIdx, (uint32_t)(io_fd->maxHBufSize - sz_hData )); + TRAC_ERR( "HOMER list size %d is larger than HOMER data buffer %d", + curIdx, (io_fd->maxHBufSize - sz_hData )); rc = FAIL; break; } @@ -1324,6 +1361,7 @@ int32_t FirData_init( FirData_t * io_fd, } while (0); + TRAC_IMP("FirData_init done"); return rc; @@ -1352,6 +1390,17 @@ int32_t FirData_captureCsFirData( uint8_t * i_hBuf, uint32_t i_hBufSize, break; } +#ifdef DEBUG_PRD_CHKSTOP_ANALYSIS + TRAC_IMP("going to print all pointers from fd"); + TRAC_IMP("hBuf:0x%08X, maxHbufSize:0x%08X, hData:0x%08X", + (uint32_t)(fd.hBuf), (uint32_t)(fd.maxHBufSize), (uint32_t)(fd.hData)); + TRAC_IMP("pBuf:0x%08X, maxPBufSize:0x%08X, pData:0x%08X, pBufSize:0x%08X", + (uint32_t)(fd.pBuf), (uint32_t)(fd.maxPBufSize), (uint32_t)(fd.pData), + (uint32_t)(fd.pBufSize)); + TRAC_IMP("hPtrs:0x%08X, ecDepRegs:0x%08X", (uint32_t)(fd.hPtrs), + (uint32_t)(fd.ecDepReg)); +#endif + /* Check for valid HOMER data. */ if ( HOMER_FIR2 != fd.hData->header ) { @@ -1360,24 +1409,21 @@ int32_t FirData_captureCsFirData( uint8_t * i_hBuf, uint32_t i_hBufSize, break; /* nothing to analyze. */ } - /* Start adding register data to PNOR for each target. */ FirData_addTrgtsToPnor( &fd ); /* Write Buffer to PNOR */ -/* TODO: enable when function is supported. - rc = PNOR_writeFirData( fd.hData->pnorInfo, fd.pBuf, fd.pBufSize ); + //rc = PNOR_writeFirData( fd.hData->pnorInfo, fd.pBuf, fd.pBufSize ); if ( SUCCESS != rc ) { TRAC_ERR( FUNC"Failed to process FIR data" ); break; } -*/ } while (0); if ( SUCCESS != rc ) { - TRAC_ERR( FUNC"Failed: i_hBuf=%08x, i_hBufSize=0x%08x, i_pBuf=%08x, " + TRAC_ERR( "Failed: i_hBuf=%p, i_hBufSize=0x%08x, i_pBuf=%p, " "i_pBufSize=%08x", (uint32_t)i_hBuf, (uint32_t)i_hBufSize, (uint32_t)i_pBuf, (uint32_t)i_pBufSize ); } diff --git a/src/occ_gpe0/firdata/fir_data_collect.c b/src/occ_gpe0/firdata/fir_data_collect.c index d4e1b5e..cf1de9d 100644 --- a/src/occ_gpe0/firdata/fir_data_collect.c +++ b/src/occ_gpe0/firdata/fir_data_collect.c @@ -48,7 +48,7 @@ void fir_data_collect(void) // Homer data section and size uint8_t *l_hBuf = (uint8_t*) G_gpe_shared_data->fir_params_buffer_ptr; - uint32_t l_hBufSize = HOMER_FIR_PARM_SIZE; + uint32_t l_hBufSize = FIR_PARMS_SECTION_SIZE; // PNOR working buffer in SRAM and size uint8_t *l_pBuf = (uint8_t*) G_gpe_shared_data->fir_heap_buffer_ptr; diff --git a/src/occ_gpe0/firdata/homerData_common.h b/src/occ_gpe0/firdata/homerData_common.h index 66aa53a..23ee7ed 100644 --- a/src/occ_gpe0/firdata/homerData_common.h +++ b/src/occ_gpe0/firdata/homerData_common.h @@ -163,6 +163,7 @@ typedef struct __attribute__((packed)) /* NOTE: This structure is 4-byte word aligned. */ typedef struct __attribute__((packed)) { + uint32_t chipType : 4; /** See HOMER_ChipType_t. */ uint32_t trgtType : 6; /** See TrgtType_t. */ uint32_t regType : 4; /** See RegType_t. */ diff --git a/src/occ_gpe0/firdata/native.c b/src/occ_gpe0/firdata/native.c index 0a57867..337c97b 100644 --- a/src/occ_gpe0/firdata/native.c +++ b/src/occ_gpe0/firdata/native.c @@ -42,7 +42,7 @@ int32_t xscom_read( uint32_t i_address, uint64_t * o_data ) //P9 SCOM logic requires a target. However, if we're here, then it doesn't //matter which target we pass in, so long as isMaster is true. This will //allow to take the branch of code that schedules GPE scom job. See - //src/occ_405/firdata/scom_util.c for more info. + //src/occ_gpe0/firdata/scom_util.c for more info. SCOM_Trgt_t l_tempTarget; l_tempTarget.type = TRGT_PROC; l_tempTarget.isMaster = TRUE; @@ -64,7 +64,7 @@ int32_t xscom_write( uint32_t i_address, uint64_t i_data ) //P9 SCOM logic requires a target. However, if we're here, then it doesn't //matter which target we pass in, so long as isMaster is true. This will //allow to take the branch of code that schedules GPE scom job. See - //src/occ_405/firdata/scom_util.c for more info. + //src/occ_gpe0/firdata/scom_util.c for more info. SCOM_Trgt_t l_tempTarget; l_tempTarget.type = TRGT_PROC; l_tempTarget.isMaster = TRUE; diff --git a/src/occ_gpe0/firdata/pnorData_common.h b/src/occ_gpe0/firdata/pnorData_common.h index 3037e39..8ec238c 100644 --- a/src/occ_gpe0/firdata/pnorData_common.h +++ b/src/occ_gpe0/firdata/pnorData_common.h @@ -144,8 +144,8 @@ static inline PNOR_Trgt_t PNOR_getTrgt( uint32_t i_trgtType, uint32_t i_chipPos, /* NOTE: This structure is 4-byte word aligned. */ typedef struct __attribute__((packed)) { - uint32_t addr; /** 32-bit address */ uint64_t val; /** 64-bit value */ + uint32_t addr; /** 32-bit address */ } PNOR_Reg_t; diff --git a/src/occ_gpe0/firdata/scom_util.c b/src/occ_gpe0/firdata/scom_util.c index 491c213..5f5656a 100644 --- a/src/occ_gpe0/firdata/scom_util.c +++ b/src/occ_gpe0/firdata/scom_util.c @@ -30,8 +30,7 @@ #include <scom_util.h> #include "scom_addr_util.h" #include <sbe_fifo.h> - -bool G_request_created = FALSE; +#include <ppe42_scom.h> enum { /*FSI addresses are byte offsets, so need to multiply by 4 @@ -340,47 +339,6 @@ int32_t translate_addr( SCOM_Trgt_t i_trgt, uint64_t i_addr, uint64_t * o_addr ) } /** - * @brief Performs a getscom operation with no address translation. - * @param i_chip Chip to SCOM. - * @param i_addr Address to SCOM. - * @param o_val Returned value. - * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. - */ -int32_t getscomraw( SCOM_Trgt_t i_chip, uint32_t i_addr, uint64_t * o_val ) -{ - int32_t l_rc = SUCCESS; - - //Use SBE FIFO if it's a slave proc - if(!i_chip.isMaster) - { - return getFifoScom(&i_chip, i_addr, o_val); - } - *o_val = 0; - l_rc = FAIL; - - return l_rc; -} - -/** - * @brief Perform a putscom operation with no address translation. - * @param i_chip Chip to SCOM. - * @param i_addr Address to SCOM. - * @param i_val Value to write. - * @return Non-SUCCESS if an internal function fails. SUCCESS otherwise. - */ -int32_t putscomraw( SCOM_Trgt_t i_chip, uint32_t i_addr, uint64_t i_val ) -{ - int32_t l_rc = SUCCESS; - - //Use SBE FIFO if it's a slave proc - if(!i_chip.isMaster) - { - return putFifoScom(&i_chip, i_addr, i_val); - } - return l_rc; -} - -/** * @brief Executes standard getscom. * @param i_trgt Chip to SCOM. * @param i_addr Address to SCOM. @@ -399,8 +357,15 @@ int32_t SCOM_getScom( SCOM_Trgt_t i_trgt, uint32_t i_addr, uint64_t * o_val ) rc = translate_addr( i_trgt, i_addr, &trans_addr ); if ( SUCCESS == rc ) { - /* Do the SCOM. */ - rc = getscomraw( chip_targ, trans_addr, o_val ); + //Use SBE FIFO if it's a slave proc + if(!chip_targ.isMaster) + { + return getFifoScom(&chip_targ, trans_addr, o_val); + } + else + { + rc = getscom_abs(trans_addr, o_val); + } } return rc; @@ -447,7 +412,14 @@ int32_t SCOM_getIdScom( SCOM_Trgt_t i_trgt, uint64_t i_addr, uint32_t * o_val ) data_buffer |= 0x8000000000000000; /* perform write before the read with the new */ - rc = putscomraw( i_trgt, phys_addr, data_buffer ); + if(!chip_targ.isMaster) + { + rc = putFifoScom(&chip_targ, phys_addr, data_buffer); + } + else + { + rc = putscom_abs(phys_addr, data_buffer); + } if ( SUCCESS != rc ) return rc; // Loop on read until we see done, error, or we timeout @@ -457,7 +429,15 @@ int32_t SCOM_getIdScom( SCOM_Trgt_t i_trgt, uint64_t i_addr, uint32_t * o_val ) { /* Now perform the op requested using the passed in */ /* IO_Buffer to pass the read data back to caller. */ - rc = getscomraw( chip_targ, phys_addr, &(scomout.data64) ); + //Use SBE FIFO if it's a slave proc + if(!chip_targ.isMaster) + { + rc = getFifoScom(&chip_targ, trans_addr, &(scomout.data64)); + } + else + { + rc = getscom_abs(trans_addr, &(scomout.data64)); + } if ( SUCCESS != rc ) return rc; /* Check for PIB error. */ @@ -512,7 +492,14 @@ int32_t SCOM_putScom( SCOM_Trgt_t i_trgt, uint32_t i_addr, uint64_t i_val ) if ( SUCCESS == l_rc ) { /* Do the SCOM. */ - l_rc = putscomraw( l_chip_targ, l_trans_addr, i_val ); + if(!l_chip_targ.isMaster) + { + return putFifoScom(&l_chip_targ, i_addr, i_val); + } + else + { + l_rc = putscom_abs(l_trans_addr, i_val); + } } return l_rc; |