Enabled FFDC and Simics

    Also included:
    -- Some more cmdh files into the build
    -- Workaround for OCB Timer divider register in Simics
    -- Workaround to start APSS tasks until DCOM is back

    RTC: 133819

Change-Id: Ie19c2a544f64c40126c2bc4a0af6fabfe6430d21
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19998
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>

13 files changed, 198 insertions, 112 deletions

diff --git a/src/occ_405/Makefile b/src/occ_405/Makefile
index da572d0..1d173dc 100755
--- a/src/occ_405/Makefile
+++ b/src/occ_405/Makefile
@@ -40,6 +40,7 @@ OCCLIB := $(OBJDIR)/occlib/libocc.a
 PPC405LIB := $(OBJDIR)/ppc405lib/libppc405.a
 LINK_OBJS = $(OBJS) $(SSXLIB) $(COMMONLIB) $(OCCLIB) $(PPC405LIB)
 LINK_SCRIPT = $(addprefix $(OBJDIR)/, linkscript)
+LINK_CMD_SCRIPT = linkocc.cmd
 LDFLAGS += --oformat=elf32-powerpc -melf32ppc
 LIB_DIRS =  -L$(OBJDIR)/ssx \
             -L$(OBJDIR)/ssx/ppc405 \
@@ -69,15 +70,15 @@ $(OBJDIR)/$(IMAGE_NAME).out: $(LINK_OBJS) $(LINK_SCRIPT)
 	$(LD) -e __ssx_boot -T$(LINK_SCRIPT) $(LDFLAGS) -Map $(OBJDIR)/$(IMAGE_NAME).map -Bstatic -o $(OBJDIR)/$(IMAGE_NAME).out $(LIB_DIRS) -lssx -locc -lppc405 -lcommon
 
 #pass the link command file through the C preprocessor to evaluate macros and remove comments
-$(LINK_SCRIPT): linkocc.cmd
-	$(CPP) -E -x c -P $(DEFS) linkocc.cmd -o $(LINK_SCRIPT)
+#$(LINK_SCRIPT): linkocc.cmd
+$(LINK_SCRIPT): $(LINK_CMD_SCRIPT)
+	$(CPP) -E -x c -P $(DEFS) $(LINK_CMD_SCRIPT) -o $(LINK_SCRIPT)
 
 #Create an obj directory if needed
 $(LINK_OBJS) $(OBJS) $(OBJS:.o=.d): | $(OBJDIRS)
 
 $(OBJDIRS):
 	mkdir -p $(OBJDIRS)
-	
 
 #Build the SSX kernel library
 $(SSXLIB):
@@ -112,6 +113,6 @@ clean:
 	rm -fr $(OBJDIR)
 
 #Add dependencies to header files
-ifneq ($(MAKECMDGOALS),clean)
-include $(OBJS:.o=.d) 
-endif
+#ifneq ($(MAKECMDGOALS),clean)
+#include $(OBJS:.o=.d)
+#endif
diff --git a/src/occ_405/aplt/appletManager.c b/src/occ_405/aplt/appletManager.c
index e739803..b6effcc 100755
--- a/src/occ_405/aplt/appletManager.c
+++ b/src/occ_405/aplt/appletManager.c
@@ -40,7 +40,9 @@
 #include "pba_firmware_registers.h"
 #include "occhw_pba.h"
 #include "occhw_async.h"
+#if PPC405_MMU_SUPPORT
 #include "ppc405_mmu.h"
+#endif
 #include "occhw.h"
 #include "cmdh_fsp.h"
 
@@ -376,6 +378,7 @@ errlHndl_t __attribute__((optimize("O1"))) initAppletAddr( void )
 
     // copy SSX mmu map to ApltInfo structure
     // startApplet() will use it to clear tlb entry
+#if PPC405_MMU_SUPPORT
     G_ApltInfo.mmuMapWritePermission = G_applet0_mmu_map;
     G_TestApltInfo.mmuMapWritePermission = G_applet1_mmu_map;
 
@@ -384,7 +387,7 @@ errlHndl_t __attribute__((optimize("O1"))) initAppletAddr( void )
     // mmu map/unmap several times.
     G_applet0_mmu_map = 0;
     G_applet1_mmu_map = 0;
-
+#endif
     return l_err;
 }
 
@@ -450,7 +453,7 @@ void initAppletManager( void )
         }
 
         CHECKPOINT(APP_SEMS_CREATED);
-
+#if PPC405_MMU_SUPPORT
         // Map mainstore to oci space so that we can walk through
         // OCC signed image to get applet addresses
         int l_ssxRc = ppc405_mmu_map(0,         //Mainstore address 0x0
@@ -482,7 +485,7 @@ void initAppletManager( void )
                               0);                               //userdata2
             break;
         }
-
+#endif /* PPC405_MMU_SUPPORT */
         CHECKPOINT(APP_MEM_MAPPED);
 
         // set to indicate to do mmu unmap after we are done using it.
@@ -505,6 +508,8 @@ void initAppletManager( void )
     {
         CHECKPOINT(APP_MEM_UNMAP);
 
+#if PPC405_MMU_SUPPORT
+
         // Unmap mmu mapping for main store to oci space.
         // NOTE: This needs to be unmapped because 1) PowerBus disruptions
         // could leave OCC hung for several uS if main memory accessed at
@@ -545,6 +550,7 @@ void initAppletManager( void )
                 commitErrl(&l_err);
             }
         }
+#endif /* PPC405_MMU_SUPPORT */
     }
 
     if( NULL != l_rc )
@@ -783,6 +789,9 @@ void startApplet( const OCC_APLT_TYPE i_isTestAplt )
         // re-load the test applet every time since they all use the same applet ID.
         if ( (l_info->appId == OCC_APLT_TEST) || (l_info->appId != l_info->previousAppId) )
         {
+
+#if PPC405_MMU_SUPPORT
+
             // 1a. check applet read-only/executable permissions, unmap it if existed.
             //     whole applet memory region in SRAM should be free first, then set it to
             //     writable for copyimage and calculate checksum.
@@ -864,6 +873,8 @@ void startApplet( const OCC_APLT_TYPE i_isTestAplt )
                 break;
             }
 
+#endif /* PPC405_MMU_SUPPORT */
+
             // 2. read applet header info
             // 3. copy applet image to SRAM using DMA
 
@@ -994,6 +1005,8 @@ void startApplet( const OCC_APLT_TYPE i_isTestAplt )
             // get it for next step to protect text and data section
             l_applet_readonly_size = l_apltHeader->readonly_size;
 
+#if PPC405_MMU_SUPPORT
+
             // 5b. unmap (remove permissions) on SRAM applet after copying applet image.
             //     permissions should be set correctly in SRAM rodata/rwdata section in next step.
             if ( l_info->mmuMapWritePermission != 0 )
@@ -1076,6 +1089,8 @@ void startApplet( const OCC_APLT_TYPE i_isTestAplt )
                 }
             }
 
+#endif /* PPC405_MMU_SUPPORT */
+
             // save off current applet being run (already copied) into previous
             // ie: cache applet id
             // NOTE: This is done here, to ensure the full set up is always completed
diff --git a/src/occ_405/cmdh/cmdh_mnfg_intf.c b/src/occ_405/cmdh/cmdh_mnfg_intf.c
index 4717982..26f993a 100755
--- a/src/occ_405/cmdh/cmdh_mnfg_intf.c
+++ b/src/occ_405/cmdh/cmdh_mnfg_intf.c
@@ -410,8 +410,9 @@ uint8_t cmdh_mnfg_list_sensors(const cmdh_fsp_cmd_t * i_cmd_ptr,
         // Do sanity check on the function inputs
         if ((NULL == i_cmd_ptr) || (NULL == o_rsp_ptr))
         {
+// TODO: THESE TRACES NEED TO BE VERIFIED
             TRAC_ERR("cmdh_mnfg_list_sensors: invalid pointers. cmd[0x%08x] rsp[0x%08x]",
-                     i_cmd_ptr, o_rsp_ptr);
+                     (uint32_t) i_cmd_ptr, (uint32_t) o_rsp_ptr);
             l_rc = ERRL_RC_INTERNAL_FAIL;
             break;
         }
@@ -553,8 +554,9 @@ uint8_t cmdh_mnfg_get_sensor(const cmdh_fsp_cmd_t * i_cmd_ptr,
         // Do sanity check on the function inputs
         if ((NULL == i_cmd_ptr) || (NULL == o_rsp_ptr))
         {
+// TODO: THESE TRACES NEED TO BE VERIFIED
             TRAC_ERR("cmdh_mnfg_get_sensor: invalid pointers. cmd[0x%08x] rsp[0x%08x]",
-                     i_cmd_ptr, o_rsp_ptr);
+                     (uint32_t) i_cmd_ptr, (uint32_t) o_rsp_ptr);
             l_rc = ERRL_RC_INTERNAL_FAIL;
             break;
         }
diff --git a/src/occ_405/cmdh/ll_ffdc.S b/src/occ_405/cmdh/ll_ffdc.S
index 08d5179..2fd6d78 100644
--- a/src/occ_405/cmdh/ll_ffdc.S
+++ b/src/occ_405/cmdh/ll_ffdc.S
@@ -188,7 +188,8 @@
 # FFDC Constants
 # --------------
 
-    .set        FFDC_BUFFER_ADDR, 0xFFFF7000
+    # The FFDC buffer is the response buffer
+    .set        FFDC_BUFFER_ADDR, 0xFFFB6800
     .set        FFDC_DBCR0, (DBCR0_EDM | DBCR0_TDE | DBCR0_FT)
     .set        FFDC_END_MARKER, 0xFFDCFFDC
     .set        FFDC_OCC_CHECKPOINT, 0x0F00
@@ -810,12 +811,21 @@ __save_ffdc_regs:
     # Save OISR1
     _lwzi       %r5, %r5, OCB_OISR1
     _stwi       %r5, %r3, OISR1
+
+    # TODO/NOTE: These registers were commented out for P9 because
+    # they were removed from the headerfile, ocb_register_addresses.h:
+    # OUDER0, OUDER1, OCIR0, OCIR1, ODHER0, ODHER1
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save OUDER0
-    _lwzi       %r5, %r5, OCB_OUDER0
-    _stwi       %r5, %r3, OUDER0
+    #_lwzi       %r5, %r5, OCB_OUDER0
+    #_stwi       %r5, %r3, OUDER0
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save OUDER1
-    _lwzi       %r5, %r5, OCB_OUDER1
-    _stwi       %r5, %r3, OUDER1
+    #_lwzi       %r5, %r5, OCB_OUDER1
+    #_stwi       %r5, %r3, OUDER1
+
     # Save OIMR0
     _lwzi       %r5, %r5, OCB_OIMR0
     _stwi       %r5, %r3, OIMR0
@@ -834,12 +844,17 @@ __save_ffdc_regs:
     # Save OIEPR1
     _lwzi       %r5, %r5, OCB_OIEPR1
     _stwi       %r5, %r3, OIEPR1
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save OCIR0
-    _lwzi       %r5, %r5, OCB_OCIR0
-    _stwi       %r5, %r3, OCIR0
+    #_lwzi       %r5, %r5, OCB_OCIR0
+    #_stwi       %r5, %r3, OCIR0
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save OCIR1
-    _lwzi       %r5, %r5, OCB_OCIR1
-    _stwi       %r5, %r3, OCIR1
+    #_lwzi       %r5, %r5, OCB_OCIR1
+    #_stwi       %r5, %r3, OCIR1
+
     # Save ONISR0
     _lwzi       %r5, %r5, OCB_ONISR0
     _stwi       %r5, %r3, ONISR0
@@ -852,12 +867,17 @@ __save_ffdc_regs:
     # Save OCISR1
     _lwzi       %r5, %r5, OCB_OCISR1
     _stwi       %r5, %r3, OCISR1
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save ODHER0
-    _lwzi       %r5, %r5, OCB_ODHER0
-    _stwi       %r5, %r3, ODHER0
+    #_lwzi       %r5, %r5, OCB_ODHER0
+    #_stwi       %r5, %r3, ODHER0
+
+    # TODO: DETERMINE IF THIS REGISTER EXISTS
     # Save ODHER1
-    _lwzi       %r5, %r5, OCB_ODHER1
-    _stwi       %r5, %r3, ODHER1
+    #_lwzi       %r5, %r5, OCB_ODHER1
+    #_stwi       %r5, %r3, ODHER1
+
     # Save ssx timebase
     _lwzsd      %r5, __ssx_timebase_frequency_mhz
     _stwi       %r5, %r3, FFDC_TIMEBASE
diff --git a/src/occ_405/homer.c b/src/occ_405/homer.c
index a0331ce..1ab014b 100755
--- a/src/occ_405/homer.c
+++ b/src/occ_405/homer.c
@@ -74,6 +74,8 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
     {
         *o_ssx_rc = SSX_OK;
 
+#if PPC405_MMU_SUPPORT
+
         /*
          * Map to mainstore at HOMER host data offset. The first parameter is
          * the effective address where the data can be accessed once mapped, the
@@ -86,7 +88,7 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
                                    0,
                                    0,
                                    &l_mmuMapHomer);
-
+#endif
         if (SSX_OK != *o_ssx_rc)
         {
             l_rc = HOMER_SSX_MAP_ERR;
@@ -164,13 +166,14 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
                     }
                 }
             }
-
+#if PPC405_MMU_SUPPORT
             // Unmap the HOMER before returning to caller
             *o_ssx_rc = ppc405_mmu_unmap(&l_mmuMapHomer);
             if ((SSX_OK != *o_ssx_rc) && (HOMER_SUCCESS == l_rc))
             {
                 l_rc = HOMER_SSX_UNMAP_ERR;
             }
+#endif
         }
     }
 
diff --git a/src/occ_405/img_defs.mk b/src/occ_405/img_defs.mk
index 7dcc129..de8aec6 100644
--- a/src/occ_405/img_defs.mk
+++ b/src/occ_405/img_defs.mk
@@ -143,9 +143,9 @@ SSX_THREAD_SUPPORT = 1
 endif
 
 # TODO: Enable this once we get MMU support working in simics
-# TEMP: Does this work in Simics?
+# Currently, turning on MMU support causes an SSX panic (in Simics)
 ifeq "$(PPC405_MMU_SUPPORT)" ""
-PPC405_MMU_SUPPORT = 1
+PPC405_MMU_SUPPORT = 0
 endif
 
 ifeq "$(OCCHW_ASYNC_SUPPORT)" ""
diff --git a/src/occ_405/linkocc.cmd b/src/occ_405/linkocc.cmd
index c44247c..e24cb9c 100755
--- a/src/occ_405/linkocc.cmd
+++ b/src/occ_405/linkocc.cmd
@@ -61,15 +61,21 @@ OUTPUT_FORMAT(elf32-powerpc);
 //  Define the beginning of SRAM, the location of the PowerPC exception
 //  vectors (must be 64K-aligned) and the location of the boot branch.
 
-//  512 KB SRAM at the top of the 32-bit address space
+//  512 KB SRAM at the top of the 768K SRAM. SRAM starts at 0xfff00000
+//  Here we start at 0xfff40000 because the bottom 256K is reserved for
+//  -- IPC Common space (0xfff00000 - 0xfff01000)
+//  -- GPE0 (0xfff01000 - 0xfff10000)
+//  -- GPE1 (0xfff10000 - 0xfff20000)
+//  -- GPE2 (0xfff20000 - 0xfff30000)
+//  -- GPE3 (0xfff30000 - 0xfff40000)
 
 //  Last 1kB must be reserved for PORE-SLW, so stack can't be in that space
 
-#define origin            0xfff80000
-#define vectors           0xfff80000
+#define origin            0xfff40000
+#define vectors           0xfff40000
 #define reset             0xffffffec
-#define sram_available    (reset - origin)
 #define sram_size         0x00080000
+#define sram_available    sram_size
 #define reserved_for_slw  0x400
 
 // The SRAM controller aliases the SRAM at 8 x 128MB boundaries to support
@@ -105,7 +111,8 @@ _SSX_INITIAL_STACK_LIMIT = _SSX_INITIAL_STACK - INITIAL_STACK_SIZE;
 
 // .vectors_0000
 
-#define text_0000
+#define text_0000 \
+*(.vectors_0000)
 
 #define data_0000 main.o(imageHeader)
 
@@ -195,7 +202,7 @@ occhw_async.o(.text) \
 //occhw_async_pore.o(.text) \
 occhw_async_ocb.o(.text) \
 occhw_async_pba.o(.text) \
-occhw_pmc.o(.text) \
+occhw_scom.o(.text) \
 occhw_ocb.o(.text) \
 occhw_pba.o(.text) \
 occhw_id.o(.text) \
@@ -203,7 +210,6 @@ occhw_id.o(.text) \
 ppc405_lib_core.o(.text) \
 ssx_core.o(.text)
 
-
 #define data_2000
 
 // .vectors_0000 is always packed with header information
@@ -247,10 +253,11 @@ ppc405_boot.o(.text) \
 ppc405_init.o(.text) \
 occhw_init.o(.text)
 
-#ifndef PPC405_MMU_SUPPORT
-ASSERT((0), "OCC Application Firmware can not be compiled without \
-PPC405_MMU_SUPPORT compile flag")
-#endif
+// TEMP: Commented out for Simics, as there is no MMU support yet
+//#ifndef PPC405_MMU_SUPPORT
+//ASSERT((0), "OCC Application Firmware can not be compiled without \
+//PPC405_MMU_SUPPORT compile flag")
+//#endif
 
 // Define memory areas.
 
@@ -262,6 +269,11 @@ MEMORY
  boot         : ORIGIN = reset,  LENGTH = 20
 }
 
+// This symbol is only needed by external debug tools, so add this command
+// to ensure that table is pulled in by the linker even if ppc405 code
+// never references it.
+EXTERN(ssx_debug_ptrs);
+
 // NB: The code that sets up the MMU assumes that the linker script provides a
 // standard set of symbols that define the base address and size of each
 // expected section. Any section with a non-0 size will be mapped in the MMU
@@ -327,7 +339,8 @@ SECTIONS
     // Non-cacheable and write-through data is placed in low memory to
     // improve latency.  PORE-private text and data is also placed here. PORE
     // text and data are segregated to enable relocated PORE disassembly of
-    //.text.pore.
+    //.text.pore. PORE text is read-only to OCC, however PORE data is writable
+    // by OCC to allow shared data structures (e.g., PTS).
 
     // When running without the MMU we need to carefully arrange things such
     // that the noncacheable and writethrough data is linked at the correct
@@ -354,15 +367,14 @@ SECTIONS
 
     ALIASED_SECTION(.noncacheable_ro)
     ALIASED_SECTION(.text.pore)
-    ALIASED_SECTION(.data.pore)
 
     . = ALIGN(1024);
     _NONCACHEABLE_RO_SECTION_SIZE = . - _NONCACHEABLE_RO_SECTION_BASE;
 
-
     _NONCACHEABLE_SECTION_BASE = .;
 
     ALIASED_SECTION(.noncacheable)
+    ALIASED_SECTION(.data.pore)
 
     . = ALIGN(1024);
     _NONCACHEABLE_SECTION_SIZE = . - _NONCACHEABLE_SECTION_BASE;
@@ -388,12 +400,13 @@ SECTIONS
     // To enable non-cacheable sections w/o the MMU will require setting up
     // the linker script to use aliased addresses of the SRAM.
 
-#if PPC405_MMU_SUPPORT == 0
-    ASSERT(((_NONCACHEABLE_RO_SECTION_SIZE == 0) &&
-            (_NONCACHEABLE_SECTION_SIZE == 0) &&
-            (_WRITETHROUGH_SECTION_SIZE == 0)),
-           " Non-cacheable and writethrough sections are currently only supported for MMU-enabled configurations.  Enabling these capabilities for untranslated addresses will require some modifications of the linker script.  ")
-#endif
+// TEMP: Commented out for Simics, as there is no MMU support yet
+//#if PPC405_MMU_SUPPORT == 0
+//    ASSERT(((_NONCACHEABLE_RO_SECTION_SIZE == 0) &&
+//            (_NONCACHEABLE_SECTION_SIZE == 0) &&
+//            (_WRITETHROUGH_SECTION_SIZE == 0)),
+//           " Non-cacheable and writethrough sections are currently only supported for MMU-enabled configurations.  Enabling these capabilities for untranslated addresses will require some modifications of the linker script.  ")
+//#endif
 
 
     ////////////////////////////////
@@ -461,7 +474,10 @@ SECTIONS
     // Other text
     // It's not clear why boot.S is generating empty .glink,.iplt
 
-   .otext . : { *(.text) *(.text.startup) gpe.bin*(*) gpe_1.bin*(*)} > sram
+    // In P8, this is where we put the GPE code. I do not believe we
+    // want to do that anymore, since we have allocated the bottom 256K
+    // of SRAM for that purpose.
+   .otext . : { *(.text) *(.text.startup)} > sram
    .glink . : { *(.glink) } > sram
 
      __CTOR_LIST__ = .;
@@ -505,9 +521,12 @@ SECTIONS
 
    _INIT_ONLY_DATA_BASE = .;
 
-   // _SSX_INITIAL_STACK_LIMIT = .;
-   // . = . + INITIAL_STACK_SIZE;
-   // _SSX_INITIAL_STACK = . - 1;
+   // TODO: These three lines were previously commented out (P8). Do we need
+   // space allocated for the stack? What was the reason for eliminating
+   // it in P8?
+   _SSX_INITIAL_STACK_LIMIT = .;
+   . = . + INITIAL_STACK_SIZE;
+   _SSX_INITIAL_STACK = . - 1;
 
    _INITCALL_SECTION_BASE = .;
    .data.initcall . : { *(.data.initcall) } > sram
@@ -564,7 +583,7 @@ SECTIONS
     // FIR data heap section
     ////////////////////////////////
     __CUR_COUNTER__ = .;
-    _FIR_HEAP_SECTION_BASE = 0xffff2000;
+    _FIR_HEAP_SECTION_BASE = 0xfffb1000;
     _FIR_HEAP_SECTION_SIZE = 0x3000;
     . = _FIR_HEAP_SECTION_BASE;
     .firHeap . : {*(firHeap) . = ALIGN(1024);} > sram
@@ -574,7 +593,7 @@ SECTIONS
     // FIR data parms section
     ////////////////////////////////
     __CUR_COUNTER__ = .;
-    _FIR_PARMS_SECTION_BASE = 0xffff5000;
+    _FIR_PARMS_SECTION_BASE = 0xfffb4000;
     _FIR_PARMS_SECTION_SIZE = 0x1000;
     . = _FIR_PARMS_SECTION_BASE;
     .firParms . : {*(firParms) . = ALIGN(1024);} > sram
@@ -585,9 +604,9 @@ SECTIONS
     ////////////////////////////////
     __CUR_COUNTER__ = .;
 
-    _LINEAR_WR_WINDOW_SECTION_BASE = 0xffff6000;
+    _LINEAR_WR_WINDOW_SECTION_BASE = 0xfffb5000;
     _LINEAR_WR_WINDOW_SECTION_SIZE = 0x1000;
-    _LINEAR_RD_WINDOW_SECTION_BASE = 0xffff7000;
+    _LINEAR_RD_WINDOW_SECTION_BASE = 0xfffb6800;
     _LINEAR_RD_WINDOW_SECTION_SIZE = 0x1000;
     . = _LINEAR_WR_WINDOW_SECTION_BASE;
     .linear_wr . : {*(linear_wr) . = ALIGN(_LINEAR_WR_WINDOW_SECTION_SIZE);} > sram
@@ -599,7 +618,7 @@ SECTIONS
     // Applet areas
     ////////////////////////////////
        __CUR_COUNTER__ = .;
-    _APPLET0_SECTION_BASE = 0xffff8000;
+    _APPLET0_SECTION_BASE = 0xfffb8000;
     . = _APPLET0_SECTION_BASE;
     // Section aligned to 128 to make occ main application image 128 bytes
     // aligned which is requirement for applet manager when traversing through
@@ -608,7 +627,7 @@ SECTIONS
 
     . = __CUR_COUNTER__;
     _APPLET0_SECTION_SIZE = 0x00004000;
-    _APPLET1_SECTION_BASE = 0xffffc000;
+    _APPLET1_SECTION_BASE = 0xfffbc000;
     _APPLET1_SECTION_SIZE = 0x00003c00;
 
     //////////////////////////////
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index f81fe52..bf0d653 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -159,8 +159,7 @@ void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority)
      * @devdesc    Failure detected in processor
      *             power management controller (PMC)
      */
-    // TEMP -- NO ERRL YET
-/*
+/* TEMP NO MORE PMC
     l_err = createErrl( PMC_HW_ERROR_ISR,          // i_modId,
                         PMC_FAILURE,               // i_reasonCode,
                         OCC_NO_EXTENDED_RC,
@@ -169,17 +168,13 @@ void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority)
                         DEFAULT_TRACE_SIZE,        // i_traceSz,
                         0,                         // i_userData1,
                         0);                        // i_userData2
-*/
     //Add our register dump to the error log
-    /*addUsrDtlsToErrl(l_err,
+    addUsrDtlsToErrl(l_err,
             (uint8_t*) &l_pmc_ffdc,
             sizeof(l_pmc_ffdc),
             ERRL_USR_DTL_STRUCT_VERSION_1,
             ERRL_USR_DTL_BINARY_DATA);
-    */
 
-// TEMP -- NO ERRL YET
-/*
     //Add firmware callout
     addCalloutToErrl(l_err,
             ERRL_CALLOUT_TYPE_COMPONENT_ID,
@@ -307,7 +302,6 @@ void occ_irq_setup()
 END TEMP */
     }while(0);
 
-/* TEMP -- NO ERRL YET
     if(l_rc)
     {
         //single error for all error cases, just look at trace to see where it failed.
@@ -318,7 +312,7 @@ END TEMP */
          * @userdata1  SSX return code
          * @userdata4  OCC_NO_EXTENDED_RC
          * @devdesc    Firmware failure initializing IRQ
-         */ /*
+         */
         l_err = createErrl( OCC_IRQ_SETUP,             // i_modId,
                             SSX_GENERIC_FAILURE,       // i_reasonCode,
                             OCC_NO_EXTENDED_RC,
@@ -336,7 +330,6 @@ END TEMP */
 
         commitErrl(&l_err);
     }
-*/
 }
 
 /*
@@ -418,7 +411,6 @@ void occ_ipc_setup()
 
     }while(0);
 
-/* TEMP -- NO ERRL YET
     if(l_rc)
     {
         // Log single error for all error cases, just look at trace to see where it failed.
@@ -429,7 +421,7 @@ void occ_ipc_setup()
          * @userdata1  IPC return code
          * @userdata4  OCC_NO_EXTENDED_RC
          * @devdesc    Firmware failure initializing IPC
-         */ /*
+         */
         l_err = createErrl( OCC_IRQ_SETUP,             // i_modId,
                             SSX_GENERIC_FAILURE,       // i_reasonCode,
                             OCC_NO_EXTENDED_RC,
@@ -447,7 +439,6 @@ void occ_ipc_setup()
 
         commitErrl(&l_err);
     }
-*/
 }
 
 
@@ -603,13 +594,11 @@ void master_occ_init()
             &l_status);           // Error status
 */
 
-
     if( (NULL != l_errl)  || (l_status !=  OCC_APLT_SUCCESS))
     {
         TRAC_ERR("APSS init applet returned error: l_status: 0x%x", l_status);
         // commit & delete. CommitErrl handles NULL error log handle
-        // TEMP -- NO ERRL / RESET YET
-        //REQUEST_RESET(l_errl);
+        REQUEST_RESET(l_errl);
     }
 
     // Reinitialize the PBAX Queues
@@ -726,8 +715,7 @@ void mainThrdTimerCallback(void * i_argPtr)
          * @userdata4   OCC_NO_EXTENDED_RC
          * @devdesc     SSX semaphore related failure
          */
-        // TEMP -- NO ERRL YET
-/*
+
         errlHndl_t l_err = createErrl(MAIN_THRD_TIMER_MID,          //modId
                                       SSX_GENERIC_FAILURE,          //reasoncode
                                       OCC_NO_EXTENDED_RC,           //Extended reason code
@@ -736,10 +724,10 @@ void mainThrdTimerCallback(void * i_argPtr)
                                       DEFAULT_TRACE_SIZE,           //Trace Size
                                       l_rc,                         //userdata1
                                       0);                           //userdata2
-*/
+
         // Commit Error
         // TEMP - NO RESET YET
-//        REQUEST_RESET(l_err);
+        REQUEST_RESET(l_err);
     }
 }
 
@@ -804,8 +792,7 @@ void initMainThrdSemAndTimer()
          * @userdata4   OCC_NO_EXTENDED_RC
          * @devdesc     SSX semaphore related failure
          */
-        // TEMP -- NO ERRL OR RESET YET
-/*
+
         errlHndl_t l_err = createErrl(MAIN_THRD_SEM_INIT_MID,       //modId
                                       SSX_GENERIC_FAILURE,          //reasoncode
                                       OCC_NO_EXTENDED_RC,           //Extended reason code
@@ -816,7 +803,6 @@ void initMainThrdSemAndTimer()
                                       l_timerRc);                   //userdata2
 
         REQUEST_RESET(l_err);
-*/
     }
 }
 
@@ -913,6 +899,14 @@ void Main_thread_routine(void *private)
     // enable switch to actually start the watchdog function.
 //    ENABLE_WDOG;
 
+// TEMP: Normally these flags are set elsewhere, after the BMC/FSP
+//       send us configuration data. This is a temporary hack until
+//       that communication is enabled. Required for APSS tasks.
+    rtl_set_run_mask(RTL_FLAG_OBS);
+    rtl_clr_run_mask(RTL_FLAG_STANDBY);
+    rtl_clr_run_mask(RTL_FLAG_APSS_NOT_INITD);
+    rtl_clr_run_mask(RTL_FLAG_RST_REQ);
+// END TEMP
     while (TRUE)
     {
         // Count each loop so the watchdog can tell the main thread is
@@ -1007,7 +1001,6 @@ void Main_thread_routine(void *private)
             }
         }
 
-/* TEMP -- NO ERRL OR RESET YET
         if( l_ssxrc != SSX_OK)
         {
             /* @
@@ -1017,7 +1010,7 @@ void Main_thread_routine(void *private)
              * @userdata1   semaphore pending return code
              * @userdata4   OCC_NO_EXTENDED_RC
              * @devdesc     SSX semaphore related failure
-             */ /*
+             */
 
             errlHndl_t l_err = createErrl(MAIN_THRD_ROUTINE_MID,        //modId
                                           SSX_GENERIC_FAILURE,          //reasoncode
@@ -1030,7 +1023,6 @@ void Main_thread_routine(void *private)
 
             REQUEST_RESET(l_err);
         }
-*/
     } // while loop
 }
 
@@ -1052,6 +1044,8 @@ int main(int argc, char **argv)
     // Initialize TLB for Linear Window access here so we
     // can write checkpoints into the fsp response buffer.
     // ----------------------------------------------------
+
+#if PPC405_MMU_SUPPORT
     l_ssxrc = ppc405_mmu_map(
             CMDH_OCC_RESPONSE_BASE_ADDRESS,
             CMDH_OCC_RESPONSE_BASE_ADDRESS,
@@ -1081,6 +1075,7 @@ int main(int argc, char **argv)
         //failure means we can't talk to FSP.
         SSX_PANIC(0x01000002);
     }
+#endif /* PPC405_MMU_SUPPORT */
 
 /* TEMP -- NO FIR SUPPORT IN PHASE1
     // Setup the TLB for writing to the FIR parms section
@@ -1283,7 +1278,10 @@ int main(int argc, char **argv)
     // enable and register additional interrupt handlers
     CHECKPOINT(INITIALIZING_IRQS);
 
-    occ_irq_setup();
+//  TODO: Uncomment when this is resolved. Causes SSX panic currently.
+//        Not needed until we want to be able to catch hardware OCC or
+//        PMC (or equivalent) errors.
+//  occ_irq_setup();
 
     CHECKPOINT(IRQS_INITIALIZED);
 
@@ -1308,7 +1306,6 @@ int main(int argc, char **argv)
     if( SSX_OK != l_rc)
     {
         TRAC_ERR("Failure creating/resuming main thread: rc: 0x%x", -l_rc);
-/* TEMP -- NO ERRL OR RESET YET
         /* @
          * @errortype
          * @moduleid    MAIN_MID
@@ -1316,7 +1313,7 @@ int main(int argc, char **argv)
          * @userdata1   return code
          * @userdata4   OCC_NO_EXTENDED_RC
          * @devdesc     Firmware internal error creating thread
-         */ /*
+         */
         errlHndl_t l_err = createErrl(MAIN_MID,                 //modId
                                       SSX_GENERIC_FAILURE,      //reasoncode
                                       OCC_NO_EXTENDED_RC,       //Extended reason code
@@ -1327,7 +1324,6 @@ int main(int argc, char **argv)
                                       0);                       //userdata2
         // Commit Error log
         REQUEST_RESET(l_err);
-*/
     }
 
     // Enter SSX Kernel
diff --git a/src/occ_405/occLinkInputFile b/src/occ_405/occLinkInputFile
index c302319..6532215 100644
--- a/src/occ_405/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
@@ -4,7 +4,9 @@ INPUT (
         cmdh_fsp.o
         cmdh_fsp_cmds_datacnfg.o
         errl.o
+        ffdc.o
         homer.o
+        ll_ffdc.o
         main.o
         occ_sys_config.o
         occbuildname.o
@@ -45,5 +47,4 @@ INPUT (
         ppc405_cache_init.o
         ppc405_mmu_asm.o
         ppc405_breakpoint.o
-        ppc405_thread_init.o
-        ppc405_mmu.o )
+        ppc405_thread_init.o )
diff --git a/src/occ_405/pss/apss.c b/src/occ_405/pss/apss.c
index 00d67ad..77a111f 100755
--- a/src/occ_405/pss/apss.c
+++ b/src/occ_405/pss/apss.c
@@ -310,7 +310,7 @@ void task_apss_start_pwr_meas(struct task *i_self)
     int             l_rc                = 0;
     static bool     L_scheduled         = FALSE;
     static bool     L_idle_traced       = FALSE;
-//    static bool     L_ffdc_collected    = FALSE;
+    static bool     L_ffdc_collected    = FALSE;
 
     // Create/schedule GPE_start_pwr_meas_read (non-blocking)
     APSS_DBG("GPE_start_pwr_meas_read started\n");
@@ -341,7 +341,6 @@ void task_apss_start_pwr_meas(struct task *i_self)
             if ((ASYNC_REQUEST_STATE_COMPLETE != G_meas_start_request.request.completion_state) ||
                 (0 != G_gpe_start_pwr_meas_read_args.error.error))
             {
-/*  TEMP No error handling
                 //error should only be non-zero in the case where the GPE timed out waiting for
                 //the APSS master to complete the last operation.  Just keep retrying until
                 //DCOM resets us due to not having valid power data.
@@ -365,7 +364,7 @@ void task_apss_start_pwr_meas(struct task *i_self)
                      * @userdata1   GPE returned rc code
                      * @userdata4   ERC_APSS_COMPLETE_FAILURE
                      * @devdesc     Failure getting power measurement data from APSS
-                     */ /*
+                     */
                     l_err = createErrl(PSS_MID_APSS_START_MEAS,   // i_modId
                                        APSS_GPE_FAILURE,          // i_reasonCode
                                        ERC_APSS_COMPLETE_FAILURE,
@@ -386,7 +385,6 @@ void task_apss_start_pwr_meas(struct task *i_self)
                       // Set to true so that we don't log this error again.
                     L_ffdc_collected = TRUE;
                 }
-*/
             }
 
         }
@@ -504,7 +502,6 @@ void task_apss_continue_pwr_meas(struct task *i_self)
                 // Collect FFDC and log error once.
                 if (!L_ffdc_collected)
                 {
-/* TEMP no error logging
                     errlHndl_t l_err = NULL;
 
                     /*
@@ -515,7 +512,7 @@ void task_apss_continue_pwr_meas(struct task *i_self)
                      * @userdata2   0
                      * @userdata4   ERC_APSS_COMPLETE_FAILURE
                      * @devdesc     Failure getting power measurement data from APSS
-                     */ /*
+                     */
                     l_err = createErrl(PSS_MID_APSS_CONT_MEAS,   // i_modId
                                        APSS_GPE_FAILURE,          // i_reasonCode
                                        ERC_APSS_COMPLETE_FAILURE,
@@ -533,7 +530,6 @@ void task_apss_continue_pwr_meas(struct task *i_self)
 
                     // Commit Error
                     commitErrl(&l_err);
-*/
                       // Set to true so that we don't log this error again.
                     L_ffdc_collected = TRUE;
                 }
@@ -548,7 +544,6 @@ void task_apss_continue_pwr_meas(struct task *i_self)
         l_rc = gpe_request_schedule(&G_meas_cont_request);
         if (0 != l_rc)
         {
-/*  TEMP no error logging
             errlHndl_t l_err = NULL;
 
             TRAC_ERR("task_apss_cont_pwr_meas: schedule failed w/rc=0x%08X (%d us)", l_rc,
@@ -562,7 +557,7 @@ void task_apss_continue_pwr_meas(struct task *i_self)
              * @userdata2   0
              * @userdata4   ERC_APSS_SCHEDULE_FAILURE
              * @devdesc     task_apss_continue_pwr_meas schedule failed
-             */ /*
+             */
             l_err = createErrl(PSS_MID_APSS_CONT_MEAS,
                                SSX_GENERIC_FAILURE,
                                ERC_APSS_SCHEDULE_FAILURE,
@@ -574,7 +569,6 @@ void task_apss_continue_pwr_meas(struct task *i_self)
 
             // Request reset since this should never happen.
             REQUEST_RESET(l_err);
-*/
             L_scheduled = FALSE;
             break;
         }
@@ -680,7 +674,7 @@ void task_apss_complete_pwr_meas(struct task *i_self)
     int         l_rc                = 0;
     static bool L_scheduled         = FALSE;
     static bool L_idle_traced       = FALSE;
-//    static bool L_ffdc_collected    = FALSE;
+    static bool L_ffdc_collected    = FALSE;
 
     // Create/schedule GPE_apss_complete_pwr_meas_read (non-blocking)
     APSS_DBG("Calling task_apss_complete_pwr_meas.\n");
@@ -709,7 +703,6 @@ void task_apss_complete_pwr_meas(struct task *i_self)
             if ((ASYNC_REQUEST_STATE_COMPLETE != G_meas_complete_request.request.completion_state) ||
                 (0 != G_gpe_complete_pwr_meas_read_args.error.error))
             {
-/* TEMP no error logging
                 // Error should only be non-zero in the case where the GPE timed out waiting for
                 // the APSS master to complete the last operation. Just keep retrying until
                 // DCOM resets us due to not having valid power data.
@@ -733,7 +726,7 @@ void task_apss_complete_pwr_meas(struct task *i_self)
                      * @userdata2   0
                      * @userdata4   ERC_APSS_COMPLETE_FAILURE
                      * @devdesc     Failure getting power measurement data from APSS
-                     */ /*
+                     */
                     l_err = createErrl(PSS_MID_APSS_COMPLETE_MEAS,   // i_modId
                                        APSS_GPE_FAILURE,          // i_reasonCode
                                        ERC_APSS_COMPLETE_FAILURE,
@@ -754,8 +747,6 @@ void task_apss_complete_pwr_meas(struct task *i_self)
                     // Set to true so that we don't log this error again.
                     L_ffdc_collected = TRUE;
                 }
-*/
-
             }
         }
 
@@ -782,9 +773,6 @@ void task_apss_complete_pwr_meas(struct task *i_self)
              * @userdata4   ERC_APSS_SCHEDULE_FAILURE
              * @devdesc     task_apss_complete_pwr_meas schedule failed
              */
-
-/* TEMP no error logging
-
             l_err = createErrl(PSS_MID_APSS_COMPLETE_MEAS,
                                SSX_GENERIC_FAILURE,
                                ERC_APSS_SCHEDULE_FAILURE,
@@ -796,7 +784,6 @@ void task_apss_complete_pwr_meas(struct task *i_self)
 
             // Request reset since this should never happen.
             REQUEST_RESET(l_err);
-*/
             L_scheduled = FALSE;
             break;
         }
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index 8b5a8d8..d9a9b3b 100755
--- a/src/occ_405/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -36,6 +36,42 @@
 
 #include "global_app_cfg.h"
 
+// These versions of SSX_PANIC are being changed so that they exactly
+// mirror each other and are exactly structured at 8 instructions only and
+// make only one branch to outside code.
+#ifndef __ASSEMBLER__
+#ifndef SSX_PANIC
+#define SSX_PANIC(code)                                             \
+do {                                                                \
+    barrier();                                                      \
+    asm volatile ("stw  %r3, __occ_panic_save_r3@sda21(0)");        \
+    asm volatile ("mflr %r3");                                      \
+    asm volatile ("stw  %r4, __occ_panic_save_r4@sda21(0)");        \
+    asm volatile ("lis  %%r4, %0"::"i" (code >> 16));               \
+    asm volatile ("ori  %%r4, %%r4, %0"::"i" (code & 0xffff));      \
+    asm volatile ("bl   __ssx_checkpoint_panic_and_save_ffdc");     \
+    asm volatile ("trap");                                          \
+    asm volatile (".long %0" : : "i" (code));                       \
+} while (0)
+#endif // SSX_PANIC
+#else  /* __ASSEMBLER__ */
+#ifndef SSX_PANIC
+// This macro cannot be more than 8 instructions long, but it can be less than
+// 8.
+#define SSX_PANIC(code) _ssx_panic code
+    .macro  _ssx_panic, code
+    stw     %r3, __occ_panic_save_r3@sda21(0)
+    mflr    %r3
+    stw     %r4, __occ_panic_save_r4@sda21(0)
+    lis     %r4, \code@h
+    ori     %r4, %r4, \code@l
+    bl      __ssx_checkpoint_panic_and_save_ffdc
+    trap
+    .long   \code
+    .endm
+#endif // SSX_PANIC
+#endif /* __ASSEMBLER__ */
+
 /// Static configuration data for external interrupts:
 ///
 /// IRQ#, TYPE, POLARITY, ENABLE
diff --git a/src/occ_405/thread/threadSch.c b/src/occ_405/thread/threadSch.c
index 48fb419..9261027 100755
--- a/src/occ_405/thread/threadSch.c
+++ b/src/occ_405/thread/threadSch.c
@@ -44,14 +44,16 @@ SsxTimer G_threadSchTimer;
 // Index of highest priority thread in G_scheduledThreads
 uint16_t G_threadSchedulerIndex = 0;
 
+// TEMP: Commented out cmd handler and dcom threads for Simics enablement.
+//       Will need to reenable them when we need them again.
 // Array that holds the threads that need scheduling
 SsxThread* G_scheduledThreads[] =
 {
     &Main_thread,
-    &Cmd_Hndl_thread,
+//    &Cmd_Hndl_thread,
     &App_thread,
     &TestAppletThread,
-    &Dcom_thread,
+//    &Dcom_thread,
 };
 
 // Error log counter for the callback so that only 1 error log is created
diff --git a/src/occ_405/topfiles.mk b/src/occ_405/topfiles.mk
index 5fa952c..e047152 100644
--- a/src/occ_405/topfiles.mk
+++ b/src/occ_405/topfiles.mk
@@ -25,6 +25,10 @@
 TOP-C-SOURCES = aplt/appletManager.c \
                 cmdh/cmdh_fsp.c \
                 cmdh/cmdh_fsp_cmds_datacnfg.c \
+                cmdh/cmdh_mnfg_intf.c \
+                cmdh/cmdh_tunable_parms.c \
+                cmdh/snapshot.c \
+                cmdh/ffdc.c \
                 errl/errl.c \
                 homer.c \
                 main.c \
@@ -40,7 +44,7 @@ TOP-C-SOURCES = aplt/appletManager.c \
                 timer/timer.c \
                 trac/trac_interface.c \
 
-TOP-S-SOURCES = 
+TOP-S-SOURCES = cmdh/ll_ffdc.S \
 
 
 TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o)