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| author | William Bryan <wilbryan@us.ibm.com> | 2015-12-03 12:52:53 -0600 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2015-12-04 14:22:09 -0600 |
| commit | 3e24c506a99c48c0a2386c9206712f12d3ba2105 (patch) | |
| tree | 1c2acdab1ce0f3b1646283d9472250526140ce06 /src/occ_405/state.c | |
| parent | 0694c6bb509e5d91a7f2c7b1f4924e114500dca1 (diff) | |
| download | talos-occ-3e24c506a99c48c0a2386c9206712f12d3ba2105.tar.gz talos-occ-3e24c506a99c48c0a2386c9206712f12d3ba2105.zip | |
Enable set role command and retry APSS init
Added changes to enable Simics console tracing
Enabled memory configuration packet
Removed Pstate data config command
RTC: 141646
RTC: 142030
Change-Id: I85807a76bb9364b1f3b865fa91c28a3f46446531
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22434
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/state.c')
| -rwxr-xr-x | src/occ_405/state.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/occ_405/state.c b/src/occ_405/state.c index b691fe1..8cb1124 100755 --- a/src/occ_405/state.c +++ b/src/occ_405/state.c @@ -132,7 +132,7 @@ errlHndl_t SMGR_standby_to_observation() if( SMGR_MASK_OBSERVATION_READY == (SMGR_validate_get_valid_states() & SMGR_MASK_OBSERVATION_READY)) { - l_error_logged = FALSE; // @at015a + l_error_logged = FALSE; TRAC_IMP("SMGR: Standby to Observation Transition Started"); // TEMP -- NOT SUPPORTED YET IN PHASE1 @@ -176,7 +176,7 @@ errlHndl_t SMGR_standby_to_observation() TRAC_IMP("SMGR: Standby to Observation Transition Completed"); } - else if(FALSE == l_error_logged)// @at015a + else if(FALSE == l_error_logged) { l_error_logged = TRUE; TRAC_ERR("SMGR: Standby to Observation Transition Failed"); @@ -197,7 +197,7 @@ errlHndl_t SMGR_standby_to_observation() 0, //userdata1 0); //userdata2 - // @wb001 -- Callout firmware + // Callout firmware addCalloutToErrl(l_errlHndl, ERRL_CALLOUT_TYPE_COMPONENT_ID, ERRL_COMPONENT_ID_FIRMWARE, @@ -277,7 +277,7 @@ errlHndl_t SMGR_observation_to_active() { if(FALSE == l_error_logged) { - TRAC_ERR("SMGR: Timeout waiting for Pstates to be enabled, master state=%d, slave state=%d, pmc_mode[%08x], chips_present[%02x], pmc_deconfig[%08x]", //gm034 + TRAC_ERR("SMGR: Timeout waiting for Pstates to be enabled, master state=%d, slave state=%d, pmc_mode[%08x], chips_present[%02x], pmc_deconfig[%08x]", G_proc_dcm_sync_state.sync_state_master, G_proc_dcm_sync_state.sync_state_slave, in32(PMC_MODE_REG), @@ -323,7 +323,7 @@ errlHndl_t SMGR_observation_to_active() l_pmgp1.value = 0; l_pmgp1.fields.dpll_freq_override_enable = 1; l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_AND, l_core), - ~l_pmgp1.value, NULL); //commit errors internally -- gm033 + ~l_pmgp1.value, NULL); //commit errors internally if(l_rc) { TRAC_ERR("Failed disabling dpll frequency override. rc=0x%08x, core=%d", l_rc, l_core); @@ -561,9 +561,7 @@ errlHndl_t SMGR_all_to_safe() // If we are master, make sure we are broadcasting that the requested // state is "safe state" -// TEMP -- IN PHASE1 WE ARE ALWAYS MASTER -// if (OCC_MASTER == G_occ_role) - if (TRUE) + if (OCC_MASTER == G_occ_role) { G_occ_external_req_state = OCC_STATE_SAFE; } |
