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authorWilliam Bryan <wilbryan@us.ibm.com>2015-08-03 12:38:58 -0500
committerWilliam A. Bryan <wilbryan@us.ibm.com>2015-08-03 15:32:27 -0500
commit420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3 (patch)
treec9f6691eddba39193e39aa769367e1267fb9fc86 /src/occ_405/ssx_app_cfg.h
parentadade8c8ef30ed519322674c762d95663009c5d4 (diff)
downloadtalos-occ-420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3.tar.gz
talos-occ-420e6d248cc6d2b3c39bc3970e3bb6747b3bddc3.zip
new ssx and lib files
Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/ssx_app_cfg.h')
-rwxr-xr-xsrc/occ_405/ssx_app_cfg.h77
1 files changed, 77 insertions, 0 deletions
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
new file mode 100755
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--- /dev/null
+++ b/src/occ_405/ssx_app_cfg.h
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/occ_405/ssx_app_cfg.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2011,2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+
+#ifndef __SSX_APP_CFG_H__
+#define __SSX_APP_CFG_H__
+
+// These versions of SSX_PANIC are being changed so that they exactly
+// mirror each other and are exactly structured at 8 instructions only and
+// make only one branch to outside code.
+#ifndef __ASSEMBLER__
+#ifndef SSX_PANIC
+#define SSX_PANIC(code) \
+do { \
+ barrier(); \
+ asm volatile ("stw %r3, __occ_panic_save_r3@sda21(0)"); \
+ asm volatile ("mflr %r3"); \
+ asm volatile ("stw %r4, __occ_panic_save_r4@sda21(0)"); \
+ asm volatile ("lis %%r4, %0"::"i" (code >> 16)); \
+ asm volatile ("ori %%r4, %%r4, %0"::"i" (code & 0xffff)); \
+ asm volatile ("bl __ssx_checkpoint_panic_and_save_ffdc"); \
+ asm volatile ("trap"); \
+ asm volatile (".long %0" : : "i" (code)); \
+} while (0)
+#endif // SSX_PANIC
+#else /* __ASSEMBLER__ */
+#ifndef SSX_PANIC
+// This macro cannot be more than 8 instructions long, but it can be less than
+// 8.
+#define SSX_PANIC(code) _ssx_panic code
+ .macro _ssx_panic, code
+ stw %r3, __occ_panic_save_r3@sda21(0)
+ mflr %r3
+ stw %r4, __occ_panic_save_r4@sda21(0)
+ lis %r4, \code@h
+ ori %r4, %r4, \code@l
+ bl __ssx_checkpoint_panic_and_save_ffdc
+ trap
+ .long \code
+ .endm
+#endif // SSX_PANIC
+#endif /* __ASSEMBLER__ */
+
+#define INIT_SEC_NM_STR "initSection"
+#define INIT_SECTION __attribute__ ((section (INIT_SEC_NM_STR)))
+
+#define SIMICS_ENVIRONMENT 0
+
+/// Since OCC Firmware desires time intervals longer than 7 seconds, we will
+/// change the interval to be a uint64_t instead of a uint32_t so we don't
+/// hit the overflow condition
+#define SSX_TIME_INTERVAL_TYPE uint64_t
+
+#endif /* __SSX_APP_CFG_H__ */
+
+
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