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| author | William Bryan <wilbryan@us.ibm.com> | 2015-08-21 15:17:53 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2015-08-26 16:45:54 -0500 |
| commit | 0f26c7e693a059bc77529c03e2bec44486131e4a (patch) | |
| tree | 9d2502293f3557eaea41bede138597a5f86f8736 /src/occ_405/ssx_app_cfg.h | |
| parent | d4b74d20664271d6736008d87591a5fcbf815ded (diff) | |
| download | talos-occ-0f26c7e693a059bc77529c03e2bec44486131e4a.tar.gz talos-occ-0f26c7e693a059bc77529c03e2bec44486131e4a.zip | |
Enabled FFDC and Simics
Also included:
-- Some more cmdh files into the build
-- Workaround for OCB Timer divider register in Simics
-- Workaround to start APSS tasks until DCOM is back
RTC: 133819
Change-Id: Ie19c2a544f64c40126c2bc4a0af6fabfe6430d21
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19998
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/ssx_app_cfg.h')
| -rwxr-xr-x | src/occ_405/ssx_app_cfg.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h index 8b5a8d8..d9a9b3b 100755 --- a/src/occ_405/ssx_app_cfg.h +++ b/src/occ_405/ssx_app_cfg.h @@ -36,6 +36,42 @@ #include "global_app_cfg.h" +// These versions of SSX_PANIC are being changed so that they exactly +// mirror each other and are exactly structured at 8 instructions only and +// make only one branch to outside code. +#ifndef __ASSEMBLER__ +#ifndef SSX_PANIC +#define SSX_PANIC(code) \ +do { \ + barrier(); \ + asm volatile ("stw %r3, __occ_panic_save_r3@sda21(0)"); \ + asm volatile ("mflr %r3"); \ + asm volatile ("stw %r4, __occ_panic_save_r4@sda21(0)"); \ + asm volatile ("lis %%r4, %0"::"i" (code >> 16)); \ + asm volatile ("ori %%r4, %%r4, %0"::"i" (code & 0xffff)); \ + asm volatile ("bl __ssx_checkpoint_panic_and_save_ffdc"); \ + asm volatile ("trap"); \ + asm volatile (".long %0" : : "i" (code)); \ +} while (0) +#endif // SSX_PANIC +#else /* __ASSEMBLER__ */ +#ifndef SSX_PANIC +// This macro cannot be more than 8 instructions long, but it can be less than +// 8. +#define SSX_PANIC(code) _ssx_panic code + .macro _ssx_panic, code + stw %r3, __occ_panic_save_r3@sda21(0) + mflr %r3 + stw %r4, __occ_panic_save_r4@sda21(0) + lis %r4, \code@h + ori %r4, %r4, \code@l + bl __ssx_checkpoint_panic_and_save_ffdc + trap + .long \code + .endm +#endif // SSX_PANIC +#endif /* __ASSEMBLER__ */ + /// Static configuration data for external interrupts: /// /// IRQ#, TYPE, POLARITY, ENABLE |
