diff options
author | Wael El-Essawy <welessa@us.ibm.com> | 2016-10-27 12:54:20 -0500 |
---|---|---|
committer | Wael El-Essawy <welessa@us.ibm.com> | 2016-11-03 15:08:04 -0400 |
commit | 45ceb3d13361ac099c7b0b9f2ff51a731e296ed1 (patch) | |
tree | 0b9edc946040fe0f3bd2b2f82a09b1f3d94ebc56 /src/occ_405/rtls | |
parent | aa7187f24959d2ec1fbee81a5d100a749161096f (diff) | |
download | talos-occ-45ceb3d13361ac099c7b0b9f2ff51a731e296ed1.tar.gz talos-occ-45ceb3d13361ac099c7b0b9f2ff51a731e296ed1.zip |
Implement task_poke_watchdogs
task_poke_watchdogs() should be called every 2ms (ticks 1 and 9) on both
master and slaves while in observation and active state and do the following:
1. Every time called: Enable/Reset the OCC heartbeat: done by a write to
OCB OCC Heartbeat Register (set count to 8ms)
2. Every time called: Reset memory deadman timer for 1 MCA (skip if not
present and just wait until next call to check next MCA to keep same
timing of reset per MCA regardless of # present) Resetting the deadman
is done by reading one of the memory performance counters, use one at
SCOM offset 0x13C. NOTE: Will take 16ms (8 MCAs x 2ms) to reset all
memory timers, this is fine since the shortest time the deadman timeout
can be configured to is 28ms
3. Every 4ms (on tick 1 only) : Verify PGPE is still functional by reading
PGPE Beacon from SRAM if after 8ms (2 consecutive checks) there is no
change to the PGPE Beacon count then log an error and request reset.
In addition, this commit adds entries for the PGPE image header and shared
SRAM in the TLB, and partially reads PGPE image header parameters.
Change-Id: I9906102b3349506612d55c57e9f5c28441eaeb39
RTC: 154960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31916
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/rtls')
-rwxr-xr-x | src/occ_405/rtls/rtls.h | 1 | ||||
-rwxr-xr-x | src/occ_405/rtls/rtls_tables.c | 16 |
2 files changed, 2 insertions, 15 deletions
diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h index 0aead87..7a45afe 100755 --- a/src/occ_405/rtls/rtls.h +++ b/src/occ_405/rtls/rtls.h @@ -58,7 +58,6 @@ typedef enum { // TASK_ID_CORE_DATA_CONTROL, // TASK_ID_GPU_SM, // GPU State Machine TASK_ID_DIMM_SM, // DIMM State Machine -// TASK_ID_MEM_DEADMAN, // Memory deadman timer TASK_ID_MEMORY_CONTROL, // Memory (centaur/dimm) control task TASK_ID_NEST_DTS, TASK_END // This must always be the last enum in this list, diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c index ef42d90..a577069 100755 --- a/src/occ_405/rtls/rtls_tables.c +++ b/src/occ_405/rtls/rtls_tables.c @@ -118,8 +118,6 @@ task_t G_task_table[TASK_END] = { // TEMP -- NOT YET IMPLEMENTED // { FLAGS_GPU_SM, task_gpu_sm, NULL }, // TASK_ID_GPU_SM { FLAGS_MEMORY_DATA, task_dimm_sm, NULL }, // TASK_ID_DIMM_SM -// TEMP -- NOT YET IMPLEMENTED -// { FLAGS_MEM_DEADMAN, task_mem_deadman, NULL }, // TASK_ID_MEM_DEADMAN { FLAGS_MEMORY_CONTROL, task_memory_control, (void *) &G_memory_control_task }, // TASK_ID_MEMORY_CONTROL { FLAGS_NEST_DTS, task_nest_dts, NULL }, }; @@ -136,7 +134,6 @@ const uint8_t G_tick0_seq[] = { TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, - TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -152,11 +149,11 @@ const uint8_t G_tick1_seq[] = { TASK_ID_APSS_CONT, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, + TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -193,7 +190,6 @@ const uint8_t G_tick3_seq[] = { TASK_ID_CORE_DATA_HIGH, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -218,7 +214,6 @@ const uint8_t G_tick4_seq[] = { TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, - TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -234,7 +229,6 @@ const uint8_t G_tick5_seq[] = { TASK_ID_APSS_CONT, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -274,7 +268,6 @@ const uint8_t G_tick7_seq[] = { TASK_ID_CORE_DATA_HIGH, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -299,7 +292,6 @@ const uint8_t G_tick8_seq[] = { TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, - TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -315,11 +307,11 @@ const uint8_t G_tick9_seq[] = { TASK_ID_APSS_CONT, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, + TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -355,7 +347,6 @@ const uint8_t G_tick11_seq[] = { TASK_ID_CORE_DATA_HIGH, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -380,7 +371,6 @@ const uint8_t G_tick12_seq[] = { TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, TASK_ID_DCOM_RX_OUTBX, - TASK_ID_POKE_WDT, TASK_ID_DCOM_TX_OUTBX, TASK_ID_DCOM_TX_INBX, TASK_ID_AMEC_SLAVE, @@ -396,7 +386,6 @@ const uint8_t G_tick13_seq[] = { TASK_ID_APSS_CONT, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -436,7 +425,6 @@ const uint8_t G_tick15_seq[] = { TASK_ID_CORE_DATA_HIGH, TASK_ID_APSS_DONE, TASK_ID_MEMORY_CONTROL, - //TASK_ID_MEM_DEADMAN, //TASK_ID_CORE_DATA_CONTROL, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, |