Implement new tick table

RTC: 140184
Change-Id: Iadf0ead19c1eeb67d71449471a29f96f2b6ecd57
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21740
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher Cain <cjcain@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>

2 files changed, 191 insertions, 39 deletions

diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h
index 4e0d571..edd6de4 100755
--- a/src/occ_405/rtls/rtls.h
+++ b/src/occ_405/rtls/rtls.h
@@ -44,10 +44,9 @@ typedef enum {
     TASK_ID_APSS_CONT,
 //    TASK_ID_CORE_DATA_HIGH,
     TASK_ID_APSS_DONE,
-//    TASK_ID_FAST_CORE_DATA,
 //    TASK_ID_DCOM_RX_INBX,
 //    TASK_ID_DCOM_TX_INBX,
-    TASK_ID_POKE_WDT,    // Reset ppc405 watchdog and OCB timer
+    TASK_ID_POKE_WDT,                 // Reset ppc405 watchdog and OCB timer
 //    TASK_ID_DCOM_WAIT_4_MSTR,
 //    TASK_ID_DCOM_RX_OUTBX,
 //    TASK_ID_DCOM_TX_OUTBX,
@@ -55,9 +54,10 @@ typedef enum {
     TASK_ID_CHECK_FOR_CHECKSTOP,
 //    TASK_ID_AMEC_SLAVE,             // AMEC SMH tasks
 //    TASK_ID_AMEC_MASTER,            // AMEC SMH tasks
-//    TASK_ID_CENTAUR_DATA,           // Centaur task
 //    TASK_ID_CORE_DATA_CONTROL,
-//    TASK_ID_CENTAUR_CONTROL,        // Centaur task
+//    TASK_ID_GPU_SM,                 // GPU State Machine
+//    TASK_ID_DIMM_SM,                // DIMM State Machine
+//    TASK_ID_MEM_DEADMAN,            // Memory deadman timer
     TASK_END  // This must always be the last enum in this list,
               // so that TASK_END always equals the last task ID + 1.
 } task_id_t;
@@ -108,7 +108,7 @@ typedef struct
 
 // Tick Timer definitions
 #define MICS_PER_TICK 250  // Number of micro-seconds per tick
-#define MAX_NUM_TICKS 8    // Number of entries in the global tick table (power of 2)
+#define MAX_NUM_TICKS 16   // Number of entries in the global tick table (power of 2)
 
 // The value of the current tick
 extern uint32_t G_current_tick;
diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c
index 63c083f..c4dc9d3 100755
--- a/src/occ_405/rtls/rtls_tables.c
+++ b/src/occ_405/rtls/rtls_tables.c
@@ -64,10 +64,16 @@
 #define FLAGS_CHECK_FOR_CHECKSTOP        RTL_FLAG_MSTR | RTL_FLAG_NOTMSTR | RTL_FLAG_OBS | RTL_FLAG_ACTIVE | RTL_FLAG_MSTR_READY | RTL_FLAG_NO_APSS | RTL_FLAG_RUN | RTL_FLAG_STANDBY | RTL_FLAG_RST_REQ | RTL_FLAG_APSS_NOT_INITD
 
 #define FLAGS_CORE_DATA_CONTROL          RTL_FLAG_MSTR | RTL_FLAG_NOTMSTR |                RTL_FLAG_ACTIVE | RTL_FLAG_MSTR_READY | RTL_FLAG_NO_APSS | RTL_FLAG_RUN |                                       RTL_FLAG_APSS_NOT_INITD
+
 // Don't run watchdog poke in all cases, expecially if a reset request is pending
 #define FLAGS_POKE_WDT RTL_FLAG_RUN | RTL_FLAG_MSTR | RTL_FLAG_NOTMSTR | RTL_FLAG_STANDBY | \
                        RTL_FLAG_OBS | RTL_FLAG_ACTIVE | RTL_FLAG_MSTR_READY | RTL_FLAG_NO_APSS | RTL_FLAG_APSS_NOT_INITD
 
+// TEMP/TODO: These are not yet implemented
+#define FLAGS_GPU_SM
+#define FLAGS_DIMM_SM
+#define FLAGS_MEM_DEADMAN
+
 // Global tick sequences
 // The number and size of these will vary as the real tick sequences are developed over time.
 
@@ -96,8 +102,6 @@ task_t G_task_table[TASK_END] = {
 //    { FLAGS_HIGH_CORES_DATA,       task_core_data,                 (void *) &G_high_cores},
     { FLAGS_APSS_DONE_MEAS,        task_apss_complete_pwr_meas,    NULL },  // TASK_ID_APSS_DONE
 // TEMP -- NOT SUPPORTED YET IN PHASE1
-//    { FLAGS_FAST_CORES_DATA,       task_fast_core_data,            NULL },
-// TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_DCOM_RX_SLV_INBX,      task_dcom_rx_slv_inbox,         NULL },  // TASK_ID_DCOM_RX_INBX
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_DCOM_TX_SLV_INBX,      task_dcom_tx_slv_inbox,         NULL },  // TASK_ID_DCOM_TX_INBX
@@ -115,23 +119,23 @@ task_t G_task_table[TASK_END] = {
 //    { FLAGS_AMEC_SLAVE,            task_amec_slave,                NULL },  // TASK_ID_AMEC_SLAVE
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_AMEC_MASTER,           task_amec_master,               NULL },  // TASK_ID_AMEC_MASTER
-// TEMP -- PORE ISSUES
-//    { FLAGS_CENTAUR_DATA,          task_centaur_data,              (void *) &G_centaur_data_task}, // TASK_ID_CENTAUR_DATA
 // TEMP -- NOT SUPPORTED YET IN PHASE1
 //    { FLAGS_CORE_DATA_CONTROL,     task_core_data_control,         NULL },  // TASK_ID_CORE_DATA_CONTROL
-// TEMP -- PORE ISSUES
-//    { FLAGS_CENTAUR_CONTROL,       task_centaur_control,           (void *) &G_centaur_control_task },  // TASK_ID_CENTAUR_CONTROL
+// TEMP -- NOT YET IMPLEMENTED
+//    { FLAGS_GPU_SM,                task_gpu_sm,                    NULL },  // TASK_ID_GPU_SM
+// TEMP -- NOT YET IMPLEMENTED
+//    { FLAGS_DIMM_SM,               task_dimm_sm,                   NULL },  // TASK_ID_DIMM_SM
+// TEMP -- NOT YET IMPLEMENTED
+//    { FLAGS_MEM_DEADMAN,           task_mem_deadman,               NULL },  // TASK_ID_MEM_DEADMAN
 };
 
 const uint8_t G_tick0_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -148,12 +152,10 @@ const uint8_t G_tick0_seq[] = {
 const uint8_t G_tick1_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
+                                //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -169,12 +171,10 @@ const uint8_t G_tick1_seq[] = {
 const uint8_t G_tick2_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -189,13 +189,11 @@ const uint8_t G_tick2_seq[] = {
 
 const uint8_t G_tick3_seq[] = {
                                 TASK_ID_APSS_START,
-                                //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
+                                //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -211,12 +209,10 @@ const uint8_t G_tick3_seq[] = {
 const uint8_t G_tick4_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -233,12 +229,10 @@ const uint8_t G_tick4_seq[] = {
 const uint8_t G_tick5_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
-                                //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
+                                //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -254,12 +248,10 @@ const uint8_t G_tick5_seq[] = {
 const uint8_t G_tick6_seq[] = {
                                 TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_DIMM_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -274,13 +266,165 @@ const uint8_t G_tick6_seq[] = {
 
 const uint8_t G_tick7_seq[] = {
                                 TASK_ID_APSS_START,
+                                //TASK_ID_GPU_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_MEM_DEADMAN,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick8_seq[] = {
+                                TASK_ID_APSS_START,
                                 //TASK_ID_CORE_DATA_LOW,
-                                //TASK_ID_CENTAUR_DATA,
+                                //TASK_ID_DIMM_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_POKE_WDT,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick9_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_CORE_DATA_LOW,
+                                //TASK_ID_GPU_SM,
+                                TASK_ID_APSS_CONT,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_MEM_DEADMAN,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick10_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_CORE_DATA_LOW,
+                                //TASK_ID_DIMM_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick11_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_GPU_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_MEM_DEADMAN,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick12_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_CORE_DATA_LOW,
+                                //TASK_ID_DIMM_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                TASK_ID_POKE_WDT,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick13_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_CORE_DATA_LOW,
+                                //TASK_ID_GPU_SM,
+                                TASK_ID_APSS_CONT,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_MEM_DEADMAN,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick14_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_CORE_DATA_LOW,
+                                //TASK_ID_DIMM_SM,
+                                TASK_ID_APSS_CONT,
+                                //TASK_ID_CORE_DATA_HIGH,
+                                TASK_ID_APSS_DONE,
+                                //TASK_ID_CORE_DATA_CONTROL,
+                                //TASK_ID_DCOM_WAIT_4_MSTR,
+                                //TASK_ID_DCOM_RX_INBX,
+                                //TASK_ID_DCOM_RX_OUTBX,
+                                //TASK_ID_DCOM_TX_OUTBX,
+                                //TASK_ID_DCOM_TX_INBX,
+                                //TASK_ID_AMEC_SLAVE,
+                                //TASK_ID_AMEC_MASTER,
+                                //TASK_ID_DCOM_PARSE_FW_MSG,
+                                //TASK_ID_CHECK_FOR_CHECKSTOP,
+                                TASK_END };
+
+const uint8_t G_tick15_seq[] = {
+                                TASK_ID_APSS_START,
+                                //TASK_ID_GPU_SM,
                                 TASK_ID_APSS_CONT,
                                 //TASK_ID_CORE_DATA_HIGH,
                                 TASK_ID_APSS_DONE,
-                                //TASK_ID_FAST_CORE_DATA,
-                                //TASK_ID_CENTAUR_CONTROL,
+                                //TASK_ID_MEM_DEADMAN,
                                 //TASK_ID_CORE_DATA_CONTROL,
                                 //TASK_ID_DCOM_WAIT_4_MSTR,
                                 //TASK_ID_DCOM_RX_INBX,
@@ -303,6 +447,14 @@ const uint8_t *G_tick_table[MAX_NUM_TICKS] = {
     G_tick4_seq,
     G_tick5_seq,
     G_tick6_seq,
-    G_tick7_seq
+    G_tick7_seq,
+    G_tick8_seq,
+    G_tick9_seq,
+    G_tick10_seq,
+    G_tick11_seq,
+    G_tick12_seq,
+    G_tick13_seq,
+    G_tick14_seq,
+    G_tick15_seq,
 };