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authorWael El-Essawy <welessa@us.ibm.com>2016-12-09 18:28:26 -0600
committerWael El-Essawy <welessa@us.ibm.com>2017-01-27 12:00:02 -0500
commit360934dea9355e488206267d7f9fd9b1c753cf16 (patch)
treed5fb9e4ae46b9b9afe9adca7b1e0ac72e5d7219a /src/occ_405/proc/proc_data_control.h
parentc35e73bb81af40e6cca73b35ea8db61a8f17f5a8 (diff)
downloadtalos-occ-360934dea9355e488206267d7f9fd9b1c753cf16.tar.gz
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Pstates Support in OCC
1. Initialize Pstates global parameters (G_proc_fmax, G_proc_fmin, G_khz_per_pstate and G_proc_pmin from the OCC Pstate Parameter Block) 2. When frequency config data packet is received and OCC is NOT already in Active state: Send IPC command to PGPE to set pState clips to be wide open from min frequency to turbo First verify min/max frequency from TMGT is within what PGPE allows saved in G_proc_fmax and G_proc_fmin if not within bounds trace and clip to G_proc_fmax/fmin) 3. Transition to active state: Send IPC command to PGPE to start pState protocol (give correct data for OCC vs OPAL in control of Pstates) and if OPAL system update OPAL shared memory with Pstate information. 4. amec_slv_freq_smh(): Send IPC command to PGPE to set requested pState (PowerVM) or set clips (OPAL). 5. Address all the TODO/TEMP/#if 0 in amec_freq.c either remove or add RTC# for when it will be addressed Change-Id: Ic323321b8c66945732a6b7345ad85d6f41a62edd RTC: 130201 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33704 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/proc/proc_data_control.h')
-rwxr-xr-xsrc/occ_405/proc/proc_data_control.h27
1 files changed, 16 insertions, 11 deletions
diff --git a/src/occ_405/proc/proc_data_control.h b/src/occ_405/proc/proc_data_control.h
index ec65c2f..4188c08 100755
--- a/src/occ_405/proc/proc_data_control.h
+++ b/src/occ_405/proc/proc_data_control.h
@@ -30,21 +30,26 @@
#include <ssx.h>
#include "rtls.h"
#include "p9_pstates_common.h"
+#include "pstate_pgpe_occ_api.h"
-//#include "gpe_control.h"
+/// Per-quad Pstate/Clip control data-structure
+///
+/// Firmware maintains a copy of PstateClipStruct structures - with an entry
+/// for each quad on the chip - and updates the pstate/clip fields in place.
+/// The PGPE IPC procedures (MSGID_405_SET_PMCR and MSGID_405_CLIPS)
+/// are run periodically to update the core psates or clips control values
+/// from this data structure. The array can (should) be cleared initially.
+typedef struct {
-// Initialze the structures used by the GPE
-void proc_core_data_control_init( void );
+ /// The Pstate control values
+ ipcmsg_set_pmcr_t pstates;
-// Task that sets the PMCR, PMBR, PMICR
-void task_core_data_control( task_t * i_task );
+ /// The clipping values
+ ipcmsg_clip_update_t clips;
-// Function to demonstrate setting Pstates to all cores
-void proc_set_pstate_all(Pstate i_pstate);
+} PstatesClips;
-// Function to demonstrate setting Pstates one core
-void proc_set_core_pstate(Pstate i_pstate, uint8_t i_core);
+// Task that sets the PMCR, PMBR, PMICR
+void task_core_data_control( task_t * i_task );
-// Sets the Pmin/Pmax clip values for one core
-void proc_set_core_bounds(Pstate i_pmin, Pstate i_pmax, uint8_t i_core);
#endif
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