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author | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-04 10:51:30 -0500 |
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committer | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-13 12:42:50 -0400 |
commit | 81347d935a940206a2c594568f1a677241347d92 (patch) | |
tree | 97259dc1e372b007ea450c4481cd8e75be10aee8 /src/occ_405/proc/proc_data_control.c | |
parent | 676a6cba19fa56177f90a44f4c3f762984be7715 (diff) | |
download | talos-occ-81347d935a940206a2c594568f1a677241347d92.tar.gz talos-occ-81347d935a940206a2c594568f1a677241347d92.zip |
Fix Ping Pong and HOMER addresses, usign new P9 pba_region default value.
The new P9 pba_region field in the PBA_MODE register is now 0b10
contrary to the P8 pba_region setting of 0b00.
Addresses have been corrected for Ping Pong communications,
HOMER Host Data, Sapphire Table, and HTMGT send and receive Buffers.
Replaced Sapphire legacy term with OPAL.
Defined COMMON_BASE_ADDRESS, and offset addresses relative to it.
modified HOMER_HD_OFFSET, OCC_HTMGT_CMD_OFFSET_HOMER,
OCC_HTMGT_RSP_OFFSET_HOMER, and OPAL_OFFSET_HOMER according
to new P9 specifications.
Change-Id: Ib233181c4ad1837b57c45144d1256b87799dc5bc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24085
Tested-by: FSP CI Jenkins
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/proc/proc_data_control.c')
-rwxr-xr-x | src/occ_405/proc/proc_data_control.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/occ_405/proc/proc_data_control.c b/src/occ_405/proc/proc_data_control.c index 9f55d91..c68b422 100755 --- a/src/occ_405/proc/proc_data_control.c +++ b/src/occ_405/proc/proc_data_control.c @@ -220,12 +220,12 @@ void task_core_data_control( task_t * i_task ) G_core_data_control_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32); if(G_sysConfigData.system_type.kvm) { - //Set the chiplet bounds (pmax/pmin) only on sapphire + //Set the chiplet bounds (pmax/pmin) only on opal G_core_data_control_parms.select = GPE_SET_PSTATES_PMBR; } else { - //Set the chiplet pstate request on non-sapphire systems + //Set the chiplet pstate request on non-opal systems G_core_data_control_parms.select = GPE_SET_PSTATES_PMCR; } |