Memory Power Control when entering and exiting IPS (Idle Power Save)

memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.

Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

1 files changed, 3 insertions, 12 deletions

diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h
index 26cb519..abd92c9 100755
--- a/src/occ_405/occ_sys_config.h
+++ b/src/occ_405/occ_sys_config.h
@@ -35,6 +35,7 @@
 #include <state.h>
 #include <apss.h>
 #include <dimm.h>
+#include <mem_structs.h>
 
 #define MAX_NUM_OCC              4
 #define MAX_NUM_NODES            4
@@ -279,16 +280,6 @@ typedef struct
     uint16_t    reserved3;               //reserved
 } mem_throt_config_data_t;
 
-// this enum defines memory power control
-typedef enum
-{
-    MEM_PWR_CTL_OFF                  = 0x00,
-    MEM_PWR_CTL_POWER_DOWN           = 0x01,
-    MEM_PWR_CTL_PD_AND_STR           = 0x02,
-    MEM_PWR_CTL_PD_AND_STR_CLK_STOP  = 0x03,
-    MEM_PWR_CTL_NO_SUPPORT           = 0xFF,
-} eMemoryPowerControlSetting;
-
 
 // Sys Config Structure
 
@@ -399,8 +390,8 @@ typedef struct
   uint32_t dimm_huids[MAX_NUM_CENTAURS][NUM_DIMMS_PER_CENTAUR];
   uint8_t mem_type;
   uint8_t dimm_i2c_engine;
-  eMemoryPowerControlSetting ips_mem_pwr_ctl;     // IPS memory power control
-  eMemoryPowerControlSetting default_mem_pwr_ctl; // default memory power control
+  uint8_t ips_mem_pwr_ctl;     // IPS memory power control
+  uint8_t default_mem_pwr_ctl; // default memory power control
 
   // --------------------------------------
   // Memory Throttle limits