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author | mbroyles <mbroyles@us.ibm.com> | 2016-10-18 09:07:27 -0500 |
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committer | Martha Broyles <mbroyles@us.ibm.com> | 2016-10-20 17:15:07 -0400 |
commit | 9af547bcc5ff79e711d1e497a3ff56b30d313448 (patch) | |
tree | bfb88a83bf0936a93789211a8d99d9b7d2200ee2 /src/occ_405/occ_sys_config.h | |
parent | 055aad1e072a479e2f7ab89f60e75ff2ad6c85d6 (diff) | |
download | talos-occ-9af547bcc5ff79e711d1e497a3ff56b30d313448.tar.gz talos-occ-9af547bcc5ff79e711d1e497a3ff56b30d313448.zip |
Support new APSS Function IDs
RTC: 162291
Change-Id: I979615313a9c5e860fa570736e0ce598b978f877
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31416
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Diffstat (limited to 'src/occ_405/occ_sys_config.h')
-rwxr-xr-x | src/occ_405/occ_sys_config.h | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h index e0799b6..b7abf18 100755 --- a/src/occ_405/occ_sys_config.h +++ b/src/occ_405/occ_sys_config.h @@ -96,6 +96,8 @@ typedef union #define MAX_DOM_OC_LATCH 4 #define MAX_CONN_OC_SIGNALS 5 #define MAX_PROC_CENT_CH 4 +#define MAX_GPU_DOMAINS 2 +#define MAX_NUM_GPU_PER_DOMAIN 3 // List of all possible APSS Channel assignments (Function IDs) // Each channel in the APSS will be associated with only one of these @@ -127,10 +129,16 @@ typedef enum ADC_GND_REMOTE_SENSE = 0x15, ADC_TOTAL_SYS_CURRENT = 0x16, ADC_MEM_CACHE = 0x17, - ADC_GPU_SENSE = 0x18, - ADC_MEMORY_PROC_0_0 = 0x19, //NOTE: On Habanero, the processor has 4 centaurs with 1 APSS channel - ADC_MEMORY_PROC_0_1 = 0x1A, // assigned to each one of them. ADC_MEMORY_PROC_0 will be used - ADC_MEMORY_PROC_0_2 = 0x1B, // for the first one and these are for the other 3. + ADC_GPU_0_0 = 0x18, // ADC_GPU_x_y x=Proc, y=GPU (max of 3 GPUs/proc) + ADC_MEMORY_PROC_0_0 = 0x19, + ADC_MEMORY_PROC_0_1 = 0x1A, + ADC_MEMORY_PROC_0_2 = 0x1B, + ADC_12V_STANDBY_CURRENT = 0x1C, + ADC_GPU_0_1 = 0x1D, + ADC_GPU_0_2 = 0x1E, + ADC_GPU_1_0 = 0x1F, + ADC_GPU_1_1 = 0x20, + ADC_GPU_1_2 = 0x21, NUM_ADC_ASSIGNMENT_TYPES // This should always be the last member } eApssAdcChannelAssignments; @@ -195,7 +203,8 @@ typedef struct uint8_t sense_12v; uint8_t remote_gnd; uint8_t mem_cache; - uint8_t gpu; + uint8_t current_12v_stby; + uint8_t gpu[MAX_GPU_DOMAINS][MAX_NUM_GPU_PER_DOMAIN]; } apssAdcChannelData_t; // Master/Slave Configuration @@ -420,9 +429,6 @@ typedef struct } occModuleConfigData_t; __attribute__ ((__aligned__ (128))) -// Default PstateSuperStructure that can be used instead of TMGT provided one. -extern const unsigned char G_defaultOccPstateSuperStructure[]; - // MASTER PCAP values. extern pcap_config_data_t G_master_pcap_data; |