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author | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-02 22:20:14 -0500 |
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committer | Wael El-Essawy <welessa@us.ibm.com> | 2016-05-25 16:19:23 -0400 |
commit | 6d29cab23da5bacaf0772bb8dd6265c4b442760c (patch) | |
tree | d7dee4b726108c87734bd1508abccf47d1a230e4 /src/occ_405/occ_sys_config.h | |
parent | 6f82299cb1e306dabef5bbae1a9d4e5817dbcea9 (diff) | |
download | talos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.tar.gz talos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.zip |
Pstate Infrastructure & Support config data required for active state
- Support all config data required for active state.
- Set 'active ready' bit in poll response when all config data has been received.
- Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist.
- Put in TODO call PGPE to enable pstates this will also be telling PGPE how to
set PMCR mode register (OCC control pstates or OPAL).
- Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard
codes until PGPE is available.
- Call to "proc_pstate_initialize()" moved to state transition to observation
- Cleanup proc_freq2pstate()
- rewrite amec_slv_freq_smh()
- the calls to proc_set_core_bounds() and proc_set_core_pstate() will be
replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores
or set pstate for all given cores.
- Remove all DCM related code.
Change-Id: I449d188b2cffc345afca19717dcbea037f159114
RTC:130224
RTC:150935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977
Tested-by: FSP CI Jenkins
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/occ_sys_config.h')
-rwxr-xr-x | src/occ_405/occ_sys_config.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h index 796d0bf..ec5e9aa 100755 --- a/src/occ_405/occ_sys_config.h +++ b/src/occ_405/occ_sys_config.h @@ -45,6 +45,7 @@ #define MAX_NUM_MEM_CONTROLLERS 8 #define MAX_NUM_CENTAURS 8 #define NUM_PROC_VRMS 2 +#define MAX_NUM_MCU_PORTS 4 #define NUM_PROC_CHIPS_PER_OCC 1 #define NUM_CENTAURS_PER_MEM_CONTROLLER 1 @@ -225,13 +226,22 @@ typedef struct // Memory Throttle settings typedef struct { - uint16_t min_ot_n_per_mba; //minimum value + uint16_t min_n_per_mba; //minimum value + uint16_t min_mem_power; // Max mem Power @min (x0.1W) + + uint16_t pcap1_n_per_mba; //max mba value for Power Cap Level 1 + uint16_t pcap1_mem_power; //max memory power @PCAP L1 + + uint16_t pcap2_n_per_mba; //max mba value for Power Cap Level 2 + uint16_t pcap2_mem_power; //max memory power @PCAP L2 + uint16_t nom_n_per_mba; //max mba value for nominal mode uint16_t nom_n_per_chip; //chip setting for nominal mode - uint16_t turbo_n_per_mba; //max mba value for turbo mode - uint16_t turbo_n_per_chip; //chip setting for nominal mode + uint16_t nom_mem_power; //max memory power @Redundant + uint16_t ovs_n_per_mba; //max mba value for oversubscription uint16_t ovs_n_per_chip; //chip setting for oversubscription + uint16_t ovs_mem_power; //max memory power @oversubscription } mem_throt_config_data_t; // Sys Config Structure |