diff options
author | William Bryan <wilbryan@us.ibm.com> | 2017-04-05 14:24:34 -0500 |
---|---|---|
committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-04-26 12:53:32 -0400 |
commit | 14e46463c4aa168343162b159ba0e9f05654fb27 (patch) | |
tree | e0b2e29dfac88ec0906a2402c5dcd6f26ff3164e /src/occ_405/main.c | |
parent | 7da6a9afd506f8854972bbf4325b2e88abfcc2ce (diff) | |
download | talos-occ-14e46463c4aa168343162b159ba0e9f05654fb27.tar.gz talos-occ-14e46463c4aa168343162b159ba0e9f05654fb27.zip |
Enable Composite mode
Change-Id: I7235c414923079701fdf1392960b3fc48363bff0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38896
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/main.c')
-rwxr-xr-x | src/occ_405/main.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/occ_405/main.c b/src/occ_405/main.c index 01f22b3..f969992 100755 --- a/src/occ_405/main.c +++ b/src/occ_405/main.c @@ -280,12 +280,13 @@ void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority) * End Function Specification */ //NOTE: use "putscom pu 6B111 0 3 101 -ib -p1" to inject the error. -#define OCC_LFIR_SPARE_BIT50 0x0000000000002000ull //gm031 +#define OCC_LFIR_SPARE_BIT50 0x0000000000002000ull void occ_hw_error_isr(void *private, SsxIrqId irq, int priority) { //set bit 50 of the OCC LFIR so that the PRDF component will log an error and callout the processor //TMGT will also see a problem and log an error but it will be informational. - _putscom(OCB_OCCLFIR_OR, OCC_LFIR_SPARE_BIT50, SCOM_TIMEOUT); + + // TODO: Determine how to set this without a SCOM. //Halt occ so that hardware will enter safe mode OCC_HALT(ERRL_RC_OCC_HW_ERROR); |