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author | mbroyles <mbroyles@us.ibm.com> | 2016-09-19 11:54:55 -0500 |
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committer | Martha Broyles <mbroyles@us.ibm.com> | 2016-09-29 11:28:53 -0400 |
commit | a57f623c26bdf3889703ed63334745c966c6096d (patch) | |
tree | b2f81389aa3bf5a420c6a115d8c10ae787375ede /src/occ_405/dimm/dimm_control.c | |
parent | d137bd848a05d5afd8a9ee5c9803f421ebd0a922 (diff) | |
download | talos-occ-a57f623c26bdf3889703ed63334745c966c6096d.tar.gz talos-occ-a57f623c26bdf3889703ed63334745c966c6096d.zip |
Enable power capping and oversubscription. RTC:137621 RTC:133156
Change-Id: I98b745ccb56d89d066508d4195250b1bf446dbc6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29898
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Diffstat (limited to 'src/occ_405/dimm/dimm_control.c')
-rw-r--r-- | src/occ_405/dimm/dimm_control.c | 41 |
1 files changed, 24 insertions, 17 deletions
diff --git a/src/occ_405/dimm/dimm_control.c b/src/occ_405/dimm/dimm_control.c index 1188e76..2b3a43d 100644 --- a/src/occ_405/dimm/dimm_control.c +++ b/src/occ_405/dimm/dimm_control.c @@ -111,7 +111,6 @@ bool dimm_control(uint8_t mc, uint8_t port) // // End Function Specification -#define DIMM_TRACE_THROTTLE_DELAY 8 void dimm_update_nlimits(uint8_t mc, uint8_t port) { /*------------------------------------------------------------------------*/ @@ -123,6 +122,10 @@ void dimm_update_nlimits(uint8_t mc, uint8_t port) /*------------------------------------------------------------------------*/ /* Code */ /*------------------------------------------------------------------------*/ + if (L_trace_throttle_count == 0) + { + L_trace_throttle_count = G_configured_mbas; + } do { @@ -138,12 +141,18 @@ void dimm_update_nlimits(uint8_t mc, uint8_t port) //Minimum N value is not state dependent l_active_limits->min_n_per_mba = l_state_limits->min_n_per_mba; - if(CURRENT_MODE() == OCC_MODE_NOMINAL) + //Power Capping memory? + if(g_amec->pcap.active_mem_level == 1) + { + l_port_dimm_maxn = l_state_limits->pcap_n_per_chip; + l_slot_dimm_maxn = l_state_limits->pcap_n_per_mba; + } + else if(CURRENT_MODE() == OCC_MODE_NOMINAL) { l_port_dimm_maxn = l_state_limits->nom_n_per_chip; l_slot_dimm_maxn = l_state_limits->nom_n_per_mba; } - else //DPS, TURBO, FFO, and SPS modes will use these settings + else //all other modes will use turbo settings { l_port_dimm_maxn = l_state_limits->turbo_n_per_chip; l_slot_dimm_maxn = l_state_limits->turbo_n_per_mba; @@ -156,25 +165,23 @@ void dimm_update_nlimits(uint8_t mc, uint8_t port) { l_active_limits->max_n_per_mba = l_slot_dimm_maxn; - //Don't repeatedly trace same slot changing, just once - if(!L_trace_throttle_count) + //Don't trace all MCAs changing, just trace one they will all + //be the same unless there is a different number of DIMMs behind + //the MCAs or a mix of DIMM sizes is supported + if(L_trace_throttle_count == G_configured_mbas) { - L_trace_throttle_count = DIMM_TRACE_THROTTLE_DELAY; TRAC_IMP("dimm_update_nlimits: New DIMM slot throttle values: " - "MC#|Port:[0x%08x], " - "Max|Min slot Power:[0x%08x], Max port power:[0x%08x] ", - (uint32_t)((mc << 16) | port), - (uint32_t)( l_active_limits->min_n_per_mba | - (l_active_limits->max_n_per_mba << 16)), - l_active_limits->max_n_per_chip << 16); - + "MC#|Port:[0x%04x], " + "Max|Min N_PER_MBA:[0x%08x], Max N_PER_CHIP:[0x%04x] ", + (uint16_t)((mc << 8) | port), + (uint32_t)( (l_active_limits->max_n_per_mba << 16) | + l_active_limits->min_n_per_mba), + l_active_limits->max_n_per_chip); } } - if(L_trace_throttle_count) - { - L_trace_throttle_count--; - } + L_trace_throttle_count &= ~(0x8000 >> ((mc * (MAX_NUM_MCU_PORTS)) + port)); + } // NIMBUS_DIMM_THROTTLING_CONFIGURED ? }while(0); |