Pstate Infrastructure & Support config data required for active state

- Support all config data required for active state.
- Set 'active ready' bit in poll response when all config data has been received.
- Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist.
- Put in TODO call PGPE to enable pstates this will also be telling PGPE how to
  set PMCR mode register (OCC control pstates or OPAL).
- Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard
  codes until PGPE is available.
- Call to "proc_pstate_initialize()" moved to state transition to observation
- Cleanup proc_freq2pstate()
- rewrite amec_slv_freq_smh()
  - the calls to proc_set_core_bounds() and proc_set_core_pstate() will be
    replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores
    or set pstate for all given cores.
- Remove all DCM related code.

Change-Id: I449d188b2cffc345afca19717dcbea037f159114
RTC:130224
RTC:150935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977
Tested-by: FSP CI Jenkins
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

5 files changed, 5 insertions, 81 deletions

diff --git a/src/occ_405/dcom/dcom.c b/src/occ_405/dcom/dcom.c
index 3f4c268..eed1cee 100755
--- a/src/occ_405/dcom/dcom.c
+++ b/src/occ_405/dcom/dcom.c
@@ -71,9 +71,6 @@ dcom_fail_count_t G_dcomSlvInboxCounter = {0};
 
 uint8_t     G_occ_role = OCC_SLAVE;
 
-
-uint8_t     G_dcm_occ_role            = OCC_DCM_SLAVE;
-
 // PBAX ID of this OCC is also its PowerBus ID.  Contains ChipId & NodeId.
 pob_id_t    G_pbax_id                  = {0};
 
@@ -88,9 +85,6 @@ PbaxTarget  G_pbax_unicast_target;
 // Number of occ's that *should* be present
 uint8_t     G_occ_num_present;
 
-// DCM Status from all Slaves
-proc_gpsm_dcm_sync_occfw_t G_dcm_sync_occfw_table[MAX_OCCS];
-
 // Master/slave event flags
 uint32_t    G_master_event_flags              = 0;
 uint32_t    G_slave_event_flags               = 0;
@@ -399,47 +393,6 @@ void dcom_error_check( const dcom_error_type_t i_error_type, const bool i_clear_
 
 // Function Specification
 //
-// Name: dcom_build_dcm_sync_msg
-//
-// Description: Copy messages from DCM Master (OCC Slave) to
-//              DCM Slave (also OCC Slave) and vice versa
-//
-// End Function Specification
-void dcom_build_dcm_sync_msg(const dcom_error_type_t i_which_msg)
-{
-    // If the OCC Master isn't a DCM, no one else is a DCM either, so
-    // no need to bother sending these messages back & forth.
-    if(proc_is_dcm())
-    {
-        if ( i_which_msg == SLAVE_INBOX )
-        {
-            uint32_t l_slv_idx = 0;
-            for(l_slv_idx = 0; l_slv_idx < MAX_OCCS; l_slv_idx++)
-            {
-                // Populate G_dcm_sync_occfw_table with the data from all OCC Slaves
-                G_dcm_sync_occfw_table[l_slv_idx] = G_dcom_slv_outbox_rx[l_slv_idx].dcm_sync;
-            }
-
-            // DCM are always in even/odd numbered pairs sequentially as
-            // DCM master = even number[0,2,4,6] DCM Slave = odd number [1,3,5,7]
-            // with DCM pairs being [0,1], [2,3], [4,5], [6,7]
-            // so we can do this simple swizzle here and not need a table to
-            // do the conversion.
-            for(l_slv_idx = 0; l_slv_idx < MAX_OCCS; l_slv_idx+=2)
-            {
-                G_dcom_slv_inbox_tx[l_slv_idx].dcm_sync = G_dcm_sync_occfw_table[l_slv_idx+1];
-                G_dcom_slv_inbox_tx[l_slv_idx+1].dcm_sync = G_dcm_sync_occfw_table[l_slv_idx];
-            }
-        }
-        else if ( i_which_msg == SLAVE_OUTBOX )
-        {
-            G_dcom_slv_outbox_tx.dcm_sync = proc_gpsm_dcm_sync_get_state();
-        }
-    }
-}
-
-// Function Specification
-//
 // Name: dcom_build_occfw_msg
 //
 // Description: Copy data into occ fw msg portion
@@ -631,9 +584,6 @@ void task_dcom_parse_occfwmsg(task_t *i_self)
     g_amec->part_config.part_list[0].soft_fmin = G_dcom_slv_inbox_rx.soft_fmin;
     g_amec->part_config.part_list[0].soft_fmax = G_dcom_slv_inbox_rx.soft_fmax;
 
-    // Update DCM Sync var that will be used in thread
-    proc_gpsm_dcm_sync_update_from_mbox(&G_dcom_slv_inbox_rx.dcm_sync);
-
     // acknowledge all masters event flags
     G_master_event_flags_ack = G_dcom_slv_inbox_rx.occ_fw_mailbox[2];
 
diff --git a/src/occ_405/dcom/dcom.h b/src/occ_405/dcom/dcom.h
index dc960d0..1ff263d 100755
--- a/src/occ_405/dcom/dcom.h
+++ b/src/occ_405/dcom/dcom.h
@@ -45,10 +45,6 @@
 #define OCC_MASTER        1
 #define OCC_BACKUP_MASTER 2
 
-// OCC roles inside a DCM socket
-#define OCC_DCM_SLAVE     0
-#define OCC_DCM_MASTER    1
-
 // Memory address space where DCOM, sensor data, OPAL communications,
 // etc take place. Uses BAR2, with pba_region = 0b10
 #define COMMON_BASE_ADDRESS 0xA0000000
@@ -99,16 +95,16 @@
 #define NUM_ENTRIES_PBAX_QUEUE0 32
 #define NUM_ENTRIES_PBAX_QUEUE1 16
 
-// Wait for defines number of retries for task 
+// Wait for defines number of retries for task
 #define MAX_WAIT_FOR_SLAVES 400
 #define MAX_WAIT_FOR_MASTER 400
 
 // general defines
 #define TOD_SIZE 6
 #define NUM_TOD_SENSORS 3
-#define SLV_INBOX_RSV_SIZE 64
+#define SLV_INBOX_RSV_SIZE 68
 #define SLV_MAILBOX_SIZE 32
-#define SLV_OUTBOX_RSV_SIZE 614
+#define SLV_OUTBOX_RSV_SIZE 618
 #define DOORBELL_RSV_SIZE 1
 
 #define DCOM_250us_GAP 1
@@ -180,12 +176,9 @@ typedef struct
           freqConfig_t sys_mode_freq;
           uint8_t      tb_record;
       };
-      uint8_t  reserved[ SLV_INBOX_RSV_SIZE ];                      // [154] - 64 bytes
+      uint8_t  reserved[ SLV_INBOX_RSV_SIZE ];                      // [154] - 68 bytes
     };
 
-    // GPSM DCM Synchronization
-    proc_gpsm_dcm_sync_occfw_t dcm_sync;                            // [220] - 4 bytes
-
     // General Firmware Message Passing
     uint8_t  occ_fw_mailbox[ SLV_MAILBOX_SIZE ];                    // [224] - 32 bytes
 
@@ -234,7 +227,7 @@ typedef struct __attribute__ ((packed))
     // Reserved Bytes
     union
     {
-        uint8_t  reserved[SLV_OUTBOX_RSV_SIZE];                  // [374] - 614 bytes
+        uint8_t  reserved[SLV_OUTBOX_RSV_SIZE];                  // [374] - 618 bytes
         struct __attribute__ ((packed))
         {
             uint8_t _reserved_1;
@@ -243,9 +236,6 @@ typedef struct __attribute__ ((packed))
         };
     };
 
-    // GPSM DCM Synchronization
-    proc_gpsm_dcm_sync_occfw_t dcm_sync;                         // [988] - 4 bytes
-
     // General Firmware Message Passing
     uint8_t  occ_fw_mailbox[SLV_MAILBOX_SIZE];                   // [992] - 32 bytes
 } dcom_slv_outbox_t __attribute__ ((aligned (128)));
@@ -410,10 +400,6 @@ extern uint8_t G_slv_outbox_complete;
 // Specifies if the OCC is a MASTER or SLAVE
 extern uint8_t G_occ_role;
 
-// Specifies if the OCC is configured to be a Master or Slave inside the DCM
-// chip. In the case of SCMs, it will always return the Master role.
-extern uint8_t G_dcm_occ_role;
-
 // Holds PowerBus ID of this OCC (Chip & node). For P9, this is the same
 // for pob_id and PBAX ID.
 extern pob_id_t G_pbax_id;
@@ -532,7 +518,4 @@ void task_dcom_parse_occfwmsg(task_t *i_self);
 // Copy occ fw msg
 void dcom_build_occfw_msg( dcom_error_type_t i_which_msg );
 
-// Copy OCC DCM Sync Messages
-void dcom_build_dcm_sync_msg(const dcom_error_type_t i_which_msg);
-
 #endif //_DCOM_H
diff --git a/src/occ_405/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index 8d660c0..ad1beba 100644
--- a/src/occ_405/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -165,9 +165,6 @@ uint32_t dcom_build_slv_inbox(void)
     G_mst_tunable_parameter_overwrite = 0;
     dcom_build_occfw_msg( SLAVE_INBOX );
 
-    // Copy Data from one DCM pair's Outbox to other DCM pair's inbox
-    dcom_build_dcm_sync_msg( SLAVE_INBOX );
-
     l_addr_of_slv_inbox_in_main_mem = dcom_which_buffer();
 
     //DOORBELL.................
diff --git a/src/occ_405/dcom/dcomSlaveTx.c b/src/occ_405/dcom/dcomSlaveTx.c
index e6cf2d2..3f05b08 100755
--- a/src/occ_405/dcom/dcomSlaveTx.c
+++ b/src/occ_405/dcom/dcomSlaveTx.c
@@ -78,9 +78,6 @@ uint32_t dcom_build_slv_outbox(void)
     // Call dcom_build_occfw_msg
     dcom_build_occfw_msg( SLAVE_OUTBOX );
 
-    // Create message that will be sent to DCM peer
-    dcom_build_dcm_sync_msg( SLAVE_OUTBOX );
-
     l_addr_of_slv_outbox_in_main_mem = dcom_which_buffer_slv_outbox();
 
     l_addr_of_slv_outbox_in_main_mem += G_pbax_id.chip_id*sizeof(dcom_slv_outbox_t);
diff --git a/src/occ_405/dcom/dcom_thread.c b/src/occ_405/dcom/dcom_thread.c
index 61606b1..c151482 100755
--- a/src/occ_405/dcom/dcom_thread.c
+++ b/src/occ_405/dcom/dcom_thread.c
@@ -163,9 +163,6 @@ void Dcom_thread_routine(void *arg)
             }
         }
 
-        // TEMP/TODO: In P8, we would call proc_gpsm_dcm_sync_enable_pstates_smh() here,
-        //            if not in safe mode. Do we need to do something similar in P9?
-
         // --------------------------------------------------
         // SSX Sleep
         // --------------------------------------------------