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author | mbroyles <mbroyles@us.ibm.com> | 2017-06-07 16:38:45 -0500 |
---|---|---|
committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-06-12 13:17:45 -0400 |
commit | a635739ec0648a64e897b401915cedabf4123943 (patch) | |
tree | ef771a2c6a682d13e0edb3d3e93cf4d12d874276 /src/occ_405/amec | |
parent | dadf2726aa024c7100fe295af78bdfc2e88fb7ef (diff) | |
download | talos-occ-a635739ec0648a64e897b401915cedabf4123943.tar.gz talos-occ-a635739ec0648a64e897b401915cedabf4123943.zip |
OCC support for no APSS and new GPU Config Data
Change-Id: Id58a06378f3c0a7fd9fb436b96823eca15028031
RTC: 160889
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41513
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec')
-rwxr-xr-x | src/occ_405/amec/amec_pcap.c | 4 | ||||
-rwxr-xr-x | src/occ_405/amec/amec_sensors_power.c | 10 | ||||
-rwxr-xr-x | src/occ_405/amec/amec_sys.h | 6 |
3 files changed, 13 insertions, 7 deletions
diff --git a/src/occ_405/amec/amec_pcap.c b/src/occ_405/amec/amec_pcap.c index b5cad52..512a82c 100755 --- a/src/occ_405/amec/amec_pcap.c +++ b/src/occ_405/amec/amec_pcap.c @@ -50,7 +50,7 @@ //*************************************************************************/ // Globals //*************************************************************************/ -extern bool G_apss_present; +extern PWR_READING_TYPE G_pwr_reading_type; //Number of ticks to wait before dropping below nominal frequency #define PWR_SETTLED_TICKS 4 @@ -374,7 +374,7 @@ void amec_power_control(void) /* Code */ /*------------------------------------------------------------------------*/ - if(G_apss_present) + if(G_pwr_reading_type == PWR_READING_TYPE_APSS) { // Calculate the pcap for the proc, memory and the power capping limit // for nominal cores. diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c index ab6f1ee..4e4f240 100755 --- a/src/occ_405/amec/amec_sensors_power.c +++ b/src/occ_405/amec/amec_sensors_power.c @@ -72,7 +72,7 @@ uint32_t G_curr_num_gpus_sys = 0; extern uint8_t G_occ_interrupt_type; extern bool G_vrm_thermal_monitoring; -extern bool G_apss_present; +extern PWR_READING_TYPE G_pwr_reading_type; //*************************************************************************/ // Code @@ -195,7 +195,7 @@ void amec_update_apss_sensors(void) { // Need to check to make sure APSS data has been received // via slave inbox first - if (G_slv_inbox_received && G_apss_present) + if (G_slv_inbox_received && (G_pwr_reading_type == PWR_READING_TYPE_APSS)) { uint8_t l_proc = G_pbax_id.chip_id; uint32_t temp32 = 0; @@ -571,12 +571,12 @@ void update_avsbus_power_sensors(const avsbus_type_e i_type) // = v(100uV) * i(10mA) / 1,000,000 const uint32_t l_power = l_chip_voltage_100uv * l_current_10ma / 1000000; sensor_update(AMECSENSOR_PTR(l_powerSensor), (uint16_t)l_power); - if(!G_apss_present) + if(G_pwr_reading_type != PWR_READING_TYPE_APSS) { // no APSS, update the processor power sensor with total processor power - // TODO RTC 160889 add in processor power for parts not measured (i.e. Vddr, Vcs, Vio etc) + // Vdd + Vdn + fixed adder for parts not measured (i.e. Vddr, Vcs, Vio etc) sensor_t *l_sensor2 = getSensorByGsid(l_powerSensor2); - const uint16_t l_proc_power = (uint16_t)l_power + l_sensor2->sample; + const uint16_t l_proc_power = (uint16_t)l_power + l_sensor2->sample + G_sysConfigData.proc_power_adder; sensor_update(AMECSENSOR_PTR(PWRPROC), l_proc_power); } } diff --git a/src/occ_405/amec/amec_sys.h b/src/occ_405/amec/amec_sys.h index 40afd49..d72a49b 100755 --- a/src/occ_405/amec/amec_sys.h +++ b/src/occ_405/amec/amec_sys.h @@ -471,9 +471,15 @@ typedef struct sensor_t temp2mscent; sensor_t tempdimmthrm; sensor_t memsp2ms_tls; + // Nimbus DIMM Sensors sensor_t tempdimm[NUM_DIMM_PORTS*NUM_DIMMS_PER_I2CPORT]; + // GPU Sensors + sensor_t tempgpu0; + sensor_t tempgpu1; + sensor_t tempgpu2; + sensor_t curvdn; sensor_t pwrvdd; sensor_t pwrvdn; |