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| author | Wael El-Essawy <welessa@us.ibm.com> | 2017-03-22 10:30:48 -0500 |
|---|---|---|
| committer | Wael El-Essawy <welessa@us.ibm.com> | 2017-05-10 13:53:16 -0400 |
| commit | cf2258322bb72a2cd868f8eaef25e9a665077f4f (patch) | |
| tree | f7a9b13ef36943246377ff623ed917fa4fd08ada /src/occ_405/amec/amec_init.c | |
| parent | ff3b5a1c08389bf766de21adcd033e3c7b86af87 (diff) | |
| download | talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.tar.gz talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.zip | |
Memory Power Control when entering and exiting IPS (Idle Power Save)
memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.
Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_init.c')
| -rw-r--r-- | src/occ_405/amec/amec_init.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/occ_405/amec/amec_init.c b/src/occ_405/amec/amec_init.c index eb08409..7343c2f 100644 --- a/src/occ_405/amec/amec_init.c +++ b/src/occ_405/amec/amec_init.c @@ -348,6 +348,9 @@ void amec_init_gamec_struct(void) // g_amec->ptr_probe250us[6] = g_amec->ptr_probe250us[6]+2; // Point to low 16 bits of testscom1 // g_amec->ptr_probe250us[7] = &g_amec->task_centaur_data_count; + // Initialize the current_mem_pwr_ctl to indicate that memory power control is not supported + // update memory control registers only if new ips/default memory power control is different + g_amec->sys.current_mem_pwr_ctl = MEM_PWR_CTL_NO_SUPPORT; } // Function Specification |
