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authormbroyles <mbroyles@us.ibm.com>2017-06-15 12:33:02 -0500
committerWilliam A. Bryan <wilbryan@us.ibm.com>2017-06-16 13:53:52 -0400
commit2c557cd7a08573c142fb508ae729887531af51c2 (patch)
treedda2ceb12032b149f4339043e38bc92847f3c9bf /src/occ_405/amec/amec_analytics.c
parentca4e0ea382d03376fba5a1d3400fc22d7ba66dd5 (diff)
downloadtalos-occ-2c557cd7a08573c142fb508ae729887531af51c2.tar.gz
talos-occ-2c557cd7a08573c142fb508ae729887531af51c2.zip
Stop State and Throttle Sensor Updates
Change-Id: Ic2589a9e3fb5bad67ce85fb7a5f2c3e9af9f5047 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41887 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shawn M. McCarney <shawnmm@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_analytics.c')
-rwxr-xr-xsrc/occ_405/amec/amec_analytics.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/src/occ_405/amec/amec_analytics.c b/src/occ_405/amec/amec_analytics.c
index 5c8edf5..9cca40d 100755
--- a/src/occ_405/amec/amec_analytics.c
+++ b/src/occ_405/amec/amec_analytics.c
@@ -190,13 +190,6 @@ void amec_analytics_main(void)
return;
}
- g_amec->packednapsleep[0] = (g_amec->proc[0].winkcnt4ms.sample<<8) +
- g_amec->proc[0].sleepcnt4ms.sample;
- // There are no other elements in proc[] array other than element 0
- g_amec->packednapsleep[1] = 0;
- g_amec->packednapsleep[2] = 0;
- g_amec->packednapsleep[3] = 0;
-
switch (g_amec->analytics_group)
{
case 45: // Group 45
@@ -342,12 +335,6 @@ void amec_analytics_main(void)
l=l+1;
}
- g_amec->g44_avg[(i*MSA)+48] = g_amec->g44_avg[(i*MSA)+48] +
- (UINT32)(g_amec->proc[i].winkcnt4ms.sample<<3); // counter of cores that entered winkle for at least part of the 2msec interval: 1/8th resolution
- g_amec->g44_avg[(i*MSA)+49] = g_amec->g44_avg[(i*MSA)+49] +
- (UINT32)(g_amec->proc[i].sleepcnt4ms.sample<<3); // counter of cores that entered sleep for at least part of the 2msec interval: 1/8th resolution
-
-
m=0; // counter for actual configured # of cores - 1.
for (j=0; j<12; j++) // Group 45 supports up to 12 cores to be configured per OCC chip
{
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