diff options
author | Fadi Kassem <fmkassem@us.ibm.com> | 2014-12-09 18:49:57 -0600 |
---|---|---|
committer | Stephan Broyles <sbroyles@us.ibm.com> | 2014-12-10 09:34:37 -0600 |
commit | c76114bbb31fb460672af61393678f721120aceb (patch) | |
tree | 002847ee445b9ff8c22bf38133645ccebe443291 /src/occ/proc | |
parent | 539d631fd028e4806b424fd51e5adffa3db2cab3 (diff) | |
download | talos-occ-c76114bbb31fb460672af61393678f721120aceb.tar.gz talos-occ-c76114bbb31fb460672af61393678f721120aceb.zip |
OCC cleanup; removed doxyfile, cleaned proc component.
Change-Id: I2ca003680d287ffc2e41a304cdf94216f3c3a3a9
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14822
Reviewed-by: Stephan Broyles <sbroyles@us.ibm.com>
Tested-by: Stephan Broyles <sbroyles@us.ibm.com>
Diffstat (limited to 'src/occ/proc')
-rwxr-xr-x | src/occ/proc/proc_data.c | 232 | ||||
-rwxr-xr-x | src/occ/proc/proc_data.h | 138 | ||||
-rwxr-xr-x | src/occ/proc/proc_data_control.c | 145 | ||||
-rwxr-xr-x | src/occ/proc/proc_data_control.h | 58 | ||||
-rwxr-xr-x | src/occ/proc/proc_data_service_codes.h | 87 | ||||
-rwxr-xr-x | src/occ/proc/proc_pstate.c | 293 | ||||
-rwxr-xr-x | src/occ/proc/proc_pstate.h | 118 | ||||
-rwxr-xr-x | src/occ/proc/test/Makefile | 32 | ||||
-rwxr-xr-x | src/occ/proc/test/app.mk | 49 | ||||
-rwxr-xr-x | src/occ/proc/test/main.c | 247 |
10 files changed, 469 insertions, 930 deletions
diff --git a/src/occ/proc/proc_data.c b/src/occ/proc/proc_data.c index af0e402..eb7fe31 100755 --- a/src/occ/proc/proc_data.c +++ b/src/occ/proc/proc_data.c @@ -1,43 +1,28 @@ -/****************************************************************************** -// @file proc_data.c -// @brief Data codes for proc component. -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_data_c proc_data.c - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * nguyenp 09/27/2011 Created - * nguyenp 09/27/2011 Added bulk core data and proc core - * initialization code. - * @01 nguyenp 10/19/2011 Added fast core data colect code. - * Added new interfaces to gain access to - * bulk core and fast core data. - * Change OCC core id numbering scheme. - * @th006 thallet 11/21/2011 RESET_REQUEST substituted for todo's - * @rc001 rickylie 12/30/2011 Moved debug trace defines to trac.h - * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments - * @th00b thallet 02/28/2012 Minor changes to make proc collection work. - * @th00f thallet 06/27/2012 Changed to use CoreData as provided by HW team - * @nh001 neilhsu 05/23/2012 Add missing error log tags - * @th010 thallet 07/11/2012 Pstate Enablement - * @th032 thallet 04/26/2013 Tuleta HW Bringup - * @th043 892554 thallet 07/23/2013 Automatic Nominal/Active state change - * @gm006 SW224414 milesg 09/16/2013 Reset and FFDC improvements - * @gm022 908890 milesg 01/23/2014 update global core presence mask from pmc deconfig register - * @sb055 911966 sbroyles 02/27/2014 Enable PBCS heartbeat - * @sbpde 922027 sbroyles 04/04/2014 Add error check to GPE proc data - * collection. - * @endverbatim - * - *///*************************************************************************/ - -//************************************************************************* -// Includes -//************************************************************************* +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_data.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + #include "proc_data.h" #include "pgp_async.h" #include "threadSch.h" @@ -51,29 +36,9 @@ #include "state.h" #include "proc_data_control.h" -//************************************************************************* -// Externs -//************************************************************************* - -//************************************************************************* -// Macros -//************************************************************************* - -//************************************************************************* -// Defines/Enums -//************************************************************************* - -//************************************************************************* -// Structures -//************************************************************************* - -//************************************************************************* -// Globals -//************************************************************************* //Global array of core data buffers -GPE_BUFFER(gpe_bulk_core_data_t G_core_data[MAX_NUM_FW_CORES+NUM_CORE_DATA_DOUBLE_BUF+NUM_CORE_DATA_EMPTY_BUF]) = {{{0}}}; // @th00b @th00f +GPE_BUFFER(gpe_bulk_core_data_t G_core_data[MAX_NUM_FW_CORES+NUM_CORE_DATA_DOUBLE_BUF+NUM_CORE_DATA_EMPTY_BUF]) = {{{0}}}; -//@01c Changed OCC core id numbering scheme //Global array of core data pointers gpe_bulk_core_data_t * G_core_data_ptrs[MAX_NUM_FW_CORES] = { &G_core_data[0], &G_core_data[1], &G_core_data[2], &G_core_data[3], &G_core_data[4], &G_core_data[5], &G_core_data[6], @@ -83,7 +48,6 @@ gpe_bulk_core_data_t * G_core_data_ptrs[MAX_NUM_FW_CORES] = { &G_core_data[0], & GPE_BUFFER(GpeGetCoreDataParms G_low_cores_data_parms); GPE_BUFFER(GpeGetCoreDataParms G_high_cores_data_parms); -//@01c Changed core data structure to fit the new core id numbering scheme //We will have separate bulk core data structure for low and high cores. //Global low and high cores structures used for task data pointers. bulk_core_data_task_t G_low_cores = { 0, 0, 5, &G_core_data[12] }; @@ -92,18 +56,15 @@ bulk_core_data_task_t G_high_cores = { 6, 6, 11, &G_core_data[13] }; //AMEC needs to know when data for a core has been collected. uint32_t G_updated_core_mask = 0; -// >> @sbpde // Mask to indicate when an empath error has been detected and empath data // should be ignored. Core bits are cleared when empath data is collected // without error. uint32_t G_empath_error_core_mask = 0; -// << @sbpde //Global G_present_cores is bitmask of all cores //(1 = present, 0 = not present. Core 0 has the most significant bit) uint32_t G_present_cores = 0; -//>@01a //Global double buffering for fast core data collection. GPE_BUFFER(gpe_fast_core_data_t G_fast_core_data[NUM_FAST_CORE_DATA_BUFF]) = {{0}}; @@ -115,7 +76,7 @@ GPE_BUFFER(gpe_fast_core_data_t * G_write_fast_core_data_ptr) = { &G_fast_core_d //Globals structure for gpe get chip data fast parms. //The Gpe parameter fields are set up each time before collect data start. -GPE_BUFFER(GpeGetChipDataFastParms G_chip_data_fast_parms); // @th008c +GPE_BUFFER(GpeGetChipDataFastParms G_chip_data_fast_parms); //Pore flex request for GPE job. The initialization //will be done one time during pore flex create. @@ -138,28 +99,18 @@ bool G_queue_not_idle_traced = FALSE; //Flag to keep tract of one time trace for GPE running case //for Fast core data. bool G_fast_core_queue_not_idle_traced = FALSE; -//<@01a -// >> @sb055 // Global to track the maximum time elapsed between pore flex schedules of // per core get_per_core_data tasks. The array is indexed by core number. uint32_t G_get_per_core_data_max_schedule_intervals[MAX_NUM_HW_CORES] = {0,}; -// << @sb055 -//************************************************************************* -// Function Prototypes -//************************************************************************* -//@rc001a - debug function declaration +// Declaration of debug functions #ifdef PROC_DEBUG void print_core_data_sensors(uint8_t core); void print_core_status(uint8_t core); void print_fast_core_data(void); #endif -//************************************************************************* -// Functions -//************************************************************************* - // Function Specification // // Name: task_core_data @@ -169,7 +120,6 @@ void print_fast_core_data(void); // individual task instances. The task function is the same but it needs // to gather data for different sets of cores. // -// Flow: 10/18/11 FN=task_core_data // // End Function Specification @@ -206,7 +156,6 @@ void task_core_data( task_t * i_task ) && ((CURRENT_TICK & (MAX_NUM_TICKS - 1)) != 0) ) { - //@rc001m PROC_DBG("Not collect data. Need to wait for tick.\n"); break; } @@ -223,7 +172,6 @@ void task_core_data( task_t * i_task ) //with the global one. The gpe routine will write new data into //a buffer that is not being accessed by the RTLoop code. - //@rc001m PROC_DBG( "Swap core_data_ptr [%x] with the global one\n", l_bulk_core_data_ptr->current_core ); @@ -241,9 +189,8 @@ void task_core_data( task_t * i_task ) //Core data has been collected so set the bit in global mask. //AMEC code will know which cores to update sensors for. AMEC is //responsible for clearing the bit later on. - G_updated_core_mask |= CORE0_PRESENT_MASK >> (l_bulk_core_data_ptr->current_core); // @th00b + G_updated_core_mask |= CORE0_PRESENT_MASK >> (l_bulk_core_data_ptr->current_core); - // >> @sbpde // Presumptively clear the empath error mask G_empath_error_core_mask &= ~(CORE0_PRESENT_MASK >> (l_bulk_core_data_ptr->current_core)); @@ -348,13 +295,12 @@ void task_core_data( task_t * i_task ) } } } - // << @sbpde // If the core is not present, then we need to point to the empty G_core_data // so that we don't use old/stale data from a leftover G_core_data - if( !CORE_PRESENT(l_bulk_core_data_ptr->current_core)) // @th00b + if( !CORE_PRESENT(l_bulk_core_data_ptr->current_core)) { - G_core_data_ptrs[l_bulk_core_data_ptr->current_core] = &G_core_data[14]; // @th00b + G_core_data_ptrs[l_bulk_core_data_ptr->current_core] = &G_core_data[14]; } //Update current core @@ -371,20 +317,19 @@ void task_core_data( task_t * i_task ) //be idle during this time it would have collected the data. if( CORE_PRESENT(l_bulk_core_data_ptr->current_core) ) { - //@rc001m PROC_DBG("Schedule PoreFlex OCC core [%x] or HW core [%x]\n", l_bulk_core_data_ptr->current_core, CORE_OCC2HW(l_bulk_core_data_ptr->current_core)); //1. Setup the get core data parms l_parms->config = - ((uint64_t) CORE0_PRESENT_MASK_GPE) >> (CORE_OCC2HW(l_bulk_core_data_ptr->current_core)); // @th008c + ((uint64_t) CORE0_PRESENT_MASK_GPE) >> (CORE_OCC2HW(l_bulk_core_data_ptr->current_core)); if( (cfam_id() == CFAM_CHIP_ID_MURANO_10) || (cfam_id() == CFAM_CHIP_ID_MURANO_11) || (cfam_id() == CFAM_CHIP_ID_MURANO_12) ) { // Due to HW243646 & HW243942 fallout, we will not be collecting EX core - // activity counter scoms until Murano DD1.3 @th032 + // activity counter scoms until Murano DD1.3 l_parms->select = GPE_GET_CORE_DATA_DTS_CPM | GPE_GET_CORE_DATA_PCB_SLAVE; } else @@ -394,7 +339,6 @@ void task_core_data( task_t * i_task ) l_parms->data = (uint32_t) l_bulk_core_data_ptr->core_data_ptr; - // >> @sb055 // Static array to record the last timestamp a get_per_core_data task was // scheduled for a core. static SsxTimebase L_last_get_per_core_data_scheduled_time[MAX_NUM_HW_CORES] = {0,}; @@ -443,7 +387,6 @@ void task_core_data( task_t * i_task ) //uint64_t l_dont_care = 0; //uint32_t core = CORE_CHIPLET_ADDRESS(PCBS_PMSTATEHISTOCC_REG, ???); //getscom(address???, &l_dont_care); - // << @sb055 //2. Port flex schedule gpe_get_per_core_data // Check pore_flex_schedule return code if error @@ -465,7 +408,7 @@ void task_core_data( task_t * i_task ) */ l_err = createErrl( PROC_TASK_CORE_DATA_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c + SSX_GENERIC_FAILURE, //reasoncode OCC_NO_EXTENDED_RC, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace //Trace Buf @@ -475,7 +418,7 @@ void task_core_data( task_t * i_task ) ); // commit error log - REQUEST_RESET(l_err); // @gm006 + REQUEST_RESET(l_err); break; } } @@ -493,8 +436,6 @@ void task_core_data( task_t * i_task ) // Description: Initialize structure for collecting core data. It // needs to be run in occ main and before RTLoop started. // -// Flow: 09-27-11 FN=proc_core_init -// // End Function Specification void proc_core_init( void ) @@ -509,7 +450,6 @@ void proc_core_init( void ) //are present and configured. We have a register that has information //of all cores that have been deconfigured in the chip so we need to read that. - //>@01a G_present_hw_cores = in32(PMC_CORE_DECONFIGURATION_REG); //Inverse the bitmask of the deconfigured register to get present @@ -519,15 +459,14 @@ void proc_core_init( void ) //Convert hardware core numering to OCC core numering. G_present_cores = ((G_present_hw_cores & LO_CORES_MASK) << 1) | ((G_present_hw_cores & HI_CORES_MASK) << 3); - //@rc001m + PROC_DBG("G_present_hw_cores =[%x] and G_present_cores =[%x] \n", G_present_hw_cores, G_present_cores); - //<@01a //Initializes low cores data PoreFlex object rc = pore_flex_create( &G_low_cores.gpe_req, //gpe_req for the task &G_pore_gpe0_queue, //queue - gpe_get_per_core_data, //entry point // @th00b + gpe_get_per_core_data, //entry point //parm for the task (uint32_t) &G_low_cores_data_parms, SSX_WAIT_FOREVER, // no timeout @@ -549,7 +488,7 @@ void proc_core_init( void ) */ l_err = createErrl( PROC_CORE_INIT_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c + SSX_GENERIC_FAILURE, //reasoncode ERC_LOW_CORE_PORE_FLEX_CREATE_FAILURE, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace //Trace Buf @@ -559,14 +498,14 @@ void proc_core_init( void ) ); // commit error log - REQUEST_RESET(l_err); // @gm006 + REQUEST_RESET(l_err); break; } //Initializes existing PoreFlex object for high cores data rc = pore_flex_create( &G_high_cores.gpe_req, //gpe_req for the task &G_pore_gpe0_queue, //queue - gpe_get_per_core_data, //entry point // @th00b + gpe_get_per_core_data, //entry point //parm for the task (uint32_t) &G_high_cores_data_parms, SSX_WAIT_FOREVER, //no timeout @@ -588,7 +527,7 @@ void proc_core_init( void ) */ l_err = createErrl( PROC_CORE_INIT_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c + SSX_GENERIC_FAILURE, //reasoncode ERC_HIGH_CORE_PORE_FLEX_CREATE_FAILURE, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace //Trace Buf @@ -598,11 +537,10 @@ void proc_core_init( void ) ); // commit error log - REQUEST_RESET(l_err); // @gm006 + REQUEST_RESET(l_err); break; } - //>@01a //Initializes PoreFlex object for fast core data rc = pore_flex_create( &G_fast_cores_req, //gpe_req for the task &G_pore_gpe0_queue, //queue @@ -628,7 +566,7 @@ void proc_core_init( void ) */ l_err = createErrl( PROC_CORE_INIT_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c + SSX_GENERIC_FAILURE, //reasoncode ERC_FAST_CORE_PORE_FLEX_CREATE_FAILURE, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace point //Trace Buf @@ -638,28 +576,24 @@ void proc_core_init( void ) ); // commit error log - REQUEST_RESET(l_err); // @gm006 + REQUEST_RESET(l_err); break; } - //<@01a } while(0); // Initialize the core data control structures at the same time - proc_core_data_control_init(); // @th010 + proc_core_data_control_init(); return; } -//>@01a // Function Specification // // Name: task_fast_core_data // // Description: Collect fast core data for all configured cores on every tick. // -// Flow: 10/18/11 FN=task_fast_core_data -// // End Function Specification void task_fast_core_data( task_t * i_task ) @@ -671,14 +605,14 @@ void task_fast_core_data( task_t * i_task ) gpe_fast_core_data_t * l_temp = NULL; uint32_t l_pres_hw_cores; - //poll the pmc deconfig register for newly deconfigured cores -- gm022 + //poll the pmc deconfig register for newly deconfigured cores l_pres_hw_cores = (~in32(PMC_CORE_DECONFIGURATION_REG)) & HW_CORES_MASK; if(l_pres_hw_cores != G_present_hw_cores) { TRAC_IMP("Present cores changed. old_hw_mask[0x%04x] new_hw_mask[0x%04x]", G_present_hw_cores, l_pres_hw_cores); - //update our global core presence masks -- gm022 + //update our global core presence masks G_present_hw_cores = l_pres_hw_cores; G_present_cores = ((l_pres_hw_cores & LO_CORES_MASK) << 1) | ((l_pres_hw_cores & HI_CORES_MASK) << 3); @@ -705,7 +639,6 @@ void task_fast_core_data( task_t * i_task ) //If the previous GPE request succeeded then swap the //G_read_fast_core_data_ptr with the G_write_fast_core_data_ptr. - //@rc001m PROC_DBG("Fast core data GPE request has been succeeded.\n"); #ifdef PROC_DEBUG @@ -718,8 +651,8 @@ void task_fast_core_data( task_t * i_task ) } //Setup the get fast core data parms - G_chip_data_fast_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32); // @th008c - G_chip_data_fast_parms.select = GPE_GET_CORE_DATA_FAST_FREQ_TARGET; // @th008c + G_chip_data_fast_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32); + G_chip_data_fast_parms.select = GPE_GET_CORE_DATA_FAST_FREQ_TARGET; G_chip_data_fast_parms.data = (uint32_t) G_write_fast_core_data_ptr; //Port flex schedule gpe_get_core_data_fast @@ -742,7 +675,7 @@ void task_fast_core_data( task_t * i_task ) */ l_err = createErrl( PROC_TASK_FAST_CORE_DATA_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c + SSX_GENERIC_FAILURE, //reasoncode OCC_NO_EXTENDED_RC, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace point //Trace Buf @@ -751,7 +684,7 @@ void task_fast_core_data( task_t * i_task ) 0 ); //userdata2 // commit error log - REQUEST_RESET(l_err); // @gm006 + REQUEST_RESET(l_err); break; } } while(0); @@ -767,8 +700,6 @@ void task_fast_core_data( task_t * i_task ) // the core associated with the specified OCC core id. Returns // NULL for core ID outside the range of 0 to 11. // -// Flow: FN=None -// // End Function Specification gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id ) { @@ -795,8 +726,6 @@ gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id // // Description: Returns a pointer to the most up-to-date fast core data // -// Flow: FN=None -// // End Function Specification gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void ) { @@ -805,9 +734,6 @@ gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void ) return G_read_fast_core_data_ptr; } -//<@01a - - #ifdef PROC_DEBUG // Function Specification @@ -816,8 +742,6 @@ gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void ) // // Description: Print out sensors data of a specified core in the chip // -// Flow: FN=None -// // End Function Specification void print_core_data_sensors(uint8_t core) @@ -826,22 +750,20 @@ void print_core_data_sensors(uint8_t core) if( l_core_data != NULL ) { - //@rc001m - PROC_DBG("\n-------------------------------\n"); - PROC_DBG("Core [%x] Sensors Data \n", core); - // @th008 -- commented these out b/c they take too long to run in task. - // -- maybe with some creative coding they could be moved to an applet - //dumpHexString(&l_core_data->sensors_tod, sizeof(l_core_data->sensors_tod), "Sensor TOD"); + PROC_DBG("\n-------------------------------\n"); + PROC_DBG("Core [%x] Sensors Data \n", core); + // TODO: Commented these out b/c they take too long to run in task. + // Consider moving this to an applet + //dumpHexString(&l_core_data->sensors_tod, sizeof(l_core_data->sensors_tod), "Sensor TOD"); //dumpHexString(&l_core_data->sensors_v0, sizeof(l_core_data->sensors_v0), "Sensor VO"); - //dumpHexString(&l_core_data->sensors_v1, sizeof(l_core_data->sensors_v1), "Sensor V1"); - //dumpHexString(&l_core_data->sensors_v8, sizeof(l_core_data->sensors_v8), "Sensor V8"); - //dumpHexString(&l_core_data->sensors_v9, sizeof(l_core_data->sensors_v9), "Sensor V9"); - PROC_DBG("\n"); + //dumpHexString(&l_core_data->sensors_v1, sizeof(l_core_data->sensors_v1), "Sensor V1"); + //dumpHexString(&l_core_data->sensors_v8, sizeof(l_core_data->sensors_v8), "Sensor V8"); + //dumpHexString(&l_core_data->sensors_v9, sizeof(l_core_data->sensors_v9), "Sensor V9"); + PROC_DBG("\n"); } else { - //@rc001m - PROC_DBG("\n G_core_data_ptrs[%x] is NULL. This should not happen.\n", core); + PROC_DBG("\n G_core_data_ptrs[%x] is NULL. This should not happen.\n", core); } return; } @@ -852,8 +774,6 @@ void print_core_data_sensors(uint8_t core) // // Description: Print out information of a specified core in the chip // -// Flow: FN=None -// // End Function Specification void print_core_status(uint8_t core) @@ -862,41 +782,36 @@ void print_core_status(uint8_t core) if( l_core_data != NULL ) { - //@rc001m PROC_DBG("\n-------------------------\n"); PROC_DBG("Core [%x] status \n", core); - // @th008 -- commented these out b/c they take too long to run in task. - // -- maybe with some creative coding they could be moved to an applet + // TODO: Commented these out b/c they take too long to run in task. + // Consider moving this to an applet //dumpHexString(&l_core_data->core_tod, sizeof(l_core_data->core_tod), "Core TOD"); //dumpHexString(&l_core_data->core_raw_cycles, sizeof(l_core_data->core_raw_cycles), "Core Raw Cycles"); //dumpHexString(&l_core_data->core_run_cycles, sizeof(l_core_data->core_run_cycles), "Run Cycles"); //dumpHexString(&l_core_data->core_dispatch, sizeof(l_core_data->core_dispatch), "Core Dispatch"); //dumpHexString(&l_core_data->core_completion, sizeof(l_core_data->core_completion), "Core Completion"); - //dumpHexString(&l_core_data->core_workrate, sizeof(l_core_data->core_workrate), "Core Workrate"); - //dumpHexString(&l_core_data->core_spurr, sizeof(l_core_data->core_spurr), "Core Spurr"); - //dumpHexString(&l_core_data->core_mem_hler_a, sizeof(l_core_data->core_mem_hler_a), "Mem A"); - //dumpHexString(&l_core_data->core_mem_hler_b, sizeof(l_core_data->core_mem_hler_b), "Mem B"); - //dumpHexString(&l_core_data->mem_tod, sizeof(l_core_data->mem_tod), "Mem TOD"); - //dumpHexString(&l_core_data->mem_raw_cycles, sizeof(l_core_data->mem_raw_cycles), "Mem Raw Cycles"); + //dumpHexString(&l_core_data->core_workrate, sizeof(l_core_data->core_workrate), "Core Workrate"); + //dumpHexString(&l_core_data->core_spurr, sizeof(l_core_data->core_spurr), "Core Spurr"); + //dumpHexString(&l_core_data->core_mem_hler_a, sizeof(l_core_data->core_mem_hler_a), "Mem A"); + //dumpHexString(&l_core_data->core_mem_hler_b, sizeof(l_core_data->core_mem_hler_b), "Mem B"); + //dumpHexString(&l_core_data->mem_tod, sizeof(l_core_data->mem_tod), "Mem TOD"); + //dumpHexString(&l_core_data->mem_raw_cycles, sizeof(l_core_data->mem_raw_cycles), "Mem Raw Cycles"); PROC_DBG("\n"); } else { - //@rc001m PROC_DBG("\n G_core_data_ptrs[%x] is NULL. This should not happen.\n", core); } return; } -//>@01a // Function Specification // // Name: print_fast_core_data // // Description: Print out fast core data of the chip // -// Flow: FN=None -// // End Function Specification void print_fast_core_data(void) @@ -905,21 +820,18 @@ void print_fast_core_data(void) if( l_fast_core_data != NULL ) { - //@rc001m PROC_DBG("\n---------------------------\n"); - // @th008 -- commented these out b/c they take too long to run in task. - // -- maybe with some creative coding they could be moved to an applet + // TODO: Commented these out b/c they take too long to run in task. + // Consider moving this to an applet //dumpHexString(&l_fast_core_data->tod, sizeof(l_fast_core_data->tod), "Fast Core Data TOD"); - //dumpHexString(&l_fast_core_data->core_data, sizeof(fast_core_data_t) * MAX_NUM_HW_CORES, "Fast Core Data"); + //dumpHexString(&l_fast_core_data->core_data, sizeof(fast_core_data_t) * MAX_NUM_HW_CORES, "Fast Core Data"); PROC_DBG("\n"); } else { - //@rc001m PROC_DBG("\n G_read_fast_core_data_ptr is NULL. This should not happen.\n"); } return; } -//<@01a #endif diff --git a/src/occ/proc/proc_data.h b/src/occ/proc/proc_data.h index 05f6913..103725c 100755 --- a/src/occ/proc/proc_data.h +++ b/src/occ/proc/proc_data.h @@ -1,57 +1,36 @@ -/****************************************************************************** -// @file proc_data.h -// @brief Data codes for proc component. -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_data_h proc_data.h - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * nguyenp 09/27/2011 Created - * nguyenp 09/27/2011 Added bulk core data and proc core - * initilization code. - * @01 nguyenp 10/19/2011 Added fast core data code. - * Added new interfaces to gain access to - * bulk core and fast core data. - * Added macro to translate occ core id - * to hardware core id and vice versa. - * @rc001 rickylie 12/30/2011 Moved debug trace defines to trac.h - * remove print_core_data_sensors - * remove print_core_status - * remove print_fast_core_data - * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments - * @th00b thallet 02/28/12 Added a couple enums,defines,macros - * @pb00E pbavari 03/11/2012 Added correct include file - * @th00f thallet 06/27/2012 Change to use Core Data struct as provided by HW team - * @sbpde 922027 sbroyles 04/04/2014 Add empath error core mask - * - * @endverbatim - * - *///*************************************************************************/ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_data.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef _PROC_DATA_H #define _PROC_DATA_H -//************************************************************************* -// Includes -//************************************************************************* -//@pb00Ec - changed from common.h to occ_common.h for ODE support #include <occ_common.h> #include <ssx.h> #include "rtls.h" #include "gpe_data.h" -//************************************************************************* -// Externs -//************************************************************************* - -//************************************************************************* -// Macros -//************************************************************************* -//>@01a //Returns 0 if the specified core is not present. Otherwise, returns none-zero. #define CORE_PRESENT(occ_core_id) \ ((CORE0_PRESENT_MASK >> occ_core_id) & G_present_cores) @@ -69,14 +48,10 @@ //is invalid then returns unconfigured core 16. #define CORE_HW2OCC(hw_core_id) \ ((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16) -//<@01a -//************************************************************************* -// Defines/Enums -//************************************************************************* #define ALL_CORES_MASK 0xffff0000 #define CORE0_PRESENT_MASK 0x80000000ul -#define CORE0_PRESENT_MASK_GPE 0x8000000000000000ull // @th008a +#define CORE0_PRESENT_MASK_GPE 0x8000000000000000ull #define MAX_NUM_HW_CORES 16 #define MAX_NUM_FW_CORES 12 @@ -84,16 +59,14 @@ #define THREADS_PER_CORE 8 #define MAX_MEM_PARTS 4 -//>@01a #define NUM_FAST_CORE_DATA_BUFF 2 -#define NUM_CORE_DATA_BUFF 7 // @th00b -#define NUM_CORE_DATA_DOUBLE_BUF 2 // @th00b -#define NUM_CORE_DATA_EMPTY_BUF 1 // @th00b +#define NUM_CORE_DATA_BUFF 7 +#define NUM_CORE_DATA_DOUBLE_BUF 2 +#define NUM_CORE_DATA_EMPTY_BUF 1 #define LO_CORES_MASK 0x7e000000 #define HI_CORES_MASK 0x007e0000 #define HW_CORES_MASK 0xffff0000 -//<@01a enum eOccProcCores { @@ -109,13 +82,9 @@ enum eOccProcCores CORE_9 = 9, CORE_10 = 10, CORE_11 = 11, -}; // @th00b - -//************************************************************************* -// Structures -//************************************************************************* +}; -typedef CoreData gpe_bulk_core_data_t; // @th00f +typedef CoreData gpe_bulk_core_data_t; //Processor data collect structures used for task data pointers //gpe_req.request.parameter points to GpeGetCoreDataParms @@ -128,7 +97,6 @@ struct bulk_core_data_task { } __attribute__ ((__packed__)); typedef struct bulk_core_data_task bulk_core_data_task_t; -//>@01a //Only PCBS_LOCAL_PSTATE_FREQ_TARGET_STATUS_REG register is being //collected at this time. Other register will be added when needed. struct fast_core_data { @@ -143,11 +111,6 @@ struct gpe_fast_core_data { fast_core_data_t core_data[MAX_NUM_HW_CORES]; } __attribute__ ((__packed__)); typedef struct gpe_fast_core_data gpe_fast_core_data_t; -//<@01a - -//************************************************************************* -// Globals -//************************************************************************* //Global low and high cores structures used for task data pointers extern bulk_core_data_task_t G_low_cores; @@ -156,27 +119,17 @@ extern bulk_core_data_task_t G_high_cores; //Global G_present_cores is bitmask of all OCC core numbering extern uint32_t G_present_cores; -//>@01a //Global G_present_hw_cores is bitmask of all hardware cores extern uint32_t G_present_hw_cores; extern uint8_t G_occ2hw_core_id[MAX_NUM_HW_CORES]; extern uint8_t G_hw2occ_core_id[MAX_NUM_HW_CORES]; -//<@01a //AMEC needs to know when data for a core has been collected. extern uint32_t G_updated_core_mask; -// >> @sbpde // External reference to empath error mask extern uint32_t G_empath_error_core_mask; -// << @sbpde - -//************************************************************************* -// Function Prototypes -//************************************************************************* -/*----------------------------------------------------------------------------*/ -/* Macros */ -/*----------------------------------------------------------------------------*/ + //Returns 0 if the specified core is not present. Otherwise, returns none-zero. #define CORE_PRESENT(occ_core_id) \ ((CORE0_PRESENT_MASK >> occ_core_id) & G_present_cores) @@ -189,11 +142,9 @@ extern uint32_t G_empath_error_core_mask; #define CLEAR_CORE_UPDATED(occ_core_id) \ G_updated_core_mask &= ~(CORE0_PRESENT_MASK >> occ_core_id) -// >> @sbpde // Evaluates to true if an empath collection error has occurred on a core #define CORE_EMPATH_ERROR(occ_core_id) \ ((CORE0_PRESENT_MASK >> occ_core_id) & G_empath_error_core_mask) -// << @sbpde //Takes an OCC core id and converts it to a core id that //can be used by the hardware. The caller needs to send in @@ -208,48 +159,21 @@ extern uint32_t G_empath_error_core_mask; //is invalid then returns unconfigured core 16. #define CORE_HW2OCC(hw_core_id) \ ((hw_core_id <= 15) ? G_hw2occ_core_id[hw_core_id] : 16) -//<@01a -/*----------------------------------------------------------------------------*/ -/* Collect bulk core data function */ -/*----------------------------------------------------------------------------*/ //Collect bulk core data for all cores in specified range void task_core_data( task_t * i_task ); -/*----------------------------------------------------------------------------*/ -/* proc core initialization function */ -/*----------------------------------------------------------------------------*/ //Initialize structures for collecting core data. void proc_core_init( void ) INIT_SECTION; -//>@01a -/*----------------------------------------------------------------------------*/ -/* Collect fast core data function */ -/*----------------------------------------------------------------------------*/ //Collect fast core data for all configured cores on every tick void task_fast_core_data( task_t * i_task ); -/*----------------------------------------------------------------------------*/ -/* Get bulk core data pointer */ -/*----------------------------------------------------------------------------*/ //Returns a pointer to the most up-to-date bulk core data for the core //associated with the specified OCC core id. gpe_bulk_core_data_t * proc_get_bulk_core_data_ptr( const uint8_t i_occ_core_id ); -/*----------------------------------------------------------------------------*/ -/* Get fast core data pointer */ -/*----------------------------------------------------------------------------*/ //Returns a pointer to the most up-to-date fast core data gpe_fast_core_data_t * proc_get_fast_core_data_ptr( void ); -//<@01a - -/*----------------------------------------------------------------------------*/ -/* Debug */ -/*----------------------------------------------------------------------------*/ -//@rc001 - -//************************************************************************* -// Functions -//************************************************************************* #endif //_PROC_DATA_H diff --git a/src/occ/proc/proc_data_control.c b/src/occ/proc/proc_data_control.c index f87625f..2b83c88 100755 --- a/src/occ/proc/proc_data_control.c +++ b/src/occ/proc/proc_data_control.c @@ -1,36 +1,35 @@ -/****************************************************************************** -// @file proc_data_control.c -// @brief Data codes for proc component. -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_data_control_c proc_data_control.c - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * @th010 thallet 06/27/2012 Created - * @th014 thallet 08/02/2012 Temporary Control Data Fix & TODO flags added - * @th015 thallet 08/03/2012 Set core Pstates function - * @gm006 SW224414 milesg 09/16/2013 Reset and FFDC improvements - * @gm008 SW226989 milesg 09/30/2013 Sapphire initial support - * @gm025 915973 milesg 02/14/2014 Full support for sapphire (KVM) mode - * - * @endverbatim - * - *///*************************************************************************/ - -//************************************************************************* -// Includes -//************************************************************************* +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_data_control.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + #include "proc_data.h" -#include "pgp_async.h" -#include "threadSch.h" +#include "pgp_async.h" +#include "threadSch.h" #include "pmc_register_addresses.h" #include "proc_data_service_codes.h" -#include "occ_service_codes.h" -#include "errl.h" +#include "occ_service_codes.h" +#include "errl.h" #include "trac.h" #include "rtls.h" #include "apss.h" @@ -38,46 +37,22 @@ #include "gpe_control.h" #include "occ_sys_config.h" -//************************************************************************* -// Externs -//************************************************************************* - -//************************************************************************* -// Macros -//************************************************************************* - -//************************************************************************* -// Defines/Enums -//************************************************************************* - -//************************************************************************* -// Structures -//************************************************************************* - -//************************************************************************* -// Globals -//************************************************************************* - -// Pore flex request for GPE job. The initialization will be done one time +// Pore flex request for GPE job. The initialization will be done one time // during pore flex create. -PoreFlex G_core_data_control_req; +PoreFlex G_core_data_control_req; // Global double buffering for core data control -GPE_BUFFER(PcbsPstateRegs G_core_data_control_a[MAX_NUM_HW_CORES]) = {{{0}}}; -GPE_BUFFER(PcbsPstateRegs G_core_data_control_b[MAX_NUM_HW_CORES]) = {{{0}}}; +GPE_BUFFER(PcbsPstateRegs G_core_data_control_a[MAX_NUM_HW_CORES]) = {{{0}}}; +GPE_BUFFER(PcbsPstateRegs G_core_data_control_b[MAX_NUM_HW_CORES]) = {{{0}}}; // Pointer to the core data control that will be used by GPE engine. -GPE_BUFFER(PcbsPstateRegs * G_core_data_control_gpewrite_ptr) = { &G_core_data_control_a[0] }; +GPE_BUFFER(PcbsPstateRegs * G_core_data_control_gpewrite_ptr) = { &G_core_data_control_a[0] }; // Pointer to the core data control that will be written to by the OCC FW. -GPE_BUFFER(PcbsPstateRegs * G_core_data_control_occwrite_ptr) = { &G_core_data_control_b[0] }; - -// The Gpe parameter fields are set up each time before the GPE starts. -GPE_BUFFER(GpeSetPstatesParms G_core_data_control_parms); +GPE_BUFFER(PcbsPstateRegs * G_core_data_control_occwrite_ptr) = { &G_core_data_control_b[0] }; -//************************************************************************* -// Functions -//************************************************************************* +// The Gpe parameter fields are set up each time before the GPE starts. +GPE_BUFFER(GpeSetPstatesParms G_core_data_control_parms); // Function Specification // @@ -86,8 +61,6 @@ GPE_BUFFER(GpeSetPstatesParms G_core_data_control_parms); // Description: Function to demonstrate setting Pstates to all cores // Should only be run from RTL // -// Flow: --/--/-- FN= -// // End Function Specification void proc_set_pstate_all(Pstate i_pstate) { @@ -112,18 +85,15 @@ void proc_set_pstate_all(Pstate i_pstate) // Description: Function to demonstrate setting Pstates to all cores // Should only be run from RTL // -// Flow: --/--/-- FN= -// // End Function Specification void proc_set_core_pstate(Pstate i_pstate, uint8_t i_core) -{ +{ set_chiplet_pstate(G_core_data_control_occwrite_ptr, CORE_OCC2HW(i_core), i_pstate, i_pstate); } -// gm025 // Function Specification // // Name: proc_set_core_bounds @@ -131,11 +101,9 @@ void proc_set_core_pstate(Pstate i_pstate, uint8_t i_core) // Description: Function to set core pmin/pmax // Should only be run from RTL // -// Flow: --/--/-- FN= -// // End Function Specification void proc_set_core_bounds(Pstate i_pmin, Pstate i_pmax, uint8_t i_core) -{ +{ Pstate l_pmax; uint8_t l_hw_core = CORE_OCC2HW(i_core); @@ -164,14 +132,12 @@ void proc_set_core_bounds(Pstate i_pmin, Pstate i_pmax, uint8_t i_core) // // Description: Initializations needed for core data control task // -// Flow: --/--/-- FN= -// // End Function Specification void proc_core_data_control_init( void ) { errlHndl_t l_err = NULL; //Error handler tracDesc_t l_trace = NULL; //Temporary trace descriptor - int rc = 0; //Return code + int rc = 0; //Return code do { @@ -196,11 +162,11 @@ void proc_core_data_control_init( void ) * @userdata1 pore_flex_create return code * @userdata4 ERC_PROC_CONTROL_INIT_FAILURE * @devdesc Failure to create poreflex object - */ + */ l_err = createErrl( PROC_CORE_INIT_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode - ERC_PROC_CONTROL_INIT_FAILURE, //Extended reason code + SSX_GENERIC_FAILURE, //reasoncode + ERC_PROC_CONTROL_INIT_FAILURE, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace //Trace Buf DEFAULT_TRACE_SIZE, //Trace Size @@ -222,8 +188,6 @@ void proc_core_data_control_init( void ) // // Description: Control core actuation for all configured cores on every tick. // -// Flow: 07/02/12 FN=task_core_data_control -// // End Function Specification void task_core_data_control( task_t * i_task ) { @@ -238,13 +202,6 @@ void task_core_data_control( task_t * i_task ) //Check to see if the previous GPE request still running if( !(async_request_is_idle(&G_core_data_control_req.request)) ) { - // Trace 1 time - This should not happen - - //if( !G_fast_core_queue_not_idle_traced ) - //{ - // TRAC_ERR("GPE is still running \n"); - // G_fast_core_queue_not_idle_traced = TRUE; - //} break; } @@ -254,16 +211,12 @@ void task_core_data_control( task_t * i_task ) //If the previous GPE request succeeded then swap the //gpewrite ptr with the occwrite ptr. l_temp = G_core_data_control_occwrite_ptr; - // TODO: For now, set these ptrs equal to each other - // This data is not thread-safe/interrupt safe - // but will need to fix this later. - //G_core_data_control_occwrite_ptr = G_core_data_control_gpewrite_ptr; // TODO: @th014 G_core_data_control_gpewrite_ptr = l_temp; } //Setup the core data control parms G_core_data_control_parms.config = (uint64_t) (((uint64_t) G_present_hw_cores) << 32); - if(G_sysConfigData.system_type.kvm) //gm025 + if(G_sysConfigData.system_type.kvm) { //Set the chiplet bounds (pmax/pmin) only on sapphire G_core_data_control_parms.select = GPE_SET_PSTATES_PMBR; @@ -288,11 +241,11 @@ void task_core_data_control( task_t * i_task ) * @userdata1 pore_flex_schedule return code * @userdata4 ERC_PROC_CONTROL_TASK_FAILURE * @devdesc Failure to schedule poreflex object - */ + */ l_err = createErrl( PROC_TASK_CORE_DATA_MOD, //modId - SSX_GENERIC_FAILURE, //reasoncode - ERC_PROC_CONTROL_TASK_FAILURE, //Extended reason code + SSX_GENERIC_FAILURE, //reasoncode + ERC_PROC_CONTROL_TASK_FAILURE, //Extended reason code ERRL_SEV_PREDICTIVE, //Severity l_trace, //TODO: create l_trace //Trace Buf DEFAULT_TRACE_SIZE, //Trace Size @@ -301,12 +254,10 @@ void task_core_data_control( task_t * i_task ) ); // commit error log - REQUEST_RESET(l_err); //@gm006 + REQUEST_RESET(l_err); break; } } while(0); return; } - - diff --git a/src/occ/proc/proc_data_control.h b/src/occ/proc/proc_data_control.h index cb4d0d1..49a1fcd 100755 --- a/src/occ/proc/proc_data_control.h +++ b/src/occ/proc/proc_data_control.h @@ -1,42 +1,36 @@ -/****************************************************************************** -// @file proc_data_control.h -// @brief Data codes for proc component. -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_data_h proc_data.h - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * @th010 thallet 07/11/2012 Created - * @th015 thallet 08/03/2012 Function to set core Pstates - * @gm025 915973 milesg 02/14/2014 Full support for sapphire (KVM) mode - * - * @endverbatim - * - *///*************************************************************************/ - +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_data_control.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + #ifndef _PROC_DATA_CONTROL_H #define _PROC_DATA_CONTROL_H -//************************************************************************* -// Includes -//************************************************************************* #include <occ_common.h> #include <ssx.h> -#include "rtls.h" +#include "rtls.h" #include "gpe_control.h" -//************************************************************************* -// Externs -//************************************************************************* - -//************************************************************************* -// Macros -//************************************************************************* - // Initialze the structures used by the GPE void proc_core_data_control_init( void ); diff --git a/src/occ/proc/proc_data_service_codes.h b/src/occ/proc/proc_data_service_codes.h index 3cf8eb4..608e860 100755 --- a/src/occ/proc/proc_data_service_codes.h +++ b/src/occ/proc/proc_data_service_codes.h @@ -1,70 +1,41 @@ -/****************************************************************************** -// @file proc_data_service_codes.h -// @brief Error codes for proc component. -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_data_service_codes_h proc_data_service_codes.h - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * nguyenp 09/23/2011 Created - * @01 nguyenp 10/19/2011 Added task fast core data module id. - * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments - * @pb00E pbavari 03/11/2012 Added correct include file - * @th032 thallet 04/26/2013 Tuleta HW Bringup - * @gm006 SW224414 milesg 09/16/2013 Reset and FFDC improvements - * @gm025 915973 milesg 02/14/2014 Full support for sapphire (KVM) mode - * - * @endverbatim - * - *///*************************************************************************/ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_data_service_codes.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef _PROC_DATA_SERVICE_CODES_H_ #define _PROC_DATA_SERVICE_CODES_H_ -//************************************************************************* -// Includes -//************************************************************************* #include <comp_ids.h> -//************************************************************************* -// Externs -//************************************************************************* - -//************************************************************************* -// Macros -//************************************************************************* - -//************************************************************************* -// Defines/Enums -//************************************************************************* enum procModuleId { - PROC_TASK_CORE_DATA_MOD = PROC_COMP_ID | 0x00, - PROC_CORE_INIT_MOD = PROC_COMP_ID | 0x01, - PROC_TASK_FAST_CORE_DATA_MOD = PROC_COMP_ID | 0x02, //@01a + PROC_TASK_CORE_DATA_MOD = PROC_COMP_ID | 0x00, + PROC_CORE_INIT_MOD = PROC_COMP_ID | 0x01, + PROC_TASK_FAST_CORE_DATA_MOD = PROC_COMP_ID | 0x02, PROC_GPST_INIT_FAILURE_MOD = PROC_COMP_ID | 0x03, - PROC_ENABLE_PSTATES_SMH_MOD = PROC_COMP_ID | 0x04, //@gm006 - PROC_PSTATE_KVM_SETUP_MOD = PROC_COMP_ID | 0x05, //@gm025 + PROC_ENABLE_PSTATES_SMH_MOD = PROC_COMP_ID | 0x04, + PROC_PSTATE_KVM_SETUP_MOD = PROC_COMP_ID | 0x05, }; -//************************************************************************* -// Structures -//************************************************************************* - -//************************************************************************* -// Globals -//************************************************************************* - -//************************************************************************* -// Function Prototypes -//************************************************************************* - -//************************************************************************* -// Functions -//************************************************************************* - #endif /* #ifndef _PROC_DATA_SERVICE_CODES_H_ */ diff --git a/src/occ/proc/proc_pstate.c b/src/occ/proc/proc_pstate.c index b5c4376..5cf4860 100755 --- a/src/occ/proc/proc_pstate.c +++ b/src/occ/proc/proc_pstate.c @@ -1,50 +1,34 @@ -/****************************************************************************** -// @file proc_pstate.c -// @brief OCC Handling of Pstates -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_pstate_c proc_pstate.c - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * @th010 thallet 07/10/2012 Created - * @th014 thallet 08/02/2012 Updated PstateSS & TODO flags added - * @th015 thallet 08/03/2012 Bounds checking on freq2pstate - * @th025 857856 thallet 10/16/2012 Dcom Master Slave SMS part 2 - * @th032 thallet 04/26/2013 Tuleta HW Bringup Changes - * @th035 881654 thallet 05/06/2013 Tuleta Bringup Pstate Fixes - * @th036 881677 thallet 05/07/2013 Cleanup - * @th040 887069 thalllet 06/11/2013 Support Nom & FFO Freq Setting for Mnfg - * @fk001 879727 fmkassem 04/16/2013 PCAP support. - * @ly009 895318 lychen 08/13/2013 OCC-Sapphire shared memory interface - * @gm006 SW224414 milesg 09/16/2013 Reset and FFDC improvements - * @gm011 903410 milesg 10/22/2013 Fail on murano dd10 or dd11 chips - * @ly010 908832 lychen 12/09/2013 Sapphire update status for reset - * @gm022 908890 milesg 01/23/2014 Fixed pstate table traces - * @gm025 915973 milesg 02/14/2014 Full support for sapphire (KVM) mode - * @wb001 919163 wilbryan 03/06/2014 Updating error call outs, descriptions, and severities - * @wb003 920760 wilbryan 03/25/2014 Update SRCs to match TPMD SRCs - * @gm033 920448 milesg 03/26/2014 use getscom/putscom ffdc wrapper - * @gs032 925755 gjsilva 05/07/2014 Optimize freq2pstate function - * @gs033 929049 gjsilva 06/13/2014 Fix computation of pstate - * @gs044 943766 gjsilva 11/03/2014 Clear bit 11 of PCBS_PMGP1_REG during KVM setup - * - * @endverbatim - * - *///*************************************************************************/ - -//************************************************************************* -// Includes -//************************************************************************* +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_pstate.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + #include "ssx.h" -#include "proc_data_service_codes.h" -#include "errl.h" +#include "proc_data_service_codes.h" +#include "errl.h" #include "trac.h" #include "rtls.h" -#include "dcom.h" +#include "dcom.h" #include "occ_common.h" #include "state.h" #include "cmdh_fsp_cmds.h" @@ -56,11 +40,8 @@ #include "proc_pstate.h" #include "scom.h" -//************************************************************************* -// Defines/Enums -//************************************************************************* // GPSM DCM Synchronization States -typedef enum +typedef enum { PROC_GPSM_SYNC_NO_PSTATE_TABLE = 0, PROC_GPSM_SYNC_PSTATE_TABLE_INSTALLED = 1, @@ -74,17 +55,7 @@ typedef enum } eProcGpsmDcmSyncStates; -//************************************************************************* -// Macros -//************************************************************************* - - - -//************************************************************************* -// Globals -//************************************************************************* - -// Instance of the PState Table in OCC SRAM. Should be placed in RO section +// Instance of the PState Table in OCC SRAM. Should be placed in RO section // so that OCC FW can't corrupt it GLOBAL_PSTATE_TABLE(G_global_pstate_table); @@ -104,37 +75,25 @@ int8_t G_proc_gpst_pmax = 0; bool G_isDcm = FALSE; // Used for Sapphire -DMA_BUFFER( sapphire_table_t G_sapphire_table ) = {{0}}; // @ly009a +DMA_BUFFER( sapphire_table_t G_sapphire_table ) = {{0}}; //KVM throttle reason coming from the frequency voting box. extern uint8_t G_amec_kvm_throt_reason; -//************************************************************************* -// Forward Declarations -//************************************************************************* - // Set DCM Sync State void proc_gpsm_dcm_sync_set_state(eProcGpsmDcmSyncStates i_dcm_sync_state); // Tracing out pstate table when it gets installed void proc_trace_pstate_table_quick(void); -//************************************************************************* -// Functions -//************************************************************************* - - // Function Specification // // Name: proc_is_hwpstate_enabled // -// Description: Checks DCM Master (or SCM) state to see if Pstate HW Mode -// is enabled. We can check the DCM master state, since DCM -// slave also knows the master and DCM master can't be in this +// Description: Checks DCM Master (or SCM) state to see if Pstate HW Mode +// is enabled. We can check the DCM master state, since DCM +// slave also knows the master and DCM master can't be in this // state if DCM slave isn't in HW mode -// -// -// Flow: xx/xx/xx FN= // // End Function Specification bool proc_is_hwpstate_enabled(void) @@ -147,12 +106,10 @@ bool proc_is_hwpstate_enabled(void) // // Name: proc_gpsm_dcm_sync_update_from_mbox // -// Description: Updates the global variable used for DCM sync based on the +// Description: Updates the global variable used for DCM sync based on the // data that was received via the master/slave mailbox. -// -// Thread: Interrupt; Callback when Slave Inbox is received // -// Flow: xx/xx/xx FN= +// Thread: Interrupt; Callback when Slave Inbox is received // // End Function Specification void proc_gpsm_dcm_sync_update_from_mbox(proc_gpsm_dcm_sync_occfw_t * i_dcm_sync_state) @@ -175,11 +132,6 @@ void proc_gpsm_dcm_sync_update_from_mbox(proc_gpsm_dcm_sync_occfw_t * i_dcm_sync // Name: proc_gpsm_dcm_sync_get_state // // Description: Return the global variable used for DCM sync -// -// -// -// -// Flow: xx/xx/xx FN= // // End Function Specification inline proc_gpsm_dcm_sync_occfw_t proc_gpsm_dcm_sync_get_state(void) @@ -193,16 +145,11 @@ inline proc_gpsm_dcm_sync_occfw_t proc_gpsm_dcm_sync_get_state(void) // Name: proc_is_dcm // // Description: Return if we are a DCM or not -// -// -// -// -// Flow: xx/xx/xx FN= // // End Function Specification inline bool proc_is_dcm(void) { - return G_isDcm; + return G_isDcm; } @@ -211,11 +158,8 @@ inline bool proc_is_dcm(void) // Name: proc_gpsm_dcm_sync_set_state // // Description: Set the state of global variable used for DCM sync -// Differnt nybble will get set depending on if we are +// Differnt nybble will get set depending on if we are // DCM Master or DCM Slave -// -// -// Flow: xx/xx/xx FN= // // End Function Specification inline void proc_gpsm_dcm_sync_set_state(eProcGpsmDcmSyncStates i_dcm_sync_state) @@ -227,7 +171,7 @@ inline void proc_gpsm_dcm_sync_set_state(eProcGpsmDcmSyncStates i_dcm_sync_state else { G_proc_dcm_sync_state.sync_state_slave = i_dcm_sync_state; - } + } } @@ -236,9 +180,6 @@ inline void proc_gpsm_dcm_sync_set_state(eProcGpsmDcmSyncStates i_dcm_sync_state // Name: proc_gpsm_dcm_sync_get_state // // Description: Return the state of global variable used for DCM sync -// -// -// Flow: xx/xx/xx FN= // // End Function Specification eProcGpsmDcmSyncStates proc_gpsm_dcm_sync_get_my_state(void) @@ -250,20 +191,17 @@ eProcGpsmDcmSyncStates proc_gpsm_dcm_sync_get_my_state(void) else { return G_proc_dcm_sync_state.sync_state_slave; - } -} // Added @th025 + } +} // Function Specification // // Name: proc_trace_pstate_table_quick // -// Description: Debug Function to Print portion of Pstate Table +// Description: Debug Function to Print portion of Pstate Table // Eventually, this should trace key elements of Pstate // table to Trace Buffer. -// -// -// Flow: xx/xx/xx FN= // // End Function Specification void proc_trace_pstate_table_quick(void) @@ -271,25 +209,25 @@ void proc_trace_pstate_table_quick(void) GlobalPstateTable * l_gpst_ptr = NULL; l_gpst_ptr = gpsm_gpst(); - // Check the pointer since it may not have been installed on chips with 0 configured cores -- gm011 + // Check the pointer since it may not have been installed on chips with 0 configured cores if(l_gpst_ptr == &G_global_pstate_table) { TRAC_IMP("GPST Installed: Pstate[0]: %d kHz, Step: %d kHz, Entries: %d, Pvsafe[%d], Psafe[%d]", - l_gpst_ptr->pstate0_frequency_khz, + l_gpst_ptr->pstate0_frequency_khz, l_gpst_ptr->frequency_step_khz, (int8_t) l_gpst_ptr->entries, - (int8_t) l_gpst_ptr->pvsafe, - (int8_t) l_gpst_ptr->psafe + (int8_t) l_gpst_ptr->pvsafe, + (int8_t) l_gpst_ptr->psafe ); TRAC_IMP("Pmin[%d]: %d kHz, Pmax[%d]: %d kHz", - (int8_t) l_gpst_ptr->pmin, + (int8_t) l_gpst_ptr->pmin, (l_gpst_ptr->pstate0_frequency_khz + ((int8_t) l_gpst_ptr->pmin) * l_gpst_ptr->frequency_step_khz), ((int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1), (l_gpst_ptr->pstate0_frequency_khz + ((int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1) * l_gpst_ptr->frequency_step_khz) ); } - else //gm011 + else { //This likely means that the processor has no configured cores (may not be an error scenario) TRAC_IMP("GPST not installed. hw pointer= 0x%08x, present cores= 0x%08x", (uint32_t)l_gpst_ptr, G_present_cores); @@ -302,11 +240,6 @@ void proc_trace_pstate_table_quick(void) // Name: proc_pstate2freq // // Description: Convert Pstate to Frequency -// -// -// -// -// Flow: xx/xx/xx FN= // // End Function Specification uint32_t proc_pstate2freq(Pstate i_pstate) @@ -341,7 +274,7 @@ uint32_t proc_pstate2freq(Pstate i_pstate) i_pstate = l_pmax; } - // Calculate Frequency based on Pstate + // Calculate Frequency based on Pstate l_freq = (l_gpst_ptr->pstate0_frequency_khz + ((int8_t) i_pstate) * l_gpst_ptr->frequency_step_khz); l_freq /= 1000; // Convert to MHz } @@ -356,11 +289,6 @@ uint32_t proc_pstate2freq(Pstate i_pstate) // Name: proc_freq2pstate // // Description: Convert Frequency to Nearest Pstate -// -// -// -// -// Flow: xx/xx/xx FN= // // End Function Specification Pstate proc_freq2pstate(uint32_t i_freq_mhz) @@ -403,7 +331,7 @@ Pstate proc_freq2pstate(uint32_t i_freq_mhz) { // We need to substract a full step (minus 1) to make sure we // are keeping things safe - l_temp_freq -= (l_gpst_ptr->frequency_step_khz - 1); + l_temp_freq -= (l_gpst_ptr->frequency_step_khz - 1); } // Next, calculate how many Pstate steps there are in that delta @@ -429,11 +357,8 @@ Pstate proc_freq2pstate(uint32_t i_freq_mhz) // Name: proc_gpsm_pstate_initialize // // Description: Initialize Pstate Table (and the rest of the Pstate -// SuperStructure). Also, initialize Global variables +// SuperStructure). Also, initialize Global variables // that will speed up the proc_freq2pstate function. -// -// -// Flow: xx/xx/xx FN= // // End Function Specification errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) @@ -446,12 +371,12 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) { /// Because early EC's of the Murano chip did not have valid #V data, /// we need to exclude them from loading a pstate table created by a - /// hardware procedure. If we run a table created from a #V on these + /// hardware procedure. If we run a table created from a #V on these /// chips, we could crash the box (or worse, burn something up!) - if ( (cfam_id() == CFAM_CHIP_ID_MURANO_10) + if ( (cfam_id() == CFAM_CHIP_ID_MURANO_10) || (cfam_id() == CFAM_CHIP_ID_MURANO_11) ) { - TRAC_ERR("OCC not supported on murano dd10 or dd11 due to bad #V data. chip id = 0x%08x"); //gm011 + TRAC_ERR("OCC not supported on murano dd10 or dd11 due to bad #V data. chip id = 0x%08x"); // Create Error Log and return to caller /* @ * @errortype @@ -464,7 +389,7 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) */ l_errlHndl = createErrl( PROC_GPST_INIT_FAILURE_MOD, //modId - INTERNAL_FAILURE, //reasoncode // @wb003 + INTERNAL_FAILURE, //reasoncode OCC_NO_EXTENDED_RC, //Extended reason code ERRL_SEV_UNRECOVERABLE, //Severity NULL, //Trace Buf @@ -489,9 +414,9 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) // Get Pstate Table Ptr l_gpst_ptr = gpsm_gpst(); - if(l_rc || (l_gpst_ptr != &G_global_pstate_table)) //gm011 + if(l_rc || (l_gpst_ptr != &G_global_pstate_table)) { - TRAC_ERR("gpsm_initialize failed with rc=0x%08x or l_gpstr_ptr=0x%08x", l_rc, l_gpst_ptr); + TRAC_ERR("gpsm_initialize failed with rc=0x%08x or l_gpstr_ptr=0x%08x", l_rc, l_gpst_ptr); // Create Error Log and return to caller /* @ @@ -505,7 +430,7 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) */ l_errlHndl = createErrl( PROC_GPST_INIT_FAILURE_MOD, //modId - INTERNAL_FAILURE, //reasoncode // @wb003 + INTERNAL_FAILURE, //reasoncode ERC_PROC_PSTATE_INSTALL_FAILURE, //Extended reason code ERRL_SEV_UNRECOVERABLE, //Severity NULL, //Trace Buf @@ -526,18 +451,18 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) } - // set up key globals based on the pstate table. - + // set up key globals based on the pstate table. + // Set the pstate state (state machine will start enabling pstates // when it sees this) proc_gpsm_dcm_sync_set_state(PROC_GPSM_SYNC_PSTATE_TABLE_INSTALLED); // Set up Key Globals for use by proc_freq2pstate functions - G_proc_gpst_fmax = l_gpst_ptr->pstate0_frequency_khz - + (((int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1) + G_proc_gpst_fmax = l_gpst_ptr->pstate0_frequency_khz + + (((int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1) * l_gpst_ptr->frequency_step_khz); - G_proc_gpst_fmin = l_gpst_ptr->pstate0_frequency_khz - + (((int8_t) l_gpst_ptr->pmin) + G_proc_gpst_fmin = l_gpst_ptr->pstate0_frequency_khz + + (((int8_t) l_gpst_ptr->pmin) * l_gpst_ptr->frequency_step_khz); G_proc_gpst_pmax = l_gpst_ptr->pmin + l_gpst_ptr->entries - 1; @@ -548,20 +473,17 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss) G_mhz_per_pstate = (l_gpst_ptr->frequency_step_khz)/1000; }while(0); - + return l_errlHndl; } -// gm025 // Function Specification // // Name: proc_pstate_kvm_setup // // Description: Get everything set up for KVM mode // -// Flow: xx/xx/xx FN= -// // End Function Specification void proc_pstate_kvm_setup() { @@ -590,7 +512,7 @@ void proc_pstate_kvm_setup() //do read-modify-write to allow pmax clip to also clip voltage (not just frequency) l_rc = getscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, l_core), - &(l_ppmr.value), NULL); //commit errors internally -- gm033 + &(l_ppmr.value), NULL); //commit errors internally if(l_rc) { TRAC_ERR("proc_pstate_kvm_setup: getscom(PCBS_PCBSPM_MODE_REG) failed. rc=%d, hw_core=%d", @@ -599,7 +521,7 @@ void proc_pstate_kvm_setup() } l_ppmr.fields.enable_clipping_of_global_pstate_req = 1; l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, l_core), - l_ppmr.value, NULL); //commit errors internally -- gm033 + l_ppmr.value, NULL); //commit errors internally if(l_rc) { TRAC_ERR("proc_pstate_kvm_setup: putscom(PCBS_PCBSPM_MODE_REG) failed. rc=%d, hw_core=%d", @@ -624,7 +546,7 @@ void proc_pstate_kvm_setup() l_pmbr.fields.pmin_clip = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang l_pmbr.fields.pmax_clip = gpst_pmax(&G_global_pstate_table); l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_POWER_MANAGEMENT_BOUNDS_REG, l_core), - l_pmbr.value, NULL); //commit errors internally -- gm033 + l_pmbr.value, NULL); //commit errors internally if(l_rc) { TRAC_ERR("proc_pstate_kvm_setup: putscom(PCBS_POWER_MANAGEMENT_BOUNDS_REG) failed. rc=0x%08x, hw_core=%d", @@ -696,12 +618,10 @@ void proc_pstate_kvm_setup() // Name: proc_gpsm_dcm_sync_enable_pstates_smh // // Description: Step through all the states & synch needed to enable -// Pstates on both master & slave on a DCM. This also +// Pstates on both master & slave on a DCM. This also // works for a SCM, which will act as DCM master (as far // as this function is concerned.) // -// Flow: xx/xx/xx FN= -// // End Function Specification void proc_gpsm_dcm_sync_enable_pstates_smh(void) { @@ -710,7 +630,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) static Pstate l_voltage_pstate, l_freq_pstate; // Local Variables - int l_rc = 0; + int l_rc = 0; errlHndl_t l_errlHndl = NULL; if(!gpsm_dcm_slave_p()) @@ -731,7 +651,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) if( G_proc_dcm_sync_state.sync_state_slave == PROC_GPSM_SYNC_PSTATE_TABLE_INSTALLED) { // Move to next state in state machine - G_proc_dcm_sync_state.sync_state_master = PROC_GPSM_SYNC_READY_TO_ENABLE_MASTER; + G_proc_dcm_sync_state.sync_state_master = PROC_GPSM_SYNC_READY_TO_ENABLE_MASTER; } } else @@ -755,8 +675,8 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) } TRAC_IMP("MSTR: Initial Pstates: V: %d, F: %d\n",l_voltage_pstate, l_freq_pstate); - // DCM SYNC (Master2Slave): Send V & F Pstate to slave - G_proc_dcm_sync_state.dcm_pair_id = G_pob_id.chip_id; + // DCM SYNC (Master2Slave): Send V & F Pstate to slave + G_proc_dcm_sync_state.dcm_pair_id = G_pob_id.chip_id; G_proc_dcm_sync_state.pstate_v = l_voltage_pstate; G_proc_dcm_sync_state.pstate_f = l_freq_pstate; @@ -814,14 +734,14 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) case PROC_GPSM_SYNC_PSTATE_HW_MODE: PROC_DBG("GPST DCM Master State %d\n",G_proc_dcm_sync_state.sync_state_master); - // DCM SYNC (Master2Slave): Wait for Slave to Enter HW Mode + // DCM SYNC (Master2Slave): Wait for Slave to Enter HW Mode if(gpsm_dcm_mode_p()){ if( G_proc_dcm_sync_state.sync_state_slave == PROC_GPSM_SYNC_PSTATE_HW_MODE) { TRAC_INFO("MSTR: Completed DCM Pstate Enable"); G_proc_dcm_sync_state.sync_state_master = PROC_GPSM_SYNC_PSTATE_HW_MODE_ENABLED; - //do additional setup if in kvm mode -- gm025 + //do additional setup if in kvm mode proc_pstate_kvm_setup(); } } @@ -830,7 +750,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) G_proc_dcm_sync_state.sync_state_master = PROC_GPSM_SYNC_PSTATE_HW_MODE_ENABLED; TRAC_INFO("MSTR: Completed SCM Pstate Enable"); - //do additional setup if in kvm mode -- gm025 + //do additional setup if in kvm mode proc_pstate_kvm_setup(); } break; @@ -863,11 +783,11 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) break; case PROC_GPSM_SYNC_PSTATE_TABLE_INSTALLED: - // Pstate table has been installed, but slave needs to wait + // Pstate table has been installed, but slave needs to wait // for master before it can do anything else. - // DCM SYNC (SlaveWaitForMaster): Send V & F Pstate to slave - // Wait for Master to complete gpsm_enable_pstates_master() + // DCM SYNC (SlaveWaitForMaster): Send V & F Pstate to slave + // Wait for Master to complete gpsm_enable_pstates_master() // before running gpsm_enable_pstates_slave() if( G_proc_dcm_sync_state.sync_state_master == PROC_GPSM_SYNC_PSTATE_MASTER_ENABLED) { @@ -879,11 +799,11 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) case PROC_GPSM_SYNC_PSTATE_MASTER_ENABLED: PROC_DBG("GPST DCM Slave State %d\n",G_proc_dcm_sync_state.sync_state_slave); - // Read the initial Pstates from the data DCM master sent + // Read the initial Pstates from the data DCM master sent l_voltage_pstate = G_proc_dcm_sync_state.pstate_v; l_freq_pstate = G_proc_dcm_sync_state.pstate_f; - // NULL is passed to this function when run on dcm slave + // NULL is passed to this function when run on dcm slave l_rc = gpsm_enable_pstates_slave(NULL, l_voltage_pstate, l_freq_pstate); if(l_rc) { @@ -894,9 +814,9 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) } TRAC_INFO("SLV: Completed DCM Pstate Slave Init\n"); - // DCM SYNC (Slave2Master): + // DCM SYNC (Slave2Master): // Tell Master that slave has run gpsm_enable_pstates_slave() - + // Go to next state G_proc_dcm_sync_state.sync_state_slave = PROC_GPSM_SYNC_PSTATE_SLAVE_ENABLED; break; @@ -916,7 +836,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) } // DCM SYNC (Slave2Master): Tell master that DCM slave made it to HW mode - + // Go to next state G_proc_dcm_sync_state.sync_state_slave = PROC_GPSM_SYNC_PSTATE_HW_MODE; } @@ -929,7 +849,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) G_proc_dcm_sync_state.sync_state_slave = PROC_GPSM_SYNC_PSTATE_HW_MODE_ENABLED; TRAC_INFO("SLV: Completed DCM Pstate Enable"); - //do additional setup if in kvm mode -- gm025 + //do additional setup if in kvm mode proc_pstate_kvm_setup(); } break; @@ -951,12 +871,12 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) } // If we are in the process of running through the state machine, - // we will do a sem_post to speed up the DCOM Thread and step us + // we will do a sem_post to speed up the DCOM Thread and step us // through faster. if( PROC_GPSM_SYNC_NO_PSTATE_TABLE != proc_gpsm_dcm_sync_get_my_state() && !proc_is_hwpstate_enabled() ) { - ssx_semaphore_post(&G_dcomThreadWakeupSem); // @th025 + ssx_semaphore_post(&G_dcomThreadWakeupSem); } // If we broke out of loops above because of an error, create an @@ -972,7 +892,7 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) * @userdata4 OCC_NO_EXTENDED_RC * @devdesc Failed to install Pstate Table */ - l_errlHndl = createErrl( //@gm006 + l_errlHndl = createErrl( PROC_ENABLE_PSTATES_SMH_MOD, //modId SSX_GENERIC_FAILURE, //reasoncode OCC_NO_EXTENDED_RC, //Extended reason code @@ -995,15 +915,11 @@ void proc_gpsm_dcm_sync_enable_pstates_smh(void) return; } - -// @ly010a // Function Specification // // Name: populate_pstate_to_sapphire_tbl // // Description: -// -// Flow: xx/xx/xx FN= // // End Function Specification void populate_pstate_to_sapphire_tbl() @@ -1017,8 +933,8 @@ void populate_pstate_to_sapphire_tbl() const int8_t l_pmax = (int8_t) l_gpst_ptr->pmin + l_gpst_ptr->entries - 1; G_sapphire_table.config.valid = 1; // default 0x01 G_sapphire_table.config.version = 1; // default 0x01 - G_sapphire_table.config.throttle = NO_THROTTLE; // defult 0x00 - G_sapphire_table.config.pmin = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang -- gm025 + G_sapphire_table.config.throttle = NO_THROTTLE; // default 0x00 + G_sapphire_table.config.pmin = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang G_sapphire_table.config.pnominal = (int8_t)proc_freq2pstate(G_sysConfigData.sys_mode_freq.table[OCC_MODE_NOMINAL]); G_sapphire_table.config.pmax = gpst_pmax(&G_global_pstate_table); const uint16_t l_entries = G_sapphire_table.config.pmax - G_sapphire_table.config.pmin + 1; @@ -1027,7 +943,7 @@ void populate_pstate_to_sapphire_tbl() for (i = 0; i < l_entries; i++) { G_sapphire_table.data[i].pstate = (int8_t) l_pmax - i; - G_sapphire_table.data[i].flag = 0; // defult 0x00 + G_sapphire_table.data[i].flag = 0; // default 0x00 if (i < l_gpst_ptr->entries) { G_sapphire_table.data[i].evid_vdd = l_gpst_ptr->pstate[i].fields.evid_vdd; @@ -1037,22 +953,18 @@ void populate_pstate_to_sapphire_tbl() { // leave the VDD & VCS Vids the same as the "Pstate Table Pmin" G_sapphire_table.data[i].evid_vdd = l_gpst_ptr->pstate[l_idx].fields.evid_vdd; - G_sapphire_table.data[i].evid_vcs = l_gpst_ptr->pstate[l_idx].fields.evid_vcs; + G_sapphire_table.data[i].evid_vcs = l_gpst_ptr->pstate[l_idx].fields.evid_vcs; } // extrapolate the frequency G_sapphire_table.data[i].freq_khz = l_gpst_ptr->pstate0_frequency_khz + (G_sapphire_table.data[i].pstate * l_gpst_ptr->frequency_step_khz); } } - -// @ly009a @ly010c // Function Specification // // Name: populate_sapphire_tbl_to_mem // // Description: -// -// Flow: xx/xx/xx FN= // // End Function Specification void populate_sapphire_tbl_to_mem() @@ -1067,12 +979,12 @@ void populate_sapphire_tbl_to_mem() BceRequest pba_copy; // Set up copy request l_ssxrc = bce_request_create(&pba_copy, // block copy object - &G_pba_bcue_queue, // sram to mainstore copy engine + &G_pba_bcue_queue, // sram to mainstore copy engine SAPPHIRE_OFFSET_IN_HOMER, // mainstore address (uint32_t) &G_sapphire_table, // sram starting address - (size_t) sizeof(G_sapphire_table), // size of copy + (size_t) sizeof(G_sapphire_table), // size of copy SSX_WAIT_FOREVER, // no timeout - NULL, // call back + NULL, // call back NULL, // call back arguments ASYNC_REQUEST_BLOCKING // callback mask ); @@ -1080,14 +992,14 @@ void populate_sapphire_tbl_to_mem() if(l_ssxrc != SSX_OK) { TRAC_ERR("populate_sapphire_tbl_to_mem: PBA request create failure rc=[%08X]", -l_ssxrc); - /* + /* * @errortype * @moduleid MAIN_STATE_TRANSITION_MID * @reasoncode SSX_GENERIC_FAILURE * @userdata1 RC for PBA block-copy engine * @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE * @devdesc SSX BCE related failure - */ + */ l_reasonCode = SSX_GENERIC_FAILURE; l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE; break; @@ -1099,7 +1011,7 @@ void populate_sapphire_tbl_to_mem() if(l_ssxrc != SSX_OK) { TRAC_ERR("populate_sapphire_tbl_to_mem: PBA request schedule failure rc=[%08X]", -l_ssxrc); - /* + /* * @errortype * @moduleid MAIN_STATE_TRANSITION_MID * @reasoncode SSX_GENERIC_FAILURE @@ -1123,8 +1035,8 @@ void populate_sapphire_tbl_to_mem() 0, //Trace Size -l_ssxrc, //userdata1 0); //userdata2 - - // @wb001 -- Callout firmware + + // Callout firmware addCalloutToErrl(l_errl, ERRL_CALLOUT_TYPE_COMPONENT_ID, ERRL_COMPONENT_ID_FIRMWARE, @@ -1134,15 +1046,12 @@ void populate_sapphire_tbl_to_mem() } } -// gm025 // Function Specification // -// Name: proc_check_for_sapphire_updates +// Name: proc_check_for_sapphire_updates // // Description: Checks if the sapphire table needs an update // and updates if necessary. -// -// Flow: xx/xx/xx FN= // // End Function Specification void proc_check_for_sapphire_updates() diff --git a/src/occ/proc/proc_pstate.h b/src/occ/proc/proc_pstate.h index b274bc7..1d1562e 100755 --- a/src/occ/proc/proc_pstate.h +++ b/src/occ/proc/proc_pstate.h @@ -1,37 +1,34 @@ -/****************************************************************************** -// @file proc_pstate.h -// @brief OCC Firmware Handline of Pstates -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _proc_pstate_h proc_pstate.h - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * @th010 thallet 04/05/2012 Created - * @th015 thallet 08/03/2012 Removed inline from functions - * @at010 859992 alvinwan 11/07/2012 Added oversubscription feature - * @fk001 879727 fmkassem 04/16/2013 PCAP support. - * @ly009 895318 lychen 08/13/2013 OCC-Sapphire shared memory interface - * @gm006 SW224414 milesg 09/16/2013 Reset and FFDC improvements - * @ly010 908832 lychen 12/09/2013 Sapphire update status for reset - * @gm025 915973 milesg 02/14/2014 Full support for sapphire (KVM) mode - * - * @endverbatim - * - *///*************************************************************************/ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/proc_pstate.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef PROC_PSTATE_H #define PROC_PSTATE_H -//************************************************************************* -// Includes -//************************************************************************* -#include "ssx.h" -#include "cmdh_service_codes.h" -#include "errl.h" +#include "ssx.h" +#include "cmdh_service_codes.h" +#include "errl.h" #include "trac.h" #include "rtls.h" #include "occ_common.h" @@ -42,33 +39,28 @@ #include "gpsm.h" #include "pstates.h" - -//************************************************************************* -// Defines/Enums -//************************************************************************* - -// GPSM DCM Synchronization - used by MBOX to transfer between DCM M & S +// GPSM DCM Synchronization - used by MBOX to transfer between DCM M & S typedef struct { - uint8_t dcm_pair_id; - uint8_t sync_state_master :4; - uint8_t sync_state_slave :4; - uint8_t pstate_v; - uint8_t pstate_f; + uint8_t dcm_pair_id; + uint8_t sync_state_master :4; + uint8_t sync_state_slave :4; + uint8_t pstate_v; + uint8_t pstate_f; } proc_gpsm_dcm_sync_occfw_t; typedef struct __attribute__ ((packed)) { uint8_t valid; uint8_t version; - // Sapphire_OCC_interface_v3.odp // @ly010c + // Sapphire_OCC_interface_v3.odp // throttle status 0x00 No throttle, 0x01 Powercap, 0x02 CPU overtemp, 0x03 power supply failure, 0x04 overcurrent, 0x05 OCC reset uint8_t throttle; int8_t pmin; int8_t pnominal; int8_t pmax; uint16_t spare; -} sapphire_config_t; // @ly009a +} sapphire_config_t; typedef struct __attribute__ ((packed)) { @@ -77,7 +69,7 @@ typedef struct __attribute__ ((packed)) uint8_t evid_vdd; uint8_t evid_vcs; uint32_t freq_khz; -} sapphire_data_t; // @ly009a +} sapphire_data_t; #define PSTATE_ENTRY_NUMBER 256 // This size must be a multiple of 128 @@ -87,7 +79,7 @@ typedef struct __attribute__ ((packed)) uint64_t reserved; sapphire_data_t data[PSTATE_ENTRY_NUMBER]; uint8_t pad[112]; -} sapphire_table_t __attribute__ ((aligned (128))); // @ly009a +} sapphire_table_t __attribute__ ((aligned (128))); enum { NO_THROTTLE = 0x00, @@ -96,24 +88,13 @@ enum { POWER_SUPPLY_FAILURE = 0x03, OVERCURRENT = 0x04, OCC_RESET = 0x05, -}; // @ly010a - -//************************************************************************* -// Externs -//************************************************************************* -extern GlobalPstateTable G_global_pstate_table; // @at010a - -extern uint32_t G_mhz_per_pstate; // @fk001a +}; -extern sapphire_table_t G_sapphire_table; // @ly009a +extern GlobalPstateTable G_global_pstate_table; -//************************************************************************* -// Functions -//************************************************************************* +extern uint32_t G_mhz_per_pstate; -// --------------------------------- -// Pstate Init Functions -// --------------------------------- +extern sapphire_table_t G_sapphire_table; // Initialize PState Table errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss); @@ -121,38 +102,29 @@ errlHndl_t proc_gpsm_pstate_initialize(const PstateSuperStructure* i_pss); // Entry function for enabling Pstates once table is installed void proc_gpsm_dcm_sync_enable_pstates_smh(void); - -// --------------------------------- -// Pstate Init DCM Sync Functions -// --------------------------------- - -// Get DCM Sync State +// Get DCM Sync State proc_gpsm_dcm_sync_occfw_t proc_gpsm_dcm_sync_get_state(void); // Pull down DCM pair's Sync State & Info via Mbox void proc_gpsm_dcm_sync_update_from_mbox(proc_gpsm_dcm_sync_occfw_t * i_dcm_sync_state); -// --------------------------------- -// Pstate Related Helper Functions -// --------------------------------- - // Helper function to translate from Frequency to nearest Pstate Pstate proc_freq2pstate(uint32_t i_freq_mhz); // Helper function to translate from Pstate to nearest Frequency uint32_t proc_pstate2freq(Pstate i_pstate); -// Helper function to determine if we are a DCM +// Helper function to determine if we are a DCM inline bool proc_is_dcm(); // Helper function to determine if we are in HW Pstate mode inline bool proc_is_hwpstate_enabled(void); // Copy pstate data to sapphire table -void populate_pstate_to_sapphire_tbl(); // @ly010a +void populate_pstate_to_sapphire_tbl(); // Copy sapphire table to mainstore memory at SAPPHIRE_OFFSET_IN_HOMER -void populate_sapphire_tbl_to_mem(); // @ly009a +void populate_sapphire_tbl_to_mem(); // Check if sapphire table needs update void proc_check_for_sapphire_updates(); diff --git a/src/occ/proc/test/Makefile b/src/occ/proc/test/Makefile index 1914163..9674839 100755 --- a/src/occ/proc/test/Makefile +++ b/src/occ/proc/test/Makefile @@ -1,23 +1,27 @@ -# $Id$ - -# @file Makefile +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# @brief Makefile occ application +# $Source: src/occ/proc/test/Makefile $ # - -# @page ChangeLogs Change Logs -# @section Makefile -# @verbatim +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2011,2014 +# [+] Google Inc. +# [+] International Business Machines Corp. # +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at # -# Change Log ****************************************************************** -# Flag Defect/Feature User Date Description -# ------ -------------- ---------- ------------ ----------- -# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments -# @ly003 861535 lychen 11/19/2012 Remove APSS configuration/gathering of Altitude & Temperature +# http://www.apache.org/licenses/LICENSE-2.0 # -# @endverbatim +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. # +# IBM_PROLOG_END_TAG proctest_CFILES = \ diff --git a/src/occ/proc/test/app.mk b/src/occ/proc/test/app.mk index a0c3072..9644b1f 100755 --- a/src/occ/proc/test/app.mk +++ b/src/occ/proc/test/app.mk @@ -1,8 +1,29 @@ -# $Id$ - -# @file app.mk +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/occ/proc/test/app.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2011,2014 +# [+] Google Inc. +# [+] International Business Machines Corp. # -# @brief mk occ application +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# Description: mk occ application # # This Makefile is included-ed into application Makefiles and # encapsulates the steps necessary to create application images. @@ -31,22 +52,6 @@ # $(APP).bin - A binary SRAM image of the application # $(APP).map - The linker map of the application -# @page ChangeLogs Change Logs -# @section app.mk -# @verbatim -# -# -# Change Log ****************************************************************** -# Flag Defect/Feature User Date Description -# ------ -------------- ---------- ------------ ----------- -# nguyenp 09/27/2011 created -# borrowed from occ/rtls/test/app.mk -# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments -# -# @endverbatim -# - - OCC = ../../ SSX = ../../../ssx LIB = ../../../lib @@ -96,8 +101,4 @@ clean_all: $(MAKE) clean $(MAKE) -C $(PGP) clean -.PHONY : doc -doc: - doxygen doc/Doxyfile - include $(OBJECTS:.o=.d) diff --git a/src/occ/proc/test/main.c b/src/occ/proc/test/main.c index 1a18808..67c0bda 100755 --- a/src/occ/proc/test/main.c +++ b/src/occ/proc/test/main.c @@ -1,35 +1,29 @@ -/****************************************************************************** -// @file main.c -// @brief OCC PROC TEST MAIN -*/ -/****************************************************************************** - * - * @page ChangeLogs Change Logs - * @section _main_c main.c - * @verbatim - * - * Flag Def/Fea Userid Date Description - * ------- ---------- -------- ---------- ---------------------------------- - * nguyenp 10/03/2011 Created - * To run the test, first need to enable - * the PROC_DBG define in proc_data.h and - * replace this main.c in occ - * directory with this main.c - * @pb00A pbavari 11/15/2011 changed name from APSS_SUPPORT to - * OCC_ALONE_SIMICS - * @dw000 dwoodham 12/12/2011 Update call to IMAGE_HEADER - * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments - * @nh001 neilhsu 05/23/2012 Add missing error log tags - * @fk003 907687 fmkassem 11/25/2013 Fix name of extended reason code - * @wb001 919163 wilbryan 03/06/2014 Updating error call outs, descriptions, and severities - * - * @endverbatim - * - *///*************************************************************************/ - - //************************************************************************* -// Includes -//************************************************************************* +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ/proc/test/main.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2014 */ +/* [+] Google Inc. */ +/* [+] International Business Machines Corp. */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + #include "ssx.h" #include "ssx_io.h" #include "simics_stdio.h" @@ -37,43 +31,21 @@ #include <threadSch.h> #include <errl.h> #include <apss.h> -#include <appletManager.h> -#include <trac.h> -#include <occ_service_codes.h> -#include <occ_sys_config.h> +#include <appletManager.h> +#include <trac.h> +#include <occ_service_codes.h> +#include <occ_sys_config.h> #include <proc_data.h> -#include <timer.h> -#include <dcom.h> +#include <timer.h> +#include <dcom.h> #include <rtls.h> -//************************************************************************* -// Externs -//************************************************************************* extern void __ssx_boot; -//************************************************************************* -// Image Header -//************************************************************************* -// @dw000c IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,OCC_APLT_TEST); -//************************************************************************* -// Macros -//************************************************************************* - -//************************************************************************* -// Defines/Enums -//************************************************************************* -/// Period in which to run #timer_routine -#define TIMER_INTERVAL (SsxInterval) SSX_MICROSECONDS(5000) - -//************************************************************************* -// Structures -//************************************************************************* - -//************************************************************************* -// Globals -//************************************************************************* +// Period in which to run #timer_routine +#define TIMER_INTERVAL (SsxInterval) SSX_MICROSECONDS(5000) int g_j = 0; int g_k = 0; @@ -81,29 +53,15 @@ int g_k = 0; SimicsStdio simics_stdout; SimicsStdio simics_stderr; -/*----------------------------------------------------------------------------*/ -/* Critical/Non-Critical stack */ -/*----------------------------------------------------------------------------*/ - uint8_t noncritical_stack[NONCRITICAL_STACK_SIZE]; uint8_t critical_stack[CRITICAL_STACK_SIZE]; -//************************************************************************* -// Function Prototypes -//************************************************************************* - -//************************************************************************* -// Functions -//************************************************************************* - // Function Specification // -// Name: pgp_validation_ssx_main_hook +// Name: pgp_validation_ssx_main_hook // // Description: // -// Flow: FN=None -// // End Function Specification void pgp_validation_ssx_main_hook(void) { @@ -112,12 +70,10 @@ void pgp_validation_ssx_main_hook(void) // Function Specification // -// Name: Cmd_Hndl_thread_routine +// Name: Cmd_Hndl_thread_routine // // Description: // -// Flow: FN=None -// // End Function Specification void Cmd_Hndl_thread_routine(void *arg) { @@ -126,12 +82,10 @@ void Cmd_Hndl_thread_routine(void *arg) // Function Specification // -// Name: Thermal_Monitor_thread_routine +// Name: Thermal_Monitor_thread_routine // // Description: // -// Flow: FN=None -// // End Function Specification void Thermal_Monitor_thread_routine(void *arg) { @@ -140,12 +94,10 @@ void Thermal_Monitor_thread_routine(void *arg) // Function Specification // -// Name: Hlth_Monitor_thread_routine +// Name: Hlth_Monitor_thread_routine // // Description: // -// Flow: FN=None -// // End Function Specification void Hlth_Monitor_thread_routine(void *arg) { @@ -154,11 +106,9 @@ void Hlth_Monitor_thread_routine(void *arg) // Function Specification // -// Name: FFDC_thread_routine +// Name: FFDC_thread_routine // // Description: -// -// Flow: FN=None // // End Function Specification void FFDC_thread_routine(void *arg) @@ -168,11 +118,9 @@ void FFDC_thread_routine(void *arg) // Function Specification // -// Name: get_core_info +// Name: get_core_info // // Description: -// -// Flow: FN=None // // End Function Specification void get_core_info() @@ -186,28 +134,20 @@ void get_core_info() l_deconfigured_cores = in32(PMC_CORE_DECONFIGURATION_REG); PROC_DEBUG( "Deconfigured cores in the chip [0x%x]\n", l_deconfigured_cores); - + l_configured_cores = ~l_deconfigured_cores & ALL_CORES_MASK; PROC_DEBUG( "Configured cores in the chip [0x%x]\n", l_configured_cores); return; } -/** Main Thread - * - * This thread currently just loops as the lowest priority thread, handling - * the lowest priority tasks. - * - */ // Function Specification // -// Name: main_thread_routine +// Name: main_thread_routine // // Description: This thread currently just loops as the lowest priority thread, handling // the lowest priority tasks. // -// Flow: FN=None -// // End Function Specification void main_thread_routine(void *private) { @@ -220,18 +160,12 @@ void main_thread_routine(void *private) int l_ssxrc = 0; // Start the critical 250uS timer - //ssx_timer_schedule(&timer, 1, TIMER_INTERVAL); + //ssx_timer_schedule(&timer, 1, TIMER_INTERVAL); // Initialize applet semaphore l_ssxrc = ssx_semaphore_create(&l_appletComplete, 0, 1); - // Initialize APSS // @cc000a - //$pb005a - ifdef apss_initialize call temporary - // until Bishop's simics model and Steve's simics model - // are synced. Bishop's model does not have apss support - // Steve's model does not have latest changes Bishop - // made for ssx. To make latest svn code usable for testing - // ifdef apss_initialize call + // Initialize APSS #ifdef OCC_ALONE_SIMICS l_rc = runApplet(OCC_APLT_APSS_INIT, // Applet enum Name NULL, // Applet arguments @@ -280,20 +214,14 @@ void main_thread_routine(void *private) } -/** Entry point for OCC execution - * - * main() currently initalizes our trace buffer along with creating threads - * and timers for execution. Note that once main runs ssx_start_threads, we - * never return as the SSX kernel takes over. - * - */ // Function Specification // -// Name: main +// Name: main // // Description: Entry point for OCC execution -// -// Flow: FN=None +// Currently initalizes our trace buffer along with creating threads +// and timers for execution. Note that once main runs ssx_start_threads, +// we never return as the SSX kernel takes over. // // End Function Specification int main(int argc, char **argv) @@ -303,7 +231,7 @@ int main(int argc, char **argv) simics_stderr_create(&simics_stderr); stdout = (FILE *)(&simics_stdout); stderr = (FILE *)(&simics_stderr); - ssxout = (FILE *)(&simics_stdout); + ssxout = (FILE *)(&simics_stdout); TRAC_INFO("Inside OCC Main"); @@ -313,8 +241,8 @@ int main(int argc, char **argv) 0); // Create Threads - ssx_thread_create(&main_thread, - main_thread_routine, + ssx_thread_create(&main_thread, + main_thread_routine, (void *)0, (SsxAddress)main_thread_stack, THREAD_STACK_SIZE, @@ -333,13 +261,13 @@ int main(int argc, char **argv) // Trace and commit error TRAC_ERR("init thread Scheduler failure"); - // commit log + // commit log // NOTE: log should be deleted by reader mechanism - commitErrl( &l_errl ); + commitErrl( &l_errl ); } - + // lets map mainstore to oci space only once - // NOTE: This will stay mapped for remainder of occ life + // NOTE: This will stay mapped for remainder of occ life // TODO: This sounds like a temporary solution and may // end up moving to simics environment setup // TODO: This map needs to be unmapped after done accessing @@ -350,13 +278,13 @@ int main(int argc, char **argv) 0, //OCI address 0x0 1048576, //Max size = 1 Mb 0, // - 0, //no TLBIE permissions only need to read + 0, //no TLBIE permissions only need to read &pba_mmu_map ); - + if ( l_ssxrc1 != SSX_OK ) { - tracDesc_t l_trace = NULL; + tracDesc_t l_trace = NULL; TRAC_ERR("mmu map failure SsxRc[0x%08X]", -l_ssxrc1 ); @@ -370,29 +298,29 @@ int main(int argc, char **argv) */ l_errl = createErrl( MAIN_MID, //modId - SSX_GENERIC_FAILURE, //reasoncode // @nh001c - ERC_MMU_MAP_FAILURE, //Extended reason code //@fk003c + SSX_GENERIC_FAILURE, //reasoncode + ERC_MMU_MAP_FAILURE, //Extended reason code ERRL_SEV_UNRECOVERABLE, //Severity l_trace, //Trace Buf DEFAULT_TRACE_SIZE, //Trace Size l_ssxrc1, //userdata1 0 //userdata2 ); - - // @wb001 -- Callout firmware + + // Callout firmware addCalloutToErrl(l_errl, ERRL_CALLOUT_TYPE_COMPONENT_ID, ERRL_COMPONENT_ID_FIRMWARE, ERRL_CALLOUT_PRIORITY_HIGH); - - // commit log + + // commit log commitErrl( &l_errl ); - - // TODO request a reset of OCC since applet manager will + + // TODO request a reset of OCC since applet manager will // be toast without this working correctly } - - //Initialize the Applet Manager @02a + + //Initialize the Applet Manager l_errl = initAppletManager(); if( l_errl ) @@ -400,13 +328,12 @@ int main(int argc, char **argv) // Trace and commit error TRAC_ERR("init Applet Manager failure"); - // commit log + // commit log commitErrl( &l_errl ); - - // TODO request a reset of OCC since applet manager will - // be toast without this working correctly - } + // TODO: request a reset of OCC since applet manager will + // be toast without this working correctly + } //Initialize structures for collecting core data. //It needs to run before RTLoop start. @@ -415,37 +342,11 @@ int main(int argc, char **argv) get_core_info(); // Initialize Realtime Loop Timer Interrupt - rtl_ocb_init(); - -//>@paulng -///////////////////////////////////////////////////////////////////////////////////////// -//Proc core data testing notes: -// -//proc data gathering data testing are imbeded in the proc_data.c file -//Only need to enable proc debug flag in the header file then test will be run. -// -//Tests cover the following: -//Test case 1: I tested the G_core_presents and verified the deconfigured registry value. -// -//Test case 2: I verified the porflex get created successfully during initilization. -// -//Test case 3: I tested the "GPE request still running" case by modified the Ticks table -// to let same set cores task run back to back. -// -//Test case 4: I tested GPE request has been succeeded for each core -// and verified the data pointers get swapped properly. -// -//Test case 5: I tested and verified the poreflex scheduled correctly. -// -//Test case 6: I tested and verified the RTL Tick table that has the both task core data -// for low/high set core ran properly. -// -///////////////////////////////////////////////////////////////////////////////////////// -//<@paulng + rtl_ocb_init(); // Enter SSX Kernel ssx_start_threads(); - + return 0; } |