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| author | Doug Gilbert <dgilbert@us.ibm.com> | 2017-10-17 14:26:56 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-10-19 12:39:37 -0400 |
| commit | e00c5e2fad7d87e2a83076a45935bc114fabfe5b (patch) | |
| tree | 9c479e0b64e848aad9187c4d3dcb5b3679b6b5d4 /src/include | |
| parent | 619a19c8bfc710697696bda561d20b777696711a (diff) | |
| download | talos-occ-e00c5e2fad7d87e2a83076a45935bc114fabfe5b.tar.gz talos-occ-e00c5e2fad7d87e2a83076a45935bc114fabfe5b.zip | |
Add pointers to all gpe trace buffers in gpe shared data.
Change-Id: I4b326e97a54050faad127ab00fd5bf6532126fe6
RTC: 161456
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48519
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/p9_memmap_occ_sram.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/include/p9_memmap_occ_sram.h b/src/include/p9_memmap_occ_sram.h new file mode 100644 index 0000000..be31637 --- /dev/null +++ b/src/include/p9_memmap_occ_sram.h @@ -0,0 +1,44 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/p9_memmap_occ_sram.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#if !defined(__P9_MEMMAP_OCC_SRAM_H__) +#define __P9_MEMMAP_OCC_SRAM_H__ + +#define OCC_SRAM_BASE_ADDR 0xFFF00000 + +#define GPE_DEBUG_PTRS_OFFSET 0x180 +#define PGPE_DEBUG_PTRS_OFFSET 0x200 +#define SGPE_DEBUG_PTRS_OFFSET 0x200 + +#define PK_TRACE_PTR_OFFSET 0x04 +#define PK_TRACE_SIZE_OFFSET 0x08 + +#define OCC_SRAM_IPC_REGION_SIZE (4 * 1024) +#define OCC_SRAM_GPE0_REGION_SIZE (60 * 1024) +#define OCC_SRAM_GPE1_REGION_SIZE (64 * 1024) + +#define GPE0_SRAM_BASE_ADDR OCC_SRAM_BASE_ADDR + OCC_SRAM_IPC_REGION_SIZE +#define GPE1_SRAM_BASE_ADDR GPE0_SRAM_BASE_ADDR + OCC_SRAM_GPE0_REGION_SIZE + +#endif |
