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authormbroyles <mbroyles@us.ibm.com>2015-08-03 11:24:54 -0500
committerWilliam A. Bryan <wilbryan@us.ibm.com>2015-08-03 12:19:46 -0500
commite304743c292e7161db5e2412d18a28c1b6f37a75 (patch)
treee3455b16f663444d7f8b00e39429bf002343e727 /src/include
parent63543ec97897f566d6977ea60bfea7adb5ad6596 (diff)
downloadtalos-occ-e304743c292e7161db5e2412d18a28c1b6f37a75.tar.gz
talos-occ-e304743c292e7161db5e2412d18a28c1b6f37a75.zip
new include dir
Change-Id: I791df565b9277ab3cd29d1616fd0affac2c3e68d Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19499 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cmehw_interrupts.h185
-rw-r--r--src/include/occhw_common.h583
-rw-r--r--src/include/occhw_interrupts.h293
-rw-r--r--src/include/occhw_irq_config.h280
-rw-r--r--src/include/registers/README35
-rw-r--r--src/include/registers/cme_firmware_registers.h4363
-rw-r--r--src/include/registers/cme_register_addresses.h175
-rw-r--r--src/include/registers/cppm_firmware_registers.h1261
-rw-r--r--src/include/registers/cppm_register_addresses.h87
-rw-r--r--src/include/registers/gpe_firmware_registers.h887
-rw-r--r--src/include/registers/gpe_register_addresses.h205
-rw-r--r--src/include/registers/ocb_firmware_registers.h5230
-rw-r--r--src/include/registers/ocb_register_addresses.h631
-rw-r--r--src/include/registers/pba_firmware_registers.h2208
-rw-r--r--src/include/registers/pba_register_addresses.h118
-rw-r--r--src/include/registers/pmc_firmware_registers.h3164
-rw-r--r--src/include/registers/pmc_register_addresses.h140
-rw-r--r--src/include/registers/ppm_firmware_registers.h1214
-rw-r--r--src/include/registers/ppm_register_addresses.h78
-rw-r--r--src/include/registers/qppm_firmware_registers.h1069
-rw-r--r--src/include/registers/qppm_register_addresses.h67
-rw-r--r--src/include/registers/sramctl_firmware_registers.h235
-rw-r--r--src/include/registers/sramctl_register_addresses.h54
-rw-r--r--src/include/registers/tpc_firmware_registers.h237
-rw-r--r--src/include/registers/tpc_register_addresses.h54
25 files changed, 22853 insertions, 0 deletions
diff --git a/src/include/cmehw_interrupts.h b/src/include/cmehw_interrupts.h
new file mode 100644
index 0000000..e7dd10a
--- /dev/null
+++ b/src/include/cmehw_interrupts.h
@@ -0,0 +1,185 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/cmehw_interrupts.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CMEHW_INTERRUPTS_H__
+#define __CMEHW_INTERRUPTS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cmehw_interrupts.h
+/// \brief Interrupt assignments and macros for the CME
+///
+
+
+////////////////////////////////////////////////////////////////////////////
+// IRQ
+////////////////////////////////////////////////////////////////////////////
+
+// The CME interrupt controller consists of 1 x 64-bit controller.
+//
+// All 64 interrupts are or'd together and presented to the PPE as a single
+// external interrupt exception.
+
+#define CMEHW_IRQ_DEBUGGER 0 /* 0x00 */
+#define CMEHW_IRQ_DEBUG_TRIGGER 1 /* 0x01 */
+#define CMEHW_IRQ_QUAD_CHECKSTOP 2 /* 0x02 */
+#define CMEHW_IRQ_SPARE_3 3 /* 0x03 */
+#define CMEHW_IRQ_OCC_HEARTBEAT_LOST 4 /* 0x04 */
+#define CMEHW_IRQ_CORE_CHECKSTOP 5 /* 0x05 */
+#define CMEHW_IRQ_BCE_BUSY_HIGH 6 /* 0x06 */
+#define CMEHW_IRQ_SPARE_7 7 /* 0x07 */
+#define CMEHW_IRQ_DOORBELL3_C0 8 /* 0x08 */
+#define CMEHW_IRQ_DOORBELL3_C1 9 /* 0x09 */
+#define CMEHW_IRQ_PC_INTR_PENDING_C0 10 /* 0x0a */
+#define CMEHW_IRQ_PC_INTR_PENDING_C1 11 /* 0x0b */
+#define CMEHW_IRQ_REG_WAKEUP_C0 12 /* 0x0c */
+#define CMEHW_IRQ_REG_WAKEUP_C1 13 /* 0x0d */
+#define CMEHW_IRQ_SPECIAL_WAKEUP_C0 14 /* 0x0e */
+#define CMEHW_IRQ_SPECIAL_WAKEUP_C1 15 /* 0x0f */
+#define CMEHW_IRQ_SPARE_16 16 /* 0x10 */
+#define CMEHW_IRQ_SPARE_17 17 /* 0x11 */
+#define CMEHW_IRQ_DOORBELL2_C0 18 /* 0x12 */
+#define CMEHW_IRQ_DOORBELL2_C1 19 /* 0x13 */
+#define CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0 20 /* 0x14 */
+#define CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1 21 /* 0x15 */
+#define CMEHW_IRQ_L2_PURGE_DONE 22 /* 0x16 */
+#define CMEHW_IRQ_NCU_PURGE_DONE 23 /* 0x17 */
+#define CMEHW_IRQ_CHTM_PURGE_DONE_C0 24 /* 0x18 */
+#define CMEHW_IRQ_CHTM_PURGE_DONE_C1 25 /* 0x19 */
+#define CMEHW_IRQ_BCE_BUSY_LOW 26 /* 0x1a */
+#define CMEHW_IRQ_SPARE_27 27 /* 0x1b */
+#define CMEHW_IRQ_SPARE_28 28 /* 0x1c */
+#define CMEHW_IRQ_COMM_RECVD 29 /* 0x1d */
+#define CMEHW_IRQ_COMM_SEND_ACK 30 /* 0x1e */
+#define CMEHW_IRQ_COMM_SEND_NACK 31 /* 0x1f */
+
+#define CMEHW_IRQ_SPARE_32 32 /* 0x20 */
+#define CMEHW_IRQ_SPARE_33 33 /* 0x21 */
+#define CMEHW_IRQ_PMCR_UPDATE_C0 34 /* 0x22 */
+#define CMEHW_IRQ_PMCR_UPDATE_C1 35 /* 0x23 */
+#define CMEHW_IRQ_DOORBELL0_C0 36 /* 0x24 */
+#define CMEHW_IRQ_DOORBELL0_C1 37 /* 0x25 */
+#define CMEHW_IRQ_SPARE_38 38 /* 0x26 */
+#define CMEHW_IRQ_SPARE_39 39 /* 0x27 */
+#define CMEHW_IRQ_DOORBELL1_C0 40 /* 0x28 */
+#define CMEHW_IRQ_DOORBELL1_C1 41 /* 0x29 */
+#define CMEHW_IRQ_PECE_INTR_DISABLED_C0 42 /* 0x2a */
+#define CMEHW_IRQ_PECE_INTR_DISABLED_C1 43 /* 0x2b */
+#define CMEHW_IRQ_RESERVED_44 44 /* 0x2c */
+#define CMEHW_IRQ_RESERVED_45 45 /* 0x2d */
+#define CMEHW_IRQ_RESERVED_46 46 /* 0x2e */
+#define CMEHW_IRQ_RESERVED_47 47 /* 0x2f */
+#define CMEHW_IRQ_RESERVED_48 48 /* 0x30 */
+#define CMEHW_IRQ_RESERVED_49 49 /* 0x31 */
+#define CMEHW_IRQ_RESERVED_50 50 /* 0x32 */
+#define CMEHW_IRQ_RESERVED_51 51 /* 0x33 */
+#define CMEHW_IRQ_RESERVED_52 52 /* 0x34 */
+#define CMEHW_IRQ_RESERVED_53 53 /* 0x35 */
+#define CMEHW_IRQ_RESERVED_54 54 /* 0x36 */
+#define CMEHW_IRQ_RESERVED_55 55 /* 0x37 */
+#define CMEHW_IRQ_RESERVED_56 56 /* 0x38 */
+#define CMEHW_IRQ_RESERVED_57 57 /* 0x39 */
+#define CMEHW_IRQ_RESERVED_58 58 /* 0x3a */
+#define CMEHW_IRQ_RESERVED_59 59 /* 0x3b */
+#define CMEHW_IRQ_RESERVED_60 60 /* 0x3c */
+#define CMEHW_IRQ_RESERVED_61 61 /* 0x3d */
+#define CMEHW_IRQ_RESERVED_62 62 /* 0x3e */
+#define CMEHW_IRQ_RESERVED_63 63 /* 0x3f */
+
+// Please keep the string definitions up-to-date as they are used for
+// reporting in the Simics simulation.
+
+#define CMEHW_IRQ_STRINGS(var) \
+ const char* var[CMEHW_IRQS] = { \
+ "CMEHW_IRQ_DEBUGGER", \
+ "CMEHW_IRQ_DEBUG_TRIGGER", \
+ "CMEHW_IRQ_QUAD_CHECKSTOP", \
+ "CMEHW_IRQ_SPARE_3", \
+ "CMEHW_IRQ_OCC_HEARTBEAT_LOST", \
+ "CMEHW_IRQ_CORE_CHECKSTOP", \
+ "CMEHW_IRQ_BCE_BUSY_HIGH", \
+ "CMEHW_IRQ_SPARE_7", \
+ "CMEHW_IRQ_DOORBELL3_C0", \
+ "CMEHW_IRQ_DOORBELL3_C1", \
+ "CMEHW_IRQ_PC_INTR_PENDING_C0", \
+ "CMEHW_IRQ_PC_INTR_PENDING_C1", \
+ "CMEHW_IRQ_REG_WAKEUP_C0", \
+ "CMEHW_IRQ_REG_WAKEUP_C1", \
+ "CMEHW_IRQ_SPECIAL_WAKEUP_C0", \
+ "CMEHW_IRQ_SPECIAL_WAKEUP_C1", \
+ "CMEHW_IRQ_SPARE_16", \
+ "CMEHW_IRQ_SPARE_17", \
+ "CMEHW_IRQ_DOORBELL2_C0", \
+ "CMEHW_IRQ_DOORBELL2_C1", \
+ "CMEHW_IRQ_PC_PM_STATE_ACTIVE_C0", \
+ "CMEHW_IRQ_PC_PM_STATE_ACTIVE_C1", \
+ "CMEHW_IRQ_L2_PURGE_DONE", \
+ "CMEHW_IRQ_NCU_PURGE_DONE", \
+ "CMEHW_IRQ_CHTM_PURGE_DONE_C0", \
+ "CMEHW_IRQ_CHTM_PURGE_DONE_C1", \
+ "CMEHW_IRQ_BCE_BUSY_LOW", \
+ "CMEHW_IRQ_SPARE_27", \
+ "CMEHW_IRQ_SPARE_28", \
+ "CMEHW_IRQ_COMM_RECVD", \
+ "CMEHW_IRQ_COMM_SEND_ACK", \
+ "CMEHW_IRQ_COMM_SEND_NACK", \
+ "CMEHW_IRQ_SPARE_32", \
+ "CMEHW_IRQ_SPARE_33", \
+ "CMEHW_IRQ_PMCR_UPDATE_C0", \
+ "CMEHW_IRQ_PMCR_UPDATE_C1", \
+ "CMEHW_IRQ_DOORBELL0_C0", \
+ "CMEHW_IRQ_DOORBELL0_C1", \
+ "CMEHW_IRQ_SPARE_38", \
+ "CMEHW_IRQ_SPARE_39", \
+ "CMEHW_IRQ_DOORBELL1_C0", \
+ "CMEHW_IRQ_DOORBELL1_C1", \
+ "CMEHW_IRQ_PECE_INTR_DISABLED_C0", \
+ "CMEHW_IRQ_PECE_INTR_DISABLED_C1", \
+ "CMEHW_IRQ_RESERVED_44", \
+ "CMEHW_IRQ_RESERVED_45", \
+ "CMEHW_IRQ_RESERVED_46", \
+ "CMEHW_IRQ_RESERVED_47", \
+ "CMEHW_IRQ_RESERVED_48", \
+ "CMEHW_IRQ_RESERVED_49", \
+ "CMEHW_IRQ_RESERVED_50", \
+ "CMEHW_IRQ_RESERVED_51", \
+ "CMEHW_IRQ_RESERVED_52", \
+ "CMEHW_IRQ_RESERVED_53", \
+ "CMEHW_IRQ_RESERVED_54", \
+ "CMEHW_IRQ_RESERVED_55", \
+ "CMEHW_IRQ_RESERVED_56", \
+ "CMEHW_IRQ_RESERVED_57", \
+ "CMEHW_IRQ_RESERVED_58", \
+ "CMEHW_IRQ_RESERVED_59", \
+ "CMEHW_IRQ_RESERVED_60", \
+ "CMEHW_IRQ_RESERVED_61", \
+ "CMEHW_IRQ_RESERVED_62", \
+ "CMEHW_IRQ_RESERVED_63", \
+ };
+
+
+#endif /* __CMEHW_INTERRUPTS_H__ */
diff --git a/src/include/occhw_common.h b/src/include/occhw_common.h
new file mode 100644
index 0000000..807a57a
--- /dev/null
+++ b/src/include/occhw_common.h
@@ -0,0 +1,583 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/occhw_common.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __OCCHW_COMMON_H__
+#define __OCCHW_COMMON_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_common.h
+/// \brief Common header for SSX and PMX versions of OCCHW
+///
+/// This header is maintained as part of the SSX port for OCCHW, but needs to be
+/// physically present in the PMX area to allow dropping PMX code as a whole
+/// to other teams.
+
+// -*- WARNING: This file is maintained as part of SSX. Do not edit in -*-
+// -*- the PMX area as your edits will be lost. -*-
+
+#include "occhw_interrupts.h"
+#include "occhw_irq_config.h"
+
+#define EXTERNAL_IRQS OCCHW_IRQS
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+extern unsigned int g_ocb_timer_divider; //grm
+#endif
+
+////////////////////////////////////////////////////////////////////////////
+// Configuration
+////////////////////////////////////////////////////////////////////////////
+
+#define OCCHW_NCORES 16
+#define OCCHW_NCORE_PARTITIONS 4
+#define OCCHW_NMCS 8
+#define OCCHW_NCENTAUR 8
+#define OCCHW_NTHREADS 8
+#define OCCHW_NDTSCPM 4
+
+#ifndef PROCESSOR_EC_LEVEL
+#define MURANO_DD10 1
+#else
+#define MURANO_DD10 0
+#endif
+
+#ifndef SIMICS_ENVIRONMENT
+#define SIMICS_ENVIRONMENT 0
+#endif
+
+/// OCC instance ID's that can be read from the PPE42 PIR and used in IPC operations.
+/// NOTE: The PPC instance ID is not associated with a register and was assigned to be
+/// four as it was most convenient to do so in the code.
+#define OCCHW_MAX_INSTANCES 5
+
+#define OCCHW_INST_ID_GPE0 0
+#define OCCHW_INST_ID_GPE1 1
+#define OCCHW_INST_ID_GPE2 2
+#define OCCHW_INST_ID_GPE3 3
+#define OCCHW_INST_ID_PPC 4
+#define OCCHW_INST_ID_MAX (OCCHW_MAX_INSTANCES - 1)
+#define OCCHW_INST_ID_MAX_GPE 3
+
+/// Fail to compile if APPCFG_OCC_INSTANCE_ID is not defined somewhere or is out of range
+#ifndef APPCFG_OCC_INSTANCE_ID
+#error "APPCFG_OCC_INSTANCE_ID must be defined by the application"
+#else
+#if ((APPCFG_OCC_INSTANCE_ID > OCCHW_INST_ID_MAX) || (APPCFG_OCC_INSTANCE_ID < 0))
+#warning "APPCFG_OCC_INSTANCE_ID is out of range"
+#endif
+#endif
+#define OCCHW_INST_ID_SELF APPCFG_OCC_INSTANCE_ID
+
+////////////////////////////////////////////////////////////////////////////
+// Clocking
+////////////////////////////////////////////////////////////////////////////
+//
+// The SSX timebase is driven by the pervasive clock, which is nest / 4. This
+// will typically be 600MHz, but may be 500MHz for power-constrained system
+// designs.
+
+/// The pervasive hang timer divider used for the OCB timer
+///
+/// This is supposed to yield an approximately 1us timer, however for MURANO
+/// DD10 we need to use an approximate 64us timer
+
+#if MURANO_DD10
+#define OCB_TIMER_DIVIDER_DEFAULT (64 * 512)
+#else
+#define OCB_TIMER_DIVIDER_DEFAULT 512
+#endif
+
+/// This is set to the above default at compile time but may be updated
+/// at run time. grm
+//#define OCB_TIMER_DIVIDER g_ocb_timer_divider
+#define OCB_TIMER_DIVIDER OCB_TIMER_DIVIDER_DEFAULT
+
+/// The OCB timer frequency
+#define OCB_TIMER_FREQUENCY_HZ (SSX_TIMEBASE_FREQUENCY_HZ / OCB_TIMER_DIVIDER)
+
+/// The pervasive hang timer divider used for the PMC (same as OCB timer)
+#define PMC_TIMER_DIVIDER OCB_TIMER_DIVIDER
+
+/// The PMC hang pulse frequency
+#define PMC_HANG_PULSE_FREQUENCY_HZ \
+ (SSX_TIMEBASE_FREQUENCY_HZ / PMC_TIMER_DIVIDER)
+
+/// The pervasive hang timer divider for PCBS 'fast' timers
+///
+/// This timer yeilds an approximate 100ns pulse with a 2.4 GHz pervasive clock
+#define PCBS_FAST_TIMER_DIVIDER 64
+
+/// The pervasive hang timer divider for PCBS 'slow' timers
+///
+/// This timer yeilds an approximate 1us pulse with a 2.4 GHz pervasive clock
+#define PCBS_SLOW_TIMER_DIVIDER 512
+
+/// The PCBS slow divider frequency
+#define PCBS_SLOW_HANG_PULSE_FREQUENCY_HZ \
+ (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_SLOW_TIMER_DIVIDER)
+
+/// The PCBS occ heartbeat pulse is predivided in hardware by 64
+#define PCBS_HEARTBEAT_DIVIDER \
+ (PCBS_SLOW_TIMER_DIVIDER * 64)
+
+/// The PCBS heartbeat pulse frequency
+#define PCBS_HEARTBEAT_PULSE_FREQUENCY_HZ \
+ (SSX_TIMEBASE_FREQUENCY_HZ / PCBS_HEARTBEAT_DIVIDER)
+
+
+
+////////////////////////////////////////////////////////////////////////////
+// OCI
+////////////////////////////////////////////////////////////////////////////
+
+// OCI Master Id assigments - required for PBA slave programming. These Ids
+// also appear as bits 12:15 of the OCI register space addresses of the OCI
+// registers for each device that contains OCI-addressable registers (GPE,
+// PMC, PBA, SLW and OCB).
+
+#define OCI_TRANSPORT_DELAY 10
+
+#define OCI_MASTER_ID_PHONY -1
+#define OCI_MASTER_ID_GPE0 0
+#define OCI_MASTER_ID_GPE1 1
+#define OCI_MASTER_ID_GPE2 2
+#define OCI_MASTER_ID_GPE3 3
+#define OCI_MASTER_ID_PBA 4
+#define OCI_MASTER_ID_OCC_ICU 5
+#define OCI_MASTER_ID_OCB 6
+#define OCI_MASTER_ID_OCC_DCU 7
+
+
+////////////////////////////////////////////////////////////////////////////
+// PIB
+////////////////////////////////////////////////////////////////////////////
+
+#define PIB_TRANSPORT_DELAY 50
+
+#define PIB_MASTER_ID_PHONY -1
+#define PIB_MASTER_ID_FSI2PIB 0x2
+#define PIB_MASTER_ID_FSI_SHIFT 0x3
+#define PIB_MASTER_ID_TOD 0x4
+#define PIB_MASTER_ID_PMC 0x6
+#define PIB_MASTER_ID_PORE_GPE 0x7
+#define PIB_MASTER_ID_PORE_SLW 0x8
+#define PIB_MASTER_ID_ADU 0x9
+#define PIB_MASTER_ID_MEMS0 0xA
+#define PIB_MASTER_ID_I2C_SLAVE 0xD
+#define PIB_MASTER_ID_PORE_SBE 0xE
+
+
+////////////////////////////////////////////////////////////////////////////
+// OCB
+////////////////////////////////////////////////////////////////////////////
+
+/// The base address of the OCI control register space
+#define OCI_REGISTER_SPACE_BASE 0xC0000000
+
+/// The base address of the entire PIB port mapped by the OCB. The
+/// OCB-contained PIB registers are based at OCB_PIB_BASE.
+#define OCB_PIB_SLAVE_BASE 0x00060000
+
+/// The size of the OCI control register address space
+///
+/// There are at most 8 slaves, each of which maps 2**16 bytes of register
+/// address space.
+#define OCI_REGISTER_SPACE_SIZE POW2_32(19)
+
+/// This macro converts an OCI register space address into a PIB address as
+/// seen through the OCB direct bridge.
+#define OCI2PIB(addr) ((((addr) & 0x0007ffff) >> 3) + OCB_PIB_SLAVE_BASE)
+
+
+// OCB communication channel constants
+
+#define OCB_INDIRECT_CHANNELS 4
+
+#define OCB_RW_READ 0
+#define OCB_RW_WRITE 1
+
+#define OCB_STREAM_MODE_DISABLED 0
+#define OCB_STREAM_MODE_ENABLED 1
+
+#define OCB_STREAM_TYPE_LINEAR 0
+#define OCB_STREAM_TYPE_CIRCULAR 1
+
+#define OCB_INTR_ACTION_FULL 0
+#define OCB_INTR_ACTION_NOT_FULL 1
+#define OCB_INTR_ACTION_EMPTY 2
+#define OCB_INTR_ACTION_NOT_EMPTY 3
+
+
+////////////////////////////////////////////////////////////////////////////
+// PMC
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __ASSEMBLER__
+
+/// A Pstate type
+///
+/// Pstates are signed, but our register access macros operate on unsigned
+/// values. To avoid bugs, Pstate register fields should always be extracted
+/// to a variable of type Pstate. If the size of Pstate variables ever
+/// changes we will have to revisit this convention.
+typedef int8_t Pstate;
+
+/// A DPLL frequency code
+///
+/// DPLL frequency codes moved from 8 to 9 bits going from P7 to P8
+typedef uint16_t DpllCode;
+
+/// A VRM11 VID code
+typedef uint8_t Vid11;
+
+#endif /* __ASSEMBLER__ */
+
+/// The minimum Pstate
+#define PSTATE_MIN -128
+
+/// The maximum Pstate
+#define PSTATE_MAX 127
+
+/// The minimum \e legal DPLL frequency code
+///
+/// This is ~1GHz with a 33.3MHz tick frequency.
+#define DPLL_MIN 0x01e
+
+/// The maximum DPLL frequency code
+#define DPLL_MAX 0x1ff
+
+/// The minimum \a legal (non-power-off) VRM11 VID code
+#define VID11_MIN 0x02
+
+/// The maximum \a legal (non-power-off) VRM11 VID code
+#define VID11_MAX 0xfd
+
+
+////////////////////////////////////////////////////////////////////////////
+// PCB
+////////////////////////////////////////////////////////////////////////////
+
+/// Convert a core chiplet 0 SCOM address to the equivalent address for any
+/// other core chiplet.
+///
+/// Note that it is unusual to address core chiplet SCOMs directly. Normally
+/// this is done as part of a GPE program where the program iterates over core
+/// chiplets, using the chiplet-0 address + a programmable offset held in a
+/// chiplet address register. Therefore the only address macro defined is the
+/// chiplet-0 address. This macro is used for the rare cases of explicit
+/// getscom()/ putscom() to a particular chiplet.
+
+#define CORE_CHIPLET_ADDRESS(addr, core) ((addr) + ((core) << 24))
+
+// PCB/PMC interrupt packet constants
+
+#define PCB_INTERRUPT_PACKET_PERVASIVE 0x0
+#define PCB_INTERRUPT_PACKET_POWER_MANAGEMENT 0x7
+
+#define PMC_INTERRUPT_TYPE_PSTATE 0x0
+#define PMC_INTERRUPT_TYPE_IDLE 0x1
+#define PMC_INTERRUPT_TYPE_NOTIFY 0x2
+
+#define PMC_INTERRUPT_SLEEP_EXIT 0x2
+#define PMC_INTERRUPT_WINKLE_EXIT 0x3
+#define PMC_INTERRUPT_SLEEP_ENTRY 0x6
+#define PMC_INTERRUPT_WINKLE_ENTRY 0x7
+
+// Reserved #define PMC_INTERRUPT_NAP_EXIT 0x1
+// Reserved #define PMC_INTERRUPT_DOZE_ENTRY 0x4
+// Reserved #define PMC_INTERRUPT_NAP_ENTRY 0x5
+
+#define PMC_INTERRUPT_PMAX_SYNC 0x1
+#define PMC_INTERRUPT_GPSA_ACK 0x2
+#define PMC_INTERRUPT_DPLL_ERROR 0x3 // Spec says "placeholder"
+
+// PCB Error codes
+
+#define PCB_ERROR_NONE 0
+#define PCB_ERROR_RESOURCE_OCCUPIED 1
+#define PCB_ERROR_CHIPLET_OFFLINE 2
+#define PCB_ERROR_PARTIAL_GOOD 3
+#define PCB_ERROR_ADDRESS_ERROR 4
+#define PCB_ERROR_CLOCK_ERROR 5
+#define PCB_ERROR_PACKET_ERROR 6
+#define PCB_ERROR_TIMEOUT 7
+
+// PCB Multicast modes
+
+#define PCB_MULTICAST_OR 0
+#define PCB_MULTICAST_AND 1
+#define PCB_MULTICAST_SELECT 2
+#define PCB_MULTICAST_COMPARE 4
+#define PCB_MULTICAST_WRITE 5
+
+/// \defgroup pcb_multicast_groups PCB Multicast Groups
+///
+/// Technically the multicast groups are programmable; This is the multicast
+/// grouping established by proc_sbe_chiplet_init().
+///
+/// - Group 0 : All functional chiplets (PRV PB XBUS ABUS PCIE TPCEX)
+/// - Group 1 : All functional EX chiplets (no cores)
+/// - Group 2 : All functional EX chiplets (core only)
+/// - Group 3 : All functional chiplets except pervasive (PRV)
+///
+/// @{
+
+#define MC_GROUP_ALL 0
+#define MC_GROUP_EX 1
+#define MC_GROUP_EX_CORE 2
+#define MC_GROUP_ALL_BUT_PRV 3
+
+/// @}
+
+
+/// Convert any SCOM address to a multicast address
+#define MC_ADDRESS(address, group, mode) \
+ (((address) & 0x00ffffff) | ((0x40 | ((mode) << 3) | (group)) << 24))
+
+
+
+////////////////////////////////////////////////////////////////////////////
+// PBA
+////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////
+// Macros for fields of PBA_MODECTL
+////////////////////////////////////
+
+/// The 64KB OCI HTM marker space is enabled by default at 0x40070000
+///
+/// See the comments for occhw_trace.h
+
+#define PBA_OCI_MARKER_BASE 0x40070000
+
+
+// SSX Kernel reserved trace addresses, see occhw_trace.h.
+
+#define SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE 0xf000
+#define SSX_TRACE_CRITICAL_IRQ_EXIT_BASE 0xf100
+#define SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE 0xf200
+#define SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE 0xf300
+#define SSX_TRACE_THREAD_SWITCH_BASE 0xf400
+#define SSX_TRACE_THREAD_SLEEP_BASE 0xf500
+#define SSX_TRACE_THREAD_WAKEUP_BASE 0xf600
+#define SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE 0xf700
+#define SSX_TRACE_THREAD_SEMAPHORE_POST_BASE 0xf800
+#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE 0xf900
+#define SSX_TRACE_THREAD_SUSPENDED_BASE 0xfa00
+#define SSX_TRACE_THREAD_DELETED_BASE 0xfb00
+#define SSX_TRACE_THREAD_COMPLETED_BASE 0xfc00
+#define SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE 0xfd00
+#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE 0xfe00
+#define SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE 0xff00
+
+
+// Please keep the string definitions up to date as they are used for
+// reporting in the Simics simulation.
+
+#define SSX_TRACE_STRINGS(var) \
+ const char* var[16] = { \
+ "Critical IRQ Entry ", \
+ "Critical IRQ Exit ", \
+ "Noncritical IRQ Entry ", \
+ "Noncritical IRQ Exit ", \
+ "Thread Switch ", \
+ "Thread Blocked : Sleep ", \
+ "Thread Unblocked : Wakeup ", \
+ "Thread Blocked : Semaphore ", \
+ "Thread Unblocked : Semaphore ", \
+ "Thread Unblocked : Sem. Timeout", \
+ "Thread Suspended ", \
+ "Thread Deleted ", \
+ "Thread Completed ", \
+ "Thread Mapped Runnable ", \
+ "Thread Mapped Semaphore Pend. ", \
+ "Thread Mapped Sleeping ", \
+ };
+
+
+// PBA transaction sizes for the block copy engines
+
+#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0
+#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1
+#define PBA_BCE_OCI_TRANSACTION_8_BYTES 2
+
+
+// PBAX communication channel constants
+
+#define PBAX_CHANNELS 2
+
+#define PBAX_INTR_ACTION_FULL 0
+#define PBAX_INTR_ACTION_NOT_FULL 1
+#define PBAX_INTR_ACTION_EMPTY 2
+#define PBAX_INTR_ACTION_NOT_EMPTY 3
+
+
+// PBA Write Buffer fields
+
+#define PBA_WBUFVALN_STATUS_EMPTY 0x01
+#define PBA_WBUFVALN_STATUS_GATHERING 0x02
+#define PBA_WBUFVALN_STATUS_WAIT 0x04
+#define PBA_WBUFVALN_STATUS_WRITING 0x08
+#define PBA_WBUFVALN_STATUS_CRESPERR 0x10
+
+
+////////////////////////////////////////////////////////////////////////////
+// VRM
+////////////////////////////////////////////////////////////////////////////
+
+// These are the command types recognized by the VRMs
+
+#define VRM_WRITE_VOLTAGE 0x0
+#define VRM_READ_STATE 0xc
+#define VRM_READ_VOLTAGE 0x3
+
+// Voltage rail designations for the read voltage command
+#define VRM_RD_VDD_RAIL 0x0
+#define VRM_RD_VCS_RAIL 0x1
+
+
+////////////////////////////////////////////////////////////////////////////
+// OHA
+////////////////////////////////////////////////////////////////////////////
+
+// Power proxy trace record idle state encodings. These encodings are unique
+// to the Power proxy trace record.
+
+#define PPT_IDLE_NON_IDLE 0x0
+#define PPT_IDLE_NAP 0x1
+#define PPT_IDLE_LIGHT_SLEEP 0x2
+#define PPT_IDLE_FAST_SLEEP 0x3
+#define PPT_IDLE_DEEP_SLEEP 0x4
+#define PPT_IDLE_LIGHT_WINKLE 0x5
+#define PPT_IDLE_FAST_WINKLE 0x6
+#define PPT_IDLE_DEEP_WINKLE 0x7
+
+
+////////////////////////////////////////////////////////////////////////////
+// PC
+////////////////////////////////////////////////////////////////////////////
+
+// SPRC numbers for PC counters. The low-order 3 bits are always defined as
+// 0. The address can also be modified by OR-ing in 0x400 to indicate
+// auto-increment addressing. Note that the frequency-sensitivity counters
+// are called "workrate" counters in the hardware documentation.
+//
+// Notes on the throttle counters:
+//
+// SPRN_IFU_THROTTLE_COUNTER
+// Cycles the IFU throttle was actually blocking fetch
+//
+// <= if_pc_didt_throttle_blocked
+//
+// SPRN_ISU_THROTTLE_COUNTER
+// Cycles that ISU throttle was active and modeably IFU throttle request
+// was not
+//
+// <= sd_pc_uthrottle_active AND
+// (NOT scom_isuonly_count_mode OR NOT trigger_didt_throttle)
+//
+// SPRN_IFU_ACTIVE_COUNTER
+// Cycles that IFU throttle active input is asserted
+//
+// <= if_pc_didt_throttle_active
+
+
+/// \note The OCC SPRC/SPRD hardware has a bug that makes it such that the OCC
+/// SPRC increments whenever the OCC SPRD is accessed, regardless of the
+/// setting of the SPRN_PC_AUTOINCREMENT bit. This bug won't be fixed.
+
+#define SPRN_CORE_INSTRUCTION_DISPATCH 0x200
+#define SPRN_CORE_INSTRUCTION_COMPLETE 0x208
+#define SPRN_CORE_FREQUENCY_SENSITIVITY_BUSY 0x210
+#define SPRN_CORE_FREQUENCY_SENSITIVITY_FINISH 0x218
+#define SPRN_CORE_RUN_CYCLE 0x220
+#define SPRN_CORE_RAW_CYCLE 0x228
+#define SPRN_CORE_MEM_HIER_A 0x230
+#define SPRN_CORE_MEM_HIER_B 0x238
+#define SPRN_CORE_MEM_C_LPAR(p) (0x240 + (8 * (p)))
+#define SPRN_WEIGHTED_INSTRUCTION_PROCESSING 0x260
+#define SPRN_WEIGHTED_GPR_REGFILE_ACCESS 0x268
+#define SPRN_WEIGHTED_VRF_REGFILE_ACCESS 0x270
+#define SPRN_WEIGHTED_FLOATING_POINT_ISSUE 0x278
+#define SPRN_WEIGHTED_CACHE_READ 0x280
+#define SPRN_WEIGHTED_CACHE_WRITE 0x288
+#define SPRN_WEIGHTED_ISSUE 0x290
+#define SPRN_WEIGHTED_CACHE_ACCESS 0x298
+#define SPRN_WEIGHTED_VSU_ISSUE 0x2a0
+#define SPRN_WEIGHTED_FXU_ISSUE 0x2a8
+
+#define SPRN_THREAD_RUN_CYCLES(t) (0x2b0 + (0x20 * (t)))
+#define SPRN_THREAD_INSTRUCTION_COMPLETE(t) (0x2b8 + (0x20 * (t)))
+#define SPRN_THREAD_MEM_HIER_A(t) (0x2c0 + (0x20 * (t)))
+#define SPRN_THREAD_MEM_HIER_B(t) (0x2c8 + (0x20 * (t)))
+
+#define SPRN_IFU_THROTTLE_COUNTER 0x3b0
+#define SPRN_ISU_THROTTLE_COUNTER 0x3b8
+#define SPRN_IFU_ACTIVE_COUNTER 0x3c0
+
+#define SPRN_PC_AUTOINCREMENT 0x400
+
+
+////////////////////////////////////////////////////////////////////////////
+// Centaur
+////////////////////////////////////////////////////////////////////////////
+
+// DIMM sensor status codes
+
+/// The next sampling period began before this sensor was read or the master
+/// enable is off, or the individual sensor is disabled. If the subsequent
+/// read completes on time, this will return to valid reading. Sensor data may
+/// be accurate, but stale. If due to a stall, the StallError FIR will be
+/// set.
+#define DIMM_SENSOR_STATUS_STALLED 0
+
+/// The sensor data was not returned correctly either due to parity
+/// error or PIB bus error code. Will return to valid if the next PIB
+/// access to this sensor is valid, but a FIR will be set; Refer to FIR
+/// for exact error. Sensor data should not be considered valid while
+/// this code is present.
+#define DIMM_SENSOR_STATUS_ERROR 1
+
+/// Sensor data is valid, and has been valid since the last time this
+/// register was read.
+#define DIMM_SENSOR_STATUS_VALID_OLD 2
+
+/// Sensor data is valid and has not yet been read by a SCOM. The status code
+/// return to DIMM_SENSOR_STATUS_VALID_OLD after this register is read.
+#define DIMM_SENSOR_STATUS_VALID_NEW 3
+
+
+/// OCCHW common panic codes
+#define OCCHW_INSTANCE_MISMATCH 0x00622400
+#define OCCHW_IRQ_ROUTING_ERROR 0x00622401
+#define OCCHW_XIR_INVALID_POINTER 0x00622402
+#define OCCHW_XIR_INVALID_GPE 0x00622403
+
+
+#endif /* __OCCHW_COMMON_H__ */
diff --git a/src/include/occhw_interrupts.h b/src/include/occhw_interrupts.h
new file mode 100644
index 0000000..7f27594
--- /dev/null
+++ b/src/include/occhw_interrupts.h
@@ -0,0 +1,293 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/occhw_interrupts.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __OCCHW_INTERRUPTS_H__
+#define __OCCHW_INTERRUPTS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occ_interrupts.h
+/// \brief Interrupt assignments and macros for the OCC
+///
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif
+
+////////////////////////////////////////////////////////////////////////////
+// IRQ
+////////////////////////////////////////////////////////////////////////////
+
+// The OCB interrupt controller consists of 2 x 32-bit controllers. Unlike
+// PPC ASICs, the OCB controllers are _not_ cascaded. The combined
+// controllers are presented to the application as if there were a single
+// 64-bit interrupt controller, while the code underlying the abstraction
+// manipulates the 2 x 32-bit controllers independently.
+//
+// Note that the bits named *RESERVED* are actually implemented in the
+// controller, but the interrupt input is tied low. That means they can also
+// be used as IPI targets. Logical bits 32..63 are not implemented.
+
+#define OCCHW_IRQ_DEBUGGER 0 /* 0x00 */
+#define OCCHW_IRQ_TRACE_TRIGGER 1 /* 0x01 */
+#define OCCHW_IRQ_OCC_ERROR 2 /* 0x02 */
+#define OCCHW_IRQ_PBA_ERROR 3 /* 0x03 */
+#define OCCHW_IRQ_SRT_ERROR 4 /* 0x04 */
+#define OCCHW_IRQ_GPE0_HALT 5 /* 0x05 */
+#define OCCHW_IRQ_GPE1_HALT 6 /* 0x06 */
+#define OCCHW_IRQ_GPE2_HALT 7 /* 0x07 */
+#define OCCHW_IRQ_GPE3_HALT 8 /* 0x08 */
+#define OCCHW_IRQ_PPC405_HALT 9 /* 0x09 */
+#define OCCHW_IRQ_OCB_ERROR 10 /* 0x0a */
+#define OCCHW_IRQ_SPIPSS_ERROR 11 /* 0x0b */
+#define OCCHW_IRQ_CHECK_STOP_PPC405 12 /* 0x0c */
+#define OCCHW_IRQ_CHECK_STOP_GPE0 13 /* 0x0d */
+#define OCCHW_IRQ_CHECK_STOP_GPE1 14 /* 0x0e */
+#define OCCHW_IRQ_CHECK_STOP_GPE2 15 /* 0x0f */
+#define OCCHW_IRQ_CHECK_STOP_GPE3 16 /* 0x10 */
+#define OCCHW_IRQ_OCC_MALF_ALERT 17 /* 0x11 */
+#define OCCHW_IRQ_ADU_MALF_ALERT 18 /* 0x12 */
+#define OCCHW_IRQ_EXTERNAL_TRAP 19 /* 0x13 */
+#define OCCHW_IRQ_IVRM_PVREF_ERROR 20 /* 0x14 */
+#define OCCHW_IRQ_OCC_TIMER0 21 /* 0x15 */
+#define OCCHW_IRQ_OCC_TIMER1 22 /* 0x16 */
+#define OCCHW_IRQ_HALT_PSTATES 23 /* 0x17 */
+#define OCCHW_IRQ_IPI_SCOM 24 /* 0x18 */
+#define OCCHW_IRQ_IPI0_HI_PRIORITY 25 /* 0x19 */
+#define OCCHW_IRQ_IPI1_HI_PRIORITY 26 /* 0x1a */
+#define OCCHW_IRQ_IPI2_HI_PRIORITY 27 /* 0x1b */
+#define OCCHW_IRQ_IPI3_HI_PRIORITY 28 /* 0x1c */
+#define OCCHW_IRQ_IPI4_HI_PRIORITY 29 /* 0x1d */
+#define OCCHW_IRQ_ADCFSM_ONGOING 30 /* 0x1e */
+#define OCCHW_IRQ_RESERVED_31 31 /* 0x1f */
+
+#define OCCHW_IRQ_PBAX_OCC_SEND 32 /* 0x20 */
+#define OCCHW_IRQ_PBAX_OCC_PUSH0 33 /* 0x21 */
+#define OCCHW_IRQ_PBAX_OCC_PUSH1 34 /* 0x22 */
+#define OCCHW_IRQ_PBA_BCDE_ATTN 35 /* 0x23 */
+#define OCCHW_IRQ_PBA_BCUE_ATTN 36 /* 0x24 */
+#define OCCHW_IRQ_STRM0_PULL 37 /* 0x25 */
+#define OCCHW_IRQ_STRM0_PUSH 38 /* 0x26 */
+#define OCCHW_IRQ_STRM1_PULL 39 /* 0x27 */
+#define OCCHW_IRQ_STRM1_PUSH 40 /* 0x28 */
+#define OCCHW_IRQ_STRM2_PULL 41 /* 0x29 */
+#define OCCHW_IRQ_STRM2_PUSH 42 /* 0x2a */
+#define OCCHW_IRQ_STRM3_PULL 43 /* 0x2b */
+#define OCCHW_IRQ_STRM3_PUSH 44 /* 0x2c */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING 45 /* 0x2d */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING 46 /* 0x2e */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING 47 /* 0x2f */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING 48 /* 0x30 */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING 49 /* 0x31 */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING 50 /* 0x32 */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING 51 /* 0x33 */
+#define OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING 52 /* 0x34 */
+#define OCCHW_IRQ_PMC_O2S_0A_ONGOING 53 /* 0x35 */
+#define OCCHW_IRQ_PMC_O2S_0B_ONGOING 54 /* 0x36 */
+#define OCCHW_IRQ_PMC_O2S_1A_ONGOING 55 /* 0x37 */
+#define OCCHW_IRQ_PMC_O2S_1B_ONGOING 56 /* 0x38 */
+#define OCCHW_IRQ_PSSBRIDGE_ONGOING 57 /* 0x39 */
+#define OCCHW_IRQ_IPI0_LO_PRIORITY 58 /* 0x3a */
+#define OCCHW_IRQ_IPI1_LO_PRIORITY 59 /* 0x3b */
+#define OCCHW_IRQ_IPI2_LO_PRIORITY 60 /* 0x3c */
+#define OCCHW_IRQ_IPI3_LO_PRIORITY 61 /* 0x3d */
+#define OCCHW_IRQ_IPI4_LO_PRIORITY 62 /* 0x3e */
+#define OCCHW_IRQ_RESERVED_63 63 /* 0x3f */
+
+/// This constant is used to define the size of the table of interrupt handler
+/// structures as well as a limit for error checking. The entire 64-bit
+/// vector is now in use.
+
+#define OCCHW_IRQS 64
+
+// Please keep the string definitions up-to-date as they are used for
+// reporting in the Simics simulation.
+
+#define OCCHW_IRQ_STRINGS(var) \
+ const char* var[OCCHW_IRQS] = { \
+ "OCCHW_IRQ_DEBUGGER", \
+ "OCCHW_IRQ_TRACE_TRIGGER", \
+ "OCCHW_IRQ_OCC_ERROR", \
+ "OCCHW_IRQ_PBA_ERROR", \
+ "OCCHW_IRQ_SRT_ERROR", \
+ "OCCHW_IRQ_GPE0_HALT", \
+ "OCCHW_IRQ_GPE1_HALT", \
+ "OCCHW_IRQ_GPE2_HALT", \
+ "OCCHW_IRQ_GPE3_HALT", \
+ "OCCHW_IRQ_PPC405_HALT", \
+ "OCCHW_IRQ_OCB_ERROR", \
+ "OCCHW_IRQ_SPIPSS_ERROR", \
+ "OCCHW_IRQ_CHECK_STOP_PPC405", \
+ "OCCHW_IRQ_CHECK_STOP_GPE0", \
+ "OCCHW_IRQ_CHECK_STOP_GPE1", \
+ "OCCHW_IRQ_CHECK_STOP_GPE2", \
+ "OCCHW_IRQ_CHECK_STOP_GPE3", \
+ "OCCHW_IRQ_OCC_MALF_ALERT", \
+ "OCCHW_IRQ_ADU_MALF_ALERT", \
+ "OCCHW_IRQ_EXTERNAL_TRAP", \
+ "OCCHW_IRQ_IVRM_PVREF_ERROR", \
+ "OCCHW_IRQ_OCC_TIMER0", \
+ "OCCHW_IRQ_OCC_TIMER1", \
+ "OCCHW_IRQ_HALT_PSTATES", \
+ "OCCHW_IRQ_IPI_SCOM", \
+ "OCCHW_IRQ_IPI0_HI_PRIORITY", \
+ "OCCHW_IRQ_IPI1_HI_PRIORITY", \
+ "OCCHW_IRQ_IPI2_HI_PRIORITY", \
+ "OCCHW_IRQ_IPI3_HI_PRIORITY", \
+ "OCCHW_IRQ_IPI4_HI_PRIORITY", \
+ "OCCHW_IRQ_ADCFSM_ONGOING", \
+ "OCCHW_IRQ_RESERVED_31", \
+ "OCCHW_IRQ_PBAX_OCC_SEND", \
+ "OCCHW_IRQ_PBAX_OCC_PUSH0", \
+ "OCCHW_IRQ_PBAX_OCC_PUSH1", \
+ "OCCHW_IRQ_PBA_BCDE_ATTN", \
+ "OCCHW_IRQ_PBA_BCUE_ATTN", \
+ "OCCHW_IRQ_STRM0_PULL", \
+ "OCCHW_IRQ_STRM0_PUSH", \
+ "OCCHW_IRQ_STRM1_PULL", \
+ "OCCHW_IRQ_STRM1_PUSH", \
+ "OCCHW_IRQ_STRM2_PULL", \
+ "OCCHW_IRQ_STRM2_PUSH", \
+ "OCCHW_IRQ_STRM3_PULL", \
+ "OCCHW_IRQ_STRM3_PUSH", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING", \
+ "OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING", \
+ "OCCHW_IRQ_PMC_O2S_0A_ONGOING", \
+ "OCCHW_IRQ_PMC_O2S_0B_ONGOING", \
+ "OCCHW_IRQ_PMC_O2S_1A_ONGOING", \
+ "OCCHW_IRQ_PMC_O2S_1B_ONGOING", \
+ "OCCHW_IRQ_PSSBRIDGE_ONGOING", \
+ "OCCHW_IRQ_IPI0_LO_PRIORITY", \
+ "OCCHW_IRQ_IPI1_LO_PRIORITY", \
+ "OCCHW_IRQ_IPI2_LO_PRIORITY", \
+ "OCCHW_IRQ_IPI3_LO_PRIORITY", \
+ "OCCHW_IRQ_IPI4_LO_PRIORITY", \
+ "OCCHW_IRQ_RESERVED_63" \
+ };
+
+
+/// Routing codes for OCB interrupts
+#define OCCHW_IRQ_TARGET_ID_405_NONCRIT 0
+#define OCCHW_IRQ_TARGET_ID_405_CRIT 1
+#define OCCHW_IRQ_TARGET_ID_405_UNCOND 2
+#define OCCHW_IRQ_TARGET_ID_405_DEBUG 3
+#define OCCHW_IRQ_TARGET_ID_GPE0 4
+#define OCCHW_IRQ_TARGET_ID_GPE1 5
+#define OCCHW_IRQ_TARGET_ID_GPE2 6
+#define OCCHW_IRQ_TARGET_ID_GPE3 7
+
+// OCB interrupt type values (level or edge)
+#define OCCHW_IRQ_TYPE_LEVEL 0
+#define OCCHW_IRQ_TYPE_EDGE 1
+
+// OCB interrupt polarity values (high or low, rising falling)
+#define OCCHW_IRQ_POLARITY_LO 0
+#define OCCHW_IRQ_POLARITY_FALLING 0
+#define OCCHW_IRQ_POLARITY_HI 1
+#define OCCHW_IRQ_POLARITY_RISING 1
+
+// OCB interrupt mask values (masked or enabled)
+#define OCCHW_IRQ_MASKED 0
+#define OCCHW_IRQ_ENABLED 1
+
+// Note: All standard-product IPI uses are declared here to avoid conflicts
+// Validation- and lab-only IPI uses are documented in validation.h
+
+/// The deferred callback queue interrupt
+///
+/// This IPI is reserved for use of the async deferred callback mechanism.
+/// This IPI is used by both critical and noncritical async handlers to
+/// activate the deferred callback mechanism.
+#define OCCHW_IRQ_ASYNC_IPI OCCHW_IRQ_IPI4_LO_PRIORITY
+
+
+#ifndef __ASSEMBLER__
+
+/// This expression recognizes only those IRQ numbers that have named
+/// (non-reserved) interrupts in the OCB interrupt controller.
+
+// There are so many invalid interrupts now that it's a slight improvement in
+// code size to let the compiler optimize the invalid IRQs to a bit mask for
+// the comparison.
+
+#define OCCHW_IRQ_VALID(irq) \
+ ({unsigned __irq = (unsigned)(irq); \
+ ((__irq < OCCHW_IRQS) && \
+ ((OCCHW_IRQ_MASK64(__irq) & \
+ (OCCHW_IRQ_MASK64(OCCHW_IRQ_RESERVED_31) | \
+ OCCHW_IRQ_MASK64(OCCHW_IRQ_RESERVED_63))) == 0));})
+
+/// This is a 32-bit mask, with big-endian bit (irq % 32) set.
+#define OCCHW_IRQ_MASK32(irq) (((uint32_t)0x80000000) >> ((irq) % 32))
+
+/// This is a 64-bit mask, with big-endian bit 'irq' set.
+#define OCCHW_IRQ_MASK64(irq) (0x8000000000000000ull >> (irq))
+
+#else
+
+//assembler version of OCCHW_IRQ_MASK32
+#define OCCHW_IRQ_MASK32(irq) ((0x80000000) >> ((irq) % 32))
+
+#endif /* __ASSEMBLER__ */
+
+#ifndef __ASSEMBLER__
+
+// These macros select OCB interrupt controller registers based on the IRQ
+// number.
+
+#define OCCHW_OIMR_CLR(irq) (((irq) & 0x20) ? OCB_OIMR1_CLR : OCB_OIMR0_CLR)
+#define OCCHW_OIMR_OR(irq) (((irq) & 0x20) ? OCB_OIMR1_OR : OCB_OIMR0_OR)
+
+#define OCCHW_OISR(irq) (((irq) & 0x20) ? OCB_OISR1 : OCB_OISR0)
+#define OCCHW_OISR_CLR(irq) (((irq) & 0x20) ? OCB_OISR1_CLR : OCB_OISR0_CLR)
+#define OCCHW_OISR_OR(irq) (((irq) & 0x20) ? OCB_OISR1_OR : OCB_OISR0_OR)
+
+#define OCCHW_OIEPR(irq) (((irq) & 0x20) ? OCB_OIEPR1 : OCB_OIEPR0)
+#define OCCHW_OIEPR_OR(irq) (((irq) & 0x20) ? OCB_OIEPR1_OR : OCB_OIEPR0_OR)
+#define OCCHW_OIEPR_CLR(irq) (((irq) & 0x20) ? OCB_OIEPR1_CLR : OCB_OIEPR0_CLR)
+#define OCCHW_OITR(irq) (((irq) & 0x20) ? OCB_OITR1 : OCB_OITR0)
+#define OCCHW_OITR_OR(irq) (((irq) & 0x20) ? OCB_OITR1_OR : OCB_OITR0_OR)
+#define OCCHW_OITR_CLR(irq) (((irq) & 0x20) ? OCB_OITR1_CLR : OCB_OITR0_CLR)
+
+#define OCCHW_OIRRA(irq) (((irq) & 0x20) ? OCB_OIRR1A : OCB_OIRR0A)
+#define OCCHW_OIRRA_OR(irq) (((irq) & 0x20) ? OCB_OIRR1A_OR : OCB_OIRR0A_OR)
+#define OCCHW_OIRRA_CLR(irq) (((irq) & 0x20) ? OCB_OIRR1A_CLR : OCB_OIRR0A_CLR)
+#define OCCHW_OIRRB(irq) (((irq) & 0x20) ? OCB_OIRR1B : OCB_OIRR0B)
+#define OCCHW_OIRRB_OR(irq) (((irq) & 0x20) ? OCB_OIRR1B_OR : OCB_OIRR0B_OR)
+#define OCCHW_OIRRB_CLR(irq) (((irq) & 0x20) ? OCB_OIRR1B_CLR : OCB_OIRR0B_CLR)
+#define OCCHW_OIRRC(irq) (((irq) & 0x20) ? OCB_OIRR1C : OCB_OIRR0C)
+#define OCCHW_OIRRC_OR(irq) (((irq) & 0x20) ? OCB_OIRR1C_OR : OCB_OIRR0C_OR)
+#define OCCHW_OIRRC_CLR(irq) (((irq) & 0x20) ? OCB_OIRR1C_CLR : OCB_OIRR0C_CLR)
+#endif /* __ASSEMBLER__ */
+
+#endif /* __OCCHW_INTERRUPTS_H__ */
diff --git a/src/include/occhw_irq_config.h b/src/include/occhw_irq_config.h
new file mode 100644
index 0000000..ba0655a
--- /dev/null
+++ b/src/include/occhw_irq_config.h
@@ -0,0 +1,280 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/occhw_irq_config.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __OCCHW_IRQ_CONFIG_H__
+#define __OCCHW_IRQ_CONFIG_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_irq_config.h
+/// \brief Contains data and macros pertaining to external interrupt routing
+/// and configuration for processors running in the OCC complex.
+///
+
+/// Designate an instance (GPE 0-3 or 405) to own the routing registers
+/// 0-3 -> GPE, 4 -> 405
+#ifndef OCCHW_IRQ_ROUTE_OWNER
+#define OCCHW_IRQ_ROUTE_OWNER 0
+#endif
+
+/// This macro should be defined in the pk_app_cfg.h file for external interrupts
+/// that are to be used by the OCC instance. If not defined elsewhere then
+/// interrupts owned by this instance will have the default configuration and be
+/// masked.
+#ifndef OCCHW_EXT_IRQS_CONFIG
+#define OCCHW_EXT_IRQS_CONFIG
+#endif
+
+#ifndef __ASSEMBLER__
+/// These globals are statically initialized elsewhere
+extern uint64_t g_ext_irqs_routeA;
+extern uint64_t g_ext_irqs_routeB;
+extern uint64_t g_ext_irqs_routeC;
+extern uint64_t g_ext_irqs_type;
+extern uint64_t g_ext_irqs_owned;
+extern uint64_t g_ext_irqs_polarity;
+extern uint64_t g_ext_irqs_enable;
+
+#define OCCHW_IRQ_OWNED(irq) ((OCCHW_IRQ_MASK64(irq) & g_ext_irqs_owned) != 0)
+
+#endif
+
+/// Convert a GPE instance ID to an IRQ target ID
+#define OCCHW_GPEID_2_IRQTARGET(gpe_id) (gpe_id + OCCHW_IRQ_TARGET_ID_GPE0)
+
+/// Add a pseudo target to indicate that an interrupt is not owned by anyone
+#define OCCHW_IRQ_TARGET_ID_NONE 8
+
+/// Default interrupt routing table
+#ifndef OCCHW_IRQ_ROUTES
+#define OCCHW_IRQ_ROUTES \
+OCCHW_IRQ_DEBUGGER OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_TRACE_TRIGGER OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_OCC_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PBA_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_SRT_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_GPE0_HALT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_GPE1_HALT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_GPE2_HALT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_GPE3_HALT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PPC405_HALT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_OCB_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_SPIPSS_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_CHECK_STOP_PPC405 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_CHECK_STOP_GPE0 OCCHW_IRQ_TARGET_ID_GPE0 \
+OCCHW_IRQ_CHECK_STOP_GPE1 OCCHW_IRQ_TARGET_ID_GPE1 \
+OCCHW_IRQ_CHECK_STOP_GPE2 OCCHW_IRQ_TARGET_ID_GPE2 \
+OCCHW_IRQ_CHECK_STOP_GPE3 OCCHW_IRQ_TARGET_ID_GPE3 \
+OCCHW_IRQ_OCC_MALF_ALERT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_ADU_MALF_ALERT OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_EXTERNAL_TRAP OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_IVRM_PVREF_ERROR OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_OCC_TIMER0 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_OCC_TIMER1 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_HALT_PSTATES OCCHW_IRQ_TARGET_ID_GPE3 \
+OCCHW_IRQ_IPI_SCOM OCCHW_IRQ_TARGET_ID_GPE3 \
+OCCHW_IRQ_IPI0_HI_PRIORITY OCCHW_IRQ_TARGET_ID_GPE0 \
+OCCHW_IRQ_IPI1_HI_PRIORITY OCCHW_IRQ_TARGET_ID_GPE1 \
+OCCHW_IRQ_IPI2_HI_PRIORITY OCCHW_IRQ_TARGET_ID_GPE2 \
+OCCHW_IRQ_IPI3_HI_PRIORITY OCCHW_IRQ_TARGET_ID_GPE3 \
+OCCHW_IRQ_IPI4_HI_PRIORITY OCCHW_IRQ_TARGET_ID_405_CRIT \
+OCCHW_IRQ_ADCFSM_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_RESERVED_31 OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PBAX_OCC_SEND OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_PBAX_OCC_PUSH0 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_PBAX_OCC_PUSH1 OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_PBA_BCDE_ATTN OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_PBA_BCUE_ATTN OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM0_PULL OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM0_PUSH OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM1_PULL OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM1_PUSH OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM2_PULL OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM2_PUSH OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM3_PULL OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_STRM3_PUSH OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE0_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_O2S_0A_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_O2S_0B_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_O2S_1A_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PMC_O2S_1B_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_PSSBRIDGE_ONGOING OCCHW_IRQ_TARGET_ID_NONE \
+OCCHW_IRQ_IPI0_LO_PRIORITY OCCHW_IRQ_TARGET_ID_GPE0 \
+OCCHW_IRQ_IPI1_LO_PRIORITY OCCHW_IRQ_TARGET_ID_GPE1 \
+OCCHW_IRQ_IPI2_LO_PRIORITY OCCHW_IRQ_TARGET_ID_GPE2 \
+OCCHW_IRQ_IPI3_LO_PRIORITY OCCHW_IRQ_TARGET_ID_GPE3 \
+OCCHW_IRQ_IPI4_LO_PRIORITY OCCHW_IRQ_TARGET_ID_405_NONCRIT \
+OCCHW_IRQ_RESERVED_63 OCCHW_IRQ_TARGET_ID_NONE
+#endif
+
+// convenience macros for retrieving the IPI IRQ numbers for an OCC instance
+// NOTE: this assumes the IPI IRQs are routed as shown above
+#define OCCHW_IPI_LO_IRQ(instance_id) (OCCHW_IRQ_IPI0_LO_PRIORITY + instance_id)
+#define OCCHW_IPI_HI_IRQ(instance_id) (OCCHW_IRQ_IPI0_HI_PRIORITY + instance_id)
+
+#ifdef __ASSEMBLER__
+/// These macros aid in the initialization of the external interrupt globals. I would
+/// prefer to use CPP macros, but they don't support recursive macros which I use to
+/// convert the variable number of interrupts that a processor can control into static
+/// bitmaps used by __hwmacro_setup() at runtime.
+
+
+ //helper macro for setting up the irq configuration bitmaps for all entities in the occ complex
+ .macro .occhw_irq_config irq_num=-1 irq_type=-1 irq_polarity=-1 irq_mask=-1 parms:vararg
+ .if (( \irq_num == -1 ) && ( \irq_type == -1 ) && ( \irq_polarity == -1 ) && ( \irq_mask == -1 ))
+ .if ( .ext_irqs_defd != .ext_irqs_owned )
+ .error "###### .occhw_irq_config: Missing configuration for one or more interrupts ######"
+ .endif
+
+ .section .sdata
+ .align 3
+ .global g_ext_irqs_type
+ .global g_ext_irqs_polarity
+ .global g_ext_irqs_enable
+ g_ext_irqs_polarity:
+ .quad .ext_irqs_polarity
+ g_ext_irqs_type:
+ .quad .ext_irqs_type
+ g_ext_irqs_enable:
+ .quad .ext_irqs_enable
+ .else
+ .if (( \irq_num < 0 ) || ( \irq_num > (OCCHW_IRQS - 1)))
+ .error "###### .occhw_irq_config: invalid irq number \irq_num ######"
+ .elseif ((.ext_irqs_owned & (1 << ( OCCHW_IRQS - 1 - \irq_num ))) == 0 )
+ .error "###### .occhw_irq_config: Attempt to configure unowned irq number \irq_num ######"
+ .elseif (.ext_irqs_defd & (1 << ( OCCHW_IRQS - 1 - \irq_num )))
+ .error "###### .occhw_irq_config: duplicate definition for irq \irq_num ######"
+ .else
+ .ext_irqs_defd = .ext_irqs_defd | (1 << ( OCCHW_IRQS - 1 - \irq_num ))
+ .endif
+
+ .if (( \irq_type < 0 ) || ( \irq_type > 1 ))
+ .error "###### .occhw_irq_config: invalid/unspecified irq type \irq_type for irq \irq_num ######"
+ .else
+ .ext_irqs_type = .ext_irqs_type | ( \irq_type << ( OCCHW_IRQS - 1 - \irq_num ))
+ .endif
+
+ .if (( \irq_polarity < 0 ) || ( \irq_polarity > 1 ))
+ .error "###### .occhw_irq_config: invalid/unspecified irq polarity ( \irq_polarity ) for irq \irq_num ######"
+ .else
+ .ext_irqs_polarity = .ext_irqs_polarity | ( \irq_polarity << ( OCCHW_IRQS - 1 - \irq_num ))
+ .endif
+
+ .if (( \irq_mask < 0 ) || ( \irq_mask > 1 ))
+ .error "###### .occhw_irq_config: invalid/unspecified irq mask ( \irq_mask ) for irq \irq_num ######"
+ .else
+ .ext_irqs_enable = .ext_irqs_enable | ( \irq_mask << ( OCCHW_IRQS - 1 - \irq_num ))
+ .endif
+
+ .occhw_irq_config \parms
+ .endif
+ .endm
+
+ //recursive helper macro for setting up the irq route bitmaps for all entities in the occ complex
+ //
+ //Once completed, g_ext_irqs_route(A,B,C) will hold the correct initialization values and
+ //g_ext_irqs_owned will hold a bitmap of interrupts owned by this OCC instance
+ .macro .occhw_irq_route irq_num=-1 irq_route=-1 parms:vararg
+ .if (( \irq_num == -1 ) && ( \irq_route == -1 ))
+ .section .sdata
+ .align 3
+ .global g_ext_irqs_routeA
+ .global g_ext_irqs_routeB
+ .global g_ext_irqs_routeC
+ .global g_ext_irqs_owned
+ g_ext_irqs_routeA:
+ .quad .ext_irqs_routeA
+ g_ext_irqs_routeB:
+ .quad .ext_irqs_routeB
+ g_ext_irqs_routeC:
+ .quad .ext_irqs_routeC
+ g_ext_irqs_owned:
+ .quad .ext_irqs_owned
+ .else
+ .if (( \irq_num < 0) || ( \irq_num > (OCCHW_IRQS - 1)))
+ .error "###### .occhw_irq_route: invalid irq number \irq_num ######"
+ .elseif .ext_irqs_defd & (1 << ( OCCHW_IRQS - 1 - \irq_num ))
+ .error "###### .occhw_irq_route: Route for irq \irq_num is already defined ######"
+ .else
+ .ext_irqs_defd = .ext_irqs_defd | (1 << ( OCCHW_IRQS - 1 - \irq_num ))
+ .endif
+
+ .if (( \irq_route < 0) || ( \irq_route > 8 ))
+ .error "###### .occhw_irq_route: route # \irq_route is invalid for irq # \irq_num ######"
+ .endif
+
+ .irq_mask = 1 << ( OCCHW_IRQS - 1 - \irq_num)
+ .if \irq_route & 4
+ .ext_irqs_routeA = .ext_irqs_routeA | .irq_mask
+ .endif
+
+ .if \irq_route & 2
+ .ext_irqs_routeB = .ext_irqs_routeB | .irq_mask
+ .endif
+
+ .if \irq_route & 1
+ .ext_irqs_routeC = .ext_irqs_routeC | .irq_mask
+ .endif
+
+ .if ( \irq_route == 8 )
+ //do nothing, this irq is not owned by any OCC processor
+ .elseif (( \irq_route < 4 ) && ( APPCFG_OCC_INSTANCE_ID == 4 ))
+ .ext_irqs_owned = .ext_irqs_owned | .irq_mask
+ .elseif ( \irq_route == (OCCHW_IRQ_TARGET_ID_GPE0 + APPCFG_OCC_INSTANCE_ID))
+ .ext_irqs_owned = .ext_irqs_owned | .irq_mask
+ .endif
+
+ .occhw_irq_route \parms
+ .endif
+ .endm
+
+ //Top level macro for generating interrupt routing/configuration globals for all entities in the occ complex
+ .macro .occhw_irq_cfg_bitmaps
+ .ext_irqs_routeA = 0
+ .ext_irqs_routeB = 0
+ .ext_irqs_routeC = 0
+ .ext_irqs_owned = 0
+ .ext_irqs_type = 0
+ .ext_irqs_polarity = 0
+ .ext_irqs_enable = 0
+ .ext_irqs_defd = 0
+ .irq_mask = 0
+ .occhw_irq_route OCCHW_IRQ_ROUTES
+ .ext_irqs_defd = 0
+ .occhw_irq_config APPCFG_EXT_IRQS_CONFIG
+ .endm
+
+#endif /*__ASSEMBLER__*/
+
+#endif /*__OCCHW_IRQ_CONFIG_H__*/
diff --git a/src/include/registers/README b/src/include/registers/README
new file mode 100644
index 0000000..5520b22
--- /dev/null
+++ b/src/include/registers/README
@@ -0,0 +1,35 @@
+files and includes are deleted:
+
+//is gone in p9, parmenantly deleted
+oha_
+
+//not within occ, never included, files deleted
+sbe_
+pibmem_
+fasti2c_
+i2cengine_
+icp_
+
+//in core domain but not in occ, commented out in occhw_core.h, files deleted
+sensors_
+pc_
+
+//in centaur but not in occ, commented out in occhw.h, files deleted
+centaur_
+mcs_
+
+//needs replacement, commented out or never included, files deleted
+pcbs_ gone but needs ppm replacement, commented out in occhw.h
+pore_ gone but needs ppe replacement, not included
+tod_ commented out in occhw.h
+
+
+//files and includes stays but needs review:
+sramctl_ stay and included in occhw_sramctl.h
+plb_arbiter_ stay and included
+pmc_ gone but needs ocb replacement, still stay and included
+pba_ needs to renew for p9, still stay and included
+ocb_ already renewed for p9
+tpc_ stay and included in occhw_id, needs renew for p9
+
+
diff --git a/src/include/registers/cme_firmware_registers.h b/src/include/registers/cme_firmware_registers.h
new file mode 100644
index 0000000..a7ae86e
--- /dev/null
+++ b/src/include/registers/cme_firmware_registers.h
@@ -0,0 +1,4363 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/cme_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CME_FIRMWARE_REGISTERS_H__
+#define __CME_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cme_firmware_registers.h
+/// \brief C register structs for the CME unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union cme_scom_lfir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppe_internal_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t sram_ue : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t bce_error : 1;
+ uint64_t spare11 : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t reserved1 : 50;
+#else
+ uint64_t reserved1 : 50;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare11 : 1;
+ uint64_t bce_error : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_ue : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_internal_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfir_t;
+
+
+
+typedef union cme_scom_lfir_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppe_internal_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t sram_ue : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t bce_error : 1;
+ uint64_t spare11 : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t reserved1 : 50;
+#else
+ uint64_t reserved1 : 50;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare11 : 1;
+ uint64_t bce_error : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_ue : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_internal_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfir_and_t;
+
+
+
+typedef union cme_scom_lfir_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppe_internal_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t sram_ue : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t bce_error : 1;
+ uint64_t spare11 : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t reserved1 : 50;
+#else
+ uint64_t reserved1 : 50;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare11 : 1;
+ uint64_t bce_error : 1;
+ uint64_t sram_scrub_err : 1;
+ uint64_t sram_ce : 1;
+ uint64_t sram_ue : 1;
+ uint64_t ppe_debug_trigger : 1;
+ uint64_t ppe_halted : 1;
+ uint64_t ppe_watchdog : 1;
+ uint64_t ppe_breakpoint_error : 1;
+ uint64_t ppe_progress_error : 1;
+ uint64_t ppe_external_error : 1;
+ uint64_t ppe_internal_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfir_or_t;
+
+
+
+typedef union cme_scom_lfirmask {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_mask : 18;
+ uint64_t reserved1 : 46;
+#else
+ uint64_t reserved1 : 46;
+ uint64_t fir_mask : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfirmask_t;
+
+
+
+typedef union cme_scom_lfirmask_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_mask : 18;
+ uint64_t reserved1 : 46;
+#else
+ uint64_t reserved1 : 46;
+ uint64_t fir_mask : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfirmask_and_t;
+
+
+
+typedef union cme_scom_lfirmask_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_mask : 18;
+ uint64_t reserved1 : 46;
+#else
+ uint64_t reserved1 : 46;
+ uint64_t fir_mask : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfirmask_or_t;
+
+
+
+typedef union cme_scom_lfiract0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_action0 : 18;
+ uint64_t reserved1 : 46;
+#else
+ uint64_t reserved1 : 46;
+ uint64_t fir_action0 : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfiract0_t;
+
+
+
+typedef union cme_scom_lfiract1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_action1 : 18;
+ uint64_t reserved1 : 46;
+#else
+ uint64_t reserved1 : 46;
+ uint64_t fir_action1 : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_lfiract1_t;
+
+
+
+typedef union cme_scom_cscr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sram_access_mode : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_inject_err : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t reserved1 : 39;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved2 : 4;
+#else
+ uint64_t reserved2 : 4;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved1 : 39;
+ uint64_t spare_6_7 : 2;
+ uint64_t ecc_inject_err : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t sram_access_mode : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_cscr_t;
+
+
+
+typedef union cme_scom_cscr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sram_access_mode : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_inject_err : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t reserved1 : 39;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved2 : 4;
+#else
+ uint64_t reserved2 : 4;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved1 : 39;
+ uint64_t spare_6_7 : 2;
+ uint64_t ecc_inject_err : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t sram_access_mode : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_cscr_clr_t;
+
+
+
+typedef union cme_scom_cscr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sram_access_mode : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_inject_err : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t reserved1 : 39;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved2 : 4;
+#else
+ uint64_t reserved2 : 4;
+ uint64_t sram_scrub_index : 13;
+ uint64_t reserved1 : 39;
+ uint64_t spare_6_7 : 2;
+ uint64_t ecc_inject_err : 1;
+ uint64_t ecc_inject_type : 1;
+ uint64_t ecc_detect_dis : 1;
+ uint64_t ecc_correct_dis : 1;
+ uint64_t sram_scrub_enable : 1;
+ uint64_t sram_access_mode : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_cscr_or_t;
+
+
+
+typedef union cme_scom_csar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 3;
+ uint64_t reserved2 : 13;
+ uint64_t sram_address : 13;
+ uint64_t reserved3 : 35;
+#else
+ uint64_t reserved3 : 35;
+ uint64_t sram_address : 13;
+ uint64_t reserved2 : 13;
+ uint64_t reserved1 : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_csar_t;
+
+
+
+typedef union cme_scom_csdr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sram_data : 64;
+#else
+ uint64_t sram_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_csdr_t;
+
+
+
+typedef union cme_scom_bcecsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t busy : 1;
+ uint64_t error : 1;
+ uint64_t start : 1;
+ uint64_t stop : 1;
+ uint64_t rnw : 1;
+ uint64_t barsel : 1;
+ uint64_t priority : 1;
+ uint64_t inject_err : 1;
+ uint64_t reserved1 : 5;
+ uint64_t type : 3;
+ uint64_t reserved2 : 1;
+ uint64_t num_blocks : 11;
+ uint64_t sbase : 12;
+ uint64_t reserved3 : 2;
+ uint64_t mbase : 22;
+#else
+ uint64_t mbase : 22;
+ uint64_t reserved3 : 2;
+ uint64_t sbase : 12;
+ uint64_t num_blocks : 11;
+ uint64_t reserved2 : 1;
+ uint64_t type : 3;
+ uint64_t reserved1 : 5;
+ uint64_t inject_err : 1;
+ uint64_t priority : 1;
+ uint64_t barsel : 1;
+ uint64_t rnw : 1;
+ uint64_t stop : 1;
+ uint64_t start : 1;
+ uint64_t error : 1;
+ uint64_t busy : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_bcecsr_t;
+
+
+
+typedef union cme_scom_bcebar0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 8;
+ uint64_t base : 36;
+ uint64_t reserved2 : 13;
+ uint64_t rd_scope : 2;
+ uint64_t wr_scope : 1;
+ uint64_t vg_target_sel : 1;
+ uint64_t size : 3;
+#else
+ uint64_t size : 3;
+ uint64_t vg_target_sel : 1;
+ uint64_t wr_scope : 1;
+ uint64_t rd_scope : 2;
+ uint64_t reserved2 : 13;
+ uint64_t base : 36;
+ uint64_t reserved1 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_bcebar0_t;
+
+
+
+typedef union cme_scom_bcebar1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 8;
+ uint64_t base : 36;
+ uint64_t reserved2 : 13;
+ uint64_t rd_scope : 2;
+ uint64_t wr_scope : 1;
+ uint64_t vg_target_sel : 1;
+ uint64_t size : 3;
+#else
+ uint64_t size : 3;
+ uint64_t vg_target_sel : 1;
+ uint64_t wr_scope : 1;
+ uint64_t rd_scope : 2;
+ uint64_t reserved2 : 13;
+ uint64_t base : 36;
+ uint64_t reserved1 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_bcebar1_t;
+
+
+
+typedef union cme_scom_qfmr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t timebase : 32;
+ uint64_t cycles : 32;
+#else
+ uint64_t cycles : 32;
+ uint64_t timebase : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_qfmr_t;
+
+
+
+typedef union cme_scom_afsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t inst_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t avg_cycle_sample : 20;
+ uint64_t reserved2 : 11;
+ uint64_t sample_valid : 1;
+#else
+ uint64_t sample_valid : 1;
+ uint64_t reserved2 : 11;
+ uint64_t avg_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t inst_cycle_sample : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_afsr_t;
+
+
+
+typedef union cme_scom_aftr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t max_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t min_cycle_sample : 20;
+ uint64_t reserved2 : 12;
+#else
+ uint64_t reserved2 : 12;
+ uint64_t min_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t max_cycle_sample : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_aftr_t;
+
+
+
+typedef union cme_scom_vtsr0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_extreme_droop_ctr : 16;
+ uint64_t vdm_large_droop_ctr : 24;
+ uint64_t vdm_small_droop_ctr : 24;
+#else
+ uint64_t vdm_small_droop_ctr : 24;
+ uint64_t vdm_large_droop_ctr : 24;
+ uint64_t vdm_extreme_droop_ctr : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_vtsr0_t;
+
+
+
+typedef union cme_scom_vtsr1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 16;
+ uint64_t vdm_no_droop_ctr : 24;
+ uint64_t vdm_overvolt_ctr : 24;
+#else
+ uint64_t vdm_overvolt_ctr : 24;
+ uint64_t vdm_no_droop_ctr : 24;
+ uint64_t reserved1 : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_vtsr1_t;
+
+
+
+typedef union cme_scom_vdsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t instant_vdm_control_summary : 4;
+ uint64_t instant_cache_vdm_data : 4;
+ uint64_t instant_core0_vdm_data : 4;
+ uint64_t instant_core1_vdm_data : 4;
+ uint64_t instant_core2_vdm_data : 4;
+ uint64_t instant_core3_vdm_data : 4;
+ uint64_t reserved1 : 8;
+ uint64_t sticky_vdm_control_summary : 4;
+ uint64_t sticky_cache_vdm_data : 4;
+ uint64_t sticky_core0_vdm_data : 4;
+ uint64_t sticky_core1_vdm_data : 4;
+ uint64_t sticky_core2_vdm_data : 4;
+ uint64_t sticky_core3_vdm_data : 4;
+ uint64_t reserved2 : 8;
+#else
+ uint64_t reserved2 : 8;
+ uint64_t sticky_core3_vdm_data : 4;
+ uint64_t sticky_core2_vdm_data : 4;
+ uint64_t sticky_core1_vdm_data : 4;
+ uint64_t sticky_core0_vdm_data : 4;
+ uint64_t sticky_cache_vdm_data : 4;
+ uint64_t sticky_vdm_control_summary : 4;
+ uint64_t reserved1 : 8;
+ uint64_t instant_core3_vdm_data : 4;
+ uint64_t instant_core2_vdm_data : 4;
+ uint64_t instant_core1_vdm_data : 4;
+ uint64_t instant_core0_vdm_data : 4;
+ uint64_t instant_cache_vdm_data : 4;
+ uint64_t instant_vdm_control_summary : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_vdsr_t;
+
+
+
+typedef union cme_scom_eiir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t debugger : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t reserved_2_81 : 7;
+ uint64_t bce_timeout : 1;
+ uint64_t reserved_10_112 : 2;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t reserved_18_193 : 2;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t reserved4 : 38;
+#else
+ uint64_t reserved4 : 38;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t reserved_18_193 : 2;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t reserved_10_112 : 2;
+ uint64_t bce_timeout : 1;
+ uint64_t reserved_2_81 : 7;
+ uint64_t debug_trigger : 1;
+ uint64_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eiir_t;
+
+
+
+typedef union cme_scom_fwmr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmcr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t mask_purge_interface : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t stop_override_mode : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t fence_eisr : 1;
+ uint64_t spare_21_23 : 3;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t reserved2 : 4;
+ uint64_t cme_lcl_lcr : 32;
+#else
+ uint64_t cme_lcl_lcr : 32;
+ uint64_t reserved2 : 4;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t spare_21_23 : 3;
+ uint64_t fence_eisr : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t stop_override_mode : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t mask_purge_interface : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmcr_override_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_fwmr_t;
+
+
+
+typedef union cme_scom_fwmr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmcr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t mask_purge_interface : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t stop_override_mode : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t fence_eisr : 1;
+ uint64_t spare_21_23 : 3;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t reserved2 : 4;
+ uint64_t cme_lcl_lcr : 32;
+#else
+ uint64_t cme_lcl_lcr : 32;
+ uint64_t reserved2 : 4;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t spare_21_23 : 3;
+ uint64_t fence_eisr : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t stop_override_mode : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t mask_purge_interface : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmcr_override_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_fwmr_clr_t;
+
+
+
+typedef union cme_scom_fwmr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmcr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t mask_purge_interface : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t stop_override_mode : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t fence_eisr : 1;
+ uint64_t spare_21_23 : 3;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t reserved2 : 4;
+ uint64_t cme_lcl_lcr : 32;
+#else
+ uint64_t cme_lcl_lcr : 32;
+ uint64_t reserved2 : 4;
+ uint64_t avg_freq_tsel : 4;
+ uint64_t spare_21_23 : 3;
+ uint64_t fence_eisr : 1;
+ uint64_t stop1_active_enable : 1;
+ uint64_t auto_stop1_disable : 1;
+ uint64_t stop_active_mask : 1;
+ uint64_t stop_override_mode : 1;
+ uint64_t spare_11_15 : 5;
+ uint64_t mask_purge_interface : 1;
+ uint64_t queued_rd_en : 1;
+ uint64_t queued_wr_en : 1;
+ uint64_t lock_pcb_on_err : 1;
+ uint64_t freq_lcl_sample_en : 1;
+ uint64_t vdm_lcl_sample_en : 1;
+ uint64_t reserved_41 : 1;
+ uint64_t bcecsr_override_en : 1;
+ uint64_t pmsr_override_en : 1;
+ uint64_t pscr_override_en : 1;
+ uint64_t pmcr_override_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_fwmr_or_t;
+
+
+
+typedef union cme_scom_sicr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 40;
+ uint64_t reserved1 : 24;
+#else
+ uint64_t reserved1 : 24;
+ uint64_t data : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_sicr_t;
+
+
+
+typedef union cme_scom_sicr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 40;
+ uint64_t reserved1 : 24;
+#else
+ uint64_t reserved1 : 24;
+ uint64_t data : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_sicr_clr_t;
+
+
+
+typedef union cme_scom_sicr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 40;
+ uint64_t reserved1 : 24;
+#else
+ uint64_t reserved1 : 24;
+ uint64_t data : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_sicr_or_t;
+
+
+
+typedef union cme_scom_flags {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_flags_t;
+
+
+
+typedef union cme_scom_flags_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_flags_clr_t;
+
+
+
+typedef union cme_scom_flags_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_flags_or_t;
+
+
+
+typedef union cme_scom_srtch0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_srtch0_t;
+
+
+
+typedef union cme_scom_srtch1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_srtch1_t;
+
+
+
+typedef union cme_scom_eisr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eisr_t;
+
+
+
+typedef union cme_scom_eimr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eimr_t;
+
+
+
+typedef union cme_scom_eipr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eipr_t;
+
+
+
+typedef union cme_scom_eitr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eitr_t;
+
+
+
+typedef union cme_scom_eistr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_eistr_t;
+
+
+
+typedef union cme_scom_einr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t data : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_einr_t;
+
+
+
+typedef union cme_scom_sisr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_sisr_t;
+
+
+
+typedef union cme_scom_icrr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_icrr_t;
+
+
+
+typedef union cme_scom_xixcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xcr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t xcr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xixcr_t;
+
+
+
+typedef union cme_scom_xiramra {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xcr : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t xcr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xiramra_t;
+
+
+
+typedef union cme_scom_xiramga {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ir : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t ir : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xiramga_t;
+
+
+
+typedef union cme_scom_xiramdbg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xsr : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t xsr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xiramdbg_t;
+
+
+
+typedef union cme_scom_xiramedr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ir : 32;
+ uint64_t edr : 32;
+#else
+ uint64_t edr : 32;
+ uint64_t ir : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xiramedr_t;
+
+
+
+typedef union cme_scom_xidbgpro {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xsr : 32;
+ uint64_t iar : 32;
+#else
+ uint64_t iar : 32;
+ uint64_t xsr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xidbgpro_t;
+
+
+
+typedef union cme_scom_xisib {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sib_info : 64;
+#else
+ uint64_t sib_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xisib_t;
+
+
+
+typedef union cme_scom_ximem {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t memory_info : 64;
+#else
+ uint64_t memory_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_ximem_t;
+
+
+
+typedef union cme_scom_cmexisgb {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t storegatherbuffer_info : 64;
+#else
+ uint64_t storegatherbuffer_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_cmexisgb_t;
+
+
+
+typedef union cme_scom_xiicac {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t icache_info : 64;
+#else
+ uint64_t icache_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xiicac_t;
+
+
+
+typedef union cme_scom_xipcbq0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbqn_info : 64;
+#else
+ uint64_t pcbqn_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbq0_t;
+
+
+
+typedef union cme_scom_xipcbq1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbqn_info : 64;
+#else
+ uint64_t pcbqn_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbq1_t;
+
+
+
+typedef union cme_scom_xipcbmd0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_data : 64;
+#else
+ uint64_t pcbm_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbmd0_t;
+
+
+
+typedef union cme_scom_xipcbmd1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_data : 64;
+#else
+ uint64_t pcbm_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbmd1_t;
+
+
+
+typedef union cme_scom_xipcbmi0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_info : 64;
+#else
+ uint64_t pcbm_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbmi0_t;
+
+
+
+typedef union cme_scom_xipcbmi1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_info : 64;
+#else
+ uint64_t pcbm_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_xipcbmi1_t;
+
+
+
+typedef union cme_scom_pmsrs0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pmsrs0_t;
+
+
+
+typedef union cme_scom_pmsrs1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pmsrs1_t;
+
+
+
+typedef union cme_scom_pmcrs0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pmcrs0_t;
+
+
+
+typedef union cme_scom_pmcrs1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pmcrs1_t;
+
+
+
+typedef union cme_scom_pscrs00 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs00_t;
+
+
+
+typedef union cme_scom_pscrs10 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs10_t;
+
+
+
+typedef union cme_scom_pscrs01 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs01_t;
+
+
+
+typedef union cme_scom_pscrs11 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs11_t;
+
+
+
+typedef union cme_scom_pscrs02 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs02_t;
+
+
+
+typedef union cme_scom_pscrs12 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs12_t;
+
+
+
+typedef union cme_scom_pscrs03 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs03_t;
+
+
+
+typedef union cme_scom_pscrs13 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t spare_0 : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t ec_a_n : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t tr_a_n : 2;
+ uint64_t mtl_a_n : 4;
+ uint64_t rl_a_n : 4;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t rl_a_n : 4;
+ uint64_t mtl_a_n : 4;
+ uint64_t tr_a_n : 2;
+ uint64_t hmi_exit_enable : 1;
+ uint64_t dec_exit_enable : 1;
+ uint64_t ext_exit_enable : 1;
+ uint64_t hyp_db_exit_enable : 1;
+ uint64_t reserved_enable : 1;
+ uint64_t hyp_virt_exit_enable : 1;
+ uint64_t psll_a_n : 4;
+ uint64_t ec_a_n : 1;
+ uint64_t esl_a_n : 1;
+ uint64_t sd_a_n : 1;
+ uint64_t spare_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_scom_pscrs13_t;
+
+
+
+typedef union cme_lcl_eisr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t debugger : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t core_checkstop : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t bce_busy_high : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t bce_busy_low : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t comm_recvd : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_send_nack : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t reserved_42_431 : 2;
+ uint64_t reserved2 : 20;
+#else
+ uint64_t reserved2 : 20;
+ uint64_t reserved_42_431 : 2;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t comm_send_nack : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_recvd : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t bce_busy_low : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t bce_busy_high : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t core_checkstop : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eisr_t;
+
+
+
+typedef union cme_lcl_eisr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t debugger : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t core_checkstop : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t bce_busy_high : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t bce_busy_low : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t comm_recvd : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_send_nack : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t reserved_42_431 : 2;
+ uint64_t reserved2 : 20;
+#else
+ uint64_t reserved2 : 20;
+ uint64_t reserved_42_431 : 2;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t comm_send_nack : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_recvd : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t bce_busy_low : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t bce_busy_high : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t core_checkstop : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eisr_or_t;
+
+
+
+typedef union cme_lcl_eisr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t debugger : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t core_checkstop : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t bce_busy_high : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t bce_busy_low : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t comm_recvd : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_send_nack : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t reserved_42_431 : 2;
+ uint64_t reserved2 : 20;
+#else
+ uint64_t reserved2 : 20;
+ uint64_t reserved_42_431 : 2;
+ uint64_t doorbell1_c1 : 1;
+ uint64_t doorbell1_c0 : 1;
+ uint64_t spare_38_39 : 2;
+ uint64_t doorbell0_c1 : 1;
+ uint64_t doorbell0_c0 : 1;
+ uint64_t pmcr_update_c1 : 1;
+ uint64_t pmcr_update_c0 : 1;
+ uint64_t spare_32_33 : 2;
+ uint64_t comm_send_nack : 1;
+ uint64_t comm_send_ack : 1;
+ uint64_t comm_recvd : 1;
+ uint64_t spare_27_28 : 2;
+ uint64_t bce_busy_low : 1;
+ uint64_t chtm_purge_done_c1 : 1;
+ uint64_t chtm_purge_done_c0 : 1;
+ uint64_t ncu_purge_done : 1;
+ uint64_t l2_purge_done : 1;
+ uint64_t pc_pm_state_active_c1 : 1;
+ uint64_t pc_pm_state_active_c0 : 1;
+ uint64_t doorbell2_c1 : 1;
+ uint64_t doorbell2_c0 : 1;
+ uint64_t reg_wakeup_c1 : 1;
+ uint64_t reg_wakeup_c0 : 1;
+ uint64_t special_wakeup_c1 : 1;
+ uint64_t special_wakeup_c0 : 1;
+ uint64_t pc_intr_pending_c1 : 1;
+ uint64_t pc_intr_pending_c0 : 1;
+ uint64_t doorbell3_c1 : 1;
+ uint64_t doorbell3_c0 : 1;
+ uint64_t bce_timeout : 1;
+ uint64_t bce_busy_high : 1;
+ uint64_t spare_6_7 : 2;
+ uint64_t core_checkstop : 1;
+ uint64_t occ_heartbeat_lost : 1;
+ uint64_t pvref_fail : 1;
+ uint64_t quad_checkstop : 1;
+ uint64_t debug_trigger : 1;
+ uint64_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eisr_clr_t;
+
+
+
+typedef union cme_lcl_eimr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_mask : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_mask : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eimr_t;
+
+
+
+typedef union cme_lcl_eimr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_mask : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_mask : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eimr_or_t;
+
+
+
+typedef union cme_lcl_eimr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_mask : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_mask : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eimr_clr_t;
+
+
+
+typedef union cme_lcl_eipr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_polarity : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_polarity : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eipr_t;
+
+
+
+typedef union cme_lcl_eipr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_polarity : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_polarity : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eipr_or_t;
+
+
+
+typedef union cme_lcl_eipr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_polarity : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_polarity : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eipr_clr_t;
+
+
+
+typedef union cme_lcl_eitr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_type : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_type : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eitr_t;
+
+
+
+typedef union cme_lcl_eitr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_type : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_type : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eitr_or_t;
+
+
+
+typedef union cme_lcl_eitr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_type : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_type : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eitr_clr_t;
+
+
+
+typedef union cme_lcl_eistr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_status : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_status : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_eistr_t;
+
+
+
+typedef union cme_lcl_einr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t interrupt_input : 44;
+ uint64_t reserved1 : 20;
+#else
+ uint64_t reserved1 : 20;
+ uint64_t interrupt_input : 44;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_einr_t;
+
+
+
+typedef union cme_lcl_tsel {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fit_sel : 4;
+ uint64_t watchdog_sel : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t watchdog_sel : 4;
+ uint64_t fit_sel : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_tsel_t;
+
+
+
+typedef union cme_lcl_dbg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t en_dbg : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wide_trace : 1;
+ uint64_t reserved_10_11 : 2;
+ uint64_t sync_timer_sel : 4;
+ uint64_t fir_trigger : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t halt_input : 1;
+ uint64_t reserved1 : 43;
+#else
+ uint64_t reserved1 : 43;
+ uint64_t halt_input : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t fir_trigger : 1;
+ uint64_t sync_timer_sel : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t en_wide_trace : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t en_dbg : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_dbg_t;
+
+
+
+typedef union cme_lcl_dbg_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t en_dbg : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wide_trace : 1;
+ uint64_t reserved_10_11 : 2;
+ uint64_t sync_timer_sel : 4;
+ uint64_t fir_trigger : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t halt_input : 1;
+ uint64_t reserved1 : 43;
+#else
+ uint64_t reserved1 : 43;
+ uint64_t halt_input : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t fir_trigger : 1;
+ uint64_t sync_timer_sel : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t en_wide_trace : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t en_dbg : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_dbg_or_t;
+
+
+
+typedef union cme_lcl_dbg_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t en_dbg : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wide_trace : 1;
+ uint64_t reserved_10_11 : 2;
+ uint64_t sync_timer_sel : 4;
+ uint64_t fir_trigger : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t halt_input : 1;
+ uint64_t reserved1 : 43;
+#else
+ uint64_t reserved1 : 43;
+ uint64_t halt_input : 1;
+ uint64_t mib_gpio : 3;
+ uint64_t fir_trigger : 1;
+ uint64_t sync_timer_sel : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t en_wide_trace : 1;
+ uint64_t en_full_speed : 1;
+ uint64_t en_wait_cycles : 1;
+ uint64_t en_trace_stall : 1;
+ uint64_t en_trace_extra : 1;
+ uint64_t en_intr_addr : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t en_dbg : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_dbg_clr_t;
+
+
+
+typedef union cme_lcl_tbr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t timebase : 32;
+ uint64_t cycles : 32;
+#else
+ uint64_t cycles : 32;
+ uint64_t timebase : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_tbr_t;
+
+
+
+typedef union cme_lcl_afsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t inst_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t avg_cycle_sample : 20;
+ uint64_t reserved2 : 11;
+ uint64_t sample_valid : 1;
+#else
+ uint64_t sample_valid : 1;
+ uint64_t reserved2 : 11;
+ uint64_t avg_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t inst_cycle_sample : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_afsr_t;
+
+
+
+typedef union cme_lcl_aftr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t max_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t min_cycle_sample : 20;
+ uint64_t reserved2 : 12;
+#else
+ uint64_t reserved2 : 12;
+ uint64_t min_cycle_sample : 20;
+ uint64_t reserved1 : 12;
+ uint64_t max_cycle_sample : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_aftr_t;
+
+
+
+typedef union cme_lcl_lmcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t scom_fwmr_data : 32;
+ uint64_t reset_imprecise_qerr : 1;
+ uint64_t set_ecc_inject_err : 1;
+ uint64_t c0_halted_stop_override_disable : 1;
+ uint64_t c1_halted_stop_override_disable : 1;
+ uint64_t fence_eisr : 1;
+ uint64_t reserved1 : 27;
+#else
+ uint64_t reserved1 : 27;
+ uint64_t fence_eisr : 1;
+ uint64_t c1_halted_stop_override_disable : 1;
+ uint64_t c0_halted_stop_override_disable : 1;
+ uint64_t set_ecc_inject_err : 1;
+ uint64_t reset_imprecise_qerr : 1;
+ uint64_t scom_fwmr_data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_lmcr_t;
+
+
+
+typedef union cme_lcl_bcecsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t bce_data : 64;
+#else
+ uint64_t bce_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_bcecsr_t;
+
+
+
+typedef union cme_lcl_pmsrs0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pmsrs0_t;
+
+
+
+typedef union cme_lcl_pmsrs1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pmsrs1_t;
+
+
+
+typedef union cme_lcl_pmcrs0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pmcrs0_t;
+
+
+
+typedef union cme_lcl_pmcrs1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pmcrs1_t;
+
+
+
+typedef union cme_lcl_pecesr0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pece_cn_t0 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_cn_t1 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_cn_t2 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_cn_t3 : 6;
+ uint64_t reserved4 : 2;
+ uint64_t use_pece : 4;
+ uint64_t pc_fused_core_mode : 1;
+ uint64_t reserved5 : 27;
+#else
+ uint64_t reserved5 : 27;
+ uint64_t pc_fused_core_mode : 1;
+ uint64_t use_pece : 4;
+ uint64_t reserved4 : 2;
+ uint64_t pece_cn_t3 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_cn_t2 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_cn_t1 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_cn_t0 : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pecesr0_t;
+
+
+
+typedef union cme_lcl_pecesr1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pece_cn_t0 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_cn_t1 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_cn_t2 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_cn_t3 : 6;
+ uint64_t reserved4 : 2;
+ uint64_t use_pece : 4;
+ uint64_t pc_fused_core_mode : 1;
+ uint64_t reserved5 : 27;
+#else
+ uint64_t reserved5 : 27;
+ uint64_t pc_fused_core_mode : 1;
+ uint64_t use_pece : 4;
+ uint64_t reserved4 : 2;
+ uint64_t pece_cn_t3 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_cn_t2 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_cn_t1 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_cn_t0 : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pecesr1_t;
+
+
+
+typedef union cme_lcl_pscrs00 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs00_t;
+
+
+
+typedef union cme_lcl_pscrs10 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs10_t;
+
+
+
+typedef union cme_lcl_pscrs20 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs20_t;
+
+
+
+typedef union cme_lcl_pscrs30 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs30_t;
+
+
+
+typedef union cme_lcl_pscrs01 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs01_t;
+
+
+
+typedef union cme_lcl_pscrs11 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs11_t;
+
+
+
+typedef union cme_lcl_pscrs21 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs21_t;
+
+
+
+typedef union cme_lcl_pscrs31 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 24;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t data : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_pscrs31_t;
+
+
+
+typedef union cme_lcl_flags {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_flags_t;
+
+
+
+typedef union cme_lcl_flags_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_flags_or_t;
+
+
+
+typedef union cme_lcl_flags_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_flags_clr_t;
+
+
+
+typedef union cme_lcl_srtch0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_srtch0_t;
+
+
+
+typedef union cme_lcl_srtch1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_srtch1_t;
+
+
+
+typedef union cme_lcl_sicr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pc_entry_ack_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t l2_purge : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t reserved263 : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t reserved_36_394 : 4;
+ uint64_t reserved5 : 24;
+#else
+ uint64_t reserved5 : 24;
+ uint64_t reserved_36_394 : 4;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t reserved263 : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t l2_purge : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_entry_ack_c0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_sicr_t;
+
+
+
+typedef union cme_lcl_sicr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pc_entry_ack_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t l2_purge : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t reserved263 : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t reserved_36_394 : 4;
+ uint64_t reserved5 : 24;
+#else
+ uint64_t reserved5 : 24;
+ uint64_t reserved_36_394 : 4;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t reserved263 : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t l2_purge : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_entry_ack_c0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_sicr_or_t;
+
+
+
+typedef union cme_lcl_sicr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pc_entry_ack_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t l2_purge : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t reserved263 : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t reserved_36_394 : 4;
+ uint64_t reserved5 : 24;
+#else
+ uint64_t reserved5 : 24;
+ uint64_t reserved_36_394 : 4;
+ uint64_t ppm_spare_out_c1 : 1;
+ uint64_t ppm_spare_out_c0 : 1;
+ uint64_t hmi_request_c1 : 1;
+ uint64_t hmi_request_c0 : 1;
+ uint64_t chtm_purge_c1 : 1;
+ uint64_t chtm_purge_c0 : 1;
+ uint64_t ncu_purge_abort : 1;
+ uint64_t ncu_purge : 1;
+ uint64_t ncu_tlbie_quiesce : 1;
+ uint64_t reserved263 : 1;
+ uint64_t l2_purge_abort : 1;
+ uint64_t l2_purge : 1;
+ uint64_t special_wkup_done_c1 : 1;
+ uint64_t special_wkup_done_c0 : 1;
+ uint64_t reserved_20_212 : 2;
+ uint64_t l2_core_intf_quiesce_c1 : 1;
+ uint64_t pcc_core_intf_quiesce_c1 : 1;
+ uint64_t reserved_16_17 : 2;
+ uint64_t pcbmux_req_c1 : 1;
+ uint64_t pc_wakeup_c1 : 1;
+ uint64_t pc_block_interrupts_c1 : 1;
+ uint64_t pc_entry_ack_c1 : 1;
+ uint64_t reserved_8_111 : 4;
+ uint64_t l2_core_intf_quiesce_c0 : 1;
+ uint64_t pcc_core_intf_quiesce_c0 : 1;
+ uint64_t reserved_4_5 : 2;
+ uint64_t pcbmux_req_c0 : 1;
+ uint64_t pc_wakeup_c0 : 1;
+ uint64_t pc_block_interrupts_c0 : 1;
+ uint64_t pc_entry_ack_c0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_sicr_clr_t;
+
+
+
+typedef union cme_lcl_sisr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pc_unmasked_attn_c0 : 1;
+ uint64_t pc_instr_running_c0 : 1;
+ uint64_t pm_state_all_hv_c0 : 1;
+ uint64_t pm_state_active_c0 : 1;
+ uint64_t pm_state_c0 : 4;
+ uint64_t allow_reg_wakeup_c0 : 1;
+ uint64_t spare_9 : 1;
+ uint64_t pcbmux_grant_c0 : 1;
+ uint64_t pcbmux_grant_c1 : 1;
+ uint64_t pc_non_hv_running_c0 : 4;
+ uint64_t pc_unmasked_attn_c1 : 1;
+ uint64_t pc_instr_running_c1 : 1;
+ uint64_t pm_state_all_hv_c1 : 1;
+ uint64_t pm_state_active_c1 : 1;
+ uint64_t pm_state_c1 : 4;
+ uint64_t allow_reg_wakeup_c1 : 1;
+ uint64_t spare_25_27 : 3;
+ uint64_t pc_non_hv_running_c1 : 4;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t pc_non_hv_running_c1 : 4;
+ uint64_t spare_25_27 : 3;
+ uint64_t allow_reg_wakeup_c1 : 1;
+ uint64_t pm_state_c1 : 4;
+ uint64_t pm_state_active_c1 : 1;
+ uint64_t pm_state_all_hv_c1 : 1;
+ uint64_t pc_instr_running_c1 : 1;
+ uint64_t pc_unmasked_attn_c1 : 1;
+ uint64_t pc_non_hv_running_c0 : 4;
+ uint64_t pcbmux_grant_c1 : 1;
+ uint64_t pcbmux_grant_c0 : 1;
+ uint64_t spare_9 : 1;
+ uint64_t allow_reg_wakeup_c0 : 1;
+ uint64_t pm_state_c0 : 4;
+ uint64_t pm_state_active_c0 : 1;
+ uint64_t pm_state_all_hv_c0 : 1;
+ uint64_t pc_instr_running_c0 : 1;
+ uint64_t pc_unmasked_attn_c0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_sisr_t;
+
+
+
+typedef union cme_lcl_xipcbmd0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_data : 64;
+#else
+ uint64_t pcbm_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_xipcbmd0_t;
+
+
+
+typedef union cme_lcl_xipcbmd1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_data : 64;
+#else
+ uint64_t pcbm_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_xipcbmd1_t;
+
+
+
+typedef union cme_lcl_xipcbmi0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_info : 64;
+#else
+ uint64_t pcbm_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_xipcbmi0_t;
+
+
+
+typedef union cme_lcl_xipcbmi1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcbm_info : 64;
+#else
+ uint64_t pcbm_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_xipcbmi1_t;
+
+
+
+typedef union cme_lcl_vtsr0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_thresh_data : 64;
+#else
+ uint64_t vdm_thresh_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_vtsr0_t;
+
+
+
+typedef union cme_lcl_vtsr1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_thresh_data : 64;
+#else
+ uint64_t vdm_thresh_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_vtsr1_t;
+
+
+
+typedef union cme_lcl_vdsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_data : 64;
+#else
+ uint64_t vdm_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_vdsr_t;
+
+
+
+typedef union cme_lcl_iccr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_comm_ack : 1;
+ uint64_t cme_comm_nack : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t cme_comm_nack : 1;
+ uint64_t cme_comm_ack : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_iccr_t;
+
+
+
+typedef union cme_lcl_iccr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_comm_ack : 1;
+ uint64_t cme_comm_nack : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t cme_comm_nack : 1;
+ uint64_t cme_comm_ack : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_iccr_or_t;
+
+
+
+typedef union cme_lcl_iccr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_comm_ack : 1;
+ uint64_t cme_comm_nack : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t cme_comm_nack : 1;
+ uint64_t cme_comm_ack : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_iccr_clr_t;
+
+
+
+typedef union cme_lcl_icsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_comm_send : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t cme_comm_send : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_icsr_t;
+
+
+
+typedef union cme_lcl_icrr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_comm_recv : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t cme_comm_recv : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cme_lcl_icrr_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __CME_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/cme_register_addresses.h b/src/include/registers/cme_register_addresses.h
new file mode 100644
index 0000000..aa69886
--- /dev/null
+++ b/src/include/registers/cme_register_addresses.h
@@ -0,0 +1,175 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/cme_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CME_REGISTER_ADDRESSES_H__
+#define __CME_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cme_register_addresses.h
+/// \brief Symbolic addresses for the CME unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define CME_FIRPIB_BASE 0x10012000
+#define CME_SCOM_LFIR 0x10012000
+#define CME_SCOM_LFIR_AND 0x10012001
+#define CME_SCOM_LFIR_OR 0x10012002
+#define CME_SCOM_LFIRMASK 0x10012003
+#define CME_SCOM_LFIRMASK_AND 0x10012004
+#define CME_SCOM_LFIRMASK_OR 0x10012005
+#define CME_SCOM_LFIRACT0 0x10012006
+#define CME_SCOM_LFIRACT1 0x10012007
+#define CME_PIB_BASE 0x10012000
+#define CME_SCOM_CSCR 0x1001200a
+#define CME_SCOM_CSCR_CLR 0x1001200b
+#define CME_SCOM_CSCR_OR 0x1001200c
+#define CME_SCOM_CSAR 0x1001200d
+#define CME_SCOM_CSDR 0x1001200e
+#define CME_SCOM_BCECSR 0x1001200f
+#define CME_SCOM_BCEBAR0 0x10012010
+#define CME_SCOM_BCEBAR1 0x10012011
+#define CME_SCOM_QFMR 0x10012012
+#define CME_SCOM_AFSR 0x10012013
+#define CME_SCOM_AFTR 0x10012014
+#define CME_SCOM_VTSR0 0x10012015
+#define CME_SCOM_VTSR1 0x10012016
+#define CME_SCOM_VDSR 0x10012017
+#define CME_SCOM_EIIR 0x10012019
+#define CME_SCOM_FWMR 0x1001201a
+#define CME_SCOM_FWMR_CLR 0x1001201b
+#define CME_SCOM_FWMR_OR 0x1001201c
+#define CME_SCOM_SICR 0x1001201d
+#define CME_SCOM_SICR_CLR 0x1001201e
+#define CME_SCOM_SICR_OR 0x1001201f
+#define CME_SCOM_FLAGS 0x10012020
+#define CME_SCOM_FLAGS_CLR 0x10012021
+#define CME_SCOM_FLAGS_OR 0x10012022
+#define CME_SCOM_SRTCH0 0x10012023
+#define CME_SCOM_SRTCH1 0x10012024
+#define CME_SCOM_EISR 0x10012025
+#define CME_SCOM_EIMR 0x10012026
+#define CME_SCOM_EIPR 0x10012027
+#define CME_SCOM_EITR 0x10012028
+#define CME_SCOM_EISTR 0x10012029
+#define CME_SCOM_EINR 0x1001202a
+#define CME_SCOM_SISR 0x1001202b
+#define CME_SCOM_ICRR 0x1001202c
+#define CME_SCOM_XIXCR 0x10012030
+#define CME_SCOM_XIRAMRA 0x10012031
+#define CME_SCOM_XIRAMGA 0x10012032
+#define CME_SCOM_XIRAMDBG 0x10012033
+#define CME_SCOM_XIRAMEDR 0x10012034
+#define CME_SCOM_XIDBGPRO 0x10012035
+#define CME_SCOM_XISIB 0x10012036
+#define CME_SCOM_XIMEM 0x10012037
+#define CME_SCOM_CMEXISGB 0x10012038
+#define CME_SCOM_XIICAC 0x10012039
+#define CME_SCOM_XIPCBQ0 0x1001203a
+#define CME_SCOM_XIPCBQ1 0x1001203b
+#define CME_SCOM_XIPCBMD0 0x1001203c
+#define CME_SCOM_XIPCBMD1 0x1001203d
+#define CME_SCOM_XIPCBMI0 0x1001203e
+#define CME_SCOM_XIPCBMI1 0x1001203f
+#define CME_SCOM_PMSRS0 0x10012040
+#define CME_SCOM_PMSRS1 0x10012041
+#define CME_SCOM_PMCRS0 0x10012042
+#define CME_SCOM_PMCRS1 0x10012043
+#define CME_SCOM_PSCRS00 0x10012044
+#define CME_SCOM_PSCRS10 0x10012045
+#define CME_SCOM_PSCRS01 0x10012048
+#define CME_SCOM_PSCRS11 0x10012049
+#define CME_SCOM_PSCRS02 0x1001204c
+#define CME_SCOM_PSCRS12 0x1001204d
+#define CME_SCOM_PSCRS03 0x10012050
+#define CME_SCOM_PSCRS13 0x10012051
+#define CME_LOCAL_BASE 0xC0000000
+#define CME_LCL_EISR 0xc0000000
+#define CME_LCL_EISR_OR 0xc0000010
+#define CME_LCL_EISR_CLR 0xc0000018
+#define CME_LCL_EIMR 0xc0000020
+#define CME_LCL_EIMR_OR 0xc0000030
+#define CME_LCL_EIMR_CLR 0xc0000038
+#define CME_LCL_EIPR 0xc0000040
+#define CME_LCL_EIPR_OR 0xc0000050
+#define CME_LCL_EIPR_CLR 0xc0000058
+#define CME_LCL_EITR 0xc0000060
+#define CME_LCL_EITR_OR 0xc0000070
+#define CME_LCL_EITR_CLR 0xc0000078
+#define CME_LCL_EISTR 0xc0000080
+#define CME_LCL_EINR 0xc00000a0
+#define CME_LCL_TSEL 0xc0000100
+#define CME_LCL_DBG 0xc0000120
+#define CME_LCL_DBG_OR 0xc0000130
+#define CME_LCL_DBG_CLR 0xc0000138
+#define CME_LCL_TBR 0xc0000140
+#define CME_LCL_AFSR 0xc0000160
+#define CME_LCL_AFTR 0xc0000180
+#define CME_LCL_LMCR 0xc00001a0
+#define CME_LCL_BCECSR 0xc00001f0
+#define CME_LCL_PMSRS0 0xc0000200
+#define CME_LCL_PMSRS1 0xc0000220
+#define CME_LCL_PMCRS0 0xc0000240
+#define CME_LCL_PMCRS1 0xc0000260
+#define CME_LCL_PECESR0 0xc0000280
+#define CME_LCL_PECESR1 0xc00002a0
+#define CME_LCL_PSCRS00 0xc0000300
+#define CME_LCL_PSCRS10 0xc0000320
+#define CME_LCL_PSCRS20 0xc0000340
+#define CME_LCL_PSCRS30 0xc0000360
+#define CME_LCL_PSCRS01 0xc0000380
+#define CME_LCL_PSCRS11 0xc00003a0
+#define CME_LCL_PSCRS21 0xc00003c0
+#define CME_LCL_PSCRS31 0xc00003e0
+#define CME_LCL_FLAGS 0xc0000400
+#define CME_LCL_FLAGS_OR 0xc0000410
+#define CME_LCL_FLAGS_CLR 0xc0000418
+#define CME_LCL_SRTCH0 0xc0000420
+#define CME_LCL_SRTCH1 0xc0000440
+#define CME_LCL_SICR 0xc0000500
+#define CME_LCL_SICR_OR 0xc0000510
+#define CME_LCL_SICR_CLR 0xc0000518
+#define CME_LCL_SISR 0xc0000520
+#define CME_LCL_XIPCBMD0 0xc0000580
+#define CME_LCL_XIPCBMD1 0xc00005a0
+#define CME_LCL_XIPCBMI0 0xc00005c0
+#define CME_LCL_XIPCBMI1 0xc00005e0
+#define CME_LCL_VTSR0 0xc0000600
+#define CME_LCL_VTSR1 0xc0000620
+#define CME_LCL_VDSR 0xc0000640
+#define CME_LCL_ICCR 0xc0000700
+#define CME_LCL_ICCR_OR 0xc0000710
+#define CME_LCL_ICCR_CLR 0xc0000718
+#define CME_LCL_ICSR 0xc0000720
+#define CME_LCL_ICRR 0xc0000740
+
+#endif // __CME_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/cppm_firmware_registers.h b/src/include/registers/cppm_firmware_registers.h
new file mode 100644
index 0000000..9b224a8
--- /dev/null
+++ b/src/include/registers/cppm_firmware_registers.h
@@ -0,0 +1,1261 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/cppm_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CPPM_FIRMWARE_REGISTERS_H__
+#define __CPPM_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cppm_firmware_registers.h
+/// \brief C register structs for the CPPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union cppm_cpmmr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppm_write_disable : 1;
+ uint64_t ppm_write_override : 1;
+ uint64_t reserved1 : 10;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t enable_pece : 1;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t enable_pece : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t reserved1 : 10;
+ uint64_t ppm_write_override : 1;
+ uint64_t ppm_write_disable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cpmmr_t;
+
+
+
+typedef union cppm_cpmmr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppm_write_disable : 1;
+ uint64_t ppm_write_override : 1;
+ uint64_t reserved1 : 10;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t enable_pece : 1;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t enable_pece : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t reserved1 : 10;
+ uint64_t ppm_write_override : 1;
+ uint64_t ppm_write_disable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cpmmr_clr_t;
+
+
+
+typedef union cppm_cpmmr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ppm_write_disable : 1;
+ uint64_t ppm_write_override : 1;
+ uint64_t reserved1 : 10;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t enable_pece : 1;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t cme_special_wkup_done_dis : 1;
+ uint64_t enable_pece : 1;
+ uint64_t wkup_notify_select : 1;
+ uint64_t cme_err_notify_dis : 1;
+ uint64_t reserved1 : 10;
+ uint64_t ppm_write_override : 1;
+ uint64_t ppm_write_disable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cpmmr_or_t;
+
+
+
+typedef union cppm_perrsum {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cppm_error : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t cppm_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_perrsum_t;
+
+
+
+typedef union cppm_err {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcb_interrupt_protocol_err : 1;
+ uint64_t special_wkup_protocol_err : 1;
+ uint64_t clk_sync_err : 1;
+ uint64_t reserved_3 : 1;
+ uint64_t pece_intr_disabled : 1;
+ uint64_t deconfigured_intr : 1;
+ uint64_t reserved_6_71 : 2;
+ uint64_t reserved2 : 56;
+#else
+ uint64_t reserved2 : 56;
+ uint64_t reserved_6_71 : 2;
+ uint64_t deconfigured_intr : 1;
+ uint64_t pece_intr_disabled : 1;
+ uint64_t reserved_3 : 1;
+ uint64_t clk_sync_err : 1;
+ uint64_t special_wkup_protocol_err : 1;
+ uint64_t pcb_interrupt_protocol_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_err_t;
+
+
+
+typedef union cppm_errmsk {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 8;
+ uint64_t reserved2 : 56;
+#else
+ uint64_t reserved2 : 56;
+ uint64_t reserved1 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_errmsk_t;
+
+
+
+typedef union cppm_nc0indir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc0indir_t;
+
+
+
+typedef union cppm_nc0indir_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc0indir_clr_t;
+
+
+
+typedef union cppm_nc0indir_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc0indir_or_t;
+
+
+
+typedef union cppm_nc1indir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc1indir_t;
+
+
+
+typedef union cppm_nc1indir_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc1indir_clr_t;
+
+
+
+typedef union cppm_nc1indir_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ncn_indirect : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ncn_indirect : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_nc1indir_or_t;
+
+
+
+typedef union cppm_csar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t scratch_atomic_data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t scratch_atomic_data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_csar_t;
+
+
+
+typedef union cppm_csar_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t scratch_atomic_data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t scratch_atomic_data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_csar_clr_t;
+
+
+
+typedef union cppm_csar_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t scratch_atomic_data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t scratch_atomic_data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_csar_or_t;
+
+
+
+typedef union cppm_caccr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clk_sb_strength : 4;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sw_spare : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t clk_sync_enable : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t clk_sync_enable : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t clk_sw_spare : 1;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_caccr_t;
+
+
+
+typedef union cppm_caccr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clk_sb_strength : 4;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sw_spare : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t clk_sync_enable : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t clk_sync_enable : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t clk_sw_spare : 1;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_caccr_clr_t;
+
+
+
+typedef union cppm_caccr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clk_sb_strength : 4;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sw_spare : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t clk_sync_enable : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t clk_sync_enable : 1;
+ uint64_t quad_clk_sw_override : 1;
+ uint64_t quad_clk_sb_override : 1;
+ uint64_t clk_sw_spare : 1;
+ uint64_t clk_sw_resclk : 4;
+ uint64_t clk_sb_pulse_mode : 2;
+ uint64_t clk_sb_pulse_mode_en : 1;
+ uint64_t clk_sb_spare : 1;
+ uint64_t clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_caccr_or_t;
+
+
+
+typedef union cppm_cacsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t actual_clk_sb_strength : 4;
+ uint64_t actual_clk_sb_spare : 1;
+ uint64_t actual_clk_sb_pulse_mode_en : 1;
+ uint64_t actual_clk_sb_pulse_mode : 2;
+ uint64_t actual_clk_sw_resclk : 4;
+ uint64_t actual_clk_sw_spare : 1;
+ uint64_t clk_sync_done : 1;
+ uint64_t reserved1 : 50;
+#else
+ uint64_t reserved1 : 50;
+ uint64_t clk_sync_done : 1;
+ uint64_t actual_clk_sw_spare : 1;
+ uint64_t actual_clk_sw_resclk : 4;
+ uint64_t actual_clk_sb_pulse_mode : 2;
+ uint64_t actual_clk_sb_pulse_mode_en : 1;
+ uint64_t actual_clk_sb_spare : 1;
+ uint64_t actual_clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cacsr_t;
+
+
+
+typedef union cppm_cmedb0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_number0 : 8;
+ uint64_t cme_message_hi : 56;
+#else
+ uint64_t cme_message_hi : 56;
+ uint64_t cme_message_number0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb0_t;
+
+
+
+typedef union cppm_cmedb0_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_number0 : 8;
+ uint64_t cme_message_hi : 56;
+#else
+ uint64_t cme_message_hi : 56;
+ uint64_t cme_message_number0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb0_clr_t;
+
+
+
+typedef union cppm_cmedb0_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_number0 : 8;
+ uint64_t cme_message_hi : 56;
+#else
+ uint64_t cme_message_hi : 56;
+ uint64_t cme_message_number0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb0_or_t;
+
+
+
+typedef union cppm_cmedb1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb1_t;
+
+
+
+typedef union cppm_cmedb1_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb1_clr_t;
+
+
+
+typedef union cppm_cmedb1_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb1_or_t;
+
+
+
+typedef union cppm_cmedb2 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb2_t;
+
+
+
+typedef union cppm_cmedb2_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb2_clr_t;
+
+
+
+typedef union cppm_cmedb2_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb2_or_t;
+
+
+
+typedef union cppm_cmedb3 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb3_t;
+
+
+
+typedef union cppm_cmedb3_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb3_clr_t;
+
+
+
+typedef union cppm_cmedb3_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message_numbern : 8;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t cme_message_numbern : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedb3_or_t;
+
+
+
+typedef union cppm_cmedata {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedata_t;
+
+
+
+typedef union cppm_cmedata_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedata_clr_t;
+
+
+
+typedef union cppm_cmedata_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t data : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmedata_or_t;
+
+
+
+typedef union cppm_cmemsg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cme_message : 64;
+#else
+ uint64_t cme_message : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cmemsg_t;
+
+
+
+typedef union cppm_cisr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t hyp_intr_present : 4;
+ uint64_t os_intr_present : 4;
+ uint64_t msgsnd_intr_present : 4;
+ uint64_t ebb_intr_present : 4;
+ uint64_t hyp_intr_requested : 4;
+ uint64_t os_intr_requested : 4;
+ uint64_t msgsnd_intr_requested : 4;
+ uint64_t msgsnd_intr_sample : 4;
+ uint64_t msgsnd_ack : 1;
+ uint64_t malf_alert_present : 1;
+ uint64_t malf_alert_requested : 1;
+ uint64_t cme_special_wkup_done : 1;
+ uint64_t reserved1 : 28;
+#else
+ uint64_t reserved1 : 28;
+ uint64_t cme_special_wkup_done : 1;
+ uint64_t malf_alert_requested : 1;
+ uint64_t malf_alert_present : 1;
+ uint64_t msgsnd_ack : 1;
+ uint64_t msgsnd_intr_sample : 4;
+ uint64_t msgsnd_intr_requested : 4;
+ uint64_t os_intr_requested : 4;
+ uint64_t hyp_intr_requested : 4;
+ uint64_t ebb_intr_present : 4;
+ uint64_t msgsnd_intr_present : 4;
+ uint64_t os_intr_present : 4;
+ uint64_t hyp_intr_present : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_cisr_t;
+
+
+
+typedef union cppm_peces {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pece_t0 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_t1 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_t2 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_t3 : 6;
+ uint64_t reserved4 : 2;
+ uint64_t use_pece : 4;
+ uint64_t fused_core_mode : 1;
+ uint64_t reserved5 : 27;
+#else
+ uint64_t reserved5 : 27;
+ uint64_t fused_core_mode : 1;
+ uint64_t use_pece : 4;
+ uint64_t reserved4 : 2;
+ uint64_t pece_t3 : 6;
+ uint64_t reserved3 : 2;
+ uint64_t pece_t2 : 6;
+ uint64_t reserved2 : 2;
+ uint64_t pece_t1 : 6;
+ uint64_t reserved1 : 2;
+ uint64_t pece_t0 : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_peces_t;
+
+
+
+typedef union cppm_civrmlcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_local_control : 1;
+ uint64_t reserved_1_2 : 2;
+ uint64_t ivrm_ureg_test_en : 1;
+ uint64_t ivrm_ureg_test_id : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t ivrm_ureg_test_id : 4;
+ uint64_t ivrm_ureg_test_en : 1;
+ uint64_t reserved_1_2 : 2;
+ uint64_t ivrm_local_control : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_civrmlcr_t;
+
+
+
+typedef union cppm_ippmcmd {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t qppm_reg : 8;
+ uint64_t qppm_rnw : 1;
+ uint64_t reserved1 : 1;
+ uint64_t reserved2 : 54;
+#else
+ uint64_t reserved2 : 54;
+ uint64_t reserved1 : 1;
+ uint64_t qppm_rnw : 1;
+ uint64_t qppm_reg : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_ippmcmd_t;
+
+
+
+typedef union cppm_ippmstat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t qppm_ongoing : 1;
+ uint64_t qppm_status : 2;
+ uint64_t reserved1 : 61;
+#else
+ uint64_t reserved1 : 61;
+ uint64_t qppm_status : 2;
+ uint64_t qppm_ongoing : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_ippmstat_t;
+
+
+
+typedef union cppm_ippmwdata {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t qppm_wdata : 64;
+#else
+ uint64_t qppm_wdata : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_ippmwdata_t;
+
+
+
+typedef union cppm_ippmrdata {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t qppm_rdata : 64;
+#else
+ uint64_t qppm_rdata : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} cppm_ippmrdata_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __CPPM_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/cppm_register_addresses.h b/src/include/registers/cppm_register_addresses.h
new file mode 100644
index 0000000..1497792
--- /dev/null
+++ b/src/include/registers/cppm_register_addresses.h
@@ -0,0 +1,87 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/cppm_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CPPM_REGISTER_ADDRESSES_H__
+#define __CPPM_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cppm_register_addresses.h
+/// \brief Symbolic addresses for the CPPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define CPPM_PIB_BASE 0x000F0000
+#define CPPM_CPMMR 0x000f0106
+#define CPPM_CPMMR_CLR 0x000f0107
+#define CPPM_CPMMR_OR 0x000f0108
+#define CPPM_PERRSUM 0x000f0120
+#define CPPM_ERR 0x000f0121
+#define CPPM_ERRMSK 0x000f0122
+#define CPPM_NC0INDIR 0x000f0130
+#define CPPM_NC0INDIR_CLR 0x000f0131
+#define CPPM_NC0INDIR_OR 0x000f0132
+#define CPPM_NC1INDIR 0x000f0133
+#define CPPM_NC1INDIR_CLR 0x000f0134
+#define CPPM_NC1INDIR_OR 0x000f0135
+#define CPPM_CSAR 0x000f0138
+#define CPPM_CSAR_CLR 0x000f0139
+#define CPPM_CSAR_OR 0x000f013a
+#define CPPM_CACCR 0x000f0168
+#define CPPM_CACCR_CLR 0x000f0169
+#define CPPM_CACCR_OR 0x000f016a
+#define CPPM_CACSR 0x000f016b
+#define CPPM_CMEDB0 0x000f0190
+#define CPPM_CMEDB0_CLR 0x000f0191
+#define CPPM_CMEDB0_OR 0x000f0192
+#define CPPM_CMEDB1 0x000f0194
+#define CPPM_CMEDB1_CLR 0x000f0195
+#define CPPM_CMEDB1_OR 0x000f0196
+#define CPPM_CMEDB2 0x000f0198
+#define CPPM_CMEDB2_CLR 0x000f0199
+#define CPPM_CMEDB2_OR 0x000f019a
+#define CPPM_CMEDB3 0x000f019c
+#define CPPM_CMEDB3_CLR 0x000f019d
+#define CPPM_CMEDB3_OR 0x000f019e
+#define CPPM_CMEDATA 0x000f01a8
+#define CPPM_CMEDATA_CLR 0x000f01a9
+#define CPPM_CMEDATA_OR 0x000f01aa
+#define CPPM_CMEMSG 0x000f01ab
+#define CPPM_CISR 0x000f01ae
+#define CPPM_PECES 0x000f01af
+#define CPPM_CIVRMLCR 0x000f01b7
+#define CPPM_IPPMCMD 0x000f01c0
+#define CPPM_IPPMSTAT 0x000f01c1
+#define CPPM_IPPMWDATA 0x000f01c2
+#define CPPM_IPPMRDATA 0x000f01c3
+
+#endif // __CPPM_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/gpe_firmware_registers.h b/src/include/registers/gpe_firmware_registers.h
new file mode 100644
index 0000000..a8a8d82
--- /dev/null
+++ b/src/include/registers/gpe_firmware_registers.h
@@ -0,0 +1,887 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/gpe_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __GPE_FIRMWARE_REGISTERS_H__
+#define __GPE_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file gpe_firmware_registers.h
+/// \brief C register structs for the GPE unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union gpe_gpentsel {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fit_sel : 4;
+ uint64_t watchdog_sel : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t watchdog_sel : 4;
+ uint64_t fit_sel : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpentsel_t;
+
+
+
+typedef union gpe_gpenivpr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivpr : 23;
+ uint64_t reserved1 : 41;
+#else
+ uint64_t reserved1 : 41;
+ uint64_t ivpr : 23;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenivpr_t;
+
+
+
+typedef union gpe_gpendbg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t en_dbg : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t en_trace_full_iva : 1;
+ uint64_t dis_trace_extra : 1;
+ uint64_t dis_trace_stall : 1;
+ uint64_t en_wide_trace : 1;
+ uint64_t sync_timer_sel : 4;
+ uint64_t fir_trigger : 1;
+ uint64_t spare : 3;
+ uint64_t halt_input : 1;
+ uint64_t reserved1 : 47;
+#else
+ uint64_t reserved1 : 47;
+ uint64_t halt_input : 1;
+ uint64_t spare : 3;
+ uint64_t fir_trigger : 1;
+ uint64_t sync_timer_sel : 4;
+ uint64_t en_wide_trace : 1;
+ uint64_t dis_trace_stall : 1;
+ uint64_t dis_trace_extra : 1;
+ uint64_t en_trace_full_iva : 1;
+ uint64_t en_risctrace : 1;
+ uint64_t halt_on_trig : 1;
+ uint64_t halt_on_xstop : 1;
+ uint64_t en_dbg : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpendbg_t;
+
+
+
+typedef union gpe_gpenstr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 12;
+ uint64_t pbase : 10;
+ uint64_t reserved2 : 7;
+ uint64_t size : 3;
+ uint64_t reserved3 : 32;
+#else
+ uint64_t reserved3 : 32;
+ uint64_t size : 3;
+ uint64_t reserved2 : 7;
+ uint64_t pbase : 10;
+ uint64_t reserved1 : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenstr_t;
+
+
+
+typedef union gpe_gpenmacr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t mem_low_priority : 2;
+ uint64_t mem_high_priority : 2;
+ uint64_t local_low_priority : 2;
+ uint64_t local_high_priority : 2;
+ uint64_t sram_low_priority : 2;
+ uint64_t sram_high_priority : 2;
+ uint64_t reserved1 : 52;
+#else
+ uint64_t reserved1 : 52;
+ uint64_t sram_high_priority : 2;
+ uint64_t sram_low_priority : 2;
+ uint64_t local_high_priority : 2;
+ uint64_t local_low_priority : 2;
+ uint64_t mem_high_priority : 2;
+ uint64_t mem_low_priority : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenmacr_t;
+
+
+
+typedef union gpe_gpenxixcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xcr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t xcr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxixcr_t;
+
+
+
+typedef union gpe_gpenxiramra {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xcr : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t xcr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiramra_t;
+
+
+
+typedef union gpe_gpenxiramga {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ir : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t ir : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiramga_t;
+
+
+
+typedef union gpe_gpenxiramdbg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xsr : 32;
+ uint64_t sprg0 : 32;
+#else
+ uint64_t sprg0 : 32;
+ uint64_t xsr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiramdbg_t;
+
+
+
+typedef union gpe_gpenxiramedr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ir : 32;
+ uint64_t edr : 32;
+#else
+ uint64_t edr : 32;
+ uint64_t ir : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiramedr_t;
+
+
+
+typedef union gpe_gpenxidbgpro {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xsr : 32;
+ uint64_t iar : 32;
+#else
+ uint64_t iar : 32;
+ uint64_t xsr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxidbgpro_t;
+
+
+
+typedef union gpe_gpenxisib {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sib_info : 64;
+#else
+ uint64_t sib_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisib_t;
+
+
+
+typedef union gpe_gpenximem {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t memory_info : 64;
+#else
+ uint64_t memory_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenximem_t;
+
+
+
+typedef union gpe_gpenxisgb {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t storegatherbuffer_info : 64;
+#else
+ uint64_t storegatherbuffer_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisgb_t;
+
+
+
+typedef union gpe_gpenxiicac {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t icache_info : 64;
+#else
+ uint64_t icache_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiicac_t;
+
+
+
+typedef union gpe_gpenxidcac {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dcache_info : 64;
+#else
+ uint64_t dcache_info : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxidcac_t;
+
+
+
+typedef union gpe_gpenoxixcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xcr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t xcr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenoxixcr_t;
+
+
+
+typedef union gpe_gpenxixsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t xsr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t xsr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxixsr_t;
+
+
+
+typedef union gpe_gpenxisprg0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sprg0 : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t sprg0 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisprg0_t;
+
+
+
+typedef union gpe_gpenxiedr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t edr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t edr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiedr_t;
+
+
+
+typedef union gpe_gpenxiir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ir : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ir : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiir_t;
+
+
+
+typedef union gpe_gpenxiiar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t iar : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t iar : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiiar_t;
+
+
+
+typedef union gpe_gpenxisibu {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sib_info_upper : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t sib_info_upper : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisibu_t;
+
+
+
+typedef union gpe_gpenxisibl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sib_info_lower : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t sib_info_lower : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisibl_t;
+
+
+
+typedef union gpe_gpenximemu {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t memory_info_upper : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t memory_info_upper : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenximemu_t;
+
+
+
+typedef union gpe_gpenximeml {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t memory_info_lower : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t memory_info_lower : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenximeml_t;
+
+
+
+typedef union gpe_gpenxisgbu {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sgb_info_upper : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t sgb_info_upper : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisgbu_t;
+
+
+
+typedef union gpe_gpenxisgbl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sgb_info_lower : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t sgb_info_lower : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxisgbl_t;
+
+
+
+typedef union gpe_gpenxiicacu {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t icache_info_upper : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t icache_info_upper : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiicacu_t;
+
+
+
+typedef union gpe_gpenxiicacl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t icache_info_lower : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t icache_info_lower : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxiicacl_t;
+
+
+
+typedef union gpe_gpenxidcacu {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dcache_info_upper : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t dcache_info_upper : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxidcacu_t;
+
+
+
+typedef union gpe_gpenxidcacl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dcache_info_lower : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t dcache_info_lower : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} gpe_gpenxidcacl_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __GPE_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/gpe_register_addresses.h b/src/include/registers/gpe_register_addresses.h
new file mode 100644
index 0000000..7221692
--- /dev/null
+++ b/src/include/registers/gpe_register_addresses.h
@@ -0,0 +1,205 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/gpe_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __GPE_REGISTER_ADDRESSES_H__
+#define __GPE_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file gpe_register_addresses.h
+/// \brief Symbolic addresses for the GPE unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define GPE_OCI_BASE 0xC0000000
+#define GPE_GPENTSEL(n) (GPE_GPE0TSEL + ((GPE_GPE1TSEL - GPE_GPE0TSEL) * (n)))
+#define GPE_GPE0TSEL 0xc0000000
+#define GPE_GPE1TSEL 0xc0010000
+#define GPE_GPE2TSEL 0xc0020000
+#define GPE_GPE3TSEL 0xc0030000
+#define GPE_GPENIVPR(n) (GPE_GPE0IVPR + ((GPE_GPE1IVPR - GPE_GPE0IVPR) * (n)))
+#define GPE_GPE0IVPR 0xc0000008
+#define GPE_GPE1IVPR 0xc0010008
+#define GPE_GPE2IVPR 0xc0020008
+#define GPE_GPE3IVPR 0xc0030008
+#define GPE_GPENDBG(n) (GPE_GPE0DBG + ((GPE_GPE1DBG - GPE_GPE0DBG) * (n)))
+#define GPE_GPE0DBG 0xc0000010
+#define GPE_GPE1DBG 0xc0010010
+#define GPE_GPE2DBG 0xc0020010
+#define GPE_GPE3DBG 0xc0030010
+#define GPE_GPENSTR(n) (GPE_GPE0STR + ((GPE_GPE1STR - GPE_GPE0STR) * (n)))
+#define GPE_GPE0STR 0xc0000018
+#define GPE_GPE1STR 0xc0010018
+#define GPE_GPE2STR 0xc0020018
+#define GPE_GPE3STR 0xc0030018
+#define GPE_GPENMACR(n) (GPE_GPE0MACR + ((GPE_GPE1MACR - GPE_GPE0MACR) * (n)))
+#define GPE_GPE0MACR 0xc0000020
+#define GPE_GPE1MACR 0xc0010020
+#define GPE_GPE2MACR 0xc0020020
+#define GPE_GPE3MACR 0xc0030020
+#define GPE_GPENXIXCR(n) (GPE_GPE0XIXCR + ((GPE_GPE1XIXCR - GPE_GPE0XIXCR) * (n)))
+#define GPE_GPE0XIXCR 0xc0000080
+#define GPE_GPE1XIXCR 0xc0010080
+#define GPE_GPE2XIXCR 0xc0020080
+#define GPE_GPE3XIXCR 0xc0030080
+#define GPE_GPENXIRAMRA(n) (GPE_GPE0XIRAMRA + ((GPE_GPE1XIRAMRA - GPE_GPE0XIRAMRA) * (n)))
+#define GPE_GPE0XIRAMRA 0xc0000088
+#define GPE_GPE1XIRAMRA 0xc0010088
+#define GPE_GPE2XIRAMRA 0xc0020088
+#define GPE_GPE3XIRAMRA 0xc0030088
+#define GPE_GPENXIRAMGA(n) (GPE_GPE0XIRAMGA + ((GPE_GPE1XIRAMGA - GPE_GPE0XIRAMGA) * (n)))
+#define GPE_GPE0XIRAMGA 0xc0000090
+#define GPE_GPE1XIRAMGA 0xc0010090
+#define GPE_GPE2XIRAMGA 0xc0020090
+#define GPE_GPE3XIRAMGA 0xc0030090
+#define GPE_GPENXIRAMDBG(n) (GPE_GPE0XIRAMDBG + ((GPE_GPE1XIRAMDBG - GPE_GPE0XIRAMDBG) * (n)))
+#define GPE_GPE0XIRAMDBG 0xc0000098
+#define GPE_GPE1XIRAMDBG 0xc0010098
+#define GPE_GPE2XIRAMDBG 0xc0020098
+#define GPE_GPE3XIRAMDBG 0xc0030098
+#define GPE_GPENXIRAMEDR(n) (GPE_GPE0XIRAMEDR + ((GPE_GPE1XIRAMEDR - GPE_GPE0XIRAMEDR) * (n)))
+#define GPE_GPE0XIRAMEDR 0xc00000a0
+#define GPE_GPE1XIRAMEDR 0xc00100a0
+#define GPE_GPE2XIRAMEDR 0xc00200a0
+#define GPE_GPE3XIRAMEDR 0xc00300a0
+#define GPE_GPENXIDBGPRO(n) (GPE_GPE0XIDBGPRO + ((GPE_GPE1XIDBGPRO - GPE_GPE0XIDBGPRO) * (n)))
+#define GPE_GPE0XIDBGPRO 0xc00000a8
+#define GPE_GPE1XIDBGPRO 0xc00100a8
+#define GPE_GPE2XIDBGPRO 0xc00200a8
+#define GPE_GPE3XIDBGPRO 0xc00300a8
+#define GPE_GPENXISIB(n) (GPE_GPE0XISIB + ((GPE_GPE1XISIB - GPE_GPE0XISIB) * (n)))
+#define GPE_GPE0XISIB 0xc00000b0
+#define GPE_GPE1XISIB 0xc00100b0
+#define GPE_GPE2XISIB 0xc00200b0
+#define GPE_GPE3XISIB 0xc00300b0
+#define GPE_GPENXIMEM(n) (GPE_GPE0XIMEM + ((GPE_GPE1XIMEM - GPE_GPE0XIMEM) * (n)))
+#define GPE_GPE0XIMEM 0xc00000b8
+#define GPE_GPE1XIMEM 0xc00100b8
+#define GPE_GPE2XIMEM 0xc00200b8
+#define GPE_GPE3XIMEM 0xc00300b8
+#define GPE_GPENXISGB(n) (GPE_GPE0XISGB + ((GPE_GPE1XISGB - GPE_GPE0XISGB) * (n)))
+#define GPE_GPE0XISGB 0xc00000c0
+#define GPE_GPE1XISGB 0xc00100c0
+#define GPE_GPE2XISGB 0xc00200c0
+#define GPE_GPE3XISGB 0xc00300c0
+#define GPE_GPENXIICAC(n) (GPE_GPE0XIICAC + ((GPE_GPE1XIICAC - GPE_GPE0XIICAC) * (n)))
+#define GPE_GPE0XIICAC 0xc00000c8
+#define GPE_GPE1XIICAC 0xc00100c8
+#define GPE_GPE2XIICAC 0xc00200c8
+#define GPE_GPE3XIICAC 0xc00300c8
+#define GPE_GPENXIDCAC(n) (GPE_GPE0XIDCAC + ((GPE_GPE1XIDCAC - GPE_GPE0XIDCAC) * (n)))
+#define GPE_GPE0XIDCAC 0xc00000d0
+#define GPE_GPE1XIDCAC 0xc00100d0
+#define GPE_GPE2XIDCAC 0xc00200d0
+#define GPE_GPE3XIDCAC 0xc00300d0
+#define GPE_GPENOXIXCR(n) (GPE_GPE0OXIXCR + ((GPE_GPE1OXIXCR - GPE_GPE0OXIXCR) * (n)))
+#define GPE_GPE0OXIXCR 0xc0000100
+#define GPE_GPE1OXIXCR 0xc0010100
+#define GPE_GPE2OXIXCR 0xc0020100
+#define GPE_GPE3OXIXCR 0xc0030100
+#define GPE_GPENXIXSR(n) (GPE_GPE0XIXSR + ((GPE_GPE1XIXSR - GPE_GPE0XIXSR) * (n)))
+#define GPE_GPE0XIXSR 0xc0000108
+#define GPE_GPE1XIXSR 0xc0010108
+#define GPE_GPE2XIXSR 0xc0020108
+#define GPE_GPE3XIXSR 0xc0030108
+#define GPE_GPENXISPRG0(n) (GPE_GPE0XISPRG0 + ((GPE_GPE1XISPRG0 - GPE_GPE0XISPRG0) * (n)))
+#define GPE_GPE0XISPRG0 0xc0000110
+#define GPE_GPE1XISPRG0 0xc0010110
+#define GPE_GPE2XISPRG0 0xc0020110
+#define GPE_GPE3XISPRG0 0xc0030110
+#define GPE_GPENXIEDR(n) (GPE_GPE0XIEDR + ((GPE_GPE1XIEDR - GPE_GPE0XIEDR) * (n)))
+#define GPE_GPE0XIEDR 0xc0000118
+#define GPE_GPE1XIEDR 0xc0010118
+#define GPE_GPE2XIEDR 0xc0020118
+#define GPE_GPE3XIEDR 0xc0030118
+#define GPE_GPENXIIR(n) (GPE_GPE0XIIR + ((GPE_GPE1XIIR - GPE_GPE0XIIR) * (n)))
+#define GPE_GPE0XIIR 0xc0000120
+#define GPE_GPE1XIIR 0xc0010120
+#define GPE_GPE2XIIR 0xc0020120
+#define GPE_GPE3XIIR 0xc0030120
+#define GPE_GPENXIIAR(n) (GPE_GPE0XIIAR + ((GPE_GPE1XIIAR - GPE_GPE0XIIAR) * (n)))
+#define GPE_GPE0XIIAR 0xc0000128
+#define GPE_GPE1XIIAR 0xc0010128
+#define GPE_GPE2XIIAR 0xc0020128
+#define GPE_GPE3XIIAR 0xc0030128
+#define GPE_GPENXISIBU(n) (GPE_GPE0XISIBU + ((GPE_GPE1XISIBU - GPE_GPE0XISIBU) * (n)))
+#define GPE_GPE0XISIBU 0xc0000130
+#define GPE_GPE1XISIBU 0xc0010130
+#define GPE_GPE2XISIBU 0xc0020130
+#define GPE_GPE3XISIBU 0xc0030130
+#define GPE_GPENXISIBL(n) (GPE_GPE0XISIBL + ((GPE_GPE1XISIBL - GPE_GPE0XISIBL) * (n)))
+#define GPE_GPE0XISIBL 0xc0000138
+#define GPE_GPE1XISIBL 0xc0010138
+#define GPE_GPE2XISIBL 0xc0020138
+#define GPE_GPE3XISIBL 0xc0030138
+#define GPE_GPENXIMEMU(n) (GPE_GPE0XIMEMU + ((GPE_GPE1XIMEMU - GPE_GPE0XIMEMU) * (n)))
+#define GPE_GPE0XIMEMU 0xc0000140
+#define GPE_GPE1XIMEMU 0xc0010140
+#define GPE_GPE2XIMEMU 0xc0020140
+#define GPE_GPE3XIMEMU 0xc0030140
+#define GPE_GPENXIMEML(n) (GPE_GPE0XIMEML + ((GPE_GPE1XIMEML - GPE_GPE0XIMEML) * (n)))
+#define GPE_GPE0XIMEML 0xc0000148
+#define GPE_GPE1XIMEML 0xc0010148
+#define GPE_GPE2XIMEML 0xc0020148
+#define GPE_GPE3XIMEML 0xc0030148
+#define GPE_GPENXISGBU(n) (GPE_GPE0XISGBU + ((GPE_GPE1XISGBU - GPE_GPE0XISGBU) * (n)))
+#define GPE_GPE0XISGBU 0xc0000150
+#define GPE_GPE1XISGBU 0xc0010150
+#define GPE_GPE2XISGBU 0xc0020150
+#define GPE_GPE3XISGBU 0xc0030150
+#define GPE_GPENXISGBL(n) (GPE_GPE0XISGBL + ((GPE_GPE1XISGBL - GPE_GPE0XISGBL) * (n)))
+#define GPE_GPE0XISGBL 0xc0000158
+#define GPE_GPE1XISGBL 0xc0010158
+#define GPE_GPE2XISGBL 0xc0020158
+#define GPE_GPE3XISGBL 0xc0030158
+#define GPE_GPENXIICACU(n) (GPE_GPE0XIICACU + ((GPE_GPE1XIICACU - GPE_GPE0XIICACU) * (n)))
+#define GPE_GPE0XIICACU 0xc0000160
+#define GPE_GPE1XIICACU 0xc0010160
+#define GPE_GPE2XIICACU 0xc0020160
+#define GPE_GPE3XIICACU 0xc0030160
+#define GPE_GPENXIICACL(n) (GPE_GPE0XIICACL + ((GPE_GPE1XIICACL - GPE_GPE0XIICACL) * (n)))
+#define GPE_GPE0XIICACL 0xc0000168
+#define GPE_GPE1XIICACL 0xc0010168
+#define GPE_GPE2XIICACL 0xc0020168
+#define GPE_GPE3XIICACL 0xc0030168
+#define GPE_GPENXIDCACU(n) (GPE_GPE0XIDCACU + ((GPE_GPE1XIDCACU - GPE_GPE0XIDCACU) * (n)))
+#define GPE_GPE0XIDCACU 0xc0000170
+#define GPE_GPE1XIDCACU 0xc0010170
+#define GPE_GPE2XIDCACU 0xc0020170
+#define GPE_GPE3XIDCACU 0xc0030170
+#define GPE_GPENXIDCACL(n) (GPE_GPE0XIDCACL + ((GPE_GPE1XIDCACL - GPE_GPE0XIDCACL) * (n)))
+#define GPE_GPE0XIDCACL 0xc0000178
+#define GPE_GPE1XIDCACL 0xc0010178
+#define GPE_GPE2XIDCACL 0xc0020178
+#define GPE_GPE3XIDCACL 0xc0030178
+
+#endif // __GPE_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/ocb_firmware_registers.h b/src/include/registers/ocb_firmware_registers.h
new file mode 100644
index 0000000..898cf05
--- /dev/null
+++ b/src/include/registers/ocb_firmware_registers.h
@@ -0,0 +1,5230 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/ocb_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __OCB_FIRMWARE_REGISTERS_H__
+#define __OCB_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ocb_firmware_registers.h
+/// \brief C register structs for the OCB unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union ocb_oisr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t debugger : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t occ_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t ocb_error : 1;
+ uint32_t spipss_error : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t external_trap : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t external_trap : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t spipss_error : 1;
+ uint32_t ocb_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t occ_error : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr0_t;
+
+
+
+typedef union ocb_oisr0_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t debugger : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t occ_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t ocb_error : 1;
+ uint32_t spipss_error : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t external_trap : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t external_trap : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t spipss_error : 1;
+ uint32_t ocb_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t occ_error : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr0_clr_t;
+
+
+
+typedef union ocb_oisr0_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t debugger : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t occ_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t ocb_error : 1;
+ uint32_t spipss_error : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t external_trap : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t adcfsm_ongoing : 1;
+ uint32_t ipi4_hi_priority : 1;
+ uint32_t ipi3_hi_priority : 1;
+ uint32_t ipi2_hi_priority : 1;
+ uint32_t ipi1_hi_priority : 1;
+ uint32_t ipi0_hi_priority : 1;
+ uint32_t avs_slave1 : 1;
+ uint32_t avs_slave0 : 1;
+ uint32_t occ_timer1 : 1;
+ uint32_t occ_timer0 : 1;
+ uint32_t ivrm_pvref_error : 1;
+ uint32_t external_trap : 1;
+ uint32_t adu_malf_alert : 1;
+ uint32_t occ_malf_alert : 1;
+ uint32_t check_stop_gpe3 : 1;
+ uint32_t check_stop_gpe2 : 1;
+ uint32_t check_stop_gpe1 : 1;
+ uint32_t check_stop_gpe0 : 1;
+ uint32_t check_stop_ppc405 : 1;
+ uint32_t spipss_error : 1;
+ uint32_t ocb_error : 1;
+ uint32_t ppc405_halt : 1;
+ uint32_t gpe3_error : 1;
+ uint32_t gpe2_error : 1;
+ uint32_t gpe1_error : 1;
+ uint32_t gpe0_error : 1;
+ uint32_t srt_error : 1;
+ uint32_t pba_error : 1;
+ uint32_t occ_error : 1;
+ uint32_t trace_trigger : 1;
+ uint32_t debugger : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr0_or_t;
+
+
+
+typedef union ocb_oimr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr0_t;
+
+
+
+typedef union ocb_oimr0_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr0_clr_t;
+
+
+
+typedef union ocb_oimr0_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr0_or_t;
+
+
+
+typedef union ocb_oitr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr0_t;
+
+
+
+typedef union ocb_oitr0_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr0_clr_t;
+
+
+
+typedef union ocb_oitr0_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr0_or_t;
+
+
+
+typedef union ocb_oiepr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr0_t;
+
+
+
+typedef union ocb_oiepr0_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr0_clr_t;
+
+
+
+typedef union ocb_oiepr0_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr0_or_t;
+
+
+
+typedef union ocb_oisr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pbax_occ_send_attn : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_send_attn : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr1_t;
+
+
+
+typedef union ocb_oisr1_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pbax_occ_send_attn : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_send_attn : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr1_clr_t;
+
+
+
+typedef union ocb_oisr1_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pbax_occ_send_attn : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t spare_31 : 1;
+#else
+ uint32_t spare_31 : 1;
+ uint32_t ipi4_lo_priority : 1;
+ uint32_t ipi3_lo_priority : 1;
+ uint32_t ipi2_lo_priority : 1;
+ uint32_t ipi1_lo_priority : 1;
+ uint32_t ipi0_lo_priority : 1;
+ uint32_t pssbridge_ongoing : 1;
+ uint32_t pmc_o2s_1b_ongoing : 1;
+ uint32_t pmc_o2s_1a_ongoing : 1;
+ uint32_t pmc_o2s_0b_ongoing : 1;
+ uint32_t pmc_o2s_0a_ongoing : 1;
+ uint32_t pmc_pcb_intr_type7_pending : 1;
+ uint32_t pmc_pcb_intr_type6_pending : 1;
+ uint32_t pmc_pcb_intr_type5_pending : 1;
+ uint32_t pmc_pcb_intr_type4_pending : 1;
+ uint32_t pmc_pcb_intr_type3_pending : 1;
+ uint32_t pmc_pcb_intr_type2_pending : 1;
+ uint32_t pmc_pcb_intr_type1_pending : 1;
+ uint32_t pmc_pcb_intr_type0_pending : 1;
+ uint32_t occ_strm3_push : 1;
+ uint32_t occ_strm3_pull : 1;
+ uint32_t occ_strm2_push : 1;
+ uint32_t occ_strm2_pull : 1;
+ uint32_t occ_strm1_push : 1;
+ uint32_t occ_strm1_pull : 1;
+ uint32_t occ_strm0_push : 1;
+ uint32_t occ_strm0_pull : 1;
+ uint32_t pba_bcue_attn : 1;
+ uint32_t pba_bcde_attn : 1;
+ uint32_t pbax_occ_push1 : 1;
+ uint32_t pbax_occ_push0 : 1;
+ uint32_t pbax_occ_send_attn : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oisr1_or_t;
+
+
+
+typedef union ocb_oimr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr1_t;
+
+
+
+typedef union ocb_oimr1_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr1_clr_t;
+
+
+
+typedef union ocb_oimr1_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_mask_n : 32;
+#else
+ uint32_t interrupt_mask_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oimr1_or_t;
+
+
+
+typedef union ocb_oitr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr1_t;
+
+
+
+typedef union ocb_oitr1_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr1_clr_t;
+
+
+
+typedef union ocb_oitr1_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_type_n : 32;
+#else
+ uint32_t interrupt_type_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oitr1_or_t;
+
+
+
+typedef union ocb_oiepr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr1_t;
+
+
+
+typedef union ocb_oiepr1_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr1_clr_t;
+
+
+
+typedef union ocb_oiepr1_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_edge_pol_n : 32;
+#else
+ uint32_t interrupt_edge_pol_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oiepr1_or_t;
+
+
+
+typedef union ocb_oirr0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0a_t;
+
+
+
+typedef union ocb_oirr0a_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0a_clr_t;
+
+
+
+typedef union ocb_oirr0a_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0a_or_t;
+
+
+
+typedef union ocb_oirr0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0b_t;
+
+
+
+typedef union ocb_oirr0b_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0b_clr_t;
+
+
+
+typedef union ocb_oirr0b_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0b_or_t;
+
+
+
+typedef union ocb_oirr0c {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0c_t;
+
+
+
+typedef union ocb_oirr0c_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0c_clr_t;
+
+
+
+typedef union ocb_oirr0c_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr0c_or_t;
+
+
+
+typedef union ocb_oirr1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1a_t;
+
+
+
+typedef union ocb_oirr1a_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1a_clr_t;
+
+
+
+typedef union ocb_oirr1a_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1a_or_t;
+
+
+
+typedef union ocb_oirr1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1b_t;
+
+
+
+typedef union ocb_oirr1b_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1b_clr_t;
+
+
+
+typedef union ocb_oirr1b_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1b_or_t;
+
+
+
+typedef union ocb_oirr1c {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1c_t;
+
+
+
+typedef union ocb_oirr1c_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1c_clr_t;
+
+
+
+typedef union ocb_oirr1c_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_route_a_n : 32;
+#else
+ uint32_t interrupt_route_a_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oirr1c_or_t;
+
+
+
+typedef union ocb_onisr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_noncrit_status_n : 32;
+#else
+ uint32_t interrupt_noncrit_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_onisr0_t;
+
+
+
+typedef union ocb_ocisr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_crit_status_n : 32;
+#else
+ uint32_t interrupt_crit_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocisr0_t;
+
+
+
+typedef union ocb_ouisr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_uncon_status_n : 32;
+#else
+ uint32_t interrupt_uncon_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ouisr0_t;
+
+
+
+typedef union ocb_odisr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_debug_status_n : 32;
+#else
+ uint32_t interrupt_debug_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_odisr0_t;
+
+
+
+typedef union ocb_g0isr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe0_status_n : 32;
+#else
+ uint32_t interrupt_gpe0_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g0isr0_t;
+
+
+
+typedef union ocb_g1isr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe1_status_n : 32;
+#else
+ uint32_t interrupt_gpe1_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g1isr0_t;
+
+
+
+typedef union ocb_g2isr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe2_status_n : 32;
+#else
+ uint32_t interrupt_gpe2_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g2isr0_t;
+
+
+
+typedef union ocb_g3isr0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe3_status_n : 32;
+#else
+ uint32_t interrupt_gpe3_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g3isr0_t;
+
+
+
+typedef union ocb_onisr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_noncrit_status_n : 32;
+#else
+ uint32_t interrupt_noncrit_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_onisr1_t;
+
+
+
+typedef union ocb_ocisr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_crit_status_n : 32;
+#else
+ uint32_t interrupt_crit_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocisr1_t;
+
+
+
+typedef union ocb_ouisr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_uncon_status_n : 32;
+#else
+ uint32_t interrupt_uncon_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ouisr1_t;
+
+
+
+typedef union ocb_odisr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_debug_status_n : 32;
+#else
+ uint32_t interrupt_debug_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_odisr1_t;
+
+
+
+typedef union ocb_g0isr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe0_status_n : 32;
+#else
+ uint32_t interrupt_gpe0_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g0isr1_t;
+
+
+
+typedef union ocb_g1isr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe1_status_n : 32;
+#else
+ uint32_t interrupt_gpe1_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g1isr1_t;
+
+
+
+typedef union ocb_g2isr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe2_status_n : 32;
+#else
+ uint32_t interrupt_gpe2_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g2isr1_t;
+
+
+
+typedef union ocb_g3isr1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interrupt_gpe3_status_n : 32;
+#else
+ uint32_t interrupt_gpe3_status_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_g3isr1_t;
+
+
+
+typedef union ocb_occmisc {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_ext_intr : 1;
+ uint32_t spare : 15;
+ uint32_t reserved1 : 16;
+#else
+ uint32_t reserved1 : 16;
+ uint32_t spare : 15;
+ uint32_t core_ext_intr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occmisc_t;
+
+
+
+typedef union ocb_occmisc_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_ext_intr : 1;
+ uint32_t spare : 15;
+ uint32_t reserved1 : 16;
+#else
+ uint32_t reserved1 : 16;
+ uint32_t spare : 15;
+ uint32_t core_ext_intr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occmisc_clr_t;
+
+
+
+typedef union ocb_occmisc_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_ext_intr : 1;
+ uint32_t spare : 15;
+ uint32_t reserved1 : 16;
+#else
+ uint32_t reserved1 : 16;
+ uint32_t spare : 15;
+ uint32_t core_ext_intr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occmisc_or_t;
+
+
+
+typedef union ocb_ohtmcr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t htm_src_sel : 2;
+ uint32_t htm_stop : 1;
+ uint32_t htm_marker_slave_adrs : 3;
+ uint32_t event2halt_mode : 2;
+ uint32_t event2halt_en : 11;
+ uint32_t reserved1 : 4;
+ uint32_t event2halt_occ : 1;
+ uint32_t event2halt_gpe0 : 1;
+ uint32_t event2halt_gpe1 : 1;
+ uint32_t event2halt_gpe2 : 1;
+ uint32_t event2halt_gpe3 : 1;
+ uint32_t reserved2 : 3;
+ uint32_t event2halt_halt_state : 1;
+#else
+ uint32_t event2halt_halt_state : 1;
+ uint32_t reserved2 : 3;
+ uint32_t event2halt_gpe3 : 1;
+ uint32_t event2halt_gpe2 : 1;
+ uint32_t event2halt_gpe1 : 1;
+ uint32_t event2halt_gpe0 : 1;
+ uint32_t event2halt_occ : 1;
+ uint32_t reserved1 : 4;
+ uint32_t event2halt_en : 11;
+ uint32_t event2halt_mode : 2;
+ uint32_t htm_marker_slave_adrs : 3;
+ uint32_t htm_stop : 1;
+ uint32_t htm_src_sel : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ohtmcr_t;
+
+
+
+typedef union ocb_oehdr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t event2halt_delay : 20;
+ uint32_t reserved1 : 12;
+#else
+ uint32_t reserved1 : 12;
+ uint32_t event2halt_delay : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oehdr_t;
+
+
+
+typedef union ocb_ocicfg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t m0_priority : 2;
+ uint32_t m1_priority : 2;
+ uint32_t m2_priority : 2;
+ uint32_t m3_priority : 2;
+ uint32_t m4_priority : 2;
+ uint32_t m5_priority : 2;
+ uint32_t m6_priority : 2;
+ uint32_t m7_priority : 2;
+ uint32_t m0_priority_sel : 1;
+ uint32_t m1_priority_sel : 1;
+ uint32_t m2_priority_sel : 1;
+ uint32_t m3_priority_sel : 1;
+ uint32_t ocicfg_reserved_20 : 1;
+ uint32_t m5_priority_sel : 1;
+ uint32_t ocicfg_reserved_23 : 1;
+ uint32_t m7_priority_sel : 1;
+ uint32_t plbarb_lockerr : 1;
+ uint32_t spare_24_31 : 7;
+#else
+ uint32_t spare_24_31 : 7;
+ uint32_t plbarb_lockerr : 1;
+ uint32_t m7_priority_sel : 1;
+ uint32_t ocicfg_reserved_23 : 1;
+ uint32_t m5_priority_sel : 1;
+ uint32_t ocicfg_reserved_20 : 1;
+ uint32_t m3_priority_sel : 1;
+ uint32_t m2_priority_sel : 1;
+ uint32_t m1_priority_sel : 1;
+ uint32_t m0_priority_sel : 1;
+ uint32_t m7_priority : 2;
+ uint32_t m6_priority : 2;
+ uint32_t m5_priority : 2;
+ uint32_t m4_priority : 2;
+ uint32_t m3_priority : 2;
+ uint32_t m2_priority : 2;
+ uint32_t m1_priority : 2;
+ uint32_t m0_priority : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocicfg_t;
+
+
+
+typedef union ocb_occs0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_scratch_n : 32;
+#else
+ uint32_t occ_scratch_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occs0_t;
+
+
+
+typedef union ocb_occs1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_scratch_n : 32;
+#else
+ uint32_t occ_scratch_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occs1_t;
+
+
+
+typedef union ocb_occs2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_scratch_n : 32;
+#else
+ uint32_t occ_scratch_n : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occs2_t;
+
+
+
+typedef union ocb_occflg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_flags : 32;
+#else
+ uint32_t occ_flags : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occflg_t;
+
+
+
+typedef union ocb_occflg_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_flags : 32;
+#else
+ uint32_t occ_flags : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occflg_clr_t;
+
+
+
+typedef union ocb_occflg_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_flags : 32;
+#else
+ uint32_t occ_flags : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occflg_or_t;
+
+
+
+typedef union ocb_occhbr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t occ_heartbeat_count : 16;
+ uint32_t occ_heartbeat_en : 1;
+ uint32_t reserved1 : 15;
+#else
+ uint32_t reserved1 : 15;
+ uint32_t occ_heartbeat_en : 1;
+ uint32_t occ_heartbeat_count : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occhbr_t;
+
+
+
+typedef union ocb_ccsr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_config : 24;
+ uint32_t reserved_24_1 : 7;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_24_1 : 7;
+ uint32_t core_config : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ccsr_t;
+
+
+
+typedef union ocb_ccsr_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_config : 24;
+ uint32_t reserved_24_1 : 7;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_24_1 : 7;
+ uint32_t core_config : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ccsr_clr_t;
+
+
+
+typedef union ocb_ccsr_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_config : 24;
+ uint32_t reserved_24_1 : 7;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_24_1 : 7;
+ uint32_t core_config : 24;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ccsr_or_t;
+
+
+
+typedef union ocb_qcsr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t ex_config : 12;
+ uint32_t reserved_12_301 : 19;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_12_301 : 19;
+ uint32_t ex_config : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qcsr_t;
+
+
+
+typedef union ocb_qcsr_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t ex_config : 12;
+ uint32_t reserved_12_301 : 19;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_12_301 : 19;
+ uint32_t ex_config : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qcsr_clr_t;
+
+
+
+typedef union ocb_qcsr_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t ex_config : 12;
+ uint32_t reserved_12_301 : 19;
+ uint32_t change_in_progress : 1;
+#else
+ uint32_t change_in_progress : 1;
+ uint32_t reserved_12_301 : 19;
+ uint32_t ex_config : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qcsr_or_t;
+
+
+
+typedef union ocb_qssr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t l2_stopped : 12;
+ uint32_t l3_stopped : 12;
+ uint32_t quad_stopped : 6;
+ uint32_t reserved1 : 1;
+ uint32_t stop_in_progress : 1;
+#else
+ uint32_t stop_in_progress : 1;
+ uint32_t reserved1 : 1;
+ uint32_t quad_stopped : 6;
+ uint32_t l3_stopped : 12;
+ uint32_t l2_stopped : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qssr_t;
+
+
+
+typedef union ocb_qssr_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t l2_stopped : 12;
+ uint32_t l3_stopped : 12;
+ uint32_t quad_stopped : 6;
+ uint32_t reserved1 : 1;
+ uint32_t stop_in_progress : 1;
+#else
+ uint32_t stop_in_progress : 1;
+ uint32_t reserved1 : 1;
+ uint32_t quad_stopped : 6;
+ uint32_t l3_stopped : 12;
+ uint32_t l2_stopped : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qssr_clr_t;
+
+
+
+typedef union ocb_qssr_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t l2_stopped : 12;
+ uint32_t l3_stopped : 12;
+ uint32_t quad_stopped : 6;
+ uint32_t reserved1 : 1;
+ uint32_t stop_in_progress : 1;
+#else
+ uint32_t stop_in_progress : 1;
+ uint32_t reserved1 : 1;
+ uint32_t quad_stopped : 6;
+ uint32_t l3_stopped : 12;
+ uint32_t l2_stopped : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_qssr_or_t;
+
+
+
+typedef union ocb_otbr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t ocb_timebase : 32;
+#else
+ uint32_t ocb_timebase : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_otbr_t;
+
+
+
+typedef union ocb_otrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t timeout : 1;
+ uint32_t control : 1;
+ uint32_t auto_reload : 1;
+ uint32_t spare : 13;
+ uint32_t timer : 16;
+#else
+ uint32_t timer : 16;
+ uint32_t spare : 13;
+ uint32_t auto_reload : 1;
+ uint32_t control : 1;
+ uint32_t timeout : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_otrn_t;
+
+
+
+typedef union ocb_ocbslbrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pull_oci_region : 3;
+ uint32_t pull_start : 26;
+ uint32_t reserved1 : 3;
+#else
+ uint32_t reserved1 : 3;
+ uint32_t pull_start : 26;
+ uint32_t pull_oci_region : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbslbrn_t;
+
+
+
+typedef union ocb_ocbslcsn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pull_full : 1;
+ uint32_t pull_empty : 1;
+ uint32_t spare : 2;
+ uint32_t pull_intr_action : 2;
+ uint32_t pull_length : 5;
+ uint32_t reserved1 : 2;
+ uint32_t pull_write_ptr : 5;
+ uint32_t reserved2 : 3;
+ uint32_t pull_read_ptr : 5;
+ uint32_t reserved3 : 5;
+ uint32_t pull_enable : 1;
+#else
+ uint32_t pull_enable : 1;
+ uint32_t reserved3 : 5;
+ uint32_t pull_read_ptr : 5;
+ uint32_t reserved2 : 3;
+ uint32_t pull_write_ptr : 5;
+ uint32_t reserved1 : 2;
+ uint32_t pull_length : 5;
+ uint32_t pull_intr_action : 2;
+ uint32_t spare : 2;
+ uint32_t pull_empty : 1;
+ uint32_t pull_full : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbslcsn_t;
+
+
+
+typedef union ocb_ocbslin {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 32;
+#else
+ uint32_t reserved1 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbslin_t;
+
+
+
+typedef union ocb_ocbshbrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t push_oci_region : 3;
+ uint32_t push_start : 26;
+ uint32_t reserved1 : 3;
+#else
+ uint32_t reserved1 : 3;
+ uint32_t push_start : 26;
+ uint32_t push_oci_region : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbshbrn_t;
+
+
+
+typedef union ocb_ocbshcsn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t push_full : 1;
+ uint32_t push_empty : 1;
+ uint32_t spare : 2;
+ uint32_t push_intr_action : 2;
+ uint32_t push_length : 5;
+ uint32_t reserved1 : 2;
+ uint32_t push_write_ptr : 5;
+ uint32_t reserved2 : 3;
+ uint32_t push_read_ptr : 5;
+ uint32_t reserved3 : 5;
+ uint32_t push_enable : 1;
+#else
+ uint32_t push_enable : 1;
+ uint32_t reserved3 : 5;
+ uint32_t push_read_ptr : 5;
+ uint32_t reserved2 : 3;
+ uint32_t push_write_ptr : 5;
+ uint32_t reserved1 : 2;
+ uint32_t push_length : 5;
+ uint32_t push_intr_action : 2;
+ uint32_t spare : 2;
+ uint32_t push_empty : 1;
+ uint32_t push_full : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbshcsn_t;
+
+
+
+typedef union ocb_ocbshin {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 32;
+#else
+ uint32_t reserved1 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbshin_t;
+
+
+
+typedef union ocb_ocbsesn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t push_read_underflow : 1;
+ uint32_t pull_write_overflow : 1;
+ uint32_t reserved1 : 30;
+#else
+ uint32_t reserved1 : 30;
+ uint32_t pull_write_overflow : 1;
+ uint32_t push_read_underflow : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbsesn_t;
+
+
+
+typedef union ocb_ocblwcrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t linear_window_enable : 1;
+ uint32_t spare_0 : 2;
+ uint32_t linear_window_bar : 17;
+ uint32_t linear_window_mask : 12;
+#else
+ uint32_t linear_window_mask : 12;
+ uint32_t linear_window_bar : 17;
+ uint32_t spare_0 : 2;
+ uint32_t linear_window_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocblwcrn_t;
+
+
+
+typedef union ocb_ocblwsrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t linear_window_scresp : 3;
+ uint32_t spare0 : 5;
+ uint32_t reserved1 : 24;
+#else
+ uint32_t reserved1 : 24;
+ uint32_t spare0 : 5;
+ uint32_t linear_window_scresp : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocblwsrn_t;
+
+
+
+typedef union ocb_ocblwsbrn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t linear_window_region : 3;
+ uint32_t linear_window_base : 7;
+ uint32_t reserved1 : 22;
+#else
+ uint32_t reserved1 : 22;
+ uint32_t linear_window_base : 7;
+ uint32_t linear_window_region : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocblwsbrn_t;
+
+
+
+typedef union ocb_opit0cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit0cn_t;
+
+
+
+typedef union ocb_opit1cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit1cn_t;
+
+
+
+typedef union ocb_opit2cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit2cn_t;
+
+
+
+typedef union ocb_opit3cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit3cn_t;
+
+
+
+typedef union ocb_opit4cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit4cn_t;
+
+
+
+typedef union ocb_opit5cn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 20;
+ uint32_t pcb_intr_type_a_core_n : 12;
+#else
+ uint32_t pcb_intr_type_a_core_n : 12;
+ uint32_t reserved1 : 20;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit5cn_t;
+
+
+
+typedef union ocb_opit6qn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 28;
+ uint32_t pcb_intr_type_a_quad_n : 4;
+#else
+ uint32_t pcb_intr_type_a_quad_n : 4;
+ uint32_t reserved1 : 28;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit6qn_t;
+
+
+
+typedef union ocb_opit7qn {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 31;
+ uint32_t pcb_intr_type_a_quad_n : 1;
+#else
+ uint32_t pcb_intr_type_a_quad_n : 1;
+ uint32_t reserved1 : 31;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit7qn_t;
+
+
+
+typedef union ocb_opit0cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit0cnrp_t;
+
+
+
+typedef union ocb_opit1cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit1cnrp_t;
+
+
+
+typedef union ocb_opit2cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit2cnrp_t;
+
+
+
+typedef union ocb_opit3cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit3cnrp_t;
+
+
+
+typedef union ocb_opit4cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit4cnrp_t;
+
+
+
+typedef union ocb_opit5cnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+#else
+ uint32_t pcb_intr_type_a_reset_core_n : 10;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit5cnrp_t;
+
+
+
+typedef union ocb_opit6qnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_quad_n : 1;
+ uint32_t reserved2 : 9;
+#else
+ uint32_t reserved2 : 9;
+ uint32_t pcb_intr_type_a_reset_quad_n : 1;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit6qnrp_t;
+
+
+
+typedef union ocb_opit7qnrp {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved1 : 22;
+ uint32_t pcb_intr_type_a_reset_quad_n : 1;
+ uint32_t reserved2 : 9;
+#else
+ uint32_t reserved2 : 9;
+ uint32_t pcb_intr_type_a_reset_quad_n : 1;
+ uint32_t reserved1 : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit7qnrp_t;
+
+
+
+typedef union ocb_opitnpra {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opitnpra_t;
+
+
+
+typedef union ocb_opitnpra_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opitnpra_clr_t;
+
+
+
+typedef union ocb_opitnpra_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t pcb_intr_type_n_pending_23 : 1;
+ uint32_t pcb_intr_type_n_pending_22 : 1;
+ uint32_t pcb_intr_type_n_pending_21 : 1;
+ uint32_t pcb_intr_type_n_pending_20 : 1;
+ uint32_t pcb_intr_type_n_pending_19 : 1;
+ uint32_t pcb_intr_type_n_pending_18 : 1;
+ uint32_t pcb_intr_type_n_pending_17 : 1;
+ uint32_t pcb_intr_type_n_pending_16 : 1;
+ uint32_t pcb_intr_type_n_pending_15 : 1;
+ uint32_t pcb_intr_type_n_pending_14 : 1;
+ uint32_t pcb_intr_type_n_pending_13 : 1;
+ uint32_t pcb_intr_type_n_pending_12 : 1;
+ uint32_t pcb_intr_type_n_pending_11 : 1;
+ uint32_t pcb_intr_type_n_pending_10 : 1;
+ uint32_t pcb_intr_type_n_pending_9 : 1;
+ uint32_t pcb_intr_type_n_pending_8 : 1;
+ uint32_t pcb_intr_type_n_pending_7 : 1;
+ uint32_t pcb_intr_type_n_pending_6 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opitnpra_or_t;
+
+
+
+typedef union ocb_opit6prb {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit6prb_t;
+
+
+
+typedef union ocb_opit6prb_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit6prb_clr_t;
+
+
+
+typedef union ocb_opit6prb_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit6prb_or_t;
+
+
+
+typedef union ocb_opit7prb {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit7prb_t;
+
+
+
+typedef union ocb_opit7prb_clr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit7prb_clr_t;
+
+
+
+typedef union ocb_opit7prb_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t reserved1 : 26;
+#else
+ uint32_t reserved1 : 26;
+ uint32_t pcb_intr_type_n_pending_5 : 1;
+ uint32_t pcb_intr_type_n_pending_4 : 1;
+ uint32_t pcb_intr_type_n_pending_3 : 1;
+ uint32_t pcb_intr_type_n_pending_2 : 1;
+ uint32_t pcb_intr_type_n_pending_1 : 1;
+ uint32_t pcb_intr_type_n_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_opit7prb_or_t;
+
+
+
+typedef union ocb_o2sctrlf0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_frame_size_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_frame_size_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrlf0a_t;
+
+
+
+typedef union ocb_o2sctrls0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_out_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_out_count2_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrls0a_t;
+
+
+
+typedef union ocb_o2sctrl10a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_bridge_enable_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_bridge_enable_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl10a_t;
+
+
+
+typedef union ocb_o2sctrl20a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_inter_frame_delay_an : 17;
+ uint32_t reserved1 : 15;
+#else
+ uint32_t reserved1 : 15;
+ uint32_t o2s_inter_frame_delay_an : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl20a_t;
+
+
+
+typedef union ocb_o2sst0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_ongoing_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t reserved1 : 24;
+#else
+ uint32_t reserved1 : 24;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_ongoing_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sst0a_t;
+
+
+
+typedef union ocb_o2scmd0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2scmdan_reserved_0 : 1;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t reserved1 : 30;
+#else
+ uint32_t reserved1 : 30;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t o2scmdan_reserved_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2scmd0a_t;
+
+
+
+typedef union ocb_o2swd0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_wdata_an : 32;
+#else
+ uint32_t o2s_wdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2swd0a_t;
+
+
+
+typedef union ocb_o2srd0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_rdata_an : 32;
+#else
+ uint32_t o2s_rdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2srd0a_t;
+
+
+
+typedef union ocb_o2sctrlf0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_frame_size_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_frame_size_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrlf0b_t;
+
+
+
+typedef union ocb_o2sctrls0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_out_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_out_count2_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrls0b_t;
+
+
+
+typedef union ocb_o2sctrl10b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_bridge_enable_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_bridge_enable_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl10b_t;
+
+
+
+typedef union ocb_o2sctrl20b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_inter_frame_delay_an : 17;
+ uint32_t reserved1 : 15;
+#else
+ uint32_t reserved1 : 15;
+ uint32_t o2s_inter_frame_delay_an : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl20b_t;
+
+
+
+typedef union ocb_o2sst0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_ongoing_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t reserved1 : 24;
+#else
+ uint32_t reserved1 : 24;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_ongoing_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sst0b_t;
+
+
+
+typedef union ocb_o2scmd0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2scmdan_reserved_0 : 1;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t reserved1 : 30;
+#else
+ uint32_t reserved1 : 30;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t o2scmdan_reserved_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2scmd0b_t;
+
+
+
+typedef union ocb_o2swd0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_wdata_an : 32;
+#else
+ uint32_t o2s_wdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2swd0b_t;
+
+
+
+typedef union ocb_o2srd0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_rdata_an : 32;
+#else
+ uint32_t o2s_rdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2srd0b_t;
+
+
+
+typedef union ocb_o2sctrlf1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_frame_size_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_frame_size_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrlf1a_t;
+
+
+
+typedef union ocb_o2sctrls1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_out_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_out_count2_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrls1a_t;
+
+
+
+typedef union ocb_o2sctrl11a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_bridge_enable_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_bridge_enable_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl11a_t;
+
+
+
+typedef union ocb_o2sctrl21a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_inter_frame_delay_an : 17;
+ uint32_t reserved1 : 15;
+#else
+ uint32_t reserved1 : 15;
+ uint32_t o2s_inter_frame_delay_an : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl21a_t;
+
+
+
+typedef union ocb_o2sst1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_ongoing_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t reserved1 : 24;
+#else
+ uint32_t reserved1 : 24;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_ongoing_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sst1a_t;
+
+
+
+typedef union ocb_o2scmd1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2scmdan_reserved_0 : 1;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t reserved1 : 30;
+#else
+ uint32_t reserved1 : 30;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t o2scmdan_reserved_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2scmd1a_t;
+
+
+
+typedef union ocb_o2swd1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_wdata_an : 32;
+#else
+ uint32_t o2s_wdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2swd1a_t;
+
+
+
+typedef union ocb_o2srd1a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_rdata_an : 32;
+#else
+ uint32_t o2s_rdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2srd1a_t;
+
+
+
+typedef union ocb_o2sctrlf1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_frame_size_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t reserved1 : 8;
+#else
+ uint32_t reserved1 : 8;
+ uint32_t o2s_in_count1_an : 6;
+ uint32_t o2s_in_delay1_an : 6;
+ uint32_t o2s_out_count1_an : 6;
+ uint32_t o2s_frame_size_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrlf1b_t;
+
+
+
+typedef union ocb_o2sctrls1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_out_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_in_count2_an : 6;
+ uint32_t o2s_in_delay2_an : 6;
+ uint32_t o2s_out_count2_an : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrls1b_t;
+
+
+
+typedef union ocb_o2sctrl11b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_bridge_enable_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t reserved1 : 14;
+#else
+ uint32_t reserved1 : 14;
+ uint32_t o2s_nr_of_frames_an : 1;
+ uint32_t o2sctrl1an_reserved_14_16 : 3;
+ uint32_t o2s_clock_divider_an : 10;
+ uint32_t o2s_cpha_an : 1;
+ uint32_t o2s_cpol_an : 1;
+ uint32_t o2sctrl1an_reserved_1 : 1;
+ uint32_t o2s_bridge_enable_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl11b_t;
+
+
+
+typedef union ocb_o2sctrl21b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_inter_frame_delay_an : 17;
+ uint32_t reserved1 : 15;
+#else
+ uint32_t reserved1 : 15;
+ uint32_t o2s_inter_frame_delay_an : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sctrl21b_t;
+
+
+
+typedef union ocb_o2sst1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_ongoing_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t reserved1 : 24;
+#else
+ uint32_t reserved1 : 24;
+ uint32_t o2s_fsm_err_an : 1;
+ uint32_t o2sstan_reserved_6 : 1;
+ uint32_t o2s_write_while_bridge_busy_err_an : 1;
+ uint32_t o2sstan_reserved_1_4 : 4;
+ uint32_t o2s_ongoing_an : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2sst1b_t;
+
+
+
+typedef union ocb_o2scmd1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2scmdan_reserved_0 : 1;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t reserved1 : 30;
+#else
+ uint32_t reserved1 : 30;
+ uint32_t o2s_clear_sticky_bits_an : 1;
+ uint32_t o2scmdan_reserved_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2scmd1b_t;
+
+
+
+typedef union ocb_o2swd1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_wdata_an : 32;
+#else
+ uint32_t o2s_wdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2swd1b_t;
+
+
+
+typedef union ocb_o2srd1b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_rdata_an : 32;
+#else
+ uint32_t o2s_rdata_an : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_o2srd1b_t;
+
+
+
+typedef union ocb_ocr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t trace_disable : 1;
+ uint64_t trace_event : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t spare : 5;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare : 5;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t trace_event : 1;
+ uint64_t trace_disable : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t core_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocr_t;
+
+
+
+typedef union ocb_ocr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t trace_disable : 1;
+ uint64_t trace_event : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t spare : 5;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare : 5;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t trace_event : 1;
+ uint64_t trace_disable : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t core_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocr_clr_t;
+
+
+
+typedef union ocb_ocr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t trace_disable : 1;
+ uint64_t trace_event : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t spare : 5;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare : 5;
+ uint64_t ocr_dbg_halt : 1;
+ uint64_t pib_slave_reset_to_405_enable : 1;
+ uint64_t critical_interrupt : 1;
+ uint64_t ext_interrupt : 1;
+ uint64_t dbg_unconditional_event : 1;
+ uint64_t trace_event : 1;
+ uint64_t trace_disable : 1;
+ uint64_t oci_arb_reset : 1;
+ uint64_t system_reset : 1;
+ uint64_t chip_reset : 1;
+ uint64_t core_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocr_or_t;
+
+
+
+typedef union ocb_ocdbg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t mst_dis_abusparen : 1;
+ uint64_t mst_dis_beparen : 1;
+ uint64_t mst_dis_wrdbusparen : 1;
+ uint64_t mst_dis_rddbuspar : 1;
+ uint64_t mst_spare : 1;
+ uint64_t slv_dis_sack : 1;
+ uint64_t slv_dis_abuspar : 1;
+ uint64_t slv_dis_bepar : 1;
+ uint64_t slv_dis_be : 1;
+ uint64_t slv_dis_wrdbuspar : 1;
+ uint64_t slv_dis_rddbusparen : 1;
+ uint64_t slv_spare : 1;
+ uint64_t spare : 4;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare : 4;
+ uint64_t slv_spare : 1;
+ uint64_t slv_dis_rddbusparen : 1;
+ uint64_t slv_dis_wrdbuspar : 1;
+ uint64_t slv_dis_be : 1;
+ uint64_t slv_dis_bepar : 1;
+ uint64_t slv_dis_abuspar : 1;
+ uint64_t slv_dis_sack : 1;
+ uint64_t mst_spare : 1;
+ uint64_t mst_dis_rddbuspar : 1;
+ uint64_t mst_dis_wrdbusparen : 1;
+ uint64_t mst_dis_beparen : 1;
+ uint64_t mst_dis_abusparen : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocdbg_t;
+
+
+
+typedef union ocb_ojcfg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_src_sel : 1;
+ uint64_t run_tck : 1;
+ uint64_t tck_width : 3;
+ uint64_t jtag_trst_b : 1;
+ uint64_t dbg_halt : 1;
+ uint64_t reserved1 : 57;
+#else
+ uint64_t reserved1 : 57;
+ uint64_t dbg_halt : 1;
+ uint64_t jtag_trst_b : 1;
+ uint64_t tck_width : 3;
+ uint64_t run_tck : 1;
+ uint64_t jtag_src_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojcfg_t;
+
+
+
+typedef union ocb_ojcfg_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_src_sel : 1;
+ uint64_t run_tck : 1;
+ uint64_t tck_width : 3;
+ uint64_t jtag_trst_b : 1;
+ uint64_t dbg_halt : 1;
+ uint64_t reserved1 : 57;
+#else
+ uint64_t reserved1 : 57;
+ uint64_t dbg_halt : 1;
+ uint64_t jtag_trst_b : 1;
+ uint64_t tck_width : 3;
+ uint64_t run_tck : 1;
+ uint64_t jtag_src_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojcfg_clr_t;
+
+
+
+typedef union ocb_ojcfg_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_src_sel : 1;
+ uint64_t run_tck : 1;
+ uint64_t tck_width : 3;
+ uint64_t jtag_trst_b : 1;
+ uint64_t dbg_halt : 1;
+ uint64_t reserved1 : 57;
+#else
+ uint64_t reserved1 : 57;
+ uint64_t dbg_halt : 1;
+ uint64_t jtag_trst_b : 1;
+ uint64_t tck_width : 3;
+ uint64_t run_tck : 1;
+ uint64_t jtag_src_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojcfg_or_t;
+
+
+
+typedef union ocb_ojfrst {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 64;
+#else
+ uint64_t reserved1 : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojfrst_t;
+
+
+
+typedef union ocb_ojic {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t start_jtag_cmd : 1;
+ uint64_t do_ir : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t wr_valid : 1;
+ uint64_t reserved1 : 7;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved1 : 7;
+ uint64_t wr_valid : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_ir : 1;
+ uint64_t start_jtag_cmd : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojic_t;
+
+
+
+typedef union ocb_ojic_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t start_jtag_cmd : 1;
+ uint64_t do_ir : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t wr_valid : 1;
+ uint64_t reserved1 : 7;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved1 : 7;
+ uint64_t wr_valid : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_ir : 1;
+ uint64_t start_jtag_cmd : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojic_clr_t;
+
+
+
+typedef union ocb_ojic_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t start_jtag_cmd : 1;
+ uint64_t do_ir : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t wr_valid : 1;
+ uint64_t reserved1 : 7;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t jtag_instr : 4;
+ uint64_t reserved1 : 7;
+ uint64_t wr_valid : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_ir : 1;
+ uint64_t start_jtag_cmd : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojic_or_t;
+
+
+
+typedef union ocb_ojstat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_inprog : 1;
+ uint64_t src_sel_eq1_err : 1;
+ uint64_t run_tck_eq0_err : 1;
+ uint64_t trst_b_eq0_err : 1;
+ uint64_t ir_dr_eq0_err : 1;
+ uint64_t inprog_wr_err : 1;
+ uint64_t fsm_error : 1;
+ uint64_t reserved1 : 57;
+#else
+ uint64_t reserved1 : 57;
+ uint64_t fsm_error : 1;
+ uint64_t inprog_wr_err : 1;
+ uint64_t ir_dr_eq0_err : 1;
+ uint64_t trst_b_eq0_err : 1;
+ uint64_t run_tck_eq0_err : 1;
+ uint64_t src_sel_eq1_err : 1;
+ uint64_t jtag_inprog : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojstat_t;
+
+
+
+typedef union ocb_ojtdi {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_tdi : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t jtag_tdi : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojtdi_t;
+
+
+
+typedef union ocb_ojtdo {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t jtag_tdo : 32;
+ uint64_t jtag_src_sel : 1;
+ uint64_t run_tck : 1;
+ uint64_t tck_width : 3;
+ uint64_t jtag_trst_b : 1;
+ uint64_t dbg_halt : 1;
+ uint64_t reserved1 : 1;
+ uint64_t jtag_inprog : 1;
+ uint64_t src_sel_eq1_err : 1;
+ uint64_t run_tck_eq0_err : 1;
+ uint64_t trst_b_eq0_err : 1;
+ uint64_t ir_dr_eq0_err : 1;
+ uint64_t inprog_wr_err : 1;
+ uint64_t fsm_error : 1;
+ uint64_t reserved2 : 2;
+ uint64_t do_ir : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t wr_valid : 1;
+ uint64_t reserved3 : 7;
+ uint64_t jtag_instr : 4;
+#else
+ uint64_t jtag_instr : 4;
+ uint64_t reserved3 : 7;
+ uint64_t wr_valid : 1;
+ uint64_t do_tap_reset : 1;
+ uint64_t do_dr : 1;
+ uint64_t do_ir : 1;
+ uint64_t reserved2 : 2;
+ uint64_t fsm_error : 1;
+ uint64_t inprog_wr_err : 1;
+ uint64_t ir_dr_eq0_err : 1;
+ uint64_t trst_b_eq0_err : 1;
+ uint64_t run_tck_eq0_err : 1;
+ uint64_t src_sel_eq1_err : 1;
+ uint64_t jtag_inprog : 1;
+ uint64_t reserved1 : 1;
+ uint64_t dbg_halt : 1;
+ uint64_t jtag_trst_b : 1;
+ uint64_t tck_width : 3;
+ uint64_t run_tck : 1;
+ uint64_t jtag_src_sel : 1;
+ uint64_t jtag_tdo : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ojtdo_t;
+
+
+
+typedef union ocb_ocbarn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_region : 3;
+ uint64_t ocb_address : 26;
+ uint64_t reserved1 : 35;
+#else
+ uint64_t reserved1 : 35;
+ uint64_t ocb_address : 26;
+ uint64_t oci_region : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbarn_t;
+
+
+
+typedef union ocb_ocbcsrn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pull_read_underflow : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t ocb_stream_type : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare2 : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare2 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_stream_type : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbcsrn_t;
+
+
+
+typedef union ocb_ocbcsrn_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pull_read_underflow : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t ocb_stream_type : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare2 : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare2 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_stream_type : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbcsrn_clr_t;
+
+
+
+typedef union ocb_ocbcsrn_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pull_read_underflow : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t ocb_stream_type : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare2 : 1;
+ uint64_t reserved1 : 48;
+#else
+ uint64_t reserved1 : 48;
+ uint64_t spare2 : 1;
+ uint64_t ocb_fsm_err : 1;
+ uint64_t spare1 : 1;
+ uint64_t ocb_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_oci_slave_error : 1;
+ uint64_t ocb_oci_read_data_parity : 1;
+ uint64_t ocb_oci_timeout : 1;
+ uint64_t spare0 : 2;
+ uint64_t ocb_stream_type : 1;
+ uint64_t ocb_stream_mode : 1;
+ uint64_t push_write_overflow_en : 1;
+ uint64_t pull_read_underflow_en : 1;
+ uint64_t push_write_overflow : 1;
+ uint64_t pull_read_underflow : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbcsrn_or_t;
+
+
+
+typedef union ocb_ocbesrn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ocb_error_addr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t ocb_error_addr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbesrn_t;
+
+
+
+typedef union ocb_ocbdrn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ocb_data : 64;
+#else
+ uint64_t ocb_data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbdrn_t;
+
+
+
+typedef union ocb_otdcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t trace_bus_en : 1;
+ uint64_t ocb_trace_mux_sel : 1;
+ uint64_t occ_trace_mux_sel : 2;
+ uint64_t oci_trace_mux_sel : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t oci_trace_mux_sel : 4;
+ uint64_t occ_trace_mux_sel : 2;
+ uint64_t ocb_trace_mux_sel : 1;
+ uint64_t trace_bus_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_otdcr_t;
+
+
+
+typedef union ocb_oppcinj {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_err_inj_dcu : 1;
+ uint64_t oci_err_inj_icu : 1;
+ uint64_t oci_err_inj_ce_ue : 1;
+ uint64_t oci_err_inj_singl_cont : 1;
+ uint64_t reserved1 : 60;
+#else
+ uint64_t reserved1 : 60;
+ uint64_t oci_err_inj_singl_cont : 1;
+ uint64_t oci_err_inj_ce_ue : 1;
+ uint64_t oci_err_inj_icu : 1;
+ uint64_t oci_err_inj_dcu : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oppcinj_t;
+
+
+
+typedef union ocb_ostoear {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_spcl_timeout_addr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t occ_spcl_timeout_addr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ostoear_t;
+
+
+
+typedef union ocb_ostoesr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t icu_timeout_error : 1;
+ uint64_t icu_rnw : 1;
+ uint64_t reserved1 : 2;
+ uint64_t dcu_timeout_error : 1;
+ uint64_t dcu_rnw : 1;
+ uint64_t reserved2 : 58;
+#else
+ uint64_t reserved2 : 58;
+ uint64_t dcu_rnw : 1;
+ uint64_t dcu_timeout_error : 1;
+ uint64_t reserved1 : 2;
+ uint64_t icu_rnw : 1;
+ uint64_t icu_timeout_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ostoesr_t;
+
+
+
+typedef union ocb_orev {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_arb_revision : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t oci_arb_revision : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_orev_t;
+
+
+
+typedef union ocb_oesr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_m0_timeout_error : 1;
+ uint64_t oci_m0_rw_status : 1;
+ uint64_t oci_m0_oesr_flck : 1;
+ uint64_t oci_m0_oear_lock : 1;
+ uint64_t oci_m1_timeout_error : 1;
+ uint64_t oci_m1_rw_status : 1;
+ uint64_t oci_m1_oesr_flck : 1;
+ uint64_t oci_m1_oear_lock : 1;
+ uint64_t oci_m2_timeout_error : 1;
+ uint64_t oci_m2_rw_status : 1;
+ uint64_t oci_m2_oesr_flck : 1;
+ uint64_t oci_m2_oear_lock : 1;
+ uint64_t oci_m3_timeout_error : 1;
+ uint64_t oci_m3_rw_status : 1;
+ uint64_t oci_m3_oesr_flck : 1;
+ uint64_t oci_m3_oear_lock : 1;
+ uint64_t oci_m4_timeout_error : 1;
+ uint64_t oci_m4_rw_status : 1;
+ uint64_t oci_m4_oesr_flck : 1;
+ uint64_t oci_m4_oear_lock : 1;
+ uint64_t oci_m5_timeout_error : 1;
+ uint64_t oci_m5_rw_status : 1;
+ uint64_t oci_m5_oesr_flck : 1;
+ uint64_t oci_m5_oear_lock : 1;
+ uint64_t oci_m6_timeout_error : 1;
+ uint64_t oci_m6_rw_status : 1;
+ uint64_t oci_m6_oesr_flck : 1;
+ uint64_t oci_m6_oear_lock : 1;
+ uint64_t oci_m7_timeout_error : 1;
+ uint64_t oci_m7_rw_status : 1;
+ uint64_t oci_m7_oesr_flck : 1;
+ uint64_t oci_m7_oear_lock : 1;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t oci_m7_oear_lock : 1;
+ uint64_t oci_m7_oesr_flck : 1;
+ uint64_t oci_m7_rw_status : 1;
+ uint64_t oci_m7_timeout_error : 1;
+ uint64_t oci_m6_oear_lock : 1;
+ uint64_t oci_m6_oesr_flck : 1;
+ uint64_t oci_m6_rw_status : 1;
+ uint64_t oci_m6_timeout_error : 1;
+ uint64_t oci_m5_oear_lock : 1;
+ uint64_t oci_m5_oesr_flck : 1;
+ uint64_t oci_m5_rw_status : 1;
+ uint64_t oci_m5_timeout_error : 1;
+ uint64_t oci_m4_oear_lock : 1;
+ uint64_t oci_m4_oesr_flck : 1;
+ uint64_t oci_m4_rw_status : 1;
+ uint64_t oci_m4_timeout_error : 1;
+ uint64_t oci_m3_oear_lock : 1;
+ uint64_t oci_m3_oesr_flck : 1;
+ uint64_t oci_m3_rw_status : 1;
+ uint64_t oci_m3_timeout_error : 1;
+ uint64_t oci_m2_oear_lock : 1;
+ uint64_t oci_m2_oesr_flck : 1;
+ uint64_t oci_m2_rw_status : 1;
+ uint64_t oci_m2_timeout_error : 1;
+ uint64_t oci_m1_oear_lock : 1;
+ uint64_t oci_m1_oesr_flck : 1;
+ uint64_t oci_m1_rw_status : 1;
+ uint64_t oci_m1_timeout_error : 1;
+ uint64_t oci_m0_oear_lock : 1;
+ uint64_t oci_m0_oesr_flck : 1;
+ uint64_t oci_m0_rw_status : 1;
+ uint64_t oci_m0_timeout_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oesr_t;
+
+
+
+typedef union ocb_oear {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_timeout_addr : 32;
+ uint64_t reserved1 : 32;
+#else
+ uint64_t reserved1 : 32;
+ uint64_t oci_timeout_addr : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oear_t;
+
+
+
+typedef union ocb_oacr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_priority_mode : 1;
+ uint64_t oci_priority_order : 3;
+ uint64_t oci_hi_bus_mode : 1;
+ uint64_t oci_read_pipeline_control : 2;
+ uint64_t oci_write_pipeline_control : 1;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t oci_write_pipeline_control : 1;
+ uint64_t oci_read_pipeline_control : 2;
+ uint64_t oci_hi_bus_mode : 1;
+ uint64_t oci_priority_order : 3;
+ uint64_t oci_priority_mode : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_oacr_t;
+
+
+
+typedef union ocb_ocbear {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ocb_error_address : 32;
+ uint64_t reserved1 : 3;
+ uint64_t direct_bridge_source : 1;
+ uint64_t indirect_bridge_0_source : 1;
+ uint64_t indirect_bridge_1_source : 1;
+ uint64_t indirect_bridge_2_source : 1;
+ uint64_t indirect_bridge_3_source : 1;
+ uint64_t reserved2 : 24;
+#else
+ uint64_t reserved2 : 24;
+ uint64_t indirect_bridge_3_source : 1;
+ uint64_t indirect_bridge_2_source : 1;
+ uint64_t indirect_bridge_1_source : 1;
+ uint64_t indirect_bridge_0_source : 1;
+ uint64_t direct_bridge_source : 1;
+ uint64_t reserved1 : 3;
+ uint64_t ocb_error_address : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_ocbear_t;
+
+
+
+typedef union ocb_occlfir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0 : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t ocb_error : 1;
+ uint64_t srt_ue : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t external_trap : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+#else
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t external_trap : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_ue : 1;
+ uint64_t ocb_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t occ_fw0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfir_t;
+
+
+
+typedef union ocb_occlfir_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0 : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t ocb_error : 1;
+ uint64_t srt_ue : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t external_trap : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+#else
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t external_trap : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_ue : 1;
+ uint64_t ocb_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t occ_fw0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfir_and_t;
+
+
+
+typedef union ocb_occlfir_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0 : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t ocb_error : 1;
+ uint64_t srt_ue : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t external_trap : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+#else
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_58_61 : 4;
+ uint64_t occ_complex_fault_safe : 1;
+ uint64_t c405dcu_m_timeout : 1;
+ uint64_t c405icu_m_timeout : 1;
+ uint64_t gpe3_ocislv_err : 1;
+ uint64_t gpe2_ocislv_err : 1;
+ uint64_t gpe1_ocislv_err : 1;
+ uint64_t gpe0_ocislv_err : 1;
+ uint64_t sram_spare_direct_error3 : 1;
+ uint64_t sram_spare_direct_error2 : 1;
+ uint64_t sram_spare_direct_error1 : 1;
+ uint64_t sram_spare_direct_error0 : 1;
+ uint64_t c405_oci_machinecheck : 1;
+ uint64_t c405_ecc_ce : 1;
+ uint64_t c405_ecc_ue : 1;
+ uint64_t spare_err_38 : 1;
+ uint64_t jtagacc_err : 1;
+ uint64_t srt_fsm_err : 1;
+ uint64_t ocb_idc3_error : 1;
+ uint64_t ocb_idc2_error : 1;
+ uint64_t ocb_idc1_error : 1;
+ uint64_t ocb_idc0_error : 1;
+ uint64_t ocb_db_pib_data_parity_err : 1;
+ uint64_t ocb_pib_addr_parity_err : 1;
+ uint64_t ocb_db_oci_slave_error : 1;
+ uint64_t ocb_db_oci_read_data_parity : 1;
+ uint64_t ocb_db_oci_timeout : 1;
+ uint64_t ppc405_dbgstopack : 1;
+ uint64_t ppc405_dbgmsrwe : 1;
+ uint64_t ppc405_system_reset : 1;
+ uint64_t ppc405_chip_reset : 1;
+ uint64_t ppc405_core_reset : 1;
+ uint64_t external_trap : 1;
+ uint64_t gpe3_halted : 1;
+ uint64_t gpe2_halted : 1;
+ uint64_t gpe1_halted : 1;
+ uint64_t gpe0_halted : 1;
+ uint64_t srt_oci_addr_parity_err : 1;
+ uint64_t srt_oci_be_parity_err : 1;
+ uint64_t srt_oci_write_data_parity : 1;
+ uint64_t srt_dataout_perr : 1;
+ uint64_t srt_write_error : 1;
+ uint64_t srt_read_error : 1;
+ uint64_t srt_ce : 1;
+ uint64_t srt_ue : 1;
+ uint64_t ocb_error : 1;
+ uint64_t gpe3_error : 1;
+ uint64_t gpe2_error : 1;
+ uint64_t gpe1_error : 1;
+ uint64_t gpe0_error : 1;
+ uint64_t gpe3_watchdog_timeout : 1;
+ uint64_t gpe2_watchdog_timeout : 1;
+ uint64_t gpe1_watchdog_timeout : 1;
+ uint64_t gpe0_watchdog_timeout : 1;
+ uint64_t occ_hb_error : 1;
+ uint64_t stop_recovery_notify_prd : 1;
+ uint64_t cme_error_notify : 1;
+ uint64_t occ_fw1 : 1;
+ uint64_t occ_fw0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfir_or_t;
+
+
+
+typedef union ocb_occlfirmask {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t fir_parity_err_mask : 1;
+#else
+ uint64_t fir_parity_err_mask : 1;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t occ_fw0_mask : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfirmask_t;
+
+
+
+typedef union ocb_occlfirmask_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t fir_parity_err_mask : 1;
+#else
+ uint64_t fir_parity_err_mask : 1;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t occ_fw0_mask : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfirmask_and_t;
+
+
+
+typedef union ocb_occlfirmask_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_fw0_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t fir_parity_err_mask : 1;
+#else
+ uint64_t fir_parity_err_mask : 1;
+ uint64_t fir_parity_err_dup_mask : 1;
+ uint64_t spare_58_61_mask : 4;
+ uint64_t occ_complex_fault_safe_mask : 1;
+ uint64_t c405dcu_m_timeout_mask : 1;
+ uint64_t c405icu_m_timeout_mask : 1;
+ uint64_t gpe3_ocislv_err_mask : 1;
+ uint64_t gpe2_ocislv_err_mask : 1;
+ uint64_t gpe1_ocislv_err_mask : 1;
+ uint64_t gpe0_ocislv_err_mask : 1;
+ uint64_t sram_spare_direct_error3_mask : 1;
+ uint64_t sram_spare_direct_error2_mask : 1;
+ uint64_t sram_spare_direct_error1_mask : 1;
+ uint64_t sram_spare_direct_error0_mask : 1;
+ uint64_t c405_oci_machinecheck_mask : 1;
+ uint64_t c405_ecc_ce_mask : 1;
+ uint64_t c405_ecc_ue_mask : 1;
+ uint64_t spare_err_38_mask : 1;
+ uint64_t jtagacc_err_mask : 1;
+ uint64_t srt_fsm_err_mask : 1;
+ uint64_t ocb_idc3_error_mask : 1;
+ uint64_t ocb_idc2_error_mask : 1;
+ uint64_t ocb_idc1_error_mask : 1;
+ uint64_t ocb_idc0_error_mask : 1;
+ uint64_t ocb_db_pib_data_parity_err_mask : 1;
+ uint64_t ocb_pib_addr_parity_err_mask : 1;
+ uint64_t ocb_db_oci_slave_error_mask : 1;
+ uint64_t ocb_db_oci_read_data_parity_mask : 1;
+ uint64_t ocb_db_oci_timeout_mask : 1;
+ uint64_t ppc405_dbgstopack_mask : 1;
+ uint64_t ppc405_dbgmsrwe_mask : 1;
+ uint64_t ppc405_system_reset_mask : 1;
+ uint64_t ppc405_chip_reset_mask : 1;
+ uint64_t ppc405_core_reset_mask : 1;
+ uint64_t external_trap_mask : 1;
+ uint64_t gpe3_halted_mask : 1;
+ uint64_t gpe2_halted_mask : 1;
+ uint64_t gpe1_halted_mask : 1;
+ uint64_t gpe0_halted_mask : 1;
+ uint64_t srt_oci_addr_parity_err_mask : 1;
+ uint64_t srt_oci_be_parity_err_mask : 1;
+ uint64_t srt_oci_write_data_parity_mask : 1;
+ uint64_t srt_dataout_perr_mask : 1;
+ uint64_t srt_write_error_mask : 1;
+ uint64_t srt_read_error_mask : 1;
+ uint64_t srt_ce_mask : 1;
+ uint64_t srt_ue_mask : 1;
+ uint64_t ocb_error_mask : 1;
+ uint64_t gpe3_error_mask : 1;
+ uint64_t gpe2_error_mask : 1;
+ uint64_t gpe1_error_mask : 1;
+ uint64_t gpe0_error_mask : 1;
+ uint64_t gpe3_watchdog_timeout_mask : 1;
+ uint64_t gpe2_watchdog_timeout_mask : 1;
+ uint64_t gpe1_watchdog_timeout_mask : 1;
+ uint64_t gpe0_watchdog_timeout_mask : 1;
+ uint64_t occ_hb_malf_mask : 1;
+ uint64_t spare_3_mask : 1;
+ uint64_t spare_2_mask : 1;
+ uint64_t occ_fw1_mask : 1;
+ uint64_t occ_fw0_mask : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfirmask_or_t;
+
+
+
+typedef union ocb_occlfiract0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_action0 : 64;
+#else
+ uint64_t fir_action0 : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfiract0_t;
+
+
+
+typedef union ocb_occlfiract1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fir_action1 : 64;
+#else
+ uint64_t fir_action1 : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfiract1_t;
+
+
+
+typedef union ocb_occlfirwof {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t wof : 64;
+#else
+ uint64_t wof : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occlfirwof_t;
+
+
+
+typedef union ocb_occerrrpt {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t sram_cerrrpt : 10;
+ uint64_t jtagacc_cerrpt : 6;
+ uint64_t c405_dcu_ecc_ue : 1;
+ uint64_t c405_dcu_ecc_ce : 1;
+ uint64_t c405_icu_ecc_ue : 1;
+ uint64_t c405_icu_ecc_ce : 1;
+ uint64_t gpe0_ocislv_err : 7;
+ uint64_t reserved1 : 1;
+ uint64_t gpe1_ocislv_err : 7;
+ uint64_t reserved2 : 1;
+ uint64_t gpe2_ocislv_err : 7;
+ uint64_t reserved3 : 1;
+ uint64_t gpe3_ocislv_err : 7;
+ uint64_t reserved4 : 1;
+ uint64_t ocb_ocislv_err : 7;
+ uint64_t reserved5 : 5;
+#else
+ uint64_t reserved5 : 5;
+ uint64_t ocb_ocislv_err : 7;
+ uint64_t reserved4 : 1;
+ uint64_t gpe3_ocislv_err : 7;
+ uint64_t reserved3 : 1;
+ uint64_t gpe2_ocislv_err : 7;
+ uint64_t reserved2 : 1;
+ uint64_t gpe1_ocislv_err : 7;
+ uint64_t reserved1 : 1;
+ uint64_t gpe0_ocislv_err : 7;
+ uint64_t c405_icu_ecc_ce : 1;
+ uint64_t c405_icu_ecc_ue : 1;
+ uint64_t c405_dcu_ecc_ce : 1;
+ uint64_t c405_dcu_ecc_ue : 1;
+ uint64_t jtagacc_cerrpt : 6;
+ uint64_t sram_cerrrpt : 10;
+#endif // _BIG_ENDIAN
+ } fields;
+} ocb_occerrrpt_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __OCB_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/ocb_register_addresses.h b/src/include/registers/ocb_register_addresses.h
new file mode 100644
index 0000000..8fc1025
--- /dev/null
+++ b/src/include/registers/ocb_register_addresses.h
@@ -0,0 +1,631 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/ocb_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __OCB_REGISTER_ADDRESSES_H__
+#define __OCB_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ocb_register_addresses.h
+/// \brief Symbolic addresses for the OCB unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define OCB_OCI_BASE 0xC0060000
+#define OCB_OISR0 0xc0060000
+#define OCB_OISR0_CLR 0xc0060008
+#define OCB_OISR0_OR 0xc0060010
+#define OCB_OIMR0 0xc0060020
+#define OCB_OIMR0_CLR 0xc0060028
+#define OCB_OIMR0_OR 0xc0060030
+#define OCB_OITR0 0xc0060040
+#define OCB_OITR0_CLR 0xc0060048
+#define OCB_OITR0_OR 0xc0060050
+#define OCB_OIEPR0 0xc0060060
+#define OCB_OIEPR0_CLR 0xc0060068
+#define OCB_OIEPR0_OR 0xc0060070
+#define OCB_OISR1 0xc0060100
+#define OCB_OISR1_CLR 0xc0060108
+#define OCB_OISR1_OR 0xc0060110
+#define OCB_OIMR1 0xc0060120
+#define OCB_OIMR1_CLR 0xc0060128
+#define OCB_OIMR1_OR 0xc0060130
+#define OCB_OITR1 0xc0060140
+#define OCB_OITR1_CLR 0xc0060148
+#define OCB_OITR1_OR 0xc0060150
+#define OCB_OIEPR1 0xc0060160
+#define OCB_OIEPR1_CLR 0xc0060168
+#define OCB_OIEPR1_OR 0xc0060170
+#define OCB_OIRR0A 0xc0060200
+#define OCB_OIRR0A_CLR 0xc0060208
+#define OCB_OIRR0A_OR 0xc0060210
+#define OCB_OIRR0B 0xc0060220
+#define OCB_OIRR0B_CLR 0xc0060228
+#define OCB_OIRR0B_OR 0xc0060230
+#define OCB_OIRR0C 0xc0060240
+#define OCB_OIRR0C_CLR 0xc0060248
+#define OCB_OIRR0C_OR 0xc0060250
+#define OCB_OIRR1A 0xc0060280
+#define OCB_OIRR1A_CLR 0xc0060288
+#define OCB_OIRR1A_OR 0xc0060290
+#define OCB_OIRR1B 0xc00602a0
+#define OCB_OIRR1B_CLR 0xc00602a8
+#define OCB_OIRR1B_OR 0xc00602b0
+#define OCB_OIRR1C 0xc00602c0
+#define OCB_OIRR1C_CLR 0xc00602c8
+#define OCB_OIRR1C_OR 0xc00602d0
+#define OCB_ONISR0 0xc0060300
+#define OCB_OCISR0 0xc0060308
+#define OCB_OUISR0 0xc0060310
+#define OCB_ODISR0 0xc0060318
+#define OCB_G0ISR0 0xc0060320
+#define OCB_G1ISR0 0xc0060328
+#define OCB_G2ISR0 0xc0060330
+#define OCB_G3ISR0 0xc0060338
+#define OCB_ONISR1 0xc0060380
+#define OCB_OCISR1 0xc0060388
+#define OCB_OUISR1 0xc0060390
+#define OCB_ODISR1 0xc0060398
+#define OCB_G0ISR1 0xc00603a0
+#define OCB_G1ISR1 0xc00603a8
+#define OCB_G2ISR1 0xc00603b0
+#define OCB_G3ISR1 0xc00603b8
+#define OCB_OCCMISC 0xc0060400
+#define OCB_OCCMISC_CLR 0xc0060408
+#define OCB_OCCMISC_OR 0xc0060410
+#define OCB_OHTMCR 0xc0060418
+#define OCB_OEHDR 0xc0060420
+#define OCB_OCICFG 0xc0060428
+#define OCB_OCCS0 0xc0060430
+#define OCB_OCCS1 0xc0060438
+#define OCB_OCCS2 0xc0060440
+#define OCB_OCCFLG 0xc0060450
+#define OCB_OCCFLG_CLR 0xc0060458
+#define OCB_OCCFLG_OR 0xc0060460
+#define OCB_OCCHBR 0xc0060478
+#define OCB_CCSR 0xc0060480
+#define OCB_CCSR_CLR 0xc0060488
+#define OCB_CCSR_OR 0xc0060490
+#define OCB_QCSR 0xc00604a0
+#define OCB_QCSR_CLR 0xc00604a8
+#define OCB_QCSR_OR 0xc00604b0
+#define OCB_QSSR 0xc00604c0
+#define OCB_QSSR_CLR 0xc00604c8
+#define OCB_QSSR_OR 0xc00604d0
+#define OCB_OTBR 0xc00604f8
+#define OCB_OTRN(n) (OCB_OTR0 + ((OCB_OTR1 - OCB_OTR0) * (n)))
+#define OCB_OTR0 0xc0060800
+#define OCB_OTR1 0xc0060808
+#define OCB_OCBSLBRN(n) (OCB_OCBSLBR0 + ((OCB_OCBSLBR1 - OCB_OCBSLBR0) * (n)))
+#define OCB_OCBSLBR0 0xc0061000
+#define OCB_OCBSLBR1 0xc0061080
+#define OCB_OCBSLBR2 0xc0061100
+#define OCB_OCBSLBR3 0xc0061180
+#define OCB_OCBSLCSN(n) (OCB_OCBSLCS0 + ((OCB_OCBSLCS1 - OCB_OCBSLCS0) * (n)))
+#define OCB_OCBSLCS0 0xc0061008
+#define OCB_OCBSLCS1 0xc0061088
+#define OCB_OCBSLCS2 0xc0061108
+#define OCB_OCBSLCS3 0xc0061188
+#define OCB_OCBSLIN(n) (OCB_OCBSLI0 + ((OCB_OCBSLI1 - OCB_OCBSLI0) * (n)))
+#define OCB_OCBSLI0 0xc0061010
+#define OCB_OCBSLI1 0xc0061090
+#define OCB_OCBSLI2 0xc0061110
+#define OCB_OCBSLI3 0xc0061190
+#define OCB_OCBSHBRN(n) (OCB_OCBSHBR0 + ((OCB_OCBSHBR1 - OCB_OCBSHBR0) * (n)))
+#define OCB_OCBSHBR0 0xc0061018
+#define OCB_OCBSHBR1 0xc0061098
+#define OCB_OCBSHBR2 0xc0061118
+#define OCB_OCBSHBR3 0xc0061198
+#define OCB_OCBSHCSN(n) (OCB_OCBSHCS0 + ((OCB_OCBSHCS1 - OCB_OCBSHCS0) * (n)))
+#define OCB_OCBSHCS0 0xc0061020
+#define OCB_OCBSHCS1 0xc00610a0
+#define OCB_OCBSHCS2 0xc0061120
+#define OCB_OCBSHCS3 0xc00611a0
+#define OCB_OCBSHIN(n) (OCB_OCBSHI0 + ((OCB_OCBSHI1 - OCB_OCBSHI0) * (n)))
+#define OCB_OCBSHI0 0xc0061028
+#define OCB_OCBSHI1 0xc00610a8
+#define OCB_OCBSHI2 0xc0061128
+#define OCB_OCBSHI3 0xc00611a8
+#define OCB_OCBSESN(n) (OCB_OCBSES0 + ((OCB_OCBSES1 - OCB_OCBSES0) * (n)))
+#define OCB_OCBSES0 0xc0061030
+#define OCB_OCBSES1 0xc00610b0
+#define OCB_OCBSES2 0xc0061130
+#define OCB_OCBSES3 0xc00611b0
+#define OCB_OCBLWCRN(n) (OCB_OCBLWCR0 + ((OCB_OCBLWCR1 - OCB_OCBLWCR0) * (n)))
+#define OCB_OCBLWCR0 0xc0061040
+#define OCB_OCBLWCR1 0xc00610c0
+#define OCB_OCBLWCR2 0xc0061140
+#define OCB_OCBLWCR3 0xc00611c0
+#define OCB_OCBLWSRN(n) (OCB_OCBLWSR0 + ((OCB_OCBLWSR1 - OCB_OCBLWSR0) * (n)))
+#define OCB_OCBLWSR0 0xc0061050
+#define OCB_OCBLWSR1 0xc00610d0
+#define OCB_OCBLWSR2 0xc0061150
+#define OCB_OCBLWSR3 0xc00611d0
+#define OCB_OCBLWSBRN(n) (OCB_OCBLWSBR0 + ((OCB_OCBLWSBR1 - OCB_OCBLWSBR0) * (n)))
+#define OCB_OCBLWSBR0 0xc0061060
+#define OCB_OCBLWSBR1 0xc00610e0
+#define OCB_OCBLWSBR2 0xc0061160
+#define OCB_OCBLWSBR3 0xc00611e0
+#define OCB_OPIT0CN(n) (OCB_OPIT0C0 + ((OCB_OPIT0C1 - OCB_OPIT0C0) * (n)))
+#define OCB_OPIT0C0 0xc0062000
+#define OCB_OPIT0C1 0xc0062008
+#define OCB_OPIT0C2 0xc0062010
+#define OCB_OPIT0C3 0xc0062018
+#define OCB_OPIT0C4 0xc0062020
+#define OCB_OPIT0C5 0xc0062028
+#define OCB_OPIT0C6 0xc0062030
+#define OCB_OPIT0C7 0xc0062038
+#define OCB_OPIT0C8 0xc0062040
+#define OCB_OPIT0C9 0xc0062048
+#define OCB_OPIT0C10 0xc0062050
+#define OCB_OPIT0C11 0xc0062058
+#define OCB_OPIT0C12 0xc0062060
+#define OCB_OPIT0C13 0xc0062068
+#define OCB_OPIT0C14 0xc0062070
+#define OCB_OPIT0C15 0xc0062078
+#define OCB_OPIT0C16 0xc0062080
+#define OCB_OPIT0C17 0xc0062088
+#define OCB_OPIT0C18 0xc0062090
+#define OCB_OPIT0C19 0xc0062098
+#define OCB_OPIT0C20 0xc00620a0
+#define OCB_OPIT0C21 0xc00620a8
+#define OCB_OPIT0C22 0xc00620b0
+#define OCB_OPIT0C23 0xc00620b8
+#define OCB_OPIT1CN(n) (OCB_OPIT1C0 + ((OCB_OPIT1C1 - OCB_OPIT1C0) * (n)))
+#define OCB_OPIT1C0 0xc0062100
+#define OCB_OPIT1C1 0xc0062108
+#define OCB_OPIT1C2 0xc0062110
+#define OCB_OPIT1C3 0xc0062118
+#define OCB_OPIT1C4 0xc0062120
+#define OCB_OPIT1C5 0xc0062128
+#define OCB_OPIT1C6 0xc0062130
+#define OCB_OPIT1C7 0xc0062138
+#define OCB_OPIT1C8 0xc0062140
+#define OCB_OPIT1C9 0xc0062148
+#define OCB_OPIT1C10 0xc0062150
+#define OCB_OPIT1C11 0xc0062158
+#define OCB_OPIT1C12 0xc0062160
+#define OCB_OPIT1C13 0xc0062168
+#define OCB_OPIT1C14 0xc0062170
+#define OCB_OPIT1C15 0xc0062178
+#define OCB_OPIT1C16 0xc0062180
+#define OCB_OPIT1C17 0xc0062188
+#define OCB_OPIT1C18 0xc0062190
+#define OCB_OPIT1C19 0xc0062198
+#define OCB_OPIT1C20 0xc00621a0
+#define OCB_OPIT1C21 0xc00621a8
+#define OCB_OPIT1C22 0xc00621b0
+#define OCB_OPIT1C23 0xc00621b8
+#define OCB_OPIT2CN(n) (OCB_OPIT2C0 + ((OCB_OPIT2C1 - OCB_OPIT2C0) * (n)))
+#define OCB_OPIT2C0 0xc0062200
+#define OCB_OPIT2C1 0xc0062208
+#define OCB_OPIT2C2 0xc0062210
+#define OCB_OPIT2C3 0xc0062218
+#define OCB_OPIT2C4 0xc0062220
+#define OCB_OPIT2C5 0xc0062228
+#define OCB_OPIT2C6 0xc0062230
+#define OCB_OPIT2C7 0xc0062238
+#define OCB_OPIT2C8 0xc0062240
+#define OCB_OPIT2C9 0xc0062248
+#define OCB_OPIT2C10 0xc0062250
+#define OCB_OPIT2C11 0xc0062258
+#define OCB_OPIT2C12 0xc0062260
+#define OCB_OPIT2C13 0xc0062268
+#define OCB_OPIT2C14 0xc0062270
+#define OCB_OPIT2C15 0xc0062278
+#define OCB_OPIT2C16 0xc0062280
+#define OCB_OPIT2C17 0xc0062288
+#define OCB_OPIT2C18 0xc0062290
+#define OCB_OPIT2C19 0xc0062298
+#define OCB_OPIT2C20 0xc00622a0
+#define OCB_OPIT2C21 0xc00622a8
+#define OCB_OPIT2C22 0xc00622b0
+#define OCB_OPIT2C23 0xc00622b8
+#define OCB_OPIT3CN(n) (OCB_OPIT3C0 + ((OCB_OPIT3C1 - OCB_OPIT3C0) * (n)))
+#define OCB_OPIT3C0 0xc0062300
+#define OCB_OPIT3C1 0xc0062308
+#define OCB_OPIT3C2 0xc0062310
+#define OCB_OPIT3C3 0xc0062318
+#define OCB_OPIT3C4 0xc0062320
+#define OCB_OPIT3C5 0xc0062328
+#define OCB_OPIT3C6 0xc0062330
+#define OCB_OPIT3C7 0xc0062338
+#define OCB_OPIT3C8 0xc0062340
+#define OCB_OPIT3C9 0xc0062348
+#define OCB_OPIT3C10 0xc0062350
+#define OCB_OPIT3C11 0xc0062358
+#define OCB_OPIT3C12 0xc0062360
+#define OCB_OPIT3C13 0xc0062368
+#define OCB_OPIT3C14 0xc0062370
+#define OCB_OPIT3C15 0xc0062378
+#define OCB_OPIT3C16 0xc0062380
+#define OCB_OPIT3C17 0xc0062388
+#define OCB_OPIT3C18 0xc0062390
+#define OCB_OPIT3C19 0xc0062398
+#define OCB_OPIT3C20 0xc00623a0
+#define OCB_OPIT3C21 0xc00623a8
+#define OCB_OPIT3C22 0xc00623b0
+#define OCB_OPIT3C23 0xc00623b8
+#define OCB_OPIT4CN(n) (OCB_OPIT4C0 + ((OCB_OPIT4C1 - OCB_OPIT4C0) * (n)))
+#define OCB_OPIT4C0 0xc0062400
+#define OCB_OPIT4C1 0xc0062408
+#define OCB_OPIT4C2 0xc0062410
+#define OCB_OPIT4C3 0xc0062418
+#define OCB_OPIT4C4 0xc0062420
+#define OCB_OPIT4C5 0xc0062428
+#define OCB_OPIT4C6 0xc0062430
+#define OCB_OPIT4C7 0xc0062438
+#define OCB_OPIT4C8 0xc0062440
+#define OCB_OPIT4C9 0xc0062448
+#define OCB_OPIT4C10 0xc0062450
+#define OCB_OPIT4C11 0xc0062458
+#define OCB_OPIT4C12 0xc0062460
+#define OCB_OPIT4C13 0xc0062468
+#define OCB_OPIT4C14 0xc0062470
+#define OCB_OPIT4C15 0xc0062478
+#define OCB_OPIT4C16 0xc0062480
+#define OCB_OPIT4C17 0xc0062488
+#define OCB_OPIT4C18 0xc0062490
+#define OCB_OPIT4C19 0xc0062498
+#define OCB_OPIT4C20 0xc00624a0
+#define OCB_OPIT4C21 0xc00624a8
+#define OCB_OPIT4C22 0xc00624b0
+#define OCB_OPIT4C23 0xc00624b8
+#define OCB_OPIT5CN(n) (OCB_OPIT5C0 + ((OCB_OPIT5C1 - OCB_OPIT5C0) * (n)))
+#define OCB_OPIT5C0 0xc0062500
+#define OCB_OPIT5C1 0xc0062508
+#define OCB_OPIT5C2 0xc0062510
+#define OCB_OPIT5C3 0xc0062518
+#define OCB_OPIT5C4 0xc0062520
+#define OCB_OPIT5C5 0xc0062528
+#define OCB_OPIT5C6 0xc0062530
+#define OCB_OPIT5C7 0xc0062538
+#define OCB_OPIT5C8 0xc0062540
+#define OCB_OPIT5C9 0xc0062548
+#define OCB_OPIT5C10 0xc0062550
+#define OCB_OPIT5C11 0xc0062558
+#define OCB_OPIT5C12 0xc0062560
+#define OCB_OPIT5C13 0xc0062568
+#define OCB_OPIT5C14 0xc0062570
+#define OCB_OPIT5C15 0xc0062578
+#define OCB_OPIT5C16 0xc0062580
+#define OCB_OPIT5C17 0xc0062588
+#define OCB_OPIT5C18 0xc0062590
+#define OCB_OPIT5C19 0xc0062598
+#define OCB_OPIT5C20 0xc00625a0
+#define OCB_OPIT5C21 0xc00625a8
+#define OCB_OPIT5C22 0xc00625b0
+#define OCB_OPIT5C23 0xc00625b8
+#define OCB_OPIT6QN(n) (OCB_OPIT6Q0 + ((OCB_OPIT6Q1 - OCB_OPIT6Q0) * (n)))
+#define OCB_OPIT6Q0 0xc0062600
+#define OCB_OPIT6Q1 0xc0062608
+#define OCB_OPIT6Q2 0xc0062610
+#define OCB_OPIT6Q3 0xc0062618
+#define OCB_OPIT6Q4 0xc0062620
+#define OCB_OPIT6Q5 0xc0062628
+#define OCB_OPIT7QN(n) (OCB_OPIT7Q0 + ((OCB_OPIT7Q1 - OCB_OPIT7Q0) * (n)))
+#define OCB_OPIT7Q0 0xc0062700
+#define OCB_OPIT7Q1 0xc0062708
+#define OCB_OPIT7Q2 0xc0062710
+#define OCB_OPIT7Q3 0xc0062718
+#define OCB_OPIT7Q4 0xc0062720
+#define OCB_OPIT7Q5 0xc0062728
+#define OCB_OPIT0CNRP(n) (OCB_OPIT0C0RP + ((OCB_OPIT0C1RP - OCB_OPIT0C0RP) * (n)))
+#define OCB_OPIT0C0RP 0xc0062800
+#define OCB_OPIT0C1RP 0xc0062808
+#define OCB_OPIT0C2RP 0xc0062810
+#define OCB_OPIT0C3RP 0xc0062818
+#define OCB_OPIT0C4RP 0xc0062820
+#define OCB_OPIT0C5RP 0xc0062828
+#define OCB_OPIT0C6RP 0xc0062830
+#define OCB_OPIT0C7RP 0xc0062838
+#define OCB_OPIT0C8RP 0xc0062840
+#define OCB_OPIT0C9RP 0xc0062848
+#define OCB_OPIT0C10RP 0xc0062850
+#define OCB_OPIT0C11RP 0xc0062858
+#define OCB_OPIT0C12RP 0xc0062860
+#define OCB_OPIT0C13RP 0xc0062868
+#define OCB_OPIT0C14RP 0xc0062870
+#define OCB_OPIT0C15RP 0xc0062878
+#define OCB_OPIT0C16RP 0xc0062880
+#define OCB_OPIT0C17RP 0xc0062888
+#define OCB_OPIT0C18RP 0xc0062890
+#define OCB_OPIT0C19RP 0xc0062898
+#define OCB_OPIT0C20RP 0xc00628a0
+#define OCB_OPIT0C21RP 0xc00628a8
+#define OCB_OPIT0C22RP 0xc00628b0
+#define OCB_OPIT0C23RP 0xc00628b8
+#define OCB_OPIT1CNRP(n) (OCB_OPIT1C0RP + ((OCB_OPIT1C1RP - OCB_OPIT1C0RP) * (n)))
+#define OCB_OPIT1C0RP 0xc0062900
+#define OCB_OPIT1C1RP 0xc0062908
+#define OCB_OPIT1C2RP 0xc0062910
+#define OCB_OPIT1C3RP 0xc0062918
+#define OCB_OPIT1C4RP 0xc0062920
+#define OCB_OPIT1C5RP 0xc0062928
+#define OCB_OPIT1C6RP 0xc0062930
+#define OCB_OPIT1C7RP 0xc0062938
+#define OCB_OPIT1C8RP 0xc0062940
+#define OCB_OPIT1C9RP 0xc0062948
+#define OCB_OPIT1C10RP 0xc0062950
+#define OCB_OPIT1C11RP 0xc0062958
+#define OCB_OPIT1C12RP 0xc0062960
+#define OCB_OPIT1C13RP 0xc0062968
+#define OCB_OPIT1C14RP 0xc0062970
+#define OCB_OPIT1C15RP 0xc0062978
+#define OCB_OPIT1C16RP 0xc0062980
+#define OCB_OPIT1C17RP 0xc0062988
+#define OCB_OPIT1C18RP 0xc0062990
+#define OCB_OPIT1C19RP 0xc0062998
+#define OCB_OPIT1C20RP 0xc00629a0
+#define OCB_OPIT1C21RP 0xc00629a8
+#define OCB_OPIT1C22RP 0xc00629b0
+#define OCB_OPIT1C23RP 0xc00629b8
+#define OCB_OPIT2CNRP(n) (OCB_OPIT2C0RP + ((OCB_OPIT2C1RP - OCB_OPIT2C0RP) * (n)))
+#define OCB_OPIT2C0RP 0xc0062a00
+#define OCB_OPIT2C1RP 0xc0062a08
+#define OCB_OPIT2C2RP 0xc0062a10
+#define OCB_OPIT2C3RP 0xc0062a18
+#define OCB_OPIT2C4RP 0xc0062a20
+#define OCB_OPIT2C5RP 0xc0062a28
+#define OCB_OPIT2C6RP 0xc0062a30
+#define OCB_OPIT2C7RP 0xc0062a38
+#define OCB_OPIT2C8RP 0xc0062a40
+#define OCB_OPIT2C9RP 0xc0062a48
+#define OCB_OPIT2C10RP 0xc0062a50
+#define OCB_OPIT2C11RP 0xc0062a58
+#define OCB_OPIT2C12RP 0xc0062a60
+#define OCB_OPIT2C13RP 0xc0062a68
+#define OCB_OPIT2C14RP 0xc0062a70
+#define OCB_OPIT2C15RP 0xc0062a78
+#define OCB_OPIT2C16RP 0xc0062a80
+#define OCB_OPIT2C17RP 0xc0062a88
+#define OCB_OPIT2C18RP 0xc0062a90
+#define OCB_OPIT2C19RP 0xc0062a98
+#define OCB_OPIT2C20RP 0xc0062aa0
+#define OCB_OPIT2C21RP 0xc0062aa8
+#define OCB_OPIT2C22RP 0xc0062ab0
+#define OCB_OPIT2C23RP 0xc0062ab8
+#define OCB_OPIT3CNRP(n) (OCB_OPIT3C0RP + ((OCB_OPIT3C1RP - OCB_OPIT3C0RP) * (n)))
+#define OCB_OPIT3C0RP 0xc0062b00
+#define OCB_OPIT3C1RP 0xc0062b08
+#define OCB_OPIT3C2RP 0xc0062b10
+#define OCB_OPIT3C3RP 0xc0062b18
+#define OCB_OPIT3C4RP 0xc0062b20
+#define OCB_OPIT3C5RP 0xc0062b28
+#define OCB_OPIT3C6RP 0xc0062b30
+#define OCB_OPIT3C7RP 0xc0062b38
+#define OCB_OPIT3C8RP 0xc0062b40
+#define OCB_OPIT3C9RP 0xc0062b48
+#define OCB_OPIT3C10RP 0xc0062b50
+#define OCB_OPIT3C11RP 0xc0062b58
+#define OCB_OPIT3C12RP 0xc0062b60
+#define OCB_OPIT3C13RP 0xc0062b68
+#define OCB_OPIT3C14RP 0xc0062b70
+#define OCB_OPIT3C15RP 0xc0062b78
+#define OCB_OPIT3C16RP 0xc0062b80
+#define OCB_OPIT3C17RP 0xc0062b88
+#define OCB_OPIT3C18RP 0xc0062b90
+#define OCB_OPIT3C19RP 0xc0062b98
+#define OCB_OPIT3C20RP 0xc0062ba0
+#define OCB_OPIT3C21RP 0xc0062ba8
+#define OCB_OPIT3C22RP 0xc0062bb0
+#define OCB_OPIT3C23RP 0xc0062bb8
+#define OCB_OPIT4CNRP(n) (OCB_OPIT4C0RP + ((OCB_OPIT4C1RP - OCB_OPIT4C0RP) * (n)))
+#define OCB_OPIT4C0RP 0xc0062c00
+#define OCB_OPIT4C1RP 0xc0062c08
+#define OCB_OPIT4C2RP 0xc0062c10
+#define OCB_OPIT4C3RP 0xc0062c18
+#define OCB_OPIT4C4RP 0xc0062c20
+#define OCB_OPIT4C5RP 0xc0062c28
+#define OCB_OPIT4C6RP 0xc0062c30
+#define OCB_OPIT4C7RP 0xc0062c38
+#define OCB_OPIT4C8RP 0xc0062c40
+#define OCB_OPIT4C9RP 0xc0062c48
+#define OCB_OPIT4C10RP 0xc0062c50
+#define OCB_OPIT4C11RP 0xc0062c58
+#define OCB_OPIT4C12RP 0xc0062c60
+#define OCB_OPIT4C13RP 0xc0062c68
+#define OCB_OPIT4C14RP 0xc0062c70
+#define OCB_OPIT4C15RP 0xc0062c78
+#define OCB_OPIT4C16RP 0xc0062c80
+#define OCB_OPIT4C17RP 0xc0062c88
+#define OCB_OPIT4C18RP 0xc0062c90
+#define OCB_OPIT4C19RP 0xc0062c98
+#define OCB_OPIT4C20RP 0xc0062ca0
+#define OCB_OPIT4C21RP 0xc0062ca8
+#define OCB_OPIT4C22RP 0xc0062cb0
+#define OCB_OPIT4C23RP 0xc0062cb8
+#define OCB_OPIT5CNRP(n) (OCB_OPIT5C0RP + ((OCB_OPIT5C1RP - OCB_OPIT5C0RP) * (n)))
+#define OCB_OPIT5C0RP 0xc0062d00
+#define OCB_OPIT5C1RP 0xc0062d08
+#define OCB_OPIT5C2RP 0xc0062d10
+#define OCB_OPIT5C3RP 0xc0062d18
+#define OCB_OPIT5C4RP 0xc0062d20
+#define OCB_OPIT5C5RP 0xc0062d28
+#define OCB_OPIT5C6RP 0xc0062d30
+#define OCB_OPIT5C7RP 0xc0062d38
+#define OCB_OPIT5C8RP 0xc0062d40
+#define OCB_OPIT5C9RP 0xc0062d48
+#define OCB_OPIT5C10RP 0xc0062d50
+#define OCB_OPIT5C11RP 0xc0062d58
+#define OCB_OPIT5C12RP 0xc0062d60
+#define OCB_OPIT5C13RP 0xc0062d68
+#define OCB_OPIT5C14RP 0xc0062d70
+#define OCB_OPIT5C15RP 0xc0062d78
+#define OCB_OPIT5C16RP 0xc0062d80
+#define OCB_OPIT5C17RP 0xc0062d88
+#define OCB_OPIT5C18RP 0xc0062d90
+#define OCB_OPIT5C19RP 0xc0062d98
+#define OCB_OPIT5C20RP 0xc0062da0
+#define OCB_OPIT5C21RP 0xc0062da8
+#define OCB_OPIT5C22RP 0xc0062db0
+#define OCB_OPIT5C23RP 0xc0062db8
+#define OCB_OPIT6QNRP(n) (OCB_OPIT6Q0RP + ((OCB_OPIT6Q1RP - OCB_OPIT6Q0RP) * (n)))
+#define OCB_OPIT6Q0RP 0xc0062e00
+#define OCB_OPIT6Q1RP 0xc0062e08
+#define OCB_OPIT6Q2RP 0xc0062e10
+#define OCB_OPIT6Q3RP 0xc0062e18
+#define OCB_OPIT6Q4RP 0xc0062e20
+#define OCB_OPIT6Q5RP 0xc0062e28
+#define OCB_OPIT7QNRP(n) (OCB_OPIT7Q0RP + ((OCB_OPIT7Q1RP - OCB_OPIT7Q0RP) * (n)))
+#define OCB_OPIT7Q0RP 0xc0062f00
+#define OCB_OPIT7Q1RP 0xc0062f08
+#define OCB_OPIT7Q2RP 0xc0062f10
+#define OCB_OPIT7Q3RP 0xc0062f18
+#define OCB_OPIT7Q4RP 0xc0062f20
+#define OCB_OPIT7Q5RP 0xc0062f28
+#define OCB_OPITNPRA(n) (OCB_OPIT0PRA + ((OCB_OPIT1PRA - OCB_OPIT0PRA) * (n)))
+#define OCB_OPIT0PRA 0xc0063000
+#define OCB_OPIT1PRA 0xc0063100
+#define OCB_OPIT2PRA 0xc0063200
+#define OCB_OPIT3PRA 0xc0063300
+#define OCB_OPIT4PRA 0xc0063400
+#define OCB_OPIT5PRA 0xc0063500
+#define OCB_OPITNPRA_CLR(n) (OCB_OPIT0PRA_CLR + ((OCB_OPIT1PRA_CLR - OCB_OPIT0PRA_CLR) * (n)))
+#define OCB_OPIT0PRA_CLR 0xc0063008
+#define OCB_OPIT1PRA_CLR 0xc0063108
+#define OCB_OPIT2PRA_CLR 0xc0063208
+#define OCB_OPIT3PRA_CLR 0xc0063308
+#define OCB_OPIT4PRA_CLR 0xc0063408
+#define OCB_OPIT5PRA_CLR 0xc0063508
+#define OCB_OPITNPRA_OR(n) (OCB_OPIT0PRA_OR + ((OCB_OPIT1PRA_OR - OCB_OPIT0PRA_OR) * (n)))
+#define OCB_OPIT0PRA_OR 0xc0063010
+#define OCB_OPIT1PRA_OR 0xc0063110
+#define OCB_OPIT2PRA_OR 0xc0063210
+#define OCB_OPIT3PRA_OR 0xc0063310
+#define OCB_OPIT4PRA_OR 0xc0063410
+#define OCB_OPIT5PRA_OR 0xc0063510
+#define OCB_OPIT6PRB 0xc0063600
+#define OCB_OPIT6PRB_CLR 0xc0063608
+#define OCB_OPIT6PRB_OR 0xc0063610
+#define OCB_OPIT7PRB 0xc0063700
+#define OCB_OPIT7PRB_CLR 0xc0063708
+#define OCB_OPIT7PRB_OR 0xc0063710
+#define OCB_O2SCTRLF0A 0xc0063800
+#define OCB_O2SCTRLS0A 0xc0063808
+#define OCB_O2SCTRL10A 0xc0063810
+#define OCB_O2SCTRL20A 0xc0063818
+#define OCB_O2SST0A 0xc0063830
+#define OCB_O2SCMD0A 0xc0063838
+#define OCB_O2SWD0A 0xc0063840
+#define OCB_O2SRD0A 0xc0063848
+#define OCB_O2SCTRLF0B 0xc0063880
+#define OCB_O2SCTRLS0B 0xc0063888
+#define OCB_O2SCTRL10B 0xc0063890
+#define OCB_O2SCTRL20B 0xc0063898
+#define OCB_O2SST0B 0xc00638b0
+#define OCB_O2SCMD0B 0xc00638b8
+#define OCB_O2SWD0B 0xc00638c0
+#define OCB_O2SRD0B 0xc00638c8
+#define OCB_O2SCTRLF1A 0xc0063900
+#define OCB_O2SCTRLS1A 0xc0063908
+#define OCB_O2SCTRL11A 0xc0063910
+#define OCB_O2SCTRL21A 0xc0063918
+#define OCB_O2SST1A 0xc0063930
+#define OCB_O2SCMD1A 0xc0063938
+#define OCB_O2SWD1A 0xc0063940
+#define OCB_O2SRD1A 0xc0063948
+#define OCB_O2SCTRLF1B 0xc0063980
+#define OCB_O2SCTRLS1B 0xc0063988
+#define OCB_O2SCTRL11B 0xc0063990
+#define OCB_O2SCTRL21B 0xc0063998
+#define OCB_O2SST1B 0xc00639b0
+#define OCB_O2SCMD1B 0xc00639b8
+#define OCB_O2SWD1B 0xc00639c0
+#define OCB_O2SRD1B 0xc00639c8
+#define OCB_PIB_BASE 0x6C000
+#define OCB_OCR 0x0006d000
+#define OCB_OCR_CLR 0x0006d001
+#define OCB_OCR_OR 0x0006d002
+#define OCB_OCDBG 0x0006d003
+#define OCB_OJCFG 0x0006d004
+#define OCB_OJCFG_CLR 0x0006d005
+#define OCB_OJCFG_OR 0x0006d006
+#define OCB_OJFRST 0x0006d007
+#define OCB_OJIC 0x0006d008
+#define OCB_OJIC_CLR 0x0006d009
+#define OCB_OJIC_OR 0x0006d00a
+#define OCB_OJSTAT 0x0006d00b
+#define OCB_OJTDI 0x0006d00c
+#define OCB_OJTDO 0x0006d00d
+#define OCB_OCBARN(n) (OCB_OCBAR0 + ((OCB_OCBAR1 - OCB_OCBAR0) * (n)))
+#define OCB_OCBAR0 0x0006d010
+#define OCB_OCBAR1 0x0006d030
+#define OCB_OCBAR2 0x0006d050
+#define OCB_OCBAR3 0x0006d070
+#define OCB_OCBCSRN(n) (OCB_OCBCSR0 + ((OCB_OCBCSR1 - OCB_OCBCSR0) * (n)))
+#define OCB_OCBCSR0 0x0006d011
+#define OCB_OCBCSR1 0x0006d031
+#define OCB_OCBCSR2 0x0006d051
+#define OCB_OCBCSR3 0x0006d071
+#define OCB_OCBCSRN_CLR(n) (OCB_OCBCSR0_CLR + ((OCB_OCBCSR1_CLR - OCB_OCBCSR0_CLR) * (n)))
+#define OCB_OCBCSR0_CLR 0x0006d012
+#define OCB_OCBCSR1_CLR 0x0006d032
+#define OCB_OCBCSR2_CLR 0x0006d052
+#define OCB_OCBCSR3_CLR 0x0006d072
+#define OCB_OCBCSRN_OR(n) (OCB_OCBCSR0_OR + ((OCB_OCBCSR1_OR - OCB_OCBCSR0_OR) * (n)))
+#define OCB_OCBCSR0_OR 0x0006d013
+#define OCB_OCBCSR1_OR 0x0006d033
+#define OCB_OCBCSR2_OR 0x0006d053
+#define OCB_OCBCSR3_OR 0x0006d073
+#define OCB_OCBESRN(n) (OCB_OCBESR0 + ((OCB_OCBESR1 - OCB_OCBESR0) * (n)))
+#define OCB_OCBESR0 0x0006d014
+#define OCB_OCBESR1 0x0006d034
+#define OCB_OCBESR2 0x0006d054
+#define OCB_OCBESR3 0x0006d074
+#define OCB_OCBDRN(n) (OCB_OCBDR0 + ((OCB_OCBDR1 - OCB_OCBDR0) * (n)))
+#define OCB_OCBDR0 0x0006d015
+#define OCB_OCBDR1 0x0006d035
+#define OCB_OCBDR2 0x0006d055
+#define OCB_OCBDR3 0x0006d075
+#define OCB_OTDCR 0x0006d110
+#define OCB_OPPCINJ 0x0006d111
+#define OCB_OSTOEAR 0x0006d200
+#define OCB_OSTOESR 0x0006d201
+#define OCB_OREV 0x0006d202
+#define OCB_OESR 0x0006d204
+#define OCB_OEAR 0x0006d206
+#define OCB_OACR 0x0006d207
+#define OCB_OCBEAR 0x0006d210
+#define OCB_FIRPIB_BASE 0x01010800
+#define OCB_OCCLFIR 0x01020800
+#define OCB_OCCLFIR_AND 0x01020801
+#define OCB_OCCLFIR_OR 0x01020802
+#define OCB_OCCLFIRMASK 0x01020803
+#define OCB_OCCLFIRMASK_AND 0x01020804
+#define OCB_OCCLFIRMASK_OR 0x01020805
+#define OCB_OCCLFIRACT0 0x01020806
+#define OCB_OCCLFIRACT1 0x01020807
+#define OCB_OCCLFIRWOF 0x01020808
+#define OCB_OCCERRRPT 0x0102080a
+
+#endif // __OCB_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/pba_firmware_registers.h b/src/include/registers/pba_firmware_registers.h
new file mode 100644
index 0000000..e1b9f24
--- /dev/null
+++ b/src/include/registers/pba_firmware_registers.h
@@ -0,0 +1,2208 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/pba_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PBA_FIRMWARE_REGISTERS_H__
+#define __PBA_FIRMWARE_REGISTERS_H__
+
+// $Id: pba_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_firmware_registers.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pba_firmware_registers.h
+/// \brief C register structs for the PBA unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union pba_barn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cmd_scope : 3;
+ uint64_t reserved0 : 1;
+ uint64_t reserved1 : 10;
+ uint64_t addr : 30;
+ uint64_t _reserved0 : 20;
+#else
+ uint64_t _reserved0 : 20;
+ uint64_t addr : 30;
+ uint64_t reserved1 : 10;
+ uint64_t reserved0 : 1;
+ uint64_t cmd_scope : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_barn_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
+#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_barmskn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved0 : 23;
+ uint64_t mask : 21;
+ uint64_t _reserved0 : 20;
+#else
+ uint64_t _reserved0 : 20;
+ uint64_t mask : 21;
+ uint64_t reserved0 : 23;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_barmskn_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_fir {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_fir_t;
+
+#endif // __ASSEMBLER__
+#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
+#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
+#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
+#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
+#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
+#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
+#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
+#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
+#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
+#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
+#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
+#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
+#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
+#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
+#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
+#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
+#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
+#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
+#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
+#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
+#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
+#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
+#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
+#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
+#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
+#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
+#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
+#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
+#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
+#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
+#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
+#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
+#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
+#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
+#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
+#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
+#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
+#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
+#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000)
+#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
+#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_fir_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_fir_and_t;
+
+
+
+typedef union pba_fir_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_fir_or_t;
+
+
+
+typedef union pba_firmask {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_firmask_t;
+
+
+
+typedef union pba_firmask_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_firmask_and_t;
+
+
+
+typedef union pba_firmask_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_firmask_or_t;
+
+
+
+typedef union pba_firact0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_firact0_t;
+
+
+
+typedef union pba_firact1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_firact1_t;
+
+
+
+typedef union pba_occact {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t oci_apar_err : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t internal_err : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t reserved41 : 3;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 18;
+#else
+ uint64_t _reserved0 : 18;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err2 : 1;
+ uint64_t reserved41 : 3;
+ uint64_t pb_ackdead_fw_wr : 1;
+ uint64_t axsnd_rsverr : 1;
+ uint64_t axsnd_rsvto : 1;
+ uint64_t axsnd_dlo_rtyto : 1;
+ uint64_t axsnd_dhi_rtyto : 1;
+ uint64_t axflow_err : 1;
+ uint64_t axrcv_rsvdata_to : 1;
+ uint64_t axrcv_dlo_to : 1;
+ uint64_t axrcv_dlo_err : 1;
+ uint64_t axpush_wrerr : 1;
+ uint64_t oci_bad_reg_addr : 1;
+ uint64_t illegal_cache_op : 1;
+ uint64_t internal_err : 1;
+ uint64_t bcde_oci_dataerr : 1;
+ uint64_t bcde_ce : 1;
+ uint64_t bcde_ue_err : 1;
+ uint64_t bcde_sue_err : 1;
+ uint64_t bcde_rddatato_err : 1;
+ uint64_t bcde_pb_adrerr : 1;
+ uint64_t bcde_pb_ack_dead : 1;
+ uint64_t bcde_setup_err : 1;
+ uint64_t bcue_oci_dataerr : 1;
+ uint64_t bcue_pb_adrerr : 1;
+ uint64_t bcue_pb_ack_dead : 1;
+ uint64_t bcue_setup_err : 1;
+ uint64_t pb_crespto : 1;
+ uint64_t pb_ackdead_fw : 1;
+ uint64_t pb_badcresp : 1;
+ uint64_t pb_wradrerr_fw : 1;
+ uint64_t pb_parity_err : 1;
+ uint64_t pb_unexpdata : 1;
+ uint64_t pb_unexpcresp : 1;
+ uint64_t oci_rereqto : 1;
+ uint64_t oci_wrpar_err : 1;
+ uint64_t oci_slave_init : 1;
+ uint64_t pb_ce_fw : 1;
+ uint64_t pb_ue_fw : 1;
+ uint64_t pb_sue_fw : 1;
+ uint64_t pb_rddatato_fw : 1;
+ uint64_t pb_rdadrerr_fw : 1;
+ uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_occact_t;
+
+
+
+typedef union pba_cfg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pbreq_slvfw_max_priority : 2;
+ uint64_t pbreq_bce_max_priority : 2;
+ uint64_t pbreq_data_hang_div : 5;
+ uint64_t pbreq_oper_hang_div : 5;
+ uint64_t pbreq_drop_priority_mask : 6;
+ uint64_t reserved20 : 4;
+ uint64_t chsw_hang_on_adrerror : 1;
+ uint64_t chsw_dis_ociabuspar_check : 1;
+ uint64_t chsw_dis_ocibepar_check : 1;
+ uint64_t chsw_hang_on_derror : 1;
+ uint64_t chsw_hang_on_rereq_timeout : 1;
+ uint64_t chsw_dis_write_match_rearb : 1;
+ uint64_t chsw_dis_ocidatapar_gen : 1;
+ uint64_t chsw_dis_ocidatapar_check : 1;
+ uint64_t chsw_dis_oper_hang : 1;
+ uint64_t chsw_dis_data_hang : 1;
+ uint64_t chsw_dis_ecc_check : 1;
+ uint64_t chsw_dis_retry_backoff : 1;
+ uint64_t chsw_hang_on_invalid_cresp : 1;
+ uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
+ uint64_t chsw_dis_group_scope : 1;
+ uint64_t chsw_dis_rtag_parity_chk : 1;
+ uint64_t chsw_dis_pb_parity_chk : 1;
+ uint64_t _reserved0 : 23;
+#else
+ uint64_t _reserved0 : 23;
+ uint64_t chsw_dis_pb_parity_chk : 1;
+ uint64_t chsw_dis_rtag_parity_chk : 1;
+ uint64_t chsw_dis_group_scope : 1;
+ uint64_t chsw_en_scopeinc_on_bkill_inc : 1;
+ uint64_t chsw_hang_on_invalid_cresp : 1;
+ uint64_t chsw_dis_retry_backoff : 1;
+ uint64_t chsw_dis_ecc_check : 1;
+ uint64_t chsw_dis_data_hang : 1;
+ uint64_t chsw_dis_oper_hang : 1;
+ uint64_t chsw_dis_ocidatapar_check : 1;
+ uint64_t chsw_dis_ocidatapar_gen : 1;
+ uint64_t chsw_dis_write_match_rearb : 1;
+ uint64_t chsw_hang_on_rereq_timeout : 1;
+ uint64_t chsw_hang_on_derror : 1;
+ uint64_t chsw_dis_ocibepar_check : 1;
+ uint64_t chsw_dis_ociabuspar_check : 1;
+ uint64_t chsw_hang_on_adrerror : 1;
+ uint64_t reserved20 : 4;
+ uint64_t pbreq_drop_priority_mask : 6;
+ uint64_t pbreq_oper_hang_div : 5;
+ uint64_t pbreq_data_hang_div : 5;
+ uint64_t pbreq_bce_max_priority : 2;
+ uint64_t pbreq_slvfw_max_priority : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_cfg_t;
+
+
+
+typedef union pba_errpt0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cerr_pb_rddatato_fw : 6;
+ uint64_t cerr_pb_rdadrerr_fw : 6;
+ uint64_t cerr_pb_wradrerr_fw : 4;
+ uint64_t cerr_pb_ackdead_fw_rd : 6;
+ uint64_t cerr_pb_ackdead_fw_wr : 2;
+ uint64_t cerr_pb_unexpcresp : 11;
+ uint64_t cerr_pb_unexpdata : 6;
+ uint64_t _reserved0 : 23;
+#else
+ uint64_t _reserved0 : 23;
+ uint64_t cerr_pb_unexpdata : 6;
+ uint64_t cerr_pb_unexpcresp : 11;
+ uint64_t cerr_pb_ackdead_fw_wr : 2;
+ uint64_t cerr_pb_ackdead_fw_rd : 6;
+ uint64_t cerr_pb_wradrerr_fw : 4;
+ uint64_t cerr_pb_rdadrerr_fw : 6;
+ uint64_t cerr_pb_rddatato_fw : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_errpt0_t;
+
+
+
+typedef union pba_errpt1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cerr_pb_badcresp : 12;
+ uint64_t cerr_pb_crespto : 12;
+ uint64_t cerr_oci_rereqto : 6;
+ uint64_t cerr_bcde_setup_err : 2;
+ uint64_t cerr_bcue_setup_err : 2;
+ uint64_t cerr_bcue_oci_dataerr : 2;
+ uint64_t _reserved0 : 28;
+#else
+ uint64_t _reserved0 : 28;
+ uint64_t cerr_bcue_oci_dataerr : 2;
+ uint64_t cerr_bcue_setup_err : 2;
+ uint64_t cerr_bcde_setup_err : 2;
+ uint64_t cerr_oci_rereqto : 6;
+ uint64_t cerr_pb_crespto : 12;
+ uint64_t cerr_pb_badcresp : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_errpt1_t;
+
+
+
+typedef union pba_errpt2 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cerr_slv_internal_err : 8;
+ uint64_t cerr_bcde_internal_err : 4;
+ uint64_t cerr_bcue_internal_err : 4;
+ uint64_t cerr_bar_parity_err : 1;
+ uint64_t cerr_scomtb_err : 1;
+ uint64_t reserved18 : 2;
+ uint64_t cerr_pbdout_parity_err : 1;
+ uint64_t cerr_pb_parity_err : 3;
+ uint64_t cerr_axflow_err : 5;
+ uint64_t cerr_axpush_wrerr : 2;
+ uint64_t _reserved0 : 33;
+#else
+ uint64_t _reserved0 : 33;
+ uint64_t cerr_axpush_wrerr : 2;
+ uint64_t cerr_axflow_err : 5;
+ uint64_t cerr_pb_parity_err : 3;
+ uint64_t cerr_pbdout_parity_err : 1;
+ uint64_t reserved18 : 2;
+ uint64_t cerr_scomtb_err : 1;
+ uint64_t cerr_bar_parity_err : 1;
+ uint64_t cerr_bcue_internal_err : 4;
+ uint64_t cerr_bcde_internal_err : 4;
+ uint64_t cerr_slv_internal_err : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_errpt2_t;
+
+
+
+typedef union pba_rbufvaln {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t rd_slvnum : 2;
+ uint64_t cur_rd_addr : 23;
+ uint64_t spare1 : 3;
+ uint64_t prefetch : 1;
+ uint64_t spare2 : 2;
+ uint64_t abort : 1;
+ uint64_t spare3 : 1;
+ uint64_t buffer_status : 7;
+ uint64_t spare4 : 1;
+ uint64_t masterid : 3;
+ uint64_t _reserved0 : 20;
+#else
+ uint64_t _reserved0 : 20;
+ uint64_t masterid : 3;
+ uint64_t spare4 : 1;
+ uint64_t buffer_status : 7;
+ uint64_t spare3 : 1;
+ uint64_t abort : 1;
+ uint64_t spare2 : 2;
+ uint64_t prefetch : 1;
+ uint64_t spare1 : 3;
+ uint64_t cur_rd_addr : 23;
+ uint64_t rd_slvnum : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_rbufvaln_t;
+
+
+
+typedef union pba_wbufvaln {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t wr_slvnum : 2;
+ uint64_t start_wr_addr : 30;
+ uint64_t spare1 : 3;
+ uint64_t wr_buffer_status : 5;
+ uint64_t spare2 : 1;
+ uint64_t wr_byte_count : 7;
+ uint64_t spare3 : 16;
+#else
+ uint64_t spare3 : 16;
+ uint64_t wr_byte_count : 7;
+ uint64_t spare2 : 1;
+ uint64_t wr_buffer_status : 5;
+ uint64_t spare1 : 3;
+ uint64_t start_wr_addr : 30;
+ uint64_t wr_slvnum : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_wbufvaln_t;
+
+
+
+typedef union pba_mode {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved0 : 4;
+ uint64_t dis_rearb : 1;
+ uint64_t dis_mstid_match_pref_inv : 1;
+ uint64_t dis_slave_rdpipe : 1;
+ uint64_t dis_slave_wrpipe : 1;
+ uint64_t en_marker_ack : 1;
+ uint64_t dis_slvmatch_order : 1;
+ uint64_t en_second_wrbuf : 1;
+ uint64_t dis_rerequest_to : 1;
+ uint64_t inject_type : 2;
+ uint64_t inject_mode : 2;
+ uint64_t pba_region : 2;
+ uint64_t oci_marker_space : 3;
+ uint64_t bcde_ocitrans : 2;
+ uint64_t bcue_ocitrans : 2;
+ uint64_t dis_master_rd_pipe : 1;
+ uint64_t dis_master_wr_pipe : 1;
+ uint64_t en_slave_fairness : 1;
+ uint64_t en_event_count : 1;
+ uint64_t pb_noci_event_sel : 1;
+ uint64_t slv_event_mux : 2;
+ uint64_t enable_debug_bus : 1;
+ uint64_t debug_pb_not_oci : 1;
+ uint64_t debug_oci_mode : 5;
+ uint64_t reserved2 : 1;
+ uint64_t ocislv_fairness_mask : 5;
+ uint64_t ocislv_rereq_hang_div : 5;
+ uint64_t dis_chgrate_count : 1;
+ uint64_t pbreq_event_mux : 2;
+ uint64_t _reserved0 : 11;
+#else
+ uint64_t _reserved0 : 11;
+ uint64_t pbreq_event_mux : 2;
+ uint64_t dis_chgrate_count : 1;
+ uint64_t ocislv_rereq_hang_div : 5;
+ uint64_t ocislv_fairness_mask : 5;
+ uint64_t reserved2 : 1;
+ uint64_t debug_oci_mode : 5;
+ uint64_t debug_pb_not_oci : 1;
+ uint64_t enable_debug_bus : 1;
+ uint64_t slv_event_mux : 2;
+ uint64_t pb_noci_event_sel : 1;
+ uint64_t en_event_count : 1;
+ uint64_t en_slave_fairness : 1;
+ uint64_t dis_master_wr_pipe : 1;
+ uint64_t dis_master_rd_pipe : 1;
+ uint64_t bcue_ocitrans : 2;
+ uint64_t bcde_ocitrans : 2;
+ uint64_t oci_marker_space : 3;
+ uint64_t pba_region : 2;
+ uint64_t inject_mode : 2;
+ uint64_t inject_type : 2;
+ uint64_t dis_rerequest_to : 1;
+ uint64_t en_second_wrbuf : 1;
+ uint64_t dis_slvmatch_order : 1;
+ uint64_t en_marker_ack : 1;
+ uint64_t dis_slave_wrpipe : 1;
+ uint64_t dis_slave_rdpipe : 1;
+ uint64_t dis_mstid_match_pref_inv : 1;
+ uint64_t dis_rearb : 1;
+ uint64_t reserved0 : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_mode_t;
+
+
+
+typedef union pba_slvrst {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t set : 3;
+ uint64_t notimp1 : 1;
+ uint64_t in_prog : 4;
+ uint64_t busy_status : 4;
+ uint64_t _reserved0 : 52;
+#else
+ uint64_t _reserved0 : 52;
+ uint64_t busy_status : 4;
+ uint64_t in_prog : 4;
+ uint64_t notimp1 : 1;
+ uint64_t set : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_slvrst_t;
+
+
+
+typedef union pba_slvctln {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t enable : 1;
+ uint64_t mid_match_value : 3;
+ uint64_t _reserved0 : 1;
+ uint64_t mid_care_mask : 3;
+ uint64_t write_ttype : 3;
+ uint64_t _reserved1 : 4;
+ uint64_t read_ttype : 1;
+ uint64_t read_prefetch_ctl : 2;
+ uint64_t buf_invalidate_ctl : 1;
+ uint64_t buf_alloc_w : 1;
+ uint64_t buf_alloc_a : 1;
+ uint64_t buf_alloc_b : 1;
+ uint64_t buf_alloc_c : 1;
+ uint64_t _reserved2 : 1;
+ uint64_t dis_write_gather : 1;
+ uint64_t wr_gather_timeout : 3;
+ uint64_t write_tsize : 7;
+ uint64_t extaddr : 14;
+ uint64_t _reserved3 : 15;
+#else
+ uint64_t _reserved3 : 15;
+ uint64_t extaddr : 14;
+ uint64_t write_tsize : 7;
+ uint64_t wr_gather_timeout : 3;
+ uint64_t dis_write_gather : 1;
+ uint64_t _reserved2 : 1;
+ uint64_t buf_alloc_c : 1;
+ uint64_t buf_alloc_b : 1;
+ uint64_t buf_alloc_a : 1;
+ uint64_t buf_alloc_w : 1;
+ uint64_t buf_invalidate_ctl : 1;
+ uint64_t read_prefetch_ctl : 2;
+ uint64_t read_ttype : 1;
+ uint64_t _reserved1 : 4;
+ uint64_t write_ttype : 3;
+ uint64_t mid_care_mask : 3;
+ uint64_t _reserved0 : 1;
+ uint64_t mid_match_value : 3;
+ uint64_t enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_slvctln_t;
+
+
+
+typedef union pba_bcde_ctl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t stop : 1;
+ uint64_t start : 1;
+ uint64_t _reserved0 : 62;
+#else
+ uint64_t _reserved0 : 62;
+ uint64_t start : 1;
+ uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcde_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcde_set {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t _reserved0 : 2;
+ uint64_t copy_length : 6;
+ uint64_t _reserved1 : 56;
+#else
+ uint64_t _reserved1 : 56;
+ uint64_t copy_length : 6;
+ uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcde_set_t;
+
+
+
+typedef union pba_bcde_stat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t running : 1;
+ uint64_t waiting : 1;
+ uint64_t wrcmp : 6;
+ uint64_t _reserved0 : 6;
+ uint64_t rdcmp : 6;
+ uint64_t debug : 9;
+ uint64_t stopped : 1;
+ uint64_t error : 1;
+ uint64_t done : 1;
+ uint64_t _reserved1 : 32;
+#else
+ uint64_t _reserved1 : 32;
+ uint64_t done : 1;
+ uint64_t error : 1;
+ uint64_t stopped : 1;
+ uint64_t debug : 9;
+ uint64_t rdcmp : 6;
+ uint64_t _reserved0 : 6;
+ uint64_t wrcmp : 6;
+ uint64_t waiting : 1;
+ uint64_t running : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcde_stat_t;
+
+
+
+typedef union pba_bcde_pbadr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t _reserved0 : 2;
+ uint64_t pb_offset : 23;
+ uint64_t _reserved1 : 2;
+ uint64_t extaddr : 14;
+ uint64_t _reserved2 : 23;
+#else
+ uint64_t _reserved2 : 23;
+ uint64_t extaddr : 14;
+ uint64_t _reserved1 : 2;
+ uint64_t pb_offset : 23;
+ uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcde_pbadr_t;
+
+
+
+typedef union pba_bcde_ocibar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t addr : 25;
+ uint64_t _reserved0 : 39;
+#else
+ uint64_t _reserved0 : 39;
+ uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcde_ocibar_t;
+
+
+
+typedef union pba_bcue_ctl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t stop : 1;
+ uint64_t start : 1;
+ uint64_t _reserved0 : 62;
+#else
+ uint64_t _reserved0 : 62;
+ uint64_t start : 1;
+ uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcue_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcue_set {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t _reserved0 : 2;
+ uint64_t copy_length : 6;
+ uint64_t _reserved1 : 56;
+#else
+ uint64_t _reserved1 : 56;
+ uint64_t copy_length : 6;
+ uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcue_set_t;
+
+
+
+typedef union pba_bcue_stat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t running : 1;
+ uint64_t waiting : 1;
+ uint64_t wrcmp : 6;
+ uint64_t _reserved0 : 6;
+ uint64_t rdcmp : 6;
+ uint64_t debug : 9;
+ uint64_t stopped : 1;
+ uint64_t error : 1;
+ uint64_t done : 1;
+ uint64_t _reserved1 : 32;
+#else
+ uint64_t _reserved1 : 32;
+ uint64_t done : 1;
+ uint64_t error : 1;
+ uint64_t stopped : 1;
+ uint64_t debug : 9;
+ uint64_t rdcmp : 6;
+ uint64_t _reserved0 : 6;
+ uint64_t wrcmp : 6;
+ uint64_t waiting : 1;
+ uint64_t running : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcue_stat_t;
+
+
+
+typedef union pba_bcue_pbadr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t _reserved0 : 2;
+ uint64_t pb_offset : 23;
+ uint64_t _reserved1 : 2;
+ uint64_t extaddr : 14;
+ uint64_t _reserved2 : 23;
+#else
+ uint64_t _reserved2 : 23;
+ uint64_t extaddr : 14;
+ uint64_t _reserved1 : 2;
+ uint64_t pb_offset : 23;
+ uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcue_pbadr_t;
+
+
+
+typedef union pba_bcue_ocibar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t addr : 25;
+ uint64_t _reserved0 : 39;
+#else
+ uint64_t _reserved0 : 39;
+ uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_bcue_ocibar_t;
+
+
+
+typedef union pba_pbocrn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t _reserved0 : 16;
+ uint64_t event : 16;
+ uint64_t _reserved1 : 12;
+ uint64_t accum : 20;
+#else
+ uint64_t accum : 20;
+ uint64_t _reserved1 : 12;
+ uint64_t event : 16;
+ uint64_t _reserved0 : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_pbocrn_t;
+
+
+
+typedef union pba_xsndtx {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t snd_scope : 3;
+ uint64_t snd_qid : 1;
+ uint64_t snd_type : 1;
+ uint64_t snd_reservation : 1;
+ uint64_t spare6 : 2;
+ uint64_t snd_nodeid : 3;
+ uint64_t snd_chipid : 3;
+ uint64_t spare14 : 2;
+ uint64_t _reserved0 : 48;
+#else
+ uint64_t _reserved0 : 48;
+ uint64_t spare14 : 2;
+ uint64_t snd_chipid : 3;
+ uint64_t snd_nodeid : 3;
+ uint64_t spare6 : 2;
+ uint64_t snd_reservation : 1;
+ uint64_t snd_type : 1;
+ uint64_t snd_qid : 1;
+ uint64_t snd_scope : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xsndtx_t;
+
+
+
+typedef union pba_xcfg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pbax_en : 1;
+ uint64_t reservation_en : 1;
+ uint64_t snd_reset : 1;
+ uint64_t rcv_reset : 1;
+ uint64_t rcv_nodeid : 3;
+ uint64_t rcv_chipid : 3;
+ uint64_t spare10 : 2;
+ uint64_t rcv_brdcst_group : 8;
+ uint64_t rcv_datato_div : 5;
+ uint64_t spare25 : 2;
+ uint64_t snd_retry_count_overcom : 1;
+ uint64_t snd_retry_thresh : 8;
+ uint64_t snd_rsvto_div : 5;
+ uint64_t _reserved0 : 23;
+#else
+ uint64_t _reserved0 : 23;
+ uint64_t snd_rsvto_div : 5;
+ uint64_t snd_retry_thresh : 8;
+ uint64_t snd_retry_count_overcom : 1;
+ uint64_t spare25 : 2;
+ uint64_t rcv_datato_div : 5;
+ uint64_t rcv_brdcst_group : 8;
+ uint64_t spare10 : 2;
+ uint64_t rcv_chipid : 3;
+ uint64_t rcv_nodeid : 3;
+ uint64_t rcv_reset : 1;
+ uint64_t snd_reset : 1;
+ uint64_t reservation_en : 1;
+ uint64_t pbax_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xcfg_t;
+
+
+
+typedef union pba_xsndstat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t snd_in_progress : 1;
+ uint64_t snd_error : 1;
+ uint64_t snd_status : 6;
+ uint64_t snd_retry_count : 8;
+ uint64_t _reserved0 : 48;
+#else
+ uint64_t _reserved0 : 48;
+ uint64_t snd_retry_count : 8;
+ uint64_t snd_status : 6;
+ uint64_t snd_error : 1;
+ uint64_t snd_in_progress : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xsndstat_t;
+
+
+
+typedef union pba_xsnddat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pbax_datahi : 32;
+ uint64_t pbax_datalo : 32;
+#else
+ uint64_t pbax_datalo : 32;
+ uint64_t pbax_datahi : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xsnddat_t;
+
+
+
+typedef union pba_xrcvstat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t rcv_in_progress : 1;
+ uint64_t rcv_error : 1;
+ uint64_t rcv_write_in_progress : 1;
+ uint64_t rcv_reservation_set : 1;
+ uint64_t rcv_capture : 14;
+ uint64_t _reserved0 : 46;
+#else
+ uint64_t _reserved0 : 46;
+ uint64_t rcv_capture : 14;
+ uint64_t rcv_reservation_set : 1;
+ uint64_t rcv_write_in_progress : 1;
+ uint64_t rcv_error : 1;
+ uint64_t rcv_in_progress : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xrcvstat_t;
+
+
+
+typedef union pba_xshbrn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t push_start : 29;
+ uint64_t _reserved0 : 35;
+#else
+ uint64_t _reserved0 : 35;
+ uint64_t push_start : 29;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xshbrn_t;
+
+
+
+typedef union pba_xshcsn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t push_full : 1;
+ uint64_t push_empty : 1;
+ uint64_t spare1 : 2;
+ uint64_t push_intr_action : 2;
+ uint64_t push_length : 5;
+ uint64_t notimp1 : 2;
+ uint64_t push_write_ptr : 5;
+ uint64_t notimp2 : 3;
+ uint64_t push_read_ptr : 5;
+ uint64_t notimp3 : 5;
+ uint64_t push_enable : 1;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t push_enable : 1;
+ uint64_t notimp3 : 5;
+ uint64_t push_read_ptr : 5;
+ uint64_t notimp2 : 3;
+ uint64_t push_write_ptr : 5;
+ uint64_t notimp1 : 2;
+ uint64_t push_length : 5;
+ uint64_t push_intr_action : 2;
+ uint64_t spare1 : 2;
+ uint64_t push_empty : 1;
+ uint64_t push_full : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xshcsn_t;
+
+
+
+typedef union pba_xshincn {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved : 64;
+#else
+ uint64_t reserved : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} pba_xshincn_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PBA_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/pba_register_addresses.h b/src/include/registers/pba_register_addresses.h
new file mode 100644
index 0000000..7ebf9f1
--- /dev/null
+++ b/src/include/registers/pba_register_addresses.h
@@ -0,0 +1,118 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/pba_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PBA_REGISTER_ADDRESSES_H__
+#define __PBA_REGISTER_ADDRESSES_H__
+
+// $Id: pba_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_register_addresses.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pba_register_addresses.h
+/// \brief Symbolic addresses for the PBA unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define TRUSTEDPIB_BASE 0x02013f00
+#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
+#define PBA_BAR0 0x02013f00
+#define PBA_BAR1 0x02013f01
+#define PBA_BAR2 0x02013f02
+#define PBA_BAR3 0x02013f03
+#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
+#define PBA_BARMSK0 0x02013f04
+#define PBA_BARMSK1 0x02013f05
+#define PBA_BARMSK2 0x02013f06
+#define PBA_BARMSK3 0x02013f07
+#define PIB_BASE 0x02010840
+#define PBA_FIR 0x02010840
+#define PBA_FIR_AND 0x02010841
+#define PBA_FIR_OR 0x02010842
+#define PBA_FIRMASK 0x02010843
+#define PBA_FIRMASK_AND 0x02010844
+#define PBA_FIRMASK_OR 0x02010845
+#define PBA_FIRACT0 0x02010846
+#define PBA_FIRACT1 0x02010847
+#define PBA_OCCACT 0x0201084a
+#define PBA_CFG 0x0201084b
+#define PBA_ERRPT0 0x0201084c
+#define PBA_ERRPT1 0x0201084d
+#define PBA_ERRPT2 0x0201084e
+#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
+#define PBA_RBUFVAL0 0x02010850
+#define PBA_RBUFVAL1 0x02010851
+#define PBA_RBUFVAL2 0x02010852
+#define PBA_RBUFVAL3 0x02010853
+#define PBA_RBUFVAL4 0x02010854
+#define PBA_RBUFVAL5 0x02010855
+#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
+#define PBA_WBUFVAL0 0x02010858
+#define PBA_WBUFVAL1 0x02010859
+#define OCI_BASE 0x40020000
+#define PBA_MODE 0x40020000
+#define PBA_SLVRST 0x40020008
+#define PBA_SLVCTLN(n) (PBA_SLVCTL0 + ((PBA_SLVCTL1 - PBA_SLVCTL0) * (n)))
+#define PBA_SLVCTL0 0x40020020
+#define PBA_SLVCTL1 0x40020028
+#define PBA_SLVCTL2 0x40020030
+#define PBA_SLVCTL3 0x40020038
+#define PBA_BCDE_CTL 0x40020080
+#define PBA_BCDE_SET 0x40020088
+#define PBA_BCDE_STAT 0x40020090
+#define PBA_BCDE_PBADR 0x40020098
+#define PBA_BCDE_OCIBAR 0x400200a0
+#define PBA_BCUE_CTL 0x400200a8
+#define PBA_BCUE_SET 0x400200b0
+#define PBA_BCUE_STAT 0x400200b8
+#define PBA_BCUE_PBADR 0x400200c0
+#define PBA_BCUE_OCIBAR 0x400200c8
+#define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n)))
+#define PBA_PBOCR0 0x400200d0
+#define PBA_PBOCR1 0x400200d8
+#define PBA_PBOCR2 0x400200e0
+#define PBA_PBOCR3 0x400200e8
+#define PBA_PBOCR4 0x400200f0
+#define PBA_PBOCR5 0x400200f8
+#define PBA_XSNDTX 0x40020100
+#define PBA_XCFG 0x40020108
+#define PBA_XSNDSTAT 0x40020110
+#define PBA_XSNDDAT 0x40020118
+#define PBA_XRCVSTAT 0x40020120
+#define PBA_XSHBRN(n) (PBA_XSHBR0 + ((PBA_XSHBR1 - PBA_XSHBR0) * (n)))
+#define PBA_XSHBR0 0x40020130
+#define PBA_XSHBR1 0x40020150
+#define PBA_XSHCSN(n) (PBA_XSHCS0 + ((PBA_XSHCS1 - PBA_XSHCS0) * (n)))
+#define PBA_XSHCS0 0x40020138
+#define PBA_XSHCS1 0x40020158
+#define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n)))
+#define PBA_XSHINC0 0x40020140
+#define PBA_XSHINC1 0x40020160
+
+#endif // __PBA_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/pmc_firmware_registers.h b/src/include/registers/pmc_firmware_registers.h
new file mode 100644
index 0000000..e82ae08
--- /dev/null
+++ b/src/include/registers/pmc_firmware_registers.h
@@ -0,0 +1,3164 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/pmc_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PMC_FIRMWARE_REGISTERS_H__
+#define __PMC_FIRMWARE_REGISTERS_H__
+
+// $Id: pmc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_firmware_registers.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pmc_firmware_registers.h
+/// \brief C register structs for the PMC unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union pmc_mode_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t enable_hw_pstate_mode : 1;
+ uint32_t enable_fw_auction_pstate_mode : 1;
+ uint32_t enable_fw_pstate_mode : 1;
+ uint32_t enable_pstate_voltage_changes : 1;
+ uint32_t enable_global_actual_pstate_forwarding : 1;
+ uint32_t halt_pstate_master_fsm : 1;
+ uint32_t enable_interchip_interface : 1;
+ uint32_t interchip_mode : 1;
+ uint32_t enable_interchip_pstate_in_haps : 1;
+ uint32_t enable_pstate_stepping : 1;
+ uint32_t honor_oha_idle_state_requests : 1;
+ uint32_t vid_endianess : 1;
+ uint32_t reset_all_pmc_registers : 1;
+ uint32_t safe_mode_without_spivid : 1;
+ uint32_t halt_idle_state_master_fsm : 1;
+ uint32_t interchip_halt_if : 1;
+ uint32_t unfreeze_pstate_processing : 1;
+ uint32_t spivid_reset_if : 1;
+ uint32_t unfreeze_istate_processing : 1;
+ uint32_t _reserved0 : 13;
+#else
+ uint32_t _reserved0 : 13;
+ uint32_t unfreeze_istate_processing : 1;
+ uint32_t spivid_reset_if : 1;
+ uint32_t unfreeze_pstate_processing : 1;
+ uint32_t interchip_halt_if : 1;
+ uint32_t halt_idle_state_master_fsm : 1;
+ uint32_t safe_mode_without_spivid : 1;
+ uint32_t reset_all_pmc_registers : 1;
+ uint32_t vid_endianess : 1;
+ uint32_t honor_oha_idle_state_requests : 1;
+ uint32_t enable_pstate_stepping : 1;
+ uint32_t enable_interchip_pstate_in_haps : 1;
+ uint32_t interchip_mode : 1;
+ uint32_t enable_interchip_interface : 1;
+ uint32_t halt_pstate_master_fsm : 1;
+ uint32_t enable_global_actual_pstate_forwarding : 1;
+ uint32_t enable_pstate_voltage_changes : 1;
+ uint32_t enable_fw_pstate_mode : 1;
+ uint32_t enable_fw_auction_pstate_mode : 1;
+ uint32_t enable_hw_pstate_mode : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_mode_reg_t;
+
+
+
+typedef union pmc_hardware_auction_pstate_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t haps : 8;
+ uint32_t kuv_actual : 8;
+ uint32_t kuv_received : 8;
+ uint32_t _reserved0 : 8;
+#else
+ uint32_t _reserved0 : 8;
+ uint32_t kuv_received : 8;
+ uint32_t kuv_actual : 8;
+ int32_t haps : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_hardware_auction_pstate_reg_t;
+
+
+
+typedef union pmc_pstate_monitor_and_ctrl_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t gpst_val : 8;
+ int32_t gpsst : 8;
+ int32_t gpsa : 8;
+ int32_t gapr : 8;
+#else
+ int32_t gapr : 8;
+ int32_t gpsa : 8;
+ int32_t gpsst : 8;
+ int32_t gpst_val : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pstate_monitor_and_ctrl_reg_t;
+
+
+
+typedef union pmc_rail_bounds_register {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pmin_rail : 8;
+ int32_t pmax_rail : 8;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ int32_t pmax_rail : 8;
+ int32_t pmin_rail : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_rail_bounds_register_t;
+
+
+
+typedef union pmc_global_pstate_bounds_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t gpsi_min : 8;
+ uint32_t gpst_number_of_entries_minus_one : 7;
+ uint32_t _reserved0 : 17;
+#else
+ uint32_t _reserved0 : 17;
+ uint32_t gpst_number_of_entries_minus_one : 7;
+ uint32_t gpsi_min : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_global_pstate_bounds_reg_t;
+
+
+
+typedef union pmc_parameter_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pstate_stepsize : 7;
+ uint32_t vrm_stepdelay_range : 4;
+ uint32_t vrm_stepdelay_value : 4;
+ uint32_t hangpulse_predivider : 6;
+ uint32_t gpsa_timeout_value : 8;
+ uint32_t gpsa_timeout_value_sel : 1;
+ uint32_t _reserved0 : 2;
+#else
+ uint32_t _reserved0 : 2;
+ uint32_t gpsa_timeout_value_sel : 1;
+ uint32_t gpsa_timeout_value : 8;
+ uint32_t hangpulse_predivider : 6;
+ uint32_t vrm_stepdelay_value : 4;
+ uint32_t vrm_stepdelay_range : 4;
+ uint32_t pstate_stepsize : 7;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_parameter_reg0_t;
+
+
+
+typedef union pmc_parameter_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t ba_sram_pstate_table : 22;
+ int32_t pvsafe : 8;
+ uint32_t _reserved0 : 2;
+#else
+ uint32_t _reserved0 : 2;
+ int32_t pvsafe : 8;
+ uint32_t ba_sram_pstate_table : 22;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_parameter_reg1_t;
+
+
+
+typedef union pmc_eff_global_actual_voltage_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t maxreg_vdd : 8;
+ uint32_t maxreg_vcs : 8;
+ uint32_t eff_evid_vdd : 8;
+ uint32_t eff_evid_vcs : 8;
+#else
+ uint32_t eff_evid_vcs : 8;
+ uint32_t eff_evid_vdd : 8;
+ uint32_t maxreg_vcs : 8;
+ uint32_t maxreg_vdd : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_eff_global_actual_voltage_reg_t;
+
+
+
+typedef union pmc_global_actual_voltage_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t evid_vdd : 8;
+ uint32_t evid_vcs : 8;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t evid_vcs : 8;
+ uint32_t evid_vdd : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_global_actual_voltage_reg_t;
+
+
+
+typedef union pmc_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pstate_processing_is_suspended : 1;
+ uint32_t gpsa_bdcst_error : 1;
+ uint32_t gpsa_bdcst_resp_info : 3;
+ uint32_t gpsa_vchg_error : 1;
+ uint32_t gpsa_timeout_error : 1;
+ uint32_t gpsa_chg_ongoing : 1;
+ uint32_t volt_chg_ongoing : 1;
+ uint32_t brd_cst_ongoing : 1;
+ uint32_t gps_table_error : 1;
+ uint32_t pstate_interchip_error : 1;
+ uint32_t istate_processing_is_suspended : 1;
+ uint32_t safe_mode_engaged : 1;
+ uint32_t _reserved0 : 18;
+#else
+ uint32_t _reserved0 : 18;
+ uint32_t safe_mode_engaged : 1;
+ uint32_t istate_processing_is_suspended : 1;
+ uint32_t pstate_interchip_error : 1;
+ uint32_t gps_table_error : 1;
+ uint32_t brd_cst_ongoing : 1;
+ uint32_t volt_chg_ongoing : 1;
+ uint32_t gpsa_chg_ongoing : 1;
+ uint32_t gpsa_timeout_error : 1;
+ uint32_t gpsa_vchg_error : 1;
+ uint32_t gpsa_bdcst_resp_info : 3;
+ uint32_t gpsa_bdcst_error : 1;
+ uint32_t pstate_processing_is_suspended : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_status_reg_t;
+
+
+
+typedef union pmc_phase_enable_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t phase_enable : 4;
+ uint32_t _reserved0 : 28;
+#else
+ uint32_t _reserved0 : 28;
+ uint32_t phase_enable : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_phase_enable_reg_t;
+
+
+
+typedef union pmc_undervolting_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t puv_min : 8;
+ int32_t puv_max : 8;
+ uint32_t kuv_request : 8;
+ uint32_t _reserved0 : 8;
+#else
+ uint32_t _reserved0 : 8;
+ uint32_t kuv_request : 8;
+ int32_t puv_max : 8;
+ int32_t puv_min : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_undervolting_reg_t;
+
+
+
+typedef union pmc_core_deconfiguration_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t core_chiplet_deconf_vector : 16;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t core_chiplet_deconf_vector : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_deconfiguration_reg_t;
+
+
+
+typedef union pmc_intchp_ctrl_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_ga_fsm_enable : 1;
+ uint32_t interchip_recv_done_valid_without_if_en : 1;
+ uint32_t pmcic1_reserved_2 : 1;
+ uint32_t interchip_cpha : 1;
+ uint32_t interchip_clock_divider : 10;
+ uint32_t pmcicr1_reserved_14_17 : 4;
+ uint32_t pmcicr1_reserved_18_20 : 3;
+ uint32_t _reserved0 : 11;
+#else
+ uint32_t _reserved0 : 11;
+ uint32_t pmcicr1_reserved_18_20 : 3;
+ uint32_t pmcicr1_reserved_14_17 : 4;
+ uint32_t interchip_clock_divider : 10;
+ uint32_t interchip_cpha : 1;
+ uint32_t pmcic1_reserved_2 : 1;
+ uint32_t interchip_recv_done_valid_without_if_en : 1;
+ uint32_t interchip_ga_fsm_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_ctrl_reg1_t;
+
+
+
+typedef union pmc_intchp_ctrl_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_ping_send : 1;
+ uint32_t interchip_ping_detect_clear : 1;
+ uint32_t interchip_ping_mode : 1;
+ uint32_t pmcic2_reserved3 : 1;
+ uint32_t pmcic2_reserved4 : 1;
+ uint32_t pmcic2_reserved5_7 : 3;
+ uint32_t _reserved0 : 24;
+#else
+ uint32_t _reserved0 : 24;
+ uint32_t pmcic2_reserved5_7 : 3;
+ uint32_t pmcic2_reserved4 : 1;
+ uint32_t pmcic2_reserved3 : 1;
+ uint32_t interchip_ping_mode : 1;
+ uint32_t interchip_ping_detect_clear : 1;
+ uint32_t interchip_ping_send : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_ctrl_reg2_t;
+
+
+
+typedef union pmc_intchp_ctrl_reg4 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_ecc_gen_en : 1;
+ uint32_t interchip_ecc_check_en : 1;
+ uint32_t interchip_msg_rcv_overflow_check_en : 1;
+ uint32_t interchip_ecc_ue_block_en : 1;
+ uint32_t chksw_hw221732 : 1;
+ uint32_t slave_occ_timeout_forces_safe_mode_disable : 1;
+ uint32_t pmcic4_reserved6_7 : 2;
+ uint32_t _reserved0 : 24;
+#else
+ uint32_t _reserved0 : 24;
+ uint32_t pmcic4_reserved6_7 : 2;
+ uint32_t slave_occ_timeout_forces_safe_mode_disable : 1;
+ uint32_t chksw_hw221732 : 1;
+ uint32_t interchip_ecc_ue_block_en : 1;
+ uint32_t interchip_msg_rcv_overflow_check_en : 1;
+ uint32_t interchip_ecc_check_en : 1;
+ uint32_t interchip_ecc_gen_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_ctrl_reg4_t;
+
+
+
+typedef union pmc_intchp_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_ga_ongoing : 1;
+ uint32_t interchip_ecc_ue : 1;
+ uint32_t interchip_ecc_ce : 1;
+ uint32_t interchip_ping_detected : 1;
+ uint32_t interchip_ping_ack_detected : 1;
+ uint32_t interchip_msg_send_ongoing : 1;
+ uint32_t interchip_msg_recv_detected : 1;
+ uint32_t interchip_fsm_err : 1;
+ uint32_t interchip_ping_detect_count : 8;
+ uint32_t interchip_slave_error_code : 4;
+ uint32_t interchip_msg_snd_overflow_detected : 1;
+ uint32_t interchip_msg_rcv_overflow_detected : 1;
+ uint32_t interchip_ecc_ue_err : 1;
+ uint32_t _reserved0 : 9;
+#else
+ uint32_t _reserved0 : 9;
+ uint32_t interchip_ecc_ue_err : 1;
+ uint32_t interchip_msg_rcv_overflow_detected : 1;
+ uint32_t interchip_msg_snd_overflow_detected : 1;
+ uint32_t interchip_slave_error_code : 4;
+ uint32_t interchip_ping_detect_count : 8;
+ uint32_t interchip_fsm_err : 1;
+ uint32_t interchip_msg_recv_detected : 1;
+ uint32_t interchip_msg_send_ongoing : 1;
+ uint32_t interchip_ping_ack_detected : 1;
+ uint32_t interchip_ping_detected : 1;
+ uint32_t interchip_ecc_ce : 1;
+ uint32_t interchip_ecc_ue : 1;
+ uint32_t interchip_ga_ongoing : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_status_reg_t;
+
+
+
+typedef union pmc_intchp_command_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_reset_if : 1;
+ uint32_t interchip_halt_msg_fsm : 1;
+ uint32_t interchip_clear_sticky_bits : 1;
+ uint32_t _reserved0 : 29;
+#else
+ uint32_t _reserved0 : 29;
+ uint32_t interchip_clear_sticky_bits : 1;
+ uint32_t interchip_halt_msg_fsm : 1;
+ uint32_t interchip_reset_if : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_command_reg_t;
+
+
+
+typedef union pmc_intchp_msg_wdata {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_msg_wdata : 32;
+#else
+ uint32_t interchip_msg_wdata : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_msg_wdata_t;
+
+
+
+typedef union pmc_intchp_msg_rdata {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t interchip_msg_rdata : 32;
+#else
+ uint32_t interchip_msg_rdata : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_msg_rdata_t;
+
+
+
+typedef union pmc_intchp_pstate_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pstate_interchip : 8;
+ uint32_t _reserved0 : 24;
+#else
+ uint32_t _reserved0 : 24;
+ int32_t pstate_interchip : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_pstate_reg_t;
+
+
+
+typedef union pmc_intchp_globack_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t gaack_interchip : 1;
+ int32_t gaack_interchip_pstate : 8;
+ uint32_t _reserved0 : 23;
+#else
+ uint32_t _reserved0 : 23;
+ int32_t gaack_interchip_pstate : 8;
+ uint32_t gaack_interchip : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_intchp_globack_reg_t;
+
+
+
+typedef union pmc_fsmstate_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t mis_fsm_state : 3;
+ uint32_t mps_fsm_state : 5;
+ uint32_t svs_fsm_state : 4;
+ uint32_t o2s_fsm_state : 4;
+ uint32_t m2p_fsm_state : 4;
+ uint32_t o2p_fsm_state : 4;
+ uint32_t icp_msg_fsm_state : 5;
+ uint32_t _reserved0 : 3;
+#else
+ uint32_t _reserved0 : 3;
+ uint32_t icp_msg_fsm_state : 5;
+ uint32_t o2p_fsm_state : 4;
+ uint32_t m2p_fsm_state : 4;
+ uint32_t o2s_fsm_state : 4;
+ uint32_t svs_fsm_state : 4;
+ uint32_t mps_fsm_state : 5;
+ uint32_t mis_fsm_state : 3;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_fsmstate_status_reg_t;
+
+
+
+typedef union pmc_trace_mode_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmc_trace_mode : 4;
+ uint32_t trace_sel_data : 2;
+ uint32_t _reserved0 : 26;
+#else
+ uint32_t _reserved0 : 26;
+ uint32_t trace_sel_data : 2;
+ uint32_t pmc_trace_mode : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_trace_mode_reg_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_frame_size : 6;
+ uint32_t spivid_out_count1 : 6;
+ uint32_t spivid_in_delay1 : 6;
+ uint32_t spivid_in_count1 : 6;
+ uint32_t _reserved0 : 8;
+#else
+ uint32_t _reserved0 : 8;
+ uint32_t spivid_in_count1 : 6;
+ uint32_t spivid_in_delay1 : 6;
+ uint32_t spivid_out_count1 : 6;
+ uint32_t spivid_frame_size : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg0a_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_out_count2 : 6;
+ uint32_t spivid_in_delay2 : 6;
+ uint32_t spivid_in_count2 : 6;
+ uint32_t _reserved0 : 14;
+#else
+ uint32_t _reserved0 : 14;
+ uint32_t spivid_in_count2 : 6;
+ uint32_t spivid_in_delay2 : 6;
+ uint32_t spivid_out_count2 : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg0b_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_fsm_enable : 1;
+ uint32_t pmcscr1_reserved_1 : 1;
+ uint32_t spivid_cpol : 1;
+ uint32_t spivid_cpha : 1;
+ uint32_t spivid_clock_divider : 10;
+ uint32_t pmcscr1_reserved_2 : 4;
+ uint32_t spivid_port_enable : 3;
+ uint32_t _reserved0 : 11;
+#else
+ uint32_t _reserved0 : 11;
+ uint32_t spivid_port_enable : 3;
+ uint32_t pmcscr1_reserved_2 : 4;
+ uint32_t spivid_clock_divider : 10;
+ uint32_t spivid_cpha : 1;
+ uint32_t spivid_cpol : 1;
+ uint32_t pmcscr1_reserved_1 : 1;
+ uint32_t spivid_fsm_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg1_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_inter_frame_delay_write_status : 17;
+ uint32_t _reserved0 : 15;
+#else
+ uint32_t _reserved0 : 15;
+ uint32_t spivid_inter_frame_delay_write_status : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg2_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_inter_retry_delay : 17;
+ uint32_t pmc_100ns_pls_range : 6;
+ uint32_t _reserved0 : 9;
+#else
+ uint32_t _reserved0 : 9;
+ uint32_t pmc_100ns_pls_range : 6;
+ uint32_t spivid_inter_retry_delay : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg3_t;
+
+
+
+typedef union pmc_spiv_ctrl_reg4 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_crc_gen_en : 1;
+ uint32_t spivid_crc_check_en : 1;
+ uint32_t spivid_majority_vote_en : 1;
+ uint32_t spivid_max_retries : 5;
+ uint32_t spivid_crc_polynomial_enables : 8;
+ uint32_t spivid_crc_const_gen_enable : 1;
+ uint32_t spivid_crc_const_check_enable : 1;
+ uint32_t spivid_frame_sync_wrong_enable : 1;
+ uint32_t _reserved0 : 13;
+#else
+ uint32_t _reserved0 : 13;
+ uint32_t spivid_frame_sync_wrong_enable : 1;
+ uint32_t spivid_crc_const_check_enable : 1;
+ uint32_t spivid_crc_const_gen_enable : 1;
+ uint32_t spivid_crc_polynomial_enables : 8;
+ uint32_t spivid_max_retries : 5;
+ uint32_t spivid_majority_vote_en : 1;
+ uint32_t spivid_crc_check_en : 1;
+ uint32_t spivid_crc_gen_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_ctrl_reg4_t;
+
+
+
+typedef union pmc_spiv_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_ongoing : 1;
+ uint32_t spivid_crc_error0 : 1;
+ uint32_t spivid_crc_error1 : 1;
+ uint32_t spivid_crc_error2 : 1;
+ uint32_t spivid_retry_timeout : 1;
+ uint32_t pmcssr_reserved_1 : 2;
+ uint32_t spivid_fsm_err : 1;
+ uint32_t spivid_majority_detected_a_minority0 : 1;
+ uint32_t spivid_majority_detected_a_minority1 : 1;
+ uint32_t spivid_majority_detected_a_minority2 : 1;
+ uint32_t spivid_majority_nr_of_minorities0 : 4;
+ uint32_t spivid_majority_nr_of_minorities1 : 4;
+ uint32_t spivid_majority_nr_of_minorities2 : 4;
+ uint32_t _reserved0 : 9;
+#else
+ uint32_t _reserved0 : 9;
+ uint32_t spivid_majority_nr_of_minorities2 : 4;
+ uint32_t spivid_majority_nr_of_minorities1 : 4;
+ uint32_t spivid_majority_nr_of_minorities0 : 4;
+ uint32_t spivid_majority_detected_a_minority2 : 1;
+ uint32_t spivid_majority_detected_a_minority1 : 1;
+ uint32_t spivid_majority_detected_a_minority0 : 1;
+ uint32_t spivid_fsm_err : 1;
+ uint32_t pmcssr_reserved_1 : 2;
+ uint32_t spivid_retry_timeout : 1;
+ uint32_t spivid_crc_error2 : 1;
+ uint32_t spivid_crc_error1 : 1;
+ uint32_t spivid_crc_error0 : 1;
+ uint32_t spivid_ongoing : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_status_reg_t;
+
+
+
+typedef union pmc_spiv_command_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t spivid_halt_fsm : 1;
+ uint32_t _reserved0 : 31;
+#else
+ uint32_t _reserved0 : 31;
+ uint32_t spivid_halt_fsm : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_spiv_command_reg_t;
+
+
+
+typedef union pmc_o2s_ctrl_reg0a {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_frame_size : 6;
+ uint32_t o2s_out_count1 : 6;
+ uint32_t o2s_in_delay1 : 6;
+ uint32_t o2s_in_count1 : 6;
+ uint32_t _reserved0 : 8;
+#else
+ uint32_t _reserved0 : 8;
+ uint32_t o2s_in_count1 : 6;
+ uint32_t o2s_in_delay1 : 6;
+ uint32_t o2s_out_count1 : 6;
+ uint32_t o2s_frame_size : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_ctrl_reg0a_t;
+
+
+
+typedef union pmc_o2s_ctrl_reg0b {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_out_count2 : 6;
+ uint32_t o2s_in_delay2 : 6;
+ uint32_t o2s_in_count2 : 6;
+ uint32_t _reserved0 : 14;
+#else
+ uint32_t _reserved0 : 14;
+ uint32_t o2s_in_count2 : 6;
+ uint32_t o2s_in_delay2 : 6;
+ uint32_t o2s_out_count2 : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_ctrl_reg0b_t;
+
+
+
+typedef union pmc_o2s_ctrl_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_bridge_enable : 1;
+ uint32_t pmcocr1_reserved_1 : 1;
+ uint32_t o2s_cpol : 1;
+ uint32_t o2s_cpha : 1;
+ uint32_t o2s_clock_divider : 10;
+ uint32_t pmcocr1_reserved_2 : 3;
+ uint32_t o2s_nr_of_frames : 1;
+ uint32_t o2s_port_enable : 3;
+ uint32_t _reserved0 : 11;
+#else
+ uint32_t _reserved0 : 11;
+ uint32_t o2s_port_enable : 3;
+ uint32_t o2s_nr_of_frames : 1;
+ uint32_t pmcocr1_reserved_2 : 3;
+ uint32_t o2s_clock_divider : 10;
+ uint32_t o2s_cpha : 1;
+ uint32_t o2s_cpol : 1;
+ uint32_t pmcocr1_reserved_1 : 1;
+ uint32_t o2s_bridge_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_ctrl_reg1_t;
+
+
+
+typedef union pmc_o2s_ctrl_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_inter_frame_delay : 17;
+ uint32_t _reserved0 : 15;
+#else
+ uint32_t _reserved0 : 15;
+ uint32_t o2s_inter_frame_delay : 17;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_ctrl_reg2_t;
+
+
+
+typedef union pmc_o2s_ctrl_reg4 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_crc_gen_en : 1;
+ uint32_t o2s_crc_check_en : 1;
+ uint32_t o2s_majority_vote_en : 1;
+ uint32_t o2s_max_retries : 5;
+ uint32_t pmcocr4_reserved8_15 : 8;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t pmcocr4_reserved8_15 : 8;
+ uint32_t o2s_max_retries : 5;
+ uint32_t o2s_majority_vote_en : 1;
+ uint32_t o2s_crc_check_en : 1;
+ uint32_t o2s_crc_gen_en : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_ctrl_reg4_t;
+
+
+
+typedef union pmc_o2s_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_ongoing : 1;
+ uint32_t o2s_crc_error0 : 1;
+ uint32_t o2s_crc_error1 : 1;
+ uint32_t o2s_crc_error2 : 1;
+ uint32_t o2s_retry_timeout : 1;
+ uint32_t o2s_write_while_bridge_busy_err : 1;
+ uint32_t pmcosr_reserved_6 : 1;
+ uint32_t o2s_fsm_err : 1;
+ uint32_t o2s_majority_detected_a_minority0 : 1;
+ uint32_t o2s_majority_detected_a_minority1 : 1;
+ uint32_t o2s_majority_detected_a_minority2 : 1;
+ uint32_t o2s_majority_nr_of_minorities0 : 4;
+ uint32_t o2s_majority_nr_of_minorities1 : 4;
+ uint32_t o2s_majority_nr_of_minorities2 : 4;
+ uint32_t _reserved0 : 9;
+#else
+ uint32_t _reserved0 : 9;
+ uint32_t o2s_majority_nr_of_minorities2 : 4;
+ uint32_t o2s_majority_nr_of_minorities1 : 4;
+ uint32_t o2s_majority_nr_of_minorities0 : 4;
+ uint32_t o2s_majority_detected_a_minority2 : 1;
+ uint32_t o2s_majority_detected_a_minority1 : 1;
+ uint32_t o2s_majority_detected_a_minority0 : 1;
+ uint32_t o2s_fsm_err : 1;
+ uint32_t pmcosr_reserved_6 : 1;
+ uint32_t o2s_write_while_bridge_busy_err : 1;
+ uint32_t o2s_retry_timeout : 1;
+ uint32_t o2s_crc_error2 : 1;
+ uint32_t o2s_crc_error1 : 1;
+ uint32_t o2s_crc_error0 : 1;
+ uint32_t o2s_ongoing : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_status_reg_t;
+
+
+
+typedef union pmc_o2s_command_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_halt_retries : 1;
+ uint32_t o2s_clear_sticky_bits : 1;
+ uint32_t _reserved0 : 30;
+#else
+ uint32_t _reserved0 : 30;
+ uint32_t o2s_clear_sticky_bits : 1;
+ uint32_t o2s_halt_retries : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_command_reg_t;
+
+
+
+typedef union pmc_o2s_wdata_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_wdata : 32;
+#else
+ uint32_t o2s_wdata : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_wdata_reg_t;
+
+
+
+typedef union pmc_o2s_rdata_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2s_rdata : 32;
+#else
+ uint32_t o2s_rdata : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2s_rdata_reg_t;
+
+
+
+typedef union pmc_o2p_addr_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_write_plus_read : 1;
+ uint32_t o2p_mc : 1;
+ uint32_t o2p_slave_addr : 6;
+ uint32_t o2p_read_not_write : 1;
+ uint32_t reserved_bit_pmco2par2 : 3;
+ uint32_t o2p_pcb_port : 4;
+ uint32_t o2p_pcb_reg_addr : 16;
+#else
+ uint32_t o2p_pcb_reg_addr : 16;
+ uint32_t o2p_pcb_port : 4;
+ uint32_t reserved_bit_pmco2par2 : 3;
+ uint32_t o2p_read_not_write : 1;
+ uint32_t o2p_slave_addr : 6;
+ uint32_t o2p_mc : 1;
+ uint32_t o2p_write_plus_read : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_addr_reg_t;
+
+
+
+typedef union pmc_o2p_ctrl_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_ongoing : 1;
+ uint32_t o2p_scresp : 3;
+ uint32_t o2p_write_while_bridge_busy_err : 1;
+ uint32_t o2p_fsm_err : 1;
+ uint32_t o2p_abort : 1;
+ uint32_t o2p_parity_error : 1;
+ uint32_t o2p_clear_sticky_bits : 1;
+ uint32_t _reserved0 : 23;
+#else
+ uint32_t _reserved0 : 23;
+ uint32_t o2p_clear_sticky_bits : 1;
+ uint32_t o2p_parity_error : 1;
+ uint32_t o2p_abort : 1;
+ uint32_t o2p_fsm_err : 1;
+ uint32_t o2p_write_while_bridge_busy_err : 1;
+ uint32_t o2p_scresp : 3;
+ uint32_t o2p_ongoing : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_ctrl_status_reg_t;
+
+
+
+typedef union pmc_o2p_send_data_hi_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_send_data_hi : 32;
+#else
+ uint32_t o2p_send_data_hi : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_send_data_hi_reg_t;
+
+
+
+typedef union pmc_o2p_send_data_lo_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_send_data_lo : 32;
+#else
+ uint32_t o2p_send_data_lo : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_send_data_lo_reg_t;
+
+
+
+typedef union pmc_o2p_recv_data_hi_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_receive_data_hi : 32;
+#else
+ uint32_t o2p_receive_data_hi : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_recv_data_hi_reg_t;
+
+
+
+typedef union pmc_o2p_recv_data_lo_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t o2p_receive_data_lo : 32;
+#else
+ uint32_t o2p_receive_data_lo : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_o2p_recv_data_lo_reg_t;
+
+
+
+typedef union pmc_occ_heartbeat_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmc_occ_heartbeat_time : 16;
+ uint32_t pmc_occ_heartbeat_en : 1;
+ uint32_t _reserved0 : 15;
+#else
+ uint32_t _reserved0 : 15;
+ uint32_t pmc_occ_heartbeat_en : 1;
+ uint32_t pmc_occ_heartbeat_time : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_occ_heartbeat_reg_t;
+
+
+
+typedef union pmc_error_int_mask_hi_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmc_error_int_mask_hi : 32;
+#else
+ uint32_t pmc_error_int_mask_hi : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_error_int_mask_hi_reg_t;
+
+
+
+typedef union pmc_error_int_mask_lo_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmc_error_int_mask_lo : 32;
+#else
+ uint32_t pmc_error_int_mask_lo : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_error_int_mask_lo_reg_t;
+
+
+
+typedef union pmc_idle_suspend_mask_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmc_idle_suspend_mask : 16;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t pmc_idle_suspend_mask : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_idle_suspend_mask_reg_t;
+
+
+
+typedef union pmc_pend_idle_req_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t idle_pending_0 : 1;
+ uint32_t idle_op_0 : 2;
+ uint32_t idle_type_0 : 1;
+ uint32_t idle_scope_0 : 1;
+ uint32_t assist_mode_0 : 1;
+ uint32_t reserved_pirr_0 : 2;
+ uint32_t idle_pending_1 : 1;
+ uint32_t idle_op_1 : 2;
+ uint32_t idle_type_1 : 1;
+ uint32_t idle_scope_1 : 1;
+ uint32_t assist_mode_1 : 1;
+ uint32_t reserved_pirr_1 : 2;
+ uint32_t idle_pending_2 : 1;
+ uint32_t idle_op_2 : 2;
+ uint32_t idle_type_2 : 1;
+ uint32_t idle_scope_2 : 1;
+ uint32_t assist_mode_2 : 1;
+ uint32_t reserved_pirr_2 : 2;
+ uint32_t idle_pending_3 : 1;
+ uint32_t idle_op_3 : 2;
+ uint32_t idle_type_3 : 1;
+ uint32_t idle_scope_3 : 1;
+ uint32_t assist_mode_3 : 1;
+ uint32_t reserved_pirr_3 : 2;
+#else
+ uint32_t reserved_pirr_3 : 2;
+ uint32_t assist_mode_3 : 1;
+ uint32_t idle_scope_3 : 1;
+ uint32_t idle_type_3 : 1;
+ uint32_t idle_op_3 : 2;
+ uint32_t idle_pending_3 : 1;
+ uint32_t reserved_pirr_2 : 2;
+ uint32_t assist_mode_2 : 1;
+ uint32_t idle_scope_2 : 1;
+ uint32_t idle_type_2 : 1;
+ uint32_t idle_op_2 : 2;
+ uint32_t idle_pending_2 : 1;
+ uint32_t reserved_pirr_1 : 2;
+ uint32_t assist_mode_1 : 1;
+ uint32_t idle_scope_1 : 1;
+ uint32_t idle_type_1 : 1;
+ uint32_t idle_op_1 : 2;
+ uint32_t idle_pending_1 : 1;
+ uint32_t reserved_pirr_0 : 2;
+ uint32_t assist_mode_0 : 1;
+ uint32_t idle_scope_0 : 1;
+ uint32_t idle_type_0 : 1;
+ uint32_t idle_op_0 : 2;
+ uint32_t idle_pending_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pend_idle_req_reg0_t;
+
+
+
+typedef union pmc_pend_idle_req_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t idle_pending_4 : 1;
+ uint32_t idle_op_4 : 2;
+ uint32_t idle_type_4 : 1;
+ uint32_t idle_scope_4 : 1;
+ uint32_t assist_mode_4 : 1;
+ uint32_t reserved_pirr_4 : 2;
+ uint32_t idle_pending_5 : 1;
+ uint32_t idle_op_5 : 2;
+ uint32_t idle_type_5 : 1;
+ uint32_t idle_scope_5 : 1;
+ uint32_t assist_mode_5 : 1;
+ uint32_t reserved_pirr_5 : 2;
+ uint32_t idle_pending_6 : 1;
+ uint32_t idle_op_6 : 2;
+ uint32_t idle_type_6 : 1;
+ uint32_t idle_scope_6 : 1;
+ uint32_t assist_mode_6 : 1;
+ uint32_t reserved_pirr_6 : 2;
+ uint32_t idle_pending_7 : 1;
+ uint32_t idle_op_7 : 2;
+ uint32_t idle_type_7 : 1;
+ uint32_t idle_scope_7 : 1;
+ uint32_t assist_mode_7 : 1;
+ uint32_t reserved_pirr_7 : 2;
+#else
+ uint32_t reserved_pirr_7 : 2;
+ uint32_t assist_mode_7 : 1;
+ uint32_t idle_scope_7 : 1;
+ uint32_t idle_type_7 : 1;
+ uint32_t idle_op_7 : 2;
+ uint32_t idle_pending_7 : 1;
+ uint32_t reserved_pirr_6 : 2;
+ uint32_t assist_mode_6 : 1;
+ uint32_t idle_scope_6 : 1;
+ uint32_t idle_type_6 : 1;
+ uint32_t idle_op_6 : 2;
+ uint32_t idle_pending_6 : 1;
+ uint32_t reserved_pirr_5 : 2;
+ uint32_t assist_mode_5 : 1;
+ uint32_t idle_scope_5 : 1;
+ uint32_t idle_type_5 : 1;
+ uint32_t idle_op_5 : 2;
+ uint32_t idle_pending_5 : 1;
+ uint32_t reserved_pirr_4 : 2;
+ uint32_t assist_mode_4 : 1;
+ uint32_t idle_scope_4 : 1;
+ uint32_t idle_type_4 : 1;
+ uint32_t idle_op_4 : 2;
+ uint32_t idle_pending_4 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pend_idle_req_reg1_t;
+
+
+
+typedef union pmc_pend_idle_req_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t idle_pending_8 : 1;
+ uint32_t idle_op_8 : 2;
+ uint32_t idle_type_8 : 1;
+ uint32_t idle_scope_8 : 1;
+ uint32_t assist_mode_8 : 1;
+ uint32_t reserved_pirr_8 : 2;
+ uint32_t idle_pending_9 : 1;
+ uint32_t idle_op_9 : 2;
+ uint32_t idle_type_9 : 1;
+ uint32_t idle_scope_9 : 1;
+ uint32_t assist_mode_9 : 1;
+ uint32_t reserved_pirr_9 : 2;
+ uint32_t idle_pending_10 : 1;
+ uint32_t idle_op_10 : 2;
+ uint32_t idle_type_10 : 1;
+ uint32_t idle_scope_10 : 1;
+ uint32_t assist_mode_10 : 1;
+ uint32_t reserved_pirr_10 : 2;
+ uint32_t idle_pending_11 : 1;
+ uint32_t idle_op_11 : 2;
+ uint32_t idle_type_11 : 1;
+ uint32_t idle_scope_11 : 1;
+ uint32_t assist_mode_11 : 1;
+ uint32_t reserved_pirr_11 : 2;
+#else
+ uint32_t reserved_pirr_11 : 2;
+ uint32_t assist_mode_11 : 1;
+ uint32_t idle_scope_11 : 1;
+ uint32_t idle_type_11 : 1;
+ uint32_t idle_op_11 : 2;
+ uint32_t idle_pending_11 : 1;
+ uint32_t reserved_pirr_10 : 2;
+ uint32_t assist_mode_10 : 1;
+ uint32_t idle_scope_10 : 1;
+ uint32_t idle_type_10 : 1;
+ uint32_t idle_op_10 : 2;
+ uint32_t idle_pending_10 : 1;
+ uint32_t reserved_pirr_9 : 2;
+ uint32_t assist_mode_9 : 1;
+ uint32_t idle_scope_9 : 1;
+ uint32_t idle_type_9 : 1;
+ uint32_t idle_op_9 : 2;
+ uint32_t idle_pending_9 : 1;
+ uint32_t reserved_pirr_8 : 2;
+ uint32_t assist_mode_8 : 1;
+ uint32_t idle_scope_8 : 1;
+ uint32_t idle_type_8 : 1;
+ uint32_t idle_op_8 : 2;
+ uint32_t idle_pending_8 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pend_idle_req_reg2_t;
+
+
+
+typedef union pmc_pend_idle_req_reg3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t idle_pending_12 : 1;
+ uint32_t idle_op_12 : 2;
+ uint32_t idle_type_12 : 1;
+ uint32_t idle_scope_12 : 1;
+ uint32_t assist_mode_12 : 1;
+ uint32_t reserved_pirr_12 : 2;
+ uint32_t idle_pending_13 : 1;
+ uint32_t idle_op_13 : 2;
+ uint32_t idle_type_13 : 1;
+ uint32_t idle_scope_13 : 1;
+ uint32_t assist_mode_13 : 1;
+ uint32_t reserved_pirr_13 : 2;
+ uint32_t idle_pending_14 : 1;
+ uint32_t idle_op_14 : 2;
+ uint32_t idle_type_14 : 1;
+ uint32_t idle_scope_14 : 1;
+ uint32_t assist_mode_14 : 1;
+ uint32_t reserved_pirr_14 : 2;
+ uint32_t idle_pending_15 : 1;
+ uint32_t idle_op_15 : 2;
+ uint32_t idle_type_15 : 1;
+ uint32_t idle_scope_15 : 1;
+ uint32_t assist_mode_15 : 1;
+ uint32_t reserved_pirr_15 : 2;
+#else
+ uint32_t reserved_pirr_15 : 2;
+ uint32_t assist_mode_15 : 1;
+ uint32_t idle_scope_15 : 1;
+ uint32_t idle_type_15 : 1;
+ uint32_t idle_op_15 : 2;
+ uint32_t idle_pending_15 : 1;
+ uint32_t reserved_pirr_14 : 2;
+ uint32_t assist_mode_14 : 1;
+ uint32_t idle_scope_14 : 1;
+ uint32_t idle_type_14 : 1;
+ uint32_t idle_op_14 : 2;
+ uint32_t idle_pending_14 : 1;
+ uint32_t reserved_pirr_13 : 2;
+ uint32_t assist_mode_13 : 1;
+ uint32_t idle_scope_13 : 1;
+ uint32_t idle_type_13 : 1;
+ uint32_t idle_op_13 : 2;
+ uint32_t idle_pending_13 : 1;
+ uint32_t reserved_pirr_12 : 2;
+ uint32_t assist_mode_12 : 1;
+ uint32_t idle_scope_12 : 1;
+ uint32_t idle_type_12 : 1;
+ uint32_t idle_op_12 : 2;
+ uint32_t idle_pending_12 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pend_idle_req_reg3_t;
+
+
+
+typedef union pmc_sleep_int_req_vec_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t fastsleepentry_int_req_vec : 32;
+#else
+ uint32_t fastsleepentry_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_sleep_int_req_vec_reg0_t;
+
+
+
+typedef union pmc_sleep_int_req_vec_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deepsleepentry_int_req_vec : 32;
+#else
+ uint32_t deepsleepentry_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_sleep_int_req_vec_reg1_t;
+
+
+
+typedef union pmc_sleep_int_req_vec_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t fastsleepexit_int_req_vec : 32;
+#else
+ uint32_t fastsleepexit_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_sleep_int_req_vec_reg2_t;
+
+
+
+typedef union pmc_sleep_int_req_vec_reg3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deepsleepexit_int_req_vec : 32;
+#else
+ uint32_t deepsleepexit_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_sleep_int_req_vec_reg3_t;
+
+
+
+typedef union pmc_winkle_int_req_vec_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t fastwinkleentry_int_req_vec : 32;
+#else
+ uint32_t fastwinkleentry_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_winkle_int_req_vec_reg0_t;
+
+
+
+typedef union pmc_winkle_int_req_vec_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deepwinkleentry_int_req_vec : 32;
+#else
+ uint32_t deepwinkleentry_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_winkle_int_req_vec_reg1_t;
+
+
+
+typedef union pmc_winkle_int_req_vec_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t fastwinkleexit_int_req_vec : 32;
+#else
+ uint32_t fastwinkleexit_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_winkle_int_req_vec_reg2_t;
+
+
+
+typedef union pmc_winkle_int_req_vec_reg3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deepwinkleexit_int_req_vec : 32;
+#else
+ uint32_t deepwinkleexit_int_req_vec : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_winkle_int_req_vec_reg3_t;
+
+
+
+typedef union pmc_nap_int_req_vec_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t napentry_int_req_vec : 16;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t napentry_int_req_vec : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_nap_int_req_vec_reg0_t;
+
+
+
+typedef union pmc_nap_int_req_vec_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t napexit_int_req_vec : 25;
+ uint32_t _reserved0 : 7;
+#else
+ uint32_t _reserved0 : 7;
+ uint32_t napexit_int_req_vec : 25;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_nap_int_req_vec_reg1_t;
+
+
+
+typedef union pmc_pore_req_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porrr_reserved0 : 8;
+ uint32_t porrr_start_vector : 4;
+ uint32_t porrr_reserved1 : 8;
+ uint32_t porrr_pore_busy : 1;
+ uint32_t porrr_pore_suspended : 1;
+ uint32_t porrr_porrtc_busy : 1;
+ uint32_t _reserved0 : 9;
+#else
+ uint32_t _reserved0 : 9;
+ uint32_t porrr_porrtc_busy : 1;
+ uint32_t porrr_pore_suspended : 1;
+ uint32_t porrr_pore_busy : 1;
+ uint32_t porrr_reserved1 : 8;
+ uint32_t porrr_start_vector : 4;
+ uint32_t porrr_reserved0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_req_reg0_t;
+
+
+
+typedef union pmc_pore_req_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porrr_chiplet_enable_0 : 1;
+ uint32_t porrr_chiplet_enable_1 : 1;
+ uint32_t porrr_chiplet_enable_2 : 1;
+ uint32_t porrr_chiplet_enable_3 : 1;
+ uint32_t porrr_chiplet_enable_4 : 1;
+ uint32_t porrr_chiplet_enable_5 : 1;
+ uint32_t porrr_chiplet_enable_6 : 1;
+ uint32_t porrr_chiplet_enable_7 : 1;
+ uint32_t porrr_chiplet_enable_8 : 1;
+ uint32_t porrr_chiplet_enable_9 : 1;
+ uint32_t porrr_chiplet_enable_10 : 1;
+ uint32_t porrr_chiplet_enable_11 : 1;
+ uint32_t porrr_chiplet_enable_12 : 1;
+ uint32_t porrr_chiplet_enable_13 : 1;
+ uint32_t porrr_chiplet_enable_14 : 1;
+ uint32_t porrr_chiplet_enable_15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t porrr_chiplet_enable_15 : 1;
+ uint32_t porrr_chiplet_enable_14 : 1;
+ uint32_t porrr_chiplet_enable_13 : 1;
+ uint32_t porrr_chiplet_enable_12 : 1;
+ uint32_t porrr_chiplet_enable_11 : 1;
+ uint32_t porrr_chiplet_enable_10 : 1;
+ uint32_t porrr_chiplet_enable_9 : 1;
+ uint32_t porrr_chiplet_enable_8 : 1;
+ uint32_t porrr_chiplet_enable_7 : 1;
+ uint32_t porrr_chiplet_enable_6 : 1;
+ uint32_t porrr_chiplet_enable_5 : 1;
+ uint32_t porrr_chiplet_enable_4 : 1;
+ uint32_t porrr_chiplet_enable_3 : 1;
+ uint32_t porrr_chiplet_enable_2 : 1;
+ uint32_t porrr_chiplet_enable_1 : 1;
+ uint32_t porrr_chiplet_enable_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_req_reg1_t;
+
+
+
+typedef union pmc_pore_req_stat_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porrs_reserved0 : 8;
+ uint32_t porrs_start_vector : 4;
+ uint32_t pore_rc : 8;
+ uint32_t porrs_reserved1 : 1;
+ uint32_t porrs_recovery_write : 1;
+ uint32_t _reserved0 : 10;
+#else
+ uint32_t _reserved0 : 10;
+ uint32_t porrs_recovery_write : 1;
+ uint32_t porrs_reserved1 : 1;
+ uint32_t pore_rc : 8;
+ uint32_t porrs_start_vector : 4;
+ uint32_t porrs_reserved0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_req_stat_reg_t;
+
+
+
+typedef union pmc_pore_req_tout_th_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porrtt_timeout_threshold : 8;
+ uint32_t porrtc_no_predivide : 1;
+ uint32_t _reserved0 : 23;
+#else
+ uint32_t _reserved0 : 23;
+ uint32_t porrtc_no_predivide : 1;
+ uint32_t porrtt_timeout_threshold : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_req_tout_th_reg_t;
+
+
+
+typedef union pmc_deep_exit_mask_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t chiplet_deep_exit_mask0 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_deep_exit_mask_reg_t;
+
+
+
+typedef union pmc_deep_exit_mask_reg_and {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t chiplet_deep_exit_mask0 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_deep_exit_mask_reg_and_t;
+
+
+
+typedef union pmc_deep_exit_mask_reg_or {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t chiplet_deep_exit_mask0 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t chiplet_deep_exit_mask15 : 1;
+ uint32_t chiplet_deep_exit_mask14 : 1;
+ uint32_t chiplet_deep_exit_mask13 : 1;
+ uint32_t chiplet_deep_exit_mask12 : 1;
+ uint32_t chiplet_deep_exit_mask11 : 1;
+ uint32_t chiplet_deep_exit_mask10 : 1;
+ uint32_t chiplet_deep_exit_mask9 : 1;
+ uint32_t chiplet_deep_exit_mask8 : 1;
+ uint32_t chiplet_deep_exit_mask7 : 1;
+ uint32_t chiplet_deep_exit_mask6 : 1;
+ uint32_t chiplet_deep_exit_mask5 : 1;
+ uint32_t chiplet_deep_exit_mask4 : 1;
+ uint32_t chiplet_deep_exit_mask3 : 1;
+ uint32_t chiplet_deep_exit_mask2 : 1;
+ uint32_t chiplet_deep_exit_mask1 : 1;
+ uint32_t chiplet_deep_exit_mask0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_deep_exit_mask_reg_or_t;
+
+
+
+typedef union pmc_core_pstate_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pstate_core0 : 8;
+ int32_t pstate_core1 : 8;
+ int32_t pstate_core2 : 8;
+ int32_t pstate_core3 : 8;
+#else
+ int32_t pstate_core3 : 8;
+ int32_t pstate_core2 : 8;
+ int32_t pstate_core1 : 8;
+ int32_t pstate_core0 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_pstate_reg0_t;
+
+
+
+typedef union pmc_core_pstate_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pstate_core4 : 8;
+ int32_t pstate_core5 : 8;
+ int32_t pstate_core6 : 8;
+ int32_t pstate_core7 : 8;
+#else
+ int32_t pstate_core7 : 8;
+ int32_t pstate_core6 : 8;
+ int32_t pstate_core5 : 8;
+ int32_t pstate_core4 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_pstate_reg1_t;
+
+
+
+typedef union pmc_core_pstate_reg2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pstate_core8 : 8;
+ int32_t pstate_core9 : 8;
+ int32_t pstate_core10 : 8;
+ int32_t pstate_core11 : 8;
+#else
+ int32_t pstate_core11 : 8;
+ int32_t pstate_core10 : 8;
+ int32_t pstate_core9 : 8;
+ int32_t pstate_core8 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_pstate_reg2_t;
+
+
+
+typedef union pmc_core_pstate_reg3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ int32_t pstate_core12 : 8;
+ int32_t pstate_core13 : 8;
+ int32_t pstate_core14 : 8;
+ int32_t pstate_core15 : 8;
+#else
+ int32_t pstate_core15 : 8;
+ int32_t pstate_core14 : 8;
+ int32_t pstate_core13 : 8;
+ int32_t pstate_core12 : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_pstate_reg3_t;
+
+
+
+typedef union pmc_core_power_donation_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t power_donation_core0 : 1;
+ uint32_t power_donation_core1 : 1;
+ uint32_t power_donation_core2 : 1;
+ uint32_t power_donation_core3 : 1;
+ uint32_t power_donation_core4 : 1;
+ uint32_t power_donation_core5 : 1;
+ uint32_t power_donation_core6 : 1;
+ uint32_t power_donation_core7 : 1;
+ uint32_t power_donation_core8 : 1;
+ uint32_t power_donation_core9 : 1;
+ uint32_t power_donation_core10 : 1;
+ uint32_t power_donation_core11 : 1;
+ uint32_t power_donation_core12 : 1;
+ uint32_t power_donation_core13 : 1;
+ uint32_t power_donation_core14 : 1;
+ uint32_t power_donation_core15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t power_donation_core15 : 1;
+ uint32_t power_donation_core14 : 1;
+ uint32_t power_donation_core13 : 1;
+ uint32_t power_donation_core12 : 1;
+ uint32_t power_donation_core11 : 1;
+ uint32_t power_donation_core10 : 1;
+ uint32_t power_donation_core9 : 1;
+ uint32_t power_donation_core8 : 1;
+ uint32_t power_donation_core7 : 1;
+ uint32_t power_donation_core6 : 1;
+ uint32_t power_donation_core5 : 1;
+ uint32_t power_donation_core4 : 1;
+ uint32_t power_donation_core3 : 1;
+ uint32_t power_donation_core2 : 1;
+ uint32_t power_donation_core1 : 1;
+ uint32_t power_donation_core0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_core_power_donation_reg_t;
+
+
+
+typedef union pmc_pmax_sync_collection_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmax_sync0 : 1;
+ uint32_t pmax_sync1 : 1;
+ uint32_t pmax_sync2 : 1;
+ uint32_t pmax_sync3 : 1;
+ uint32_t pmax_sync4 : 1;
+ uint32_t pmax_sync5 : 1;
+ uint32_t pmax_sync6 : 1;
+ uint32_t pmax_sync7 : 1;
+ uint32_t pmax_sync8 : 1;
+ uint32_t pmax_sync9 : 1;
+ uint32_t pmax_sync10 : 1;
+ uint32_t pmax_sync11 : 1;
+ uint32_t pmax_sync12 : 1;
+ uint32_t pmax_sync13 : 1;
+ uint32_t pmax_sync14 : 1;
+ uint32_t pmax_sync15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t pmax_sync15 : 1;
+ uint32_t pmax_sync14 : 1;
+ uint32_t pmax_sync13 : 1;
+ uint32_t pmax_sync12 : 1;
+ uint32_t pmax_sync11 : 1;
+ uint32_t pmax_sync10 : 1;
+ uint32_t pmax_sync9 : 1;
+ uint32_t pmax_sync8 : 1;
+ uint32_t pmax_sync7 : 1;
+ uint32_t pmax_sync6 : 1;
+ uint32_t pmax_sync5 : 1;
+ uint32_t pmax_sync4 : 1;
+ uint32_t pmax_sync3 : 1;
+ uint32_t pmax_sync2 : 1;
+ uint32_t pmax_sync1 : 1;
+ uint32_t pmax_sync0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pmax_sync_collection_reg_t;
+
+
+
+typedef union pmc_pmax_sync_collection_mask_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t pmax_sync_mask0 : 1;
+ uint32_t pmax_sync_mask1 : 1;
+ uint32_t pmax_sync_mask2 : 1;
+ uint32_t pmax_sync_mask3 : 1;
+ uint32_t pmax_sync_mask4 : 1;
+ uint32_t pmax_sync_mask5 : 1;
+ uint32_t pmax_sync_mask6 : 1;
+ uint32_t pmax_sync_mask7 : 1;
+ uint32_t pmax_sync_mask8 : 1;
+ uint32_t pmax_sync_mask9 : 1;
+ uint32_t pmax_sync_mask10 : 1;
+ uint32_t pmax_sync_mask11 : 1;
+ uint32_t pmax_sync_mask12 : 1;
+ uint32_t pmax_sync_mask13 : 1;
+ uint32_t pmax_sync_mask14 : 1;
+ uint32_t pmax_sync_mask15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t pmax_sync_mask15 : 1;
+ uint32_t pmax_sync_mask14 : 1;
+ uint32_t pmax_sync_mask13 : 1;
+ uint32_t pmax_sync_mask12 : 1;
+ uint32_t pmax_sync_mask11 : 1;
+ uint32_t pmax_sync_mask10 : 1;
+ uint32_t pmax_sync_mask9 : 1;
+ uint32_t pmax_sync_mask8 : 1;
+ uint32_t pmax_sync_mask7 : 1;
+ uint32_t pmax_sync_mask6 : 1;
+ uint32_t pmax_sync_mask5 : 1;
+ uint32_t pmax_sync_mask4 : 1;
+ uint32_t pmax_sync_mask3 : 1;
+ uint32_t pmax_sync_mask2 : 1;
+ uint32_t pmax_sync_mask1 : 1;
+ uint32_t pmax_sync_mask0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pmax_sync_collection_mask_reg_t;
+
+
+
+typedef union pmc_gpsa_ack_collection_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t gpsa_ack0 : 1;
+ uint32_t gpsa_ack1 : 1;
+ uint32_t gpsa_ack2 : 1;
+ uint32_t gpsa_ack3 : 1;
+ uint32_t gpsa_ack4 : 1;
+ uint32_t gpsa_ack5 : 1;
+ uint32_t gpsa_ack6 : 1;
+ uint32_t gpsa_ack7 : 1;
+ uint32_t gpsa_ack8 : 1;
+ uint32_t gpsa_ack9 : 1;
+ uint32_t gpsa_ack10 : 1;
+ uint32_t gpsa_ack11 : 1;
+ uint32_t gpsa_ack12 : 1;
+ uint32_t gpsa_ack13 : 1;
+ uint32_t gpsa_ack14 : 1;
+ uint32_t gpsa_ack15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t gpsa_ack15 : 1;
+ uint32_t gpsa_ack14 : 1;
+ uint32_t gpsa_ack13 : 1;
+ uint32_t gpsa_ack12 : 1;
+ uint32_t gpsa_ack11 : 1;
+ uint32_t gpsa_ack10 : 1;
+ uint32_t gpsa_ack9 : 1;
+ uint32_t gpsa_ack8 : 1;
+ uint32_t gpsa_ack7 : 1;
+ uint32_t gpsa_ack6 : 1;
+ uint32_t gpsa_ack5 : 1;
+ uint32_t gpsa_ack4 : 1;
+ uint32_t gpsa_ack3 : 1;
+ uint32_t gpsa_ack2 : 1;
+ uint32_t gpsa_ack1 : 1;
+ uint32_t gpsa_ack0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_gpsa_ack_collection_reg_t;
+
+
+
+typedef union pmc_gpsa_ack_collection_mask_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t gpsa_ack_mask0 : 1;
+ uint32_t gpsa_ack_mask1 : 1;
+ uint32_t gpsa_ack_mask2 : 1;
+ uint32_t gpsa_ack_mask3 : 1;
+ uint32_t gpsa_ack_mask4 : 1;
+ uint32_t gpsa_ack_mask5 : 1;
+ uint32_t gpsa_ack_mask6 : 1;
+ uint32_t gpsa_ack_mask7 : 1;
+ uint32_t gpsa_ack_mask8 : 1;
+ uint32_t gpsa_ack_mask9 : 1;
+ uint32_t gpsa_ack_mask10 : 1;
+ uint32_t gpsa_ack_mask11 : 1;
+ uint32_t gpsa_ack_mask12 : 1;
+ uint32_t gpsa_ack_mask13 : 1;
+ uint32_t gpsa_ack_mask14 : 1;
+ uint32_t gpsa_ack_mask15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t gpsa_ack_mask15 : 1;
+ uint32_t gpsa_ack_mask14 : 1;
+ uint32_t gpsa_ack_mask13 : 1;
+ uint32_t gpsa_ack_mask12 : 1;
+ uint32_t gpsa_ack_mask11 : 1;
+ uint32_t gpsa_ack_mask10 : 1;
+ uint32_t gpsa_ack_mask9 : 1;
+ uint32_t gpsa_ack_mask8 : 1;
+ uint32_t gpsa_ack_mask7 : 1;
+ uint32_t gpsa_ack_mask6 : 1;
+ uint32_t gpsa_ack_mask5 : 1;
+ uint32_t gpsa_ack_mask4 : 1;
+ uint32_t gpsa_ack_mask3 : 1;
+ uint32_t gpsa_ack_mask2 : 1;
+ uint32_t gpsa_ack_mask1 : 1;
+ uint32_t gpsa_ack_mask0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_gpsa_ack_collection_mask_reg_t;
+
+
+
+typedef union pmc_pore_scratch_reg0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porscr_scratch0 : 32;
+#else
+ uint32_t porscr_scratch0 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_scratch_reg0_t;
+
+
+
+typedef union pmc_pore_scratch_reg1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t porscr_scratch1 : 32;
+#else
+ uint32_t porscr_scratch1 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pore_scratch_reg1_t;
+
+
+
+typedef union pmc_deep_idle_exit_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deep_exit_pending_and_masked_0 : 1;
+ uint32_t deep_exit_pending_and_masked_1 : 1;
+ uint32_t deep_exit_pending_and_masked_2 : 1;
+ uint32_t deep_exit_pending_and_masked_3 : 1;
+ uint32_t deep_exit_pending_and_masked_4 : 1;
+ uint32_t deep_exit_pending_and_masked_5 : 1;
+ uint32_t deep_exit_pending_and_masked_6 : 1;
+ uint32_t deep_exit_pending_and_masked_7 : 1;
+ uint32_t deep_exit_pending_and_masked_8 : 1;
+ uint32_t deep_exit_pending_and_masked_9 : 1;
+ uint32_t deep_exit_pending_and_masked_10 : 1;
+ uint32_t deep_exit_pending_and_masked_11 : 1;
+ uint32_t deep_exit_pending_and_masked_12 : 1;
+ uint32_t deep_exit_pending_and_masked_13 : 1;
+ uint32_t deep_exit_pending_and_masked_14 : 1;
+ uint32_t deep_exit_pending_and_masked_15 : 1;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t deep_exit_pending_and_masked_15 : 1;
+ uint32_t deep_exit_pending_and_masked_14 : 1;
+ uint32_t deep_exit_pending_and_masked_13 : 1;
+ uint32_t deep_exit_pending_and_masked_12 : 1;
+ uint32_t deep_exit_pending_and_masked_11 : 1;
+ uint32_t deep_exit_pending_and_masked_10 : 1;
+ uint32_t deep_exit_pending_and_masked_9 : 1;
+ uint32_t deep_exit_pending_and_masked_8 : 1;
+ uint32_t deep_exit_pending_and_masked_7 : 1;
+ uint32_t deep_exit_pending_and_masked_6 : 1;
+ uint32_t deep_exit_pending_and_masked_5 : 1;
+ uint32_t deep_exit_pending_and_masked_4 : 1;
+ uint32_t deep_exit_pending_and_masked_3 : 1;
+ uint32_t deep_exit_pending_and_masked_2 : 1;
+ uint32_t deep_exit_pending_and_masked_1 : 1;
+ uint32_t deep_exit_pending_and_masked_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_deep_idle_exit_reg_t;
+
+
+
+typedef union pmc_deep_status_reg {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t deep_idle_state_core0 : 1;
+ uint32_t deep_idle_state_core1 : 1;
+ uint32_t deep_idle_state_core2 : 1;
+ uint32_t deep_idle_state_core3 : 1;
+ uint32_t deep_idle_state_core4 : 1;
+ uint32_t deep_idle_state_core5 : 1;
+ uint32_t deep_idle_state_core6 : 1;
+ uint32_t deep_idle_state_core7 : 1;
+ uint32_t deep_idle_state_core8 : 1;
+ uint32_t deep_idle_state_core9 : 1;
+ uint32_t deep_idle_state_core10 : 1;
+ uint32_t deep_idle_state_core11 : 1;
+ uint32_t deep_idle_state_core12 : 1;
+ uint32_t deep_idle_state_core13 : 1;
+ uint32_t deep_idle_state_core14 : 1;
+ uint32_t deep_idle_state_core15 : 1;
+ uint32_t winkle_state_core0 : 1;
+ uint32_t winkle_state_core1 : 1;
+ uint32_t winkle_state_core2 : 1;
+ uint32_t winkle_state_core3 : 1;
+ uint32_t winkle_state_core4 : 1;
+ uint32_t winkle_state_core5 : 1;
+ uint32_t winkle_state_core6 : 1;
+ uint32_t winkle_state_core7 : 1;
+ uint32_t winkle_state_core8 : 1;
+ uint32_t winkle_state_core9 : 1;
+ uint32_t winkle_state_core10 : 1;
+ uint32_t winkle_state_core11 : 1;
+ uint32_t winkle_state_core12 : 1;
+ uint32_t winkle_state_core13 : 1;
+ uint32_t winkle_state_core14 : 1;
+ uint32_t winkle_state_core15 : 1;
+#else
+ uint32_t winkle_state_core15 : 1;
+ uint32_t winkle_state_core14 : 1;
+ uint32_t winkle_state_core13 : 1;
+ uint32_t winkle_state_core12 : 1;
+ uint32_t winkle_state_core11 : 1;
+ uint32_t winkle_state_core10 : 1;
+ uint32_t winkle_state_core9 : 1;
+ uint32_t winkle_state_core8 : 1;
+ uint32_t winkle_state_core7 : 1;
+ uint32_t winkle_state_core6 : 1;
+ uint32_t winkle_state_core5 : 1;
+ uint32_t winkle_state_core4 : 1;
+ uint32_t winkle_state_core3 : 1;
+ uint32_t winkle_state_core2 : 1;
+ uint32_t winkle_state_core1 : 1;
+ uint32_t winkle_state_core0 : 1;
+ uint32_t deep_idle_state_core15 : 1;
+ uint32_t deep_idle_state_core14 : 1;
+ uint32_t deep_idle_state_core13 : 1;
+ uint32_t deep_idle_state_core12 : 1;
+ uint32_t deep_idle_state_core11 : 1;
+ uint32_t deep_idle_state_core10 : 1;
+ uint32_t deep_idle_state_core9 : 1;
+ uint32_t deep_idle_state_core8 : 1;
+ uint32_t deep_idle_state_core7 : 1;
+ uint32_t deep_idle_state_core6 : 1;
+ uint32_t deep_idle_state_core5 : 1;
+ uint32_t deep_idle_state_core4 : 1;
+ uint32_t deep_idle_state_core3 : 1;
+ uint32_t deep_idle_state_core2 : 1;
+ uint32_t deep_idle_state_core1 : 1;
+ uint32_t deep_idle_state_core0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_deep_status_reg_t;
+
+
+
+typedef union pmc_ba_pore_exe_trigger_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t value : 32;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t value : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_ba_pore_exe_trigger_reg_t;
+
+
+
+typedef union pmc_pcbs_gaps_brdcast_addr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t value : 32;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t value : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_pcbs_gaps_brdcast_addr_t;
+
+
+
+typedef union pmc_lfir_err_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t spare_fir : 10;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_fir : 10;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_reg_t;
+
+
+
+typedef union pmc_lfir_err_reg_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t spare_fir : 10;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_fir : 10;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_reg_and_t;
+
+
+
+typedef union pmc_lfir_err_reg_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t spare_fir : 10;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t fir_parity_err : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t fir_parity_err : 1;
+ uint64_t fir_parity_err_dup : 1;
+ uint64_t spare_fir : 10;
+ uint64_t lfir_if_comp_parity_error : 1;
+ uint64_t lfir_oci_slave_err : 1;
+ uint64_t lfir_o2p_fsm_err : 1;
+ uint64_t lfir_o2p_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_majority_detected_a_minority : 1;
+ uint64_t lfir_o2s_fsm_err : 1;
+ uint64_t lfir_o2s_write_while_bridge_busy_err : 1;
+ uint64_t lfir_o2s_retry_timeout : 1;
+ uint64_t lfir_o2s_crc_error2 : 1;
+ uint64_t lfir_o2s_crc_error1 : 1;
+ uint64_t lfir_o2s_crc_error0 : 1;
+ uint64_t lfir_spivid_majority_detected_a_minority : 1;
+ uint64_t lfir_spivid_fsm_err : 1;
+ uint64_t lfir_spivid_retry_timeout : 1;
+ uint64_t lfir_spivid_crc_error2 : 1;
+ uint64_t lfir_spivid_crc_error1 : 1;
+ uint64_t lfir_spivid_crc_error0 : 1;
+ uint64_t lfir_pmc_occ_heartbeat_timeout : 1;
+ uint64_t lfir_int_comp_parity_err : 1;
+ uint64_t lfir_idle_internal_err : 1;
+ uint64_t lfir_idle_oci_master_write_timeout_err : 1;
+ uint64_t lfir_idle_poresw_timeout_err : 1;
+ uint64_t lfir_idle_poresw_write_while_inactive_err : 1;
+ uint64_t lfir_idle_poresw_status_value_err : 1;
+ uint64_t lfir_idle_poresw_status_rc_err : 1;
+ uint64_t lfir_idle_poresw_fatal_err : 1;
+ uint64_t lfir_ms_comp_parity_err : 1;
+ uint64_t lfir_pstate_ms_fsm_err : 1;
+ uint64_t lfir_pstate_interchip_errorframe_err : 1;
+ uint64_t lfir_pstate_interchip_ue_err : 1;
+ uint64_t lfir_pstate_oci_master_to_err : 1;
+ uint64_t lfir_pstate_pib_master_offline_err : 1;
+ uint64_t lfir_pstate_pib_master_nonoffline_err : 1;
+ uint64_t lfir_pstate_gack_to_err : 1;
+ uint64_t lfir_pstate_gpst_checkbyte_err : 1;
+ uint64_t lfir_pstate_oci_master_rddata_parity_err : 1;
+ uint64_t lfir_pstate_oci_master_rderr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_reg_or_t;
+
+
+
+typedef union pmc_lfir_err_mask_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_mask_0 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_mask_reg_t;
+
+
+
+typedef union pmc_lfir_err_mask_reg_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_mask_0 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_mask_reg_and_t;
+
+
+
+typedef union pmc_lfir_err_mask_reg_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_mask_0 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_mask1_48 : 1;
+ uint64_t pmc_lfir_mask1_47 : 1;
+ uint64_t pmc_lfir_mask1_37_46 : 10;
+ uint64_t pmc_lfir_mask_36 : 1;
+ uint64_t pmc_lfir_mask_35 : 1;
+ uint64_t pmc_lfir_mask_34 : 1;
+ uint64_t pmc_lfir_mask_33 : 1;
+ uint64_t pmc_lfir_mask_32 : 1;
+ uint64_t pmc_lfir_mask_31 : 1;
+ uint64_t pmc_lfir_mask_30 : 1;
+ uint64_t pmc_lfir_mask_29 : 1;
+ uint64_t pmc_lfir_mask_28 : 1;
+ uint64_t pmc_lfir_mask_27 : 1;
+ uint64_t pmc_lfir_mask_26 : 1;
+ uint64_t pmc_lfir_mask_25 : 1;
+ uint64_t pmc_lfir_mask_24 : 1;
+ uint64_t pmc_lfir_mask_23 : 1;
+ uint64_t pmc_lfir_mask_22 : 1;
+ uint64_t pmc_lfir_mask_21 : 1;
+ uint64_t pmc_lfir_mask_20 : 1;
+ uint64_t pmc_lfir_mask_19 : 1;
+ uint64_t pmc_lfir_mask_18 : 1;
+ uint64_t pmc_lfir_mask_17 : 1;
+ uint64_t pmc_lfir_mask_16 : 1;
+ uint64_t pmc_lfir_mask_15 : 1;
+ uint64_t pmc_lfir_mask_14 : 1;
+ uint64_t pmc_lfir_mask_13 : 1;
+ uint64_t pmc_lfir_mask_12 : 1;
+ uint64_t pmc_lfir_mask_11 : 1;
+ uint64_t pmc_lfir_mask_10 : 1;
+ uint64_t pmc_lfir_mask_9 : 1;
+ uint64_t pmc_lfir_mask_8 : 1;
+ uint64_t pmc_lfir_mask_7 : 1;
+ uint64_t pmc_lfir_mask_6 : 1;
+ uint64_t pmc_lfir_mask_5 : 1;
+ uint64_t pmc_lfir_mask_4 : 1;
+ uint64_t pmc_lfir_mask_3 : 1;
+ uint64_t pmc_lfir_mask_2 : 1;
+ uint64_t pmc_lfir_mask_1 : 1;
+ uint64_t pmc_lfir_mask_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_err_mask_reg_or_t;
+
+
+
+typedef union pmc_lfir_action0_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_action0_0 : 1;
+ uint64_t pmc_lfir_action0_1 : 1;
+ uint64_t pmc_lfir_action0_2 : 1;
+ uint64_t pmc_lfir_action0_3 : 1;
+ uint64_t pmc_lfir_action0_4 : 1;
+ uint64_t pmc_lfir_action0_5 : 1;
+ uint64_t pmc_lfir_action0_6 : 1;
+ uint64_t pmc_lfir_action0_7 : 1;
+ uint64_t pmc_lfir_action0_8 : 1;
+ uint64_t pmc_lfir_action0_9 : 1;
+ uint64_t pmc_lfir_action0_10 : 1;
+ uint64_t pmc_lfir_action0_11 : 1;
+ uint64_t pmc_lfir_action0_12 : 1;
+ uint64_t pmc_lfir_action0_13 : 1;
+ uint64_t pmc_lfir_action0_14 : 1;
+ uint64_t pmc_lfir_action0_15 : 1;
+ uint64_t pmc_lfir_action0_16 : 1;
+ uint64_t pmc_lfir_action0_17 : 1;
+ uint64_t pmc_lfir_action0_18 : 1;
+ uint64_t pmc_lfir_action0_19 : 1;
+ uint64_t pmc_lfir_action0_20 : 1;
+ uint64_t pmc_lfir_action0_21 : 1;
+ uint64_t pmc_lfir_action0_22 : 1;
+ uint64_t pmc_lfir_action0_23 : 1;
+ uint64_t pmc_lfir_action0_24 : 1;
+ uint64_t pmc_lfir_action0_25 : 1;
+ uint64_t pmc_lfir_action0_26 : 1;
+ uint64_t pmc_lfir_action0_27 : 1;
+ uint64_t pmc_lfir_action0_28 : 1;
+ uint64_t pmc_lfir_action0_29 : 1;
+ uint64_t pmc_lfir_action0_30 : 1;
+ uint64_t pmc_lfir_action0_31 : 1;
+ uint64_t pmc_lfir_action0_32 : 1;
+ uint64_t pmc_lfir_action0_33 : 1;
+ uint64_t pmc_lfir_action0_34 : 1;
+ uint64_t pmc_lfir_action0_35 : 1;
+ uint64_t pmc_lfir_action0_36 : 1;
+ uint64_t pmc_lfir_action0_37_46 : 10;
+ uint64_t pmc_lfir_action0_47 : 1;
+ uint64_t pmc_lfir_action0_48 : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_action0_48 : 1;
+ uint64_t pmc_lfir_action0_47 : 1;
+ uint64_t pmc_lfir_action0_37_46 : 10;
+ uint64_t pmc_lfir_action0_36 : 1;
+ uint64_t pmc_lfir_action0_35 : 1;
+ uint64_t pmc_lfir_action0_34 : 1;
+ uint64_t pmc_lfir_action0_33 : 1;
+ uint64_t pmc_lfir_action0_32 : 1;
+ uint64_t pmc_lfir_action0_31 : 1;
+ uint64_t pmc_lfir_action0_30 : 1;
+ uint64_t pmc_lfir_action0_29 : 1;
+ uint64_t pmc_lfir_action0_28 : 1;
+ uint64_t pmc_lfir_action0_27 : 1;
+ uint64_t pmc_lfir_action0_26 : 1;
+ uint64_t pmc_lfir_action0_25 : 1;
+ uint64_t pmc_lfir_action0_24 : 1;
+ uint64_t pmc_lfir_action0_23 : 1;
+ uint64_t pmc_lfir_action0_22 : 1;
+ uint64_t pmc_lfir_action0_21 : 1;
+ uint64_t pmc_lfir_action0_20 : 1;
+ uint64_t pmc_lfir_action0_19 : 1;
+ uint64_t pmc_lfir_action0_18 : 1;
+ uint64_t pmc_lfir_action0_17 : 1;
+ uint64_t pmc_lfir_action0_16 : 1;
+ uint64_t pmc_lfir_action0_15 : 1;
+ uint64_t pmc_lfir_action0_14 : 1;
+ uint64_t pmc_lfir_action0_13 : 1;
+ uint64_t pmc_lfir_action0_12 : 1;
+ uint64_t pmc_lfir_action0_11 : 1;
+ uint64_t pmc_lfir_action0_10 : 1;
+ uint64_t pmc_lfir_action0_9 : 1;
+ uint64_t pmc_lfir_action0_8 : 1;
+ uint64_t pmc_lfir_action0_7 : 1;
+ uint64_t pmc_lfir_action0_6 : 1;
+ uint64_t pmc_lfir_action0_5 : 1;
+ uint64_t pmc_lfir_action0_4 : 1;
+ uint64_t pmc_lfir_action0_3 : 1;
+ uint64_t pmc_lfir_action0_2 : 1;
+ uint64_t pmc_lfir_action0_1 : 1;
+ uint64_t pmc_lfir_action0_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_action0_reg_t;
+
+
+
+typedef union pmc_lfir_action1_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_action1_0 : 1;
+ uint64_t pmc_lfir_action1_1 : 1;
+ uint64_t pmc_lfir_action1_2 : 1;
+ uint64_t pmc_lfir_action1_3 : 1;
+ uint64_t pmc_lfir_action1_4 : 1;
+ uint64_t pmc_lfir_action1_5 : 1;
+ uint64_t pmc_lfir_action1_6 : 1;
+ uint64_t pmc_lfir_action1_7 : 1;
+ uint64_t pmc_lfir_action1_8 : 1;
+ uint64_t pmc_lfir_action1_9 : 1;
+ uint64_t pmc_lfir_action1_10 : 1;
+ uint64_t pmc_lfir_action1_11 : 1;
+ uint64_t pmc_lfir_action1_12 : 1;
+ uint64_t pmc_lfir_action1_13 : 1;
+ uint64_t pmc_lfir_action1_14 : 1;
+ uint64_t pmc_lfir_action1_15 : 1;
+ uint64_t pmc_lfir_action1_16 : 1;
+ uint64_t pmc_lfir_action1_17 : 1;
+ uint64_t pmc_lfir_action1_18 : 1;
+ uint64_t pmc_lfir_action1_19 : 1;
+ uint64_t pmc_lfir_action1_20 : 1;
+ uint64_t pmc_lfir_action1_21 : 1;
+ uint64_t pmc_lfir_action1_22 : 1;
+ uint64_t pmc_lfir_action1_23 : 1;
+ uint64_t pmc_lfir_action1_24 : 1;
+ uint64_t pmc_lfir_action1_25 : 1;
+ uint64_t pmc_lfir_action1_26 : 1;
+ uint64_t pmc_lfir_action1_27 : 1;
+ uint64_t pmc_lfir_action1_28 : 1;
+ uint64_t pmc_lfir_action1_29 : 1;
+ uint64_t pmc_lfir_action1_30 : 1;
+ uint64_t pmc_lfir_action1_31 : 1;
+ uint64_t pmc_lfir_action1_32 : 1;
+ uint64_t pmc_lfir_action1_33 : 1;
+ uint64_t pmc_lfir_action1_34 : 1;
+ uint64_t pmc_lfir_action1_35 : 1;
+ uint64_t pmc_lfir_action1_36 : 1;
+ uint64_t pmc_lfir_action1_37_46 : 10;
+ uint64_t pmc_lfir_action1_47 : 1;
+ uint64_t pmc_lfir_action1_48 : 1;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_action1_48 : 1;
+ uint64_t pmc_lfir_action1_47 : 1;
+ uint64_t pmc_lfir_action1_37_46 : 10;
+ uint64_t pmc_lfir_action1_36 : 1;
+ uint64_t pmc_lfir_action1_35 : 1;
+ uint64_t pmc_lfir_action1_34 : 1;
+ uint64_t pmc_lfir_action1_33 : 1;
+ uint64_t pmc_lfir_action1_32 : 1;
+ uint64_t pmc_lfir_action1_31 : 1;
+ uint64_t pmc_lfir_action1_30 : 1;
+ uint64_t pmc_lfir_action1_29 : 1;
+ uint64_t pmc_lfir_action1_28 : 1;
+ uint64_t pmc_lfir_action1_27 : 1;
+ uint64_t pmc_lfir_action1_26 : 1;
+ uint64_t pmc_lfir_action1_25 : 1;
+ uint64_t pmc_lfir_action1_24 : 1;
+ uint64_t pmc_lfir_action1_23 : 1;
+ uint64_t pmc_lfir_action1_22 : 1;
+ uint64_t pmc_lfir_action1_21 : 1;
+ uint64_t pmc_lfir_action1_20 : 1;
+ uint64_t pmc_lfir_action1_19 : 1;
+ uint64_t pmc_lfir_action1_18 : 1;
+ uint64_t pmc_lfir_action1_17 : 1;
+ uint64_t pmc_lfir_action1_16 : 1;
+ uint64_t pmc_lfir_action1_15 : 1;
+ uint64_t pmc_lfir_action1_14 : 1;
+ uint64_t pmc_lfir_action1_13 : 1;
+ uint64_t pmc_lfir_action1_12 : 1;
+ uint64_t pmc_lfir_action1_11 : 1;
+ uint64_t pmc_lfir_action1_10 : 1;
+ uint64_t pmc_lfir_action1_9 : 1;
+ uint64_t pmc_lfir_action1_8 : 1;
+ uint64_t pmc_lfir_action1_7 : 1;
+ uint64_t pmc_lfir_action1_6 : 1;
+ uint64_t pmc_lfir_action1_5 : 1;
+ uint64_t pmc_lfir_action1_4 : 1;
+ uint64_t pmc_lfir_action1_3 : 1;
+ uint64_t pmc_lfir_action1_2 : 1;
+ uint64_t pmc_lfir_action1_1 : 1;
+ uint64_t pmc_lfir_action1_0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_action1_reg_t;
+
+
+
+typedef union pmc_lfir_wof_reg {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pmc_lfir_wof : 49;
+ uint64_t _reserved0 : 15;
+#else
+ uint64_t _reserved0 : 15;
+ uint64_t pmc_lfir_wof : 49;
+#endif // _BIG_ENDIAN
+ } fields;
+} pmc_lfir_wof_reg_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PMC_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/pmc_register_addresses.h b/src/include/registers/pmc_register_addresses.h
new file mode 100644
index 0000000..4e98c85
--- /dev/null
+++ b/src/include/registers/pmc_register_addresses.h
@@ -0,0 +1,140 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/pmc_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PMC_REGISTER_ADDRESSES_H__
+#define __PMC_REGISTER_ADDRESSES_H__
+
+// $Id: pmc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_register_addresses.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pmc_register_addresses.h
+/// \brief Symbolic addresses for the PMC unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define PMC_OCI_BASE 0x40010000
+#define PMC_MODE_REG 0x40010000
+#define PMC_HARDWARE_AUCTION_PSTATE_REG 0x40010008
+#define PMC_PSTATE_MONITOR_AND_CTRL_REG 0x40010010
+#define PMC_RAIL_BOUNDS_REGISTER 0x40010018
+#define PMC_GLOBAL_PSTATE_BOUNDS_REG 0x40010020
+#define PMC_PARAMETER_REG0 0x40010028
+#define PMC_PARAMETER_REG1 0x40010030
+#define PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010038
+#define PMC_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010040
+#define PMC_STATUS_REG 0x40010048
+#define PMC_PHASE_ENABLE_REG 0x40010050
+#define PMC_UNDERVOLTING_REG 0x40010060
+#define PMC_CORE_DECONFIGURATION_REG 0x40010068
+#define PMC_INTCHP_CTRL_REG1 0x40010080
+#define PMC_INTCHP_CTRL_REG2 0x40010088
+#define PMC_INTCHP_CTRL_REG4 0x40010090
+#define PMC_INTCHP_STATUS_REG 0x40010098
+#define PMC_INTCHP_COMMAND_REG 0x400100a0
+#define PMC_INTCHP_MSG_WDATA 0x400100a8
+#define PMC_INTCHP_MSG_RDATA 0x400100b0
+#define PMC_INTCHP_PSTATE_REG 0x400100b8
+#define PMC_INTCHP_GLOBACK_REG 0x400100c0
+#define PMC_FSMSTATE_STATUS_REG 0x40010100
+#define PMC_TRACE_MODE_REG 0x40010180
+#define PMC_SPIV_CTRL_REG0A 0x40010200
+#define PMC_SPIV_CTRL_REG0B 0x40010208
+#define PMC_SPIV_CTRL_REG1 0x40010210
+#define PMC_SPIV_CTRL_REG2 0x40010218
+#define PMC_SPIV_CTRL_REG3 0x40010220
+#define PMC_SPIV_CTRL_REG4 0x40010228
+#define PMC_SPIV_STATUS_REG 0x40010230
+#define PMC_SPIV_COMMAND_REG 0x40010238
+#define PMC_O2S_CTRL_REG0A 0x40010280
+#define PMC_O2S_CTRL_REG0B 0x40010288
+#define PMC_O2S_CTRL_REG1 0x40010290
+#define PMC_O2S_CTRL_REG2 0x40010298
+#define PMC_O2S_CTRL_REG4 0x400102a8
+#define PMC_O2S_STATUS_REG 0x400102b0
+#define PMC_O2S_COMMAND_REG 0x400102b8
+#define PMC_O2S_WDATA_REG 0x400102c0
+#define PMC_O2S_RDATA_REG 0x400102c8
+#define PMC_O2P_ADDR_REG 0x40010300
+#define PMC_O2P_CTRL_STATUS_REG 0x40010308
+#define PMC_O2P_SEND_DATA_HI_REG 0x40010310
+#define PMC_O2P_SEND_DATA_LO_REG 0x40010318
+#define PMC_O2P_RECV_DATA_HI_REG 0x40010320
+#define PMC_O2P_RECV_DATA_LO_REG 0x40010328
+#define PMC_OCC_HEARTBEAT_REG 0x40010330
+#define PMC_ERROR_INT_MASK_HI_REG 0x40010338
+#define PMC_ERROR_INT_MASK_LO_REG 0x40010340
+#define PMC_IDLE_SUSPEND_MASK_REG 0x40010348
+#define PMC_PEND_IDLE_REQ_REG0 0x40010400
+#define PMC_PEND_IDLE_REQ_REG1 0x40010408
+#define PMC_PEND_IDLE_REQ_REG2 0x40010410
+#define PMC_PEND_IDLE_REQ_REG3 0x40010418
+#define PMC_SLEEP_INT_REQ_VEC_REG0 0x40010420
+#define PMC_SLEEP_INT_REQ_VEC_REG1 0x40010428
+#define PMC_SLEEP_INT_REQ_VEC_REG2 0x40010430
+#define PMC_SLEEP_INT_REQ_VEC_REG3 0x40010438
+#define PMC_WINKLE_INT_REQ_VEC_REG0 0x40010440
+#define PMC_WINKLE_INT_REQ_VEC_REG1 0x40010448
+#define PMC_WINKLE_INT_REQ_VEC_REG2 0x40010450
+#define PMC_WINKLE_INT_REQ_VEC_REG3 0x40010458
+#define PMC_NAP_INT_REQ_VEC_REG0 0x40010460
+#define PMC_NAP_INT_REQ_VEC_REG1 0x40010468
+#define PMC_PORE_REQ_REG0 0x40010470
+#define PMC_PORE_REQ_REG1 0x40010478
+#define PMC_PORE_REQ_STAT_REG 0x40010480
+#define PMC_PORE_REQ_TOUT_TH_REG 0x40010488
+#define PMC_DEEP_EXIT_MASK_REG 0x40010490
+#define PMC_DEEP_EXIT_MASK_REG_AND 0x40010500
+#define PMC_DEEP_EXIT_MASK_REG_OR 0x40010508
+#define PMC_CORE_PSTATE_REG0 0x400104a0
+#define PMC_CORE_PSTATE_REG1 0x400104a8
+#define PMC_CORE_PSTATE_REG2 0x400104b0
+#define PMC_CORE_PSTATE_REG3 0x400104b8
+#define PMC_CORE_POWER_DONATION_REG 0x400104c0
+#define PMC_PMAX_SYNC_COLLECTION_REG 0x400104c8
+#define PMC_PMAX_SYNC_COLLECTION_MASK_REG 0x400104d0
+#define PMC_GPSA_ACK_COLLECTION_REG 0x400104d8
+#define PMC_GPSA_ACK_COLLECTION_MASK_REG 0x400104e0
+#define PMC_PORE_SCRATCH_REG0 0x400104e8
+#define PMC_PORE_SCRATCH_REG1 0x400104f0
+#define PMC_DEEP_IDLE_EXIT_REG 0x400104f8
+#define PMC_DEEP_STATUS_REG 0x40010510
+#define PMC_PIB_BASE 0x01010840
+#define PMC_LFIR_ERR_REG 0x01010840
+#define PMC_LFIR_ERR_REG_AND 0x01010841
+#define PMC_LFIR_ERR_REG_OR 0x01010842
+#define PMC_LFIR_ERR_MASK_REG 0x01010843
+#define PMC_LFIR_ERR_MASK_REG_AND 0x01010844
+#define PMC_LFIR_ERR_MASK_REG_OR 0x01010845
+#define PMC_LFIR_ACTION0_REG 0x01010846
+#define PMC_LFIR_ACTION1_REG 0x01010847
+#define PMC_LFIR_WOF_REG 0x01010848
+
+#endif // __PMC_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/ppm_firmware_registers.h b/src/include/registers/ppm_firmware_registers.h
new file mode 100644
index 0000000..782e9ac
--- /dev/null
+++ b/src/include/registers/ppm_firmware_registers.h
@@ -0,0 +1,1214 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/ppm_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PPM_FIRMWARE_REGISTERS_H__
+#define __PPM_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppm_firmware_registers.h
+/// \brief C register structs for the PPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union ppm_gpmmr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t special_wkup_done : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t chiplet_enable : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t chiplet_enable : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t special_wkup_done : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_gpmmr_t;
+
+
+
+typedef union ppm_gpmmr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t special_wkup_done : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t chiplet_enable : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t chiplet_enable : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t special_wkup_done : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_gpmmr_clr_t;
+
+
+
+typedef union ppm_gpmmr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t special_wkup_done : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t chiplet_enable : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved2 : 48;
+#else
+ uint64_t reserved2 : 48;
+ uint64_t reset_state_indicator : 1;
+ uint64_t reserved_12_141 : 3;
+ uint64_t chiplet_enable : 1;
+ uint64_t reg_wkup_override : 1;
+ uint64_t spc_wkup_override : 1;
+ uint64_t wkup_override_en : 1;
+ uint64_t block_all_wkup_events : 1;
+ uint64_t block_reg_wkup_events : 1;
+ uint64_t regular_wkup_present : 1;
+ uint64_t regular_wkup_requested : 1;
+ uint64_t special_wkup_requested : 1;
+ uint64_t regular_wkup_active : 1;
+ uint64_t special_wkup_active : 1;
+ uint64_t special_wkup_done : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_gpmmr_or_t;
+
+
+
+typedef union ppm_spwkup_otr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t otr_special_wkup : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t otr_special_wkup : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_spwkup_otr_t;
+
+
+
+typedef union ppm_spwkup_fsp {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t fsp_special_wkup : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t fsp_special_wkup : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_spwkup_fsp_t;
+
+
+
+typedef union ppm_spwkup_occ {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_special_wkup : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t occ_special_wkup : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_spwkup_occ_t;
+
+
+
+typedef union ppm_spwkup_hyp {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t hyp_special_wkup : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t hyp_special_wkup : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_spwkup_hyp_t;
+
+
+
+typedef union ppm_sshsrc {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t stop_gated : 1;
+ uint64_t stop_transition : 2;
+ uint64_t special_wkup_done : 1;
+ uint64_t req_stop_level : 4;
+ uint64_t act_stop_level : 4;
+ uint64_t reserved1 : 52;
+#else
+ uint64_t reserved1 : 52;
+ uint64_t act_stop_level : 4;
+ uint64_t req_stop_level : 4;
+ uint64_t special_wkup_done : 1;
+ uint64_t stop_transition : 2;
+ uint64_t stop_gated : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_sshsrc_t;
+
+
+
+typedef union ppm_sshfsp {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t stop_gated_fsp : 1;
+ uint64_t special_wkup_active_fsp : 1;
+ uint64_t stop_transition__fsp : 2;
+ uint64_t req_stop_level_fsp : 4;
+ uint64_t act_stop_level_fsp : 4;
+ uint64_t deepest_req_stop_level_fsp : 4;
+ uint64_t deepest_act_stop_level_fsp : 4;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t deepest_act_stop_level_fsp : 4;
+ uint64_t deepest_req_stop_level_fsp : 4;
+ uint64_t act_stop_level_fsp : 4;
+ uint64_t req_stop_level_fsp : 4;
+ uint64_t stop_transition__fsp : 2;
+ uint64_t special_wkup_active_fsp : 1;
+ uint64_t stop_gated_fsp : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_sshfsp_t;
+
+
+
+typedef union ppm_sshocc {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t run_stop_occ : 1;
+ uint64_t special_wkup_active_occ : 1;
+ uint64_t stop_transition_occ : 2;
+ uint64_t req_stop_level_occ : 4;
+ uint64_t act_stop_level_occ : 4;
+ uint64_t deepest_req_stop_level_occ : 4;
+ uint64_t deepest_act_stop_level_occ : 4;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t deepest_act_stop_level_occ : 4;
+ uint64_t deepest_req_stop_level_occ : 4;
+ uint64_t act_stop_level_occ : 4;
+ uint64_t req_stop_level_occ : 4;
+ uint64_t stop_transition_occ : 2;
+ uint64_t special_wkup_active_occ : 1;
+ uint64_t run_stop_occ : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_sshocc_t;
+
+
+
+typedef union ppm_sshotr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t run_stop_otr : 1;
+ uint64_t special_wkup_active_otr : 1;
+ uint64_t stop_transition_otr : 2;
+ uint64_t req_stop_level_otr : 4;
+ uint64_t act_stop_level_otr : 4;
+ uint64_t deepest_req_stop_level_otr : 4;
+ uint64_t deepest_act_stop_level_otr : 4;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t deepest_act_stop_level_otr : 4;
+ uint64_t deepest_req_stop_level_otr : 4;
+ uint64_t act_stop_level_otr : 4;
+ uint64_t req_stop_level_otr : 4;
+ uint64_t stop_transition_otr : 2;
+ uint64_t special_wkup_active_otr : 1;
+ uint64_t run_stop_otr : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_sshotr_t;
+
+
+
+typedef union ppm_sshhyp {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t run_stop_hyp : 1;
+ uint64_t special_wkup_active_hyp : 1;
+ uint64_t stop_transition_hyp : 2;
+ uint64_t req_stop_level_hyp : 4;
+ uint64_t act_stop_level_hyp : 4;
+ uint64_t deepest_req_stop_level_hyp : 4;
+ uint64_t deepest_act_stop_level_hyp : 4;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t deepest_act_stop_level_hyp : 4;
+ uint64_t deepest_req_stop_level_hyp : 4;
+ uint64_t act_stop_level_hyp : 4;
+ uint64_t req_stop_level_hyp : 4;
+ uint64_t stop_transition_hyp : 2;
+ uint64_t special_wkup_active_hyp : 1;
+ uint64_t run_stop_hyp : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_sshhyp_t;
+
+
+
+typedef union ppm_pfcs {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdd_pfet_force_state : 2;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vdd_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t reserved3 : 6;
+#else
+ uint64_t reserved3 : 6;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vdd_pg_state : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_force_state : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfcs_t;
+
+
+
+typedef union ppm_pfcs_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdd_pfet_force_state : 2;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vdd_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t reserved3 : 6;
+#else
+ uint64_t reserved3 : 6;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vdd_pg_state : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_force_state : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfcs_clr_t;
+
+
+
+typedef union ppm_pfcs_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdd_pfet_force_state : 2;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vdd_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t reserved3 : 6;
+#else
+ uint64_t reserved3 : 6;
+ uint64_t vcs_pg_sel : 4;
+ uint64_t vcs_pg_state : 4;
+ uint64_t vdd_pg_sel : 4;
+ uint64_t vdd_pg_state : 4;
+ uint64_t reserved2 : 6;
+ uint64_t vcs_pfet_sel_value : 4;
+ uint64_t vcs_pfet_enable_value : 8;
+ uint64_t vdd_pfet_sel_value : 4;
+ uint64_t vdd_pfet_enable_value : 8;
+ uint64_t reserved1 : 2;
+ uint64_t vdd_pfet_regulation_finger_value : 1;
+ uint64_t vdd_pfet_regulation_finger_en : 1;
+ uint64_t vcs_pfet_sel_override : 1;
+ uint64_t vcs_pfet_val_override : 1;
+ uint64_t vdd_pfet_sel_override : 1;
+ uint64_t vdd_pfet_val_override : 1;
+ uint64_t vcs_pfet_force_state : 2;
+ uint64_t vdd_pfet_force_state : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfcs_or_t;
+
+
+
+typedef union ppm_pfdly {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t powdn_dly : 4;
+ uint64_t powup_dly : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t powup_dly : 4;
+ uint64_t powdn_dly : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfdly_t;
+
+
+
+typedef union ppm_pfsns {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdd_pfets_enabled_sense : 1;
+ uint64_t vdd_pfets_disabled_sense : 1;
+ uint64_t vcs_pfets_enabled_sense : 1;
+ uint64_t vcs_pfets_disabled_sense : 1;
+ uint64_t reserved1 : 12;
+ uint64_t tp_vdd_pfet_enable_actual : 8;
+ uint64_t tp_vcs_pfet_enable_actual : 8;
+ uint64_t reserved2 : 32;
+#else
+ uint64_t reserved2 : 32;
+ uint64_t tp_vcs_pfet_enable_actual : 8;
+ uint64_t tp_vdd_pfet_enable_actual : 8;
+ uint64_t reserved1 : 12;
+ uint64_t vcs_pfets_disabled_sense : 1;
+ uint64_t vcs_pfets_enabled_sense : 1;
+ uint64_t vdd_pfets_disabled_sense : 1;
+ uint64_t vdd_pfets_enabled_sense : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfsns_t;
+
+
+
+typedef union ppm_pfoff {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdd_voff_sel : 4;
+ uint64_t vcs_voff_sel : 4;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t vcs_voff_sel : 4;
+ uint64_t vdd_voff_sel : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pfoff_t;
+
+
+
+typedef union ppm_scratch0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_scratch0_t;
+
+
+
+typedef union ppm_scratch1 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t data : 64;
+#else
+ uint64_t data : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_scratch1_t;
+
+
+
+typedef union ppm_cgcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clkglm_async_reset : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved2 : 60;
+#else
+ uint64_t reserved2 : 60;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_async_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_cgcr_t;
+
+
+
+typedef union ppm_cgcr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clkglm_async_reset : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved2 : 60;
+#else
+ uint64_t reserved2 : 60;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_async_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_cgcr_clr_t;
+
+
+
+typedef union ppm_cgcr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t clkglm_async_reset : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved2 : 60;
+#else
+ uint64_t reserved2 : 60;
+ uint64_t clkglm_sel : 1;
+ uint64_t reserved_1_21 : 2;
+ uint64_t clkglm_async_reset : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_cgcr_or_t;
+
+
+
+typedef union ppm_pig {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t req_intr_type : 3;
+ uint64_t req_intr_payload : 12;
+ uint64_t granted_packet : 16;
+ uint64_t intr_granted : 1;
+ uint64_t reserved2 : 1;
+ uint64_t granted__source : 2;
+ uint64_t reserved3 : 1;
+ uint64_t pending_source : 3;
+ uint64_t reserved4 : 24;
+#else
+ uint64_t reserved4 : 24;
+ uint64_t pending_source : 3;
+ uint64_t reserved3 : 1;
+ uint64_t granted__source : 2;
+ uint64_t reserved2 : 1;
+ uint64_t intr_granted : 1;
+ uint64_t granted_packet : 16;
+ uint64_t req_intr_payload : 12;
+ uint64_t req_intr_type : 3;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_pig_t;
+
+
+
+typedef union ppm_ivrmcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_vid_valid : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t reserved1 : 4;
+ uint64_t reserved2 : 56;
+#else
+ uint64_t reserved2 : 56;
+ uint64_t reserved1 : 4;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_vid_valid : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmcr_t;
+
+
+
+typedef union ppm_ivrmcr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_vid_valid : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t reserved1 : 4;
+ uint64_t reserved2 : 56;
+#else
+ uint64_t reserved2 : 56;
+ uint64_t reserved1 : 4;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_vid_valid : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmcr_clr_t;
+
+
+
+typedef union ppm_ivrmcr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_vid_valid : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t reserved1 : 4;
+ uint64_t reserved2 : 56;
+#else
+ uint64_t reserved2 : 56;
+ uint64_t reserved1 : 4;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_vid_valid : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmcr_or_t;
+
+
+
+typedef union ppm_ivrmst {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_vid_done : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t ivrm_vid_done : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmst_t;
+
+
+
+typedef union ppm_ivrmdvr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_ivid : 8;
+ uint64_t reserved_8_10 : 3;
+ uint64_t ivrm_pfet_strength_core : 5;
+ uint64_t reserved_16_18 : 3;
+ uint64_t ivrm_pfet_strength_cache : 5;
+ uint64_t reserved1 : 40;
+#else
+ uint64_t reserved1 : 40;
+ uint64_t ivrm_pfet_strength_cache : 5;
+ uint64_t reserved_16_18 : 3;
+ uint64_t ivrm_pfet_strength_core : 5;
+ uint64_t reserved_8_10 : 3;
+ uint64_t ivrm_ivid : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmdvr_t;
+
+
+
+typedef union ppm_ivrmavr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t ivrm_ivid : 8;
+ uint64_t reserved1 : 3;
+ uint64_t ivrm_pfet_strength : 5;
+ uint64_t reserved2 : 3;
+ uint64_t ivrm_enabled_history : 1;
+ uint64_t reserved3 : 4;
+ uint64_t ivrm_vid_valid : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t reserved4 : 36;
+#else
+ uint64_t reserved4 : 36;
+ uint64_t ivrm_vreg_slow_dc : 1;
+ uint64_t ivrm_poweron : 1;
+ uint64_t ivrm_bypass_b : 1;
+ uint64_t ivrm_vid_valid : 1;
+ uint64_t reserved3 : 4;
+ uint64_t ivrm_enabled_history : 1;
+ uint64_t reserved2 : 3;
+ uint64_t ivrm_pfet_strength : 5;
+ uint64_t reserved1 : 3;
+ uint64_t ivrm_ivid : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_ivrmavr_t;
+
+
+
+typedef union ppm_vdmcr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_poweron : 1;
+ uint64_t vdm_disable : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t vdm_disable : 1;
+ uint64_t vdm_poweron : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_vdmcr_t;
+
+
+
+typedef union ppm_vdmcr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_poweron : 1;
+ uint64_t vdm_disable : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t vdm_disable : 1;
+ uint64_t vdm_poweron : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_vdmcr_clr_t;
+
+
+
+typedef union ppm_vdmcr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_poweron : 1;
+ uint64_t vdm_disable : 1;
+ uint64_t reserved1 : 62;
+#else
+ uint64_t reserved1 : 62;
+ uint64_t vdm_disable : 1;
+ uint64_t vdm_poweron : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} ppm_vdmcr_or_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PPM_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/ppm_register_addresses.h b/src/include/registers/ppm_register_addresses.h
new file mode 100644
index 0000000..130feeb
--- /dev/null
+++ b/src/include/registers/ppm_register_addresses.h
@@ -0,0 +1,78 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/ppm_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __PPM_REGISTER_ADDRESSES_H__
+#define __PPM_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppm_register_addresses.h
+/// \brief Symbolic addresses for the PPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define PPM_PIB_BASE 0x000F0000
+#define PPM_GPMMR 0x000f0100
+#define PPM_GPMMR_CLR 0x000f0101
+#define PPM_GPMMR_OR 0x000f0102
+#define PPM_SPWKUP_OTR 0x000f010a
+#define PPM_SPWKUP_FSP 0x000f010b
+#define PPM_SPWKUP_OCC 0x000f010c
+#define PPM_SPWKUP_HYP 0x000f010d
+#define PPM_SSHSRC 0x000f0110
+#define PPM_SSHFSP 0x000f0111
+#define PPM_SSHOCC 0x000f0112
+#define PPM_SSHOTR 0x000f0113
+#define PPM_SSHHYP 0x000f0114
+#define PPM_PFCS 0x000f0118
+#define PPM_PFCS_CLR 0x000f0119
+#define PPM_PFCS_OR 0x000f011a
+#define PPM_PFDLY 0x000f011b
+#define PPM_PFSNS 0x000f011c
+#define PPM_PFOFF 0x000f011d
+#define PPM_SCRATCH0 0x000f011e
+#define PPM_SCRATCH1 0x000f011f
+#define PPM_CGCR 0x000f0165
+#define PPM_CGCR_CLR 0x000f0166
+#define PPM_CGCR_OR 0x000f0167
+#define PPM_PIG 0x000f0180
+#define PPM_IVRMCR 0x000f01b0
+#define PPM_IVRMCR_CLR 0x000f01b1
+#define PPM_IVRMCR_OR 0x000f01b2
+#define PPM_IVRMST 0x000f01b3
+#define PPM_IVRMDVR 0x000f01b4
+#define PPM_IVRMAVR 0x000f01b5
+#define PPM_VDMCR 0x000f01b8
+#define PPM_VDMCR_CLR 0x000f01b9
+#define PPM_VDMCR_OR 0x000f01ba
+
+#endif // __PPM_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/qppm_firmware_registers.h b/src/include/registers/qppm_firmware_registers.h
new file mode 100644
index 0000000..13053a4
--- /dev/null
+++ b/src/include/registers/qppm_firmware_registers.h
@@ -0,0 +1,1069 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/qppm_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __QPPM_FIRMWARE_REGISTERS_H__
+#define __QPPM_FIRMWARE_REGISTERS_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file qppm_firmware_registers.h
+/// \brief C register structs for the QPPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union qppm_qpmmr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t fsafe : 11;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t reserved13_15 : 3;
+ uint64_t reserved2 : 4;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t pb_purge_pls : 1;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t reserved4 : 32;
+#else
+ uint64_t reserved4 : 32;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t pb_purge_pls : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t reserved2 : 4;
+ uint64_t reserved13_15 : 3;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t fsafe : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qpmmr_t;
+
+
+
+typedef union qppm_qpmmr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t fsafe : 11;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t reserved13_15 : 3;
+ uint64_t reserved2 : 4;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t pb_purge_pls : 1;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t reserved4 : 32;
+#else
+ uint64_t reserved4 : 32;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t pb_purge_pls : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t reserved2 : 4;
+ uint64_t reserved13_15 : 3;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t fsafe : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qpmmr_clr_t;
+
+
+
+typedef union qppm_qpmmr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t fsafe : 11;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t reserved13_15 : 3;
+ uint64_t reserved2 : 4;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t pb_purge_pls : 1;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t reserved4 : 32;
+#else
+ uint64_t reserved4 : 32;
+ uint64_t pb_purge_done_lvl : 1;
+ uint64_t pb_purge_pls : 1;
+ uint64_t reserved28_293 : 2;
+ uint64_t cme_interppm_dpll_sel : 1;
+ uint64_t cme_interppm_dpll_enable : 1;
+ uint64_t cme_interppm_vdm_sel : 1;
+ uint64_t cme_interppm_vdm_enable : 1;
+ uint64_t cme_interppm_aclk_sel : 1;
+ uint64_t cme_interppm_aclk_enable : 1;
+ uint64_t cme_interppm_ivrm_sel : 1;
+ uint64_t cme_interppm_ivrm_enable : 1;
+ uint64_t reserved2 : 4;
+ uint64_t reserved13_15 : 3;
+ uint64_t enable_fsafe_upon_heartbeat_loss : 1;
+ uint64_t fsafe : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qpmmr_or_t;
+
+
+
+typedef union qppm_errsum {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pm_error : 1;
+ uint64_t reserved1 : 63;
+#else
+ uint64_t reserved1 : 63;
+ uint64_t pm_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_errsum_t;
+
+
+
+typedef union qppm_err {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t pcb_interrupt_protocol_err : 1;
+ uint64_t special_wkup_protocol_err : 1;
+ uint64_t l2_ex0_clk_sync_err : 1;
+ uint64_t l2_ex1_clk_sync_err : 1;
+ uint64_t dpll_dyn_fmin_err : 1;
+ uint64_t dpll_dco_full_err : 1;
+ uint64_t dpll_dco_empty_err : 1;
+ uint64_t dpll_int_err : 1;
+ uint64_t occ_heartbeat_loss : 1;
+ uint64_t spare_8_11 : 3;
+ uint64_t reserved1 : 52;
+#else
+ uint64_t reserved1 : 52;
+ uint64_t spare_8_11 : 3;
+ uint64_t occ_heartbeat_loss : 1;
+ uint64_t dpll_int_err : 1;
+ uint64_t dpll_dco_empty_err : 1;
+ uint64_t dpll_dco_full_err : 1;
+ uint64_t dpll_dyn_fmin_err : 1;
+ uint64_t l2_ex1_clk_sync_err : 1;
+ uint64_t l2_ex0_clk_sync_err : 1;
+ uint64_t special_wkup_protocol_err : 1;
+ uint64_t pcb_interrupt_protocol_err : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_err_t;
+
+
+
+typedef union qppm_errmsk {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 12;
+ uint64_t reserved2 : 52;
+#else
+ uint64_t reserved2 : 52;
+ uint64_t reserved1 : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_errmsk_t;
+
+
+
+typedef union qppm_dpll_freq {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t fmax : 11;
+ uint64_t hires_fmax : 4;
+ uint64_t reserved2 : 1;
+ uint64_t freq_mult : 11;
+ uint64_t hires_freq_mult : 4;
+ uint64_t reserved3 : 1;
+ uint64_t fmin : 11;
+ uint64_t hires_fmin : 4;
+ uint64_t reserved4 : 16;
+#else
+ uint64_t reserved4 : 16;
+ uint64_t hires_fmin : 4;
+ uint64_t fmin : 11;
+ uint64_t reserved3 : 1;
+ uint64_t hires_freq_mult : 4;
+ uint64_t freq_mult : 11;
+ uint64_t reserved2 : 1;
+ uint64_t hires_fmax : 4;
+ uint64_t fmax : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_freq_t;
+
+
+
+typedef union qppm_dpll_ctrl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dpll_lock_sel : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dco_override : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_decr : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t ss_enable : 1;
+ uint64_t reserved_17_19 : 3;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t reserved_17_19 : 3;
+ uint64_t ss_enable : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t dco_decr : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_override : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t dpll_lock_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_ctrl_t;
+
+
+
+typedef union qppm_dpll_ctrl_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dpll_lock_sel : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dco_override : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_decr : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t ss_enable : 1;
+ uint64_t reserved_17_19 : 3;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t reserved_17_19 : 3;
+ uint64_t ss_enable : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t dco_decr : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_override : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t dpll_lock_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_ctrl_clr_t;
+
+
+
+typedef union qppm_dpll_ctrl_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t dpll_lock_sel : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dco_override : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_decr : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t ss_enable : 1;
+ uint64_t reserved_17_19 : 3;
+ uint64_t reserved1 : 44;
+#else
+ uint64_t reserved1 : 44;
+ uint64_t reserved_17_19 : 3;
+ uint64_t ss_enable : 1;
+ uint64_t ff_slewrate : 10;
+ uint64_t dco_decr : 1;
+ uint64_t dco_incr : 1;
+ uint64_t dco_override : 1;
+ uint64_t ff_bypass : 1;
+ uint64_t dynamic_filter_enable : 1;
+ uint64_t dpll_lock_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_ctrl_or_t;
+
+
+
+typedef union qppm_dpll_stat {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t freqout : 11;
+ uint64_t hires_freqout : 5;
+ uint64_t reserved2 : 40;
+ uint64_t reserved_57_60 : 4;
+ uint64_t fsafe_active : 1;
+ uint64_t freq_change : 1;
+ uint64_t lock : 1;
+#else
+ uint64_t lock : 1;
+ uint64_t freq_change : 1;
+ uint64_t fsafe_active : 1;
+ uint64_t reserved_57_60 : 4;
+ uint64_t reserved2 : 40;
+ uint64_t hires_freqout : 5;
+ uint64_t freqout : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_stat_t;
+
+
+
+typedef union qppm_dpll_ochar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t freqout_max : 11;
+ uint64_t hires_freqout_max : 5;
+ uint64_t reserved2 : 4;
+ uint64_t freqout_avg : 11;
+ uint64_t hires_freqout_avg : 5;
+ uint64_t reserved3 : 4;
+ uint64_t freqout_min : 11;
+ uint64_t hires_freqout_min : 5;
+ uint64_t reserved4 : 7;
+#else
+ uint64_t reserved4 : 7;
+ uint64_t hires_freqout_min : 5;
+ uint64_t freqout_min : 11;
+ uint64_t reserved3 : 4;
+ uint64_t hires_freqout_avg : 5;
+ uint64_t freqout_avg : 11;
+ uint64_t reserved2 : 4;
+ uint64_t hires_freqout_max : 5;
+ uint64_t freqout_max : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_ochar_t;
+
+
+
+typedef union qppm_dpll_ichar {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 1;
+ uint64_t freqin_avg : 11;
+ uint64_t hires_freqin_avg : 5;
+ uint64_t reserved2 : 4;
+ uint64_t freqin_max : 11;
+ uint64_t hires_freqin_max : 5;
+ uint64_t reserved3 : 4;
+ uint64_t freqin_min : 11;
+ uint64_t hires_freqin_min : 5;
+ uint64_t reserved4 : 7;
+#else
+ uint64_t reserved4 : 7;
+ uint64_t hires_freqin_min : 5;
+ uint64_t freqin_min : 11;
+ uint64_t reserved3 : 4;
+ uint64_t hires_freqin_max : 5;
+ uint64_t freqin_max : 11;
+ uint64_t reserved2 : 4;
+ uint64_t hires_freqin_avg : 5;
+ uint64_t freqin_avg : 11;
+ uint64_t reserved1 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_dpll_ichar_t;
+
+
+
+typedef union qppm_occhb {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_heartbeat_count : 16;
+ uint64_t occ_heartbeat_enable : 1;
+ uint64_t reserved1 : 47;
+#else
+ uint64_t reserved1 : 47;
+ uint64_t occ_heartbeat_enable : 1;
+ uint64_t occ_heartbeat_count : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_occhb_t;
+
+
+
+typedef union qppm_qaccr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_clk_sb_strength : 4;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_pulse_mode : 2;
+#else
+ uint64_t l3_clk_sb_pulse_mode : 2;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qaccr_t;
+
+
+
+typedef union qppm_qaccr_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_clk_sb_strength : 4;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_pulse_mode : 2;
+#else
+ uint64_t l3_clk_sb_pulse_mode : 2;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qaccr_clr_t;
+
+
+
+typedef union qppm_qaccr_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t core_clk_sb_strength : 4;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_pulse_mode : 2;
+#else
+ uint64_t l3_clk_sb_pulse_mode : 2;
+ uint64_t l3_clk_sb_pulse_mode_en : 1;
+ uint64_t l3_clk_sb_spare0 : 1;
+ uint64_t l3_clk_sb_strength : 4;
+ uint64_t reserved_53_55 : 3;
+ uint64_t l2_ex1_clk_sw_spare1 : 1;
+ uint64_t l2_ex1_clk_sw_resclk : 4;
+ uint64_t l2_ex1_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex1_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex1_clk_sb_spare0 : 1;
+ uint64_t l2_ex1_clk_sb_strength : 4;
+ uint64_t l2_ex1_clkglm_sel : 1;
+ uint64_t reserved_37_384 : 2;
+ uint64_t l2_ex1_clkglm_async_reset : 1;
+ uint64_t reserved_34_353 : 2;
+ uint64_t l2_ex1_clk_sync_enable : 1;
+ uint64_t l2_ex0_clk_sw_spare1 : 1;
+ uint64_t l2_ex0_clk_sw_resclk : 4;
+ uint64_t l2_ex0_clk_sb_pulse_mode : 2;
+ uint64_t l2_ex0_clk_sb_pulse_mode_en : 1;
+ uint64_t l2_ex0_clk_sb_spare0 : 1;
+ uint64_t l2_ex0_clk_sb_strength : 4;
+ uint64_t l2_ex0_clkglm_sel : 1;
+ uint64_t reserved_17_182 : 2;
+ uint64_t l2_ex0_clkglm_async_reset : 1;
+ uint64_t reserved_14_151 : 2;
+ uint64_t l2_ex0_clk_sync_enable : 1;
+ uint64_t core_clk_sw_spare : 1;
+ uint64_t core_clk_sw_resclk : 4;
+ uint64_t core_clk_sb_pulse_mode : 2;
+ uint64_t core_clk_sb_pulse_mode_en : 1;
+ uint64_t core_clk_sb_spare : 1;
+ uint64_t core_clk_sb_strength : 4;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qaccr_or_t;
+
+
+
+typedef union qppm_qacsr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved1 : 62;
+ uint64_t l2_ex0_clk_sync_done : 1;
+ uint64_t l2_ex1_clk_sync_done : 1;
+#else
+ uint64_t l2_ex1_clk_sync_done : 1;
+ uint64_t l2_ex0_clk_sync_done : 1;
+ uint64_t reserved1 : 62;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_qacsr_t;
+
+
+
+typedef union qppm_vdmcfgr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t vdm_vid_compare : 8;
+ uint64_t vdm_overvolt : 4;
+ uint64_t vdm_droop_small : 4;
+ uint64_t vdm_droop_large : 4;
+ uint64_t vdm_droop_xtreme : 4;
+ uint64_t reserved1 : 8;
+ uint64_t vid_compare_max : 8;
+ uint64_t vid_compare_min : 8;
+ uint64_t reserved2 : 16;
+#else
+ uint64_t reserved2 : 16;
+ uint64_t vid_compare_min : 8;
+ uint64_t vid_compare_max : 8;
+ uint64_t reserved1 : 8;
+ uint64_t vdm_droop_xtreme : 4;
+ uint64_t vdm_droop_large : 4;
+ uint64_t vdm_droop_small : 4;
+ uint64_t vdm_overvolt : 4;
+ uint64_t vdm_vid_compare : 8;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_vdmcfgr_t;
+
+
+
+typedef union qppm_edram_ctrl {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t l3_ex0_edram_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_edram_ctrl_t;
+
+
+
+typedef union qppm_edram_ctrl_clr {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t l3_ex0_edram_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_edram_ctrl_clr_t;
+
+
+
+typedef union qppm_edram_ctrl_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t l3_ex0_edram_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t reserved1 : 56;
+#else
+ uint64_t reserved1 : 56;
+ uint64_t l3_ex1_edram_vpp_enable : 1;
+ uint64_t l3_ex1_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex1_edram_vwl_enable : 1;
+ uint64_t l3_ex1_edram_enable : 1;
+ uint64_t l3_ex0_edram_vpp_enable : 1;
+ uint64_t l3_ex0_edram_vrow_vblh_enable : 1;
+ uint64_t l3_ex0_edram_vwl_enable : 1;
+ uint64_t l3_ex0_edram_enable : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} qppm_edram_ctrl_or_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __QPPM_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/qppm_register_addresses.h b/src/include/registers/qppm_register_addresses.h
new file mode 100644
index 0000000..afceea5
--- /dev/null
+++ b/src/include/registers/qppm_register_addresses.h
@@ -0,0 +1,67 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/qppm_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __QPPM_REGISTER_ADDRESSES_H__
+#define __QPPM_REGISTER_ADDRESSES_H__
+
+// $Id$
+// $Source$
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file qppm_register_addresses.h
+/// \brief Symbolic addresses for the QPPM unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define QPPM_PIB_BASE 0x100F0000
+#define QPPM_QPMMR 0x100f0103
+#define QPPM_QPMMR_CLR 0x100f0104
+#define QPPM_QPMMR_OR 0x100f0105
+#define QPPM_ERRSUM 0x100f0120
+#define QPPM_ERR 0x100f0121
+#define QPPM_ERRMSK 0x100f0122
+#define QPPM_DPLL_FREQ 0x100f0151
+#define QPPM_DPLL_CTRL 0x100f0152
+#define QPPM_DPLL_CTRL_CLR 0x100f0153
+#define QPPM_DPLL_CTRL_OR 0x100f0154
+#define QPPM_DPLL_STAT 0x100f0155
+#define QPPM_DPLL_OCHAR 0x100f0156
+#define QPPM_DPLL_ICHAR 0x100f0157
+#define QPPM_OCCHB 0x100f015f
+#define QPPM_QACCR 0x100f0160
+#define QPPM_QACCR_CLR 0x100f0161
+#define QPPM_QACCR_OR 0x100f0162
+#define QPPM_QACSR 0x100f0163
+#define QPPM_VDMCFGR 0x100f01b6
+#define QPPM_EDRAM_CTRL 0x100f01bd
+#define QPPM_EDRAM_CTRL_CLR 0x100f01be
+#define QPPM_EDRAM_CTRL_OR 0x100f01bf
+
+#endif // __QPPM_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/sramctl_firmware_registers.h b/src/include/registers/sramctl_firmware_registers.h
new file mode 100644
index 0000000..dd0d34f
--- /dev/null
+++ b/src/include/registers/sramctl_firmware_registers.h
@@ -0,0 +1,235 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/sramctl_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __SRAMCTL_FIRMWARE_REGISTERS_H__
+#define __SRAMCTL_FIRMWARE_REGISTERS_H__
+
+// $Id: sramctl_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_firmware_registers.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file sramctl_firmware_registers.h
+/// \brief C register structs for the SRAMCTL unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union sramctl_srbar {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t sram_region_qualifier : 2;
+ uint32_t reserved : 3;
+ uint32_t sram_bar_region : 8;
+ uint32_t _reserved0 : 19;
+#else
+ uint32_t _reserved0 : 19;
+ uint32_t sram_bar_region : 8;
+ uint32_t reserved : 3;
+ uint32_t sram_region_qualifier : 2;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srbar_t;
+
+
+
+typedef union sramctl_srmr {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t sram_enable_remap : 1;
+ uint32_t sram_arb_en_send_all_writes : 1;
+ uint32_t sram_disable_lfsr : 1;
+ uint32_t sram_lfsr_fairness_mask : 5;
+ uint32_t sram_error_inject_enable : 1;
+ uint32_t sram_ctl_trace_en : 1;
+ uint32_t sram_ctl_trace_sel : 1;
+ uint32_t reserved : 5;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t reserved : 5;
+ uint32_t sram_ctl_trace_sel : 1;
+ uint32_t sram_ctl_trace_en : 1;
+ uint32_t sram_error_inject_enable : 1;
+ uint32_t sram_lfsr_fairness_mask : 5;
+ uint32_t sram_disable_lfsr : 1;
+ uint32_t sram_arb_en_send_all_writes : 1;
+ uint32_t sram_enable_remap : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srmr_t;
+
+
+
+typedef union sramctl_srmap {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t reserved : 1;
+ uint32_t sram_remap_source : 12;
+ uint32_t _reserved0 : 1;
+ uint32_t reserved1 : 3;
+ uint32_t sram_remap_dest : 13;
+ uint32_t reserved2 : 2;
+#else
+ uint32_t reserved2 : 2;
+ uint32_t sram_remap_dest : 13;
+ uint32_t reserved1 : 3;
+ uint32_t _reserved0 : 1;
+ uint32_t sram_remap_source : 12;
+ uint32_t reserved : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srmap_t;
+
+
+
+typedef union sramctl_srear {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t sram_error_address : 16;
+ uint32_t _reserved0 : 16;
+#else
+ uint32_t _reserved0 : 16;
+ uint32_t sram_error_address : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srear_t;
+
+
+
+typedef union sramctl_srbv0 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t boot_vector_word0 : 32;
+#else
+ uint32_t boot_vector_word0 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srbv0_t;
+
+
+
+typedef union sramctl_srbv1 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t boot_vector_word1 : 32;
+#else
+ uint32_t boot_vector_word1 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srbv1_t;
+
+
+
+typedef union sramctl_srbv2 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t boot_vector_word2 : 32;
+#else
+ uint32_t boot_vector_word2 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srbv2_t;
+
+
+
+typedef union sramctl_srbv3 {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t boot_vector_word3 : 32;
+#else
+ uint32_t boot_vector_word3 : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srbv3_t;
+
+
+
+typedef union sramctl_srchsw {
+
+ uint32_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t chksw_wrfsm_dly_dis : 1;
+ uint32_t chksw_allow1_rd : 1;
+ uint32_t chksw_allow1_wr : 1;
+ uint32_t chksw_allow1_rdwr : 1;
+ uint32_t chksw_oci_parchk_dis : 1;
+ uint32_t chksw_tank_rddata_parchk_dis : 1;
+ uint32_t chksw_tank_sr_rderr_dis : 1;
+ uint32_t chksw_val_be_addr_chk_dis : 1;
+ uint32_t chksw_so_spare : 2;
+ uint32_t _reserved0 : 22;
+#else
+ uint32_t _reserved0 : 22;
+ uint32_t chksw_so_spare : 2;
+ uint32_t chksw_val_be_addr_chk_dis : 1;
+ uint32_t chksw_tank_sr_rderr_dis : 1;
+ uint32_t chksw_tank_rddata_parchk_dis : 1;
+ uint32_t chksw_oci_parchk_dis : 1;
+ uint32_t chksw_allow1_rdwr : 1;
+ uint32_t chksw_allow1_wr : 1;
+ uint32_t chksw_allow1_rd : 1;
+ uint32_t chksw_wrfsm_dly_dis : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} sramctl_srchsw_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __SRAMCTL_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/sramctl_register_addresses.h b/src/include/registers/sramctl_register_addresses.h
new file mode 100644
index 0000000..a45e203
--- /dev/null
+++ b/src/include/registers/sramctl_register_addresses.h
@@ -0,0 +1,54 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/sramctl_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __SRAMCTL_REGISTER_ADDRESSES_H__
+#define __SRAMCTL_REGISTER_ADDRESSES_H__
+
+// $Id: sramctl_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_register_addresses.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file sramctl_register_addresses.h
+/// \brief Symbolic addresses for the SRAMCTL unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define SRAMCTL_OCI_BASE 0x40050000
+#define SRAMCTL_SRBAR 0x40050000
+#define SRAMCTL_SRMR 0x40050008
+#define SRAMCTL_SRMAP 0x40050010
+#define SRAMCTL_SREAR 0x40050018
+#define SRAMCTL_SRBV0 0x40050020
+#define SRAMCTL_SRBV1 0x40050028
+#define SRAMCTL_SRBV2 0x40050030
+#define SRAMCTL_SRBV3 0x40050038
+#define SRAMCTL_SRCHSW 0x40050040
+
+#endif // __SRAMCTL_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/tpc_firmware_registers.h b/src/include/registers/tpc_firmware_registers.h
new file mode 100644
index 0000000..1a51ee5
--- /dev/null
+++ b/src/include/registers/tpc_firmware_registers.h
@@ -0,0 +1,237 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/tpc_firmware_registers.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __TPC_FIRMWARE_REGISTERS_H__
+#define __TPC_FIRMWARE_REGISTERS_H__
+
+// $Id: tpc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_firmware_registers.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file tpc_firmware_registers.h
+/// \brief C register structs for the TPC unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union tpc_perv_gp3 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t tp_chiplet_chiplet_en_dc : 1;
+ uint64_t put_in_later0 : 25;
+ uint64_t tp_chiplet_fence_pcb_dc : 1;
+ uint64_t put_in_later1 : 37;
+#else
+ uint64_t put_in_later1 : 37;
+ uint64_t tp_chiplet_fence_pcb_dc : 1;
+ uint64_t put_in_later0 : 25;
+ uint64_t tp_chiplet_chiplet_en_dc : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_perv_gp3_t;
+
+
+
+typedef union tpc_gp0 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t put_in_later0 : 40;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t put_in_later1 : 18;
+#else
+ uint64_t put_in_later1 : 18;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t put_in_later0 : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_gp0_t;
+
+
+
+typedef union tpc_gp0_and {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t put_in_later0 : 40;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t put_in_later1 : 18;
+#else
+ uint64_t put_in_later1 : 18;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t put_in_later0 : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_gp0_and_t;
+
+
+
+typedef union tpc_gp0_or {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t put_in_later0 : 40;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t put_in_later1 : 18;
+#else
+ uint64_t put_in_later1 : 18;
+ uint64_t tc_chip_id_dc : 3;
+ uint64_t tc_node_id_dc : 3;
+ uint64_t put_in_later0 : 40;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_gp0_or_t;
+
+
+
+typedef union tpc_hpr2 {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t hang_pulse_reg : 6;
+ uint64_t suppress_hang : 1;
+ uint64_t _reserved0 : 57;
+#else
+ uint64_t _reserved0 : 57;
+ uint64_t suppress_hang : 1;
+ uint64_t hang_pulse_reg : 6;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_hpr2_t;
+
+
+
+typedef union tpc_device_id {
+
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t cfam_id : 32;
+ uint64_t fuse_nx_allow_crypto : 1;
+ uint64_t fuse_vmx_crypto_dis : 1;
+ uint64_t fuse_fp_throttle_en : 1;
+ uint64_t reserved32 : 1;
+ uint64_t socket_id : 3;
+ uint64_t chippos_id : 1;
+ uint64_t _reserved0 : 24;
+#else
+ uint64_t _reserved0 : 24;
+ uint64_t chippos_id : 1;
+ uint64_t socket_id : 3;
+ uint64_t reserved32 : 1;
+ uint64_t fuse_fp_throttle_en : 1;
+ uint64_t fuse_vmx_crypto_dis : 1;
+ uint64_t fuse_nx_allow_crypto : 1;
+ uint64_t cfam_id : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} tpc_device_id_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __TPC_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/tpc_register_addresses.h b/src/include/registers/tpc_register_addresses.h
new file mode 100644
index 0000000..b5d2d07
--- /dev/null
+++ b/src/include/registers/tpc_register_addresses.h
@@ -0,0 +1,54 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/include/registers/tpc_register_addresses.h $ */
+/* */
+/* OpenPOWER OnChipController Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2015 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __TPC_REGISTER_ADDRESSES_H__
+#define __TPC_REGISTER_ADDRESSES_H__
+
+// $Id: tpc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_register_addresses.h,v $
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file tpc_register_addresses.h
+/// \brief Symbolic addresses for the TPC unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+
+#define TPC_PERVPIB_BASE 0x00050000
+#define TPC_PERV_GP3 0x0005001b
+#define TPC_PIB_BASE 0x01000000
+#define TPC_GP0 0x01000000
+#define TPC_GP0_AND 0x01000004
+#define TPC_GP0_OR 0x01000005
+#define TPC_MISCPIB_BASE 0x010f0000
+#define TPC_HPR2 0x010f0022
+#define TPC_TPCHIP_BASE 0x000f0000
+#define TPC_DEVICE_ID 0x000f000f
+
+#endif // __TPC_REGISTER_ADDRESSES_H__
+
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