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| author | William Bryan <wilbryan@us.ibm.com> | 2017-09-28 13:32:29 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-10-03 16:03:05 -0400 |
| commit | 74f721c90235a18821b97782d98349cf51e0f12d (patch) | |
| tree | 1f2fd59b41db514c0273632dd2dd7926e25a2030 /src/include | |
| parent | 76b91d0038d59b30de14108e908bc78c6d988796 (diff) | |
| download | talos-occ-74f721c90235a18821b97782d98349cf51e0f12d.tar.gz talos-occ-74f721c90235a18821b97782d98349cf51e0f12d.zip | |
GPU 405 Enable Memory Temperatures
Change-Id: Id50d12a50a05b8b3a6a6f1ce3ce4512d3299caa7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46882
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/registers/ocb_firmware_registers.h | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/src/include/registers/ocb_firmware_registers.h b/src/include/registers/ocb_firmware_registers.h index 5b6705a..010ad02 100644 --- a/src/include/registers/ocb_firmware_registers.h +++ b/src/include/registers/ocb_firmware_registers.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1411,9 +1411,21 @@ typedef union ocb_occflg { uint32_t i2c_engine2_lock_occ : 1; uint32_t i2c_engine3_lock_host : 1; uint32_t i2c_engine3_lock_occ : 1; - uint32_t reserved_occ : 10; -#else - uint32_t reserved_occ : 10; + uint32_t gpu0_reset_status : 1; + uint32_t gpu1_reset_status : 1; + uint32_t gpu2_reset_status : 1; + uint32_t reserved_occ : 3; + uint32_t wof_hcode_mode : 2; + uint32_t active_quad_update : 1; + uint32_t request_occ_safe : 1; +#else + uint32_t request_occ_safe : 1; + uint32_t active_quad_update : 1; + uint32_t wof_hcode_mode : 2; + uint32_t reserved_occ : 3; + uint32_t gpu2_reset_status : 1; + uint32_t gpu1_reset_status : 1; + uint32_t gpu0_reset_status : 1; uint32_t i2c_engine3_lock_occ : 1; uint32_t i2c_engine3_lock_host : 1; uint32_t i2c_engine2_lock_occ : 1; |
