Add Droop counter sensors

Change-Id: If4c367eaeaaf746619d537d4d8424cf018591563
RTC: 155684
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45574
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>

3 files changed, 77 insertions, 47 deletions

diff --git a/src/include/core_data.h b/src/include/core_data.h
index d3b3078..1ffe5fe 100644
--- a/src/include/core_data.h
+++ b/src/include/core_data.h
@@ -68,6 +68,13 @@
 
 #define EMPATH_CORE_THREADS 4
 
+// Droop events  cache=bit37, cores = bits 42,46,50,54
+#define CACHE_VDM_LARGE_DROOP 0x0000000004000000ull
+#define CORE0_VDM_SMALL_DROOP 0x0000000000200000ull
+#define CORE1_VDM_SMALL_DROOP 0x0000000000020000ull
+#define CORE2_VDM_SMALL_DROOP 0x0000000000002000ull
+#define CORE3_VDM_SMALL_DROOP 0x0000000000000200ull
+
 
 typedef struct
 {
@@ -85,7 +92,6 @@ typedef struct
 typedef struct
 {
     uint32_t ifu_throttle;
-    //uint32_t isu_throttle;  // No longer exists
     uint32_t ifu_active;
     uint32_t undefined;
     uint32_t v_droop;         // new for p9
@@ -106,17 +112,23 @@ typedef struct
     sensor_result_t cache[2];
 } CoreDataDts;
 
+typedef struct
+{
+    uint32_t    cache_large_event;
+    uint32_t    core_small_event;
+} DroopEvents;
 
 //
 // The instance of this data object must be 8 byte aligned
 //
-typedef struct // 128
+typedef struct // 136 bytes
 {
     CoreDataEmpath             empath;    //32
     CoreDataThrottle           throttle;  //16
     CoreDataPerThread          per_thread[EMPATH_CORE_THREADS]; // 64
-    CoreDataDts                dts;  //8
-    uint64_t                   stop_state_hist;
+    CoreDataDts                dts;              // 8
+    uint64_t                   stop_state_hist;  // 8
+    DroopEvents                droop;            // 8
 } CoreData;
 
 #ifdef __cplusplus
diff --git a/src/include/p9_config.h b/src/include/p9_config.h
index 72168e1..017921c 100644
--- a/src/include/p9_config.h
+++ b/src/include/p9_config.h
@@ -34,6 +34,10 @@
 
 #define THERM_DTS_RESULT        0x00050000
 
+#define MAX_NUM_CORES   24
+#define CORES_PER_QUAD  4
+#define MAX_NUM_QUADS   (MAX_NUM_CORES/CORES_PER_QUAD)
+
 typedef union dts_sensor_result_reg
 {
     uint64_t value;
diff --git a/src/include/registers/cme_register_addresses.h b/src/include/registers/cme_register_addresses.h
index de64e59..6870007 100644
--- a/src/include/registers/cme_register_addresses.h
+++ b/src/include/registers/cme_register_addresses.h
@@ -28,7 +28,8 @@
 /// \file cme_register_addresses.h
 /// \brief Symbolic addresses for the CME unit
 
-// *** WARNING *** - This file is generated automatically, do not edit.
+// Copied from
+// ekb/chips/p9/common/pmlib/include/registers/cme_register_addresses.h
 
 
 #define CME_FIRPIB_BASE 0x10012000
@@ -47,21 +48,22 @@
 #define CME_SCOM_CSAR 0x1001200d
 #define CME_SCOM_CSDR 0x1001200e
 #define CME_SCOM_BCECSR 0x1001200f
-#define CME_SCOM_BCEBAR0 0x10012010
-#define CME_SCOM_BCEBAR1 0x10012011
-#define CME_SCOM_QFMR 0x10012012
-#define CME_SCOM_AFSR 0x10012013
-#define CME_SCOM_AFTR 0x10012014
-#define CME_SCOM_VTSR0 0x10012015
-#define CME_SCOM_VTSR1 0x10012016
-#define CME_SCOM_VDSR 0x10012017
-#define CME_SCOM_EIIR 0x10012019
-#define CME_SCOM_FWMR 0x1001201a
-#define CME_SCOM_FWMR_CLR 0x1001201b
-#define CME_SCOM_FWMR_OR 0x1001201c
-#define CME_SCOM_SICR 0x1001201d
-#define CME_SCOM_SICR_CLR 0x1001201e
-#define CME_SCOM_SICR_OR 0x1001201f
+#define CME_SCOM_XIXCR 0x10012010
+#define CME_SCOM_XIRAMRA 0x10012011
+#define CME_SCOM_XIRAMGA 0x10012012
+#define CME_SCOM_XIRAMDBG 0x10012013
+#define CME_SCOM_XIRAMEDR 0x10012014
+#define CME_SCOM_XIDBGPRO 0x10012015
+#define CME_SCOM_XISIB 0x10012016
+#define CME_SCOM_XIMEM 0x10012017
+#define CME_SCOM_CMEXISGB 0x10012018
+#define CME_SCOM_XIICAC 0x10012019
+#define CME_SCOM_XIPCBQ0 0x1001201a
+#define CME_SCOM_XIPCBQ1 0x1001201b
+#define CME_SCOM_XIPCBMD0 0x1001201c
+#define CME_SCOM_XIPCBMD1 0x1001201d
+#define CME_SCOM_XIPCBMI0 0x1001201e
+#define CME_SCOM_XIPCBMI1 0x1001201f
 #define CME_SCOM_FLAGS 0x10012020
 #define CME_SCOM_FLAGS_CLR 0x10012021
 #define CME_SCOM_FLAGS_OR 0x10012022
@@ -73,36 +75,41 @@
 #define CME_SCOM_EITR 0x10012028
 #define CME_SCOM_EISTR 0x10012029
 #define CME_SCOM_EINR 0x1001202a
-#define CME_SCOM_SISR 0x1001202b
-#define CME_SCOM_ICRR 0x1001202c
-#define CME_SCOM_XIXCR 0x10012030
-#define CME_SCOM_XIRAMRA 0x10012031
-#define CME_SCOM_XIRAMGA 0x10012032
-#define CME_SCOM_XIRAMDBG 0x10012033
-#define CME_SCOM_XIRAMEDR 0x10012034
-#define CME_SCOM_XIDBGPRO 0x10012035
-#define CME_SCOM_XISIB 0x10012036
-#define CME_SCOM_XIMEM 0x10012037
-#define CME_SCOM_CMEXISGB 0x10012038
-#define CME_SCOM_XIICAC 0x10012039
-#define CME_SCOM_XIPCBQ0 0x1001203a
-#define CME_SCOM_XIPCBQ1 0x1001203b
-#define CME_SCOM_XIPCBMD0 0x1001203c
-#define CME_SCOM_XIPCBMD1 0x1001203d
-#define CME_SCOM_XIPCBMI0 0x1001203e
-#define CME_SCOM_XIPCBMI1 0x1001203f
+#define CME_SCOM_EIIR 0x1001202b
+#define CME_SCOM_VCCR 0x1001202c
+#define CME_SCOM_IDCR 0x1001202d
+#define CME_SCOM_CIDSR 0x1001202e
+#define CME_SCOM_QIDSR 0x1001202f
+#define CME_SCOM_BCEBAR0 0x10012030
+#define CME_SCOM_BCEBAR1 0x10012031
+#define CME_SCOM_QFMR 0x10012032
+#define CME_SCOM_AFSR 0x10012033
+#define CME_SCOM_AFTR 0x10012034
+#define CME_SCOM_VDCR 0x10012035
+#define CME_SCOM_VNCR 0x10012036
+#define CME_SCOM_VDSR 0x10012037
+#define CME_SCOM_VECR 0x10012038
+#define CME_SCOM_VCTR 0x10012039
+#define CME_SCOM_LMCR 0x1001203a
+#define CME_SCOM_LMCR_CLR 0x1001203b
+#define CME_SCOM_LMCR_OR 0x1001203c
+#define CME_SCOM_SICR 0x1001203d
+#define CME_SCOM_SICR_CLR 0x1001203e
+#define CME_SCOM_SICR_OR 0x1001203f
 #define CME_SCOM_PMSRS0 0x10012040
 #define CME_SCOM_PMSRS1 0x10012041
 #define CME_SCOM_PMCRS0 0x10012042
 #define CME_SCOM_PMCRS1 0x10012043
 #define CME_SCOM_PSCRS00 0x10012044
-#define CME_SCOM_PSCRS10 0x10012045
-#define CME_SCOM_PSCRS01 0x10012048
+#define CME_SCOM_PSCRS01 0x10012045
+#define CME_SCOM_PSCRS02 0x10012046
+#define CME_SCOM_PSCRS03 0x10012047
+#define CME_SCOM_PSCRS10 0x10012048
 #define CME_SCOM_PSCRS11 0x10012049
-#define CME_SCOM_PSCRS02 0x1001204c
-#define CME_SCOM_PSCRS12 0x1001204d
-#define CME_SCOM_PSCRS03 0x10012050
-#define CME_SCOM_PSCRS13 0x10012051
+#define CME_SCOM_PSCRS12 0x1001204a
+#define CME_SCOM_PSCRS13 0x1001204b
+#define CME_SCOM_SISR 0x1001204c
+#define CME_SCOM_ICRR 0x1001204d
 #define CME_LOCAL_BASE 0xC0000000
 #define CME_LCL_EISR 0xc0000000
 #define CME_LCL_EISR_OR 0xc0000010
@@ -126,7 +133,9 @@
 #define CME_LCL_AFSR 0xc0000160
 #define CME_LCL_AFTR 0xc0000180
 #define CME_LCL_LMCR 0xc00001a0
-#define CME_LCL_BCECSR 0xc00001f0
+#define CME_LCL_LMCR_OR 0xc00001b0
+#define CME_LCL_LMCR_CLR 0xc00001b8
+#define CME_LCL_BCECSR 0xc00001e0
 #define CME_LCL_PMSRS0 0xc0000200
 #define CME_LCL_PMSRS1 0xc0000220
 #define CME_LCL_PMCRS0 0xc0000240
@@ -154,9 +163,14 @@
 #define CME_LCL_XIPCBMD1 0xc00005a0
 #define CME_LCL_XIPCBMI0 0xc00005c0
 #define CME_LCL_XIPCBMI1 0xc00005e0
-#define CME_LCL_VTSR0 0xc0000600
-#define CME_LCL_VTSR1 0xc0000620
+#define CME_LCL_VDCR 0xc0000600
+#define CME_LCL_VNCR 0xc0000620
 #define CME_LCL_VDSR 0xc0000640
+#define CME_LCL_VECR 0xc0000660
+#define CME_LCL_VCCR 0xc0000680
+#define CME_LCL_IDCR 0xc00006a0
+#define CME_LCL_CIDSR 0xc00006c0
+#define CME_LCL_QIDSR 0xc00006e0
 #define CME_LCL_ICCR 0xc0000700
 #define CME_LCL_ICCR_OR 0xc0000710
 #define CME_LCL_ICCR_CLR 0xc0000718