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| author | mbroyles <mbroyles@us.ibm.com> | 2018-01-10 16:18:59 -0600 |
|---|---|---|
| committer | Martha Broyles <mbroyles@us.ibm.com> | 2018-01-15 13:42:20 -0500 |
| commit | 2397cb606cda005ae0fdd8455a827450fb4d8b4f (patch) | |
| tree | fc19b43040853cc2878a4f0003bc2458128b4781 /src/include | |
| parent | d868b77dfc6afd90d4fea874ae4a1175fffffaed (diff) | |
| download | talos-occ-2397cb606cda005ae0fdd8455a827450fb4d8b4f.tar.gz talos-occ-2397cb606cda005ae0fdd8455a827450fb4d8b4f.zip | |
Handle PGPE timeouts as workaround for prolonged droop events
Add "CLIP" information to poll response
Fix incorrectly throttling due to power when all cores are in stop 2 or greater
Change-Id: I502cc65ad8c4cffd7f9a1442fd4de185f3cac6e2
RTC: 183700
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51741
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/registers/ocb_firmware_registers.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/include/registers/ocb_firmware_registers.h b/src/include/registers/ocb_firmware_registers.h index 010ad02..82e94d5 100644 --- a/src/include/registers/ocb_firmware_registers.h +++ b/src/include/registers/ocb_firmware_registers.h @@ -1414,7 +1414,8 @@ typedef union ocb_occflg { uint32_t gpu0_reset_status : 1; uint32_t gpu1_reset_status : 1; uint32_t gpu2_reset_status : 1; - uint32_t reserved_occ : 3; + uint32_t reserved_occ : 2; + uint32_t pm_reset_suppress : 1; uint32_t wof_hcode_mode : 2; uint32_t active_quad_update : 1; uint32_t request_occ_safe : 1; @@ -1422,7 +1423,8 @@ typedef union ocb_occflg { uint32_t request_occ_safe : 1; uint32_t active_quad_update : 1; uint32_t wof_hcode_mode : 2; - uint32_t reserved_occ : 3; + uint32_t pm_reset_suppress : 1; + uint32_t reserved_occ : 2; uint32_t gpu2_reset_status : 1; uint32_t gpu1_reset_status : 1; uint32_t gpu0_reset_status : 1; |
