P9 Centaur sensor support

Change-Id: Ia84bc7532482ca314c26bd0bb5bf48ad6ee9c410
RTC: 163359
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54989
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

8 files changed, 2059 insertions, 33 deletions

diff --git a/src/include/centaur_mem_data.h b/src/include/centaur_mem_data.h
new file mode 100644
index 0000000..e97e3c6
--- /dev/null
+++ b/src/include/centaur_mem_data.h
@@ -0,0 +1,174 @@
+#if !defined(__CENTAUR_MEM_DATA_H__)
+#define __CENTAUR_MEM_DATA_H__
+typedef union {
+    uint16_t value;
+    struct {
+        uint16_t value;
+    } fields;
+} centaur_sensor_t;
+
+/// The layout of a Centaur DIMM sensor
+///
+/// Mnemonic macros for the 2-bit status codes (DIMM_SENSOR_STATUS_*) are
+/// currently defined in ssx/pgp/pgp_common.h
+///
+/// \todo Waiting for more info from Centaur team on how to interpret
+
+typedef union {
+    uint16_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+    uint16_t crit_trip : 1;
+    uint16_t alarm_trip : 1;
+    uint16_t below_trip : 1;
+    uint16_t sign_bit : 1;
+    uint16_t temperature : 8;
+    uint16_t temp_fraction : 2;
+    uint16_t status : 2;
+#else
+    uint16_t status : 2;
+    uint16_t temp_fraction : 2;
+    uint16_t temperature : 8;
+    uint16_t sign_bit : 1;
+    uint16_t below_trip : 1;
+    uint16_t alarm_trip : 1;
+    uint16_t crit_trip : 1;
+#endif
+    } fields;
+} centaur_dimm_sensor_t;
+
+/// The layout of the status bits of the sensor cache line
+///
+/// The sensor cache-line aggregator gets each element of the sensor cache
+/// line by an internal SCOM.  The individual PCB return codes for each SCOM
+/// are collected here (3 bits each) - note that many of the 32-bit registers
+/// come back in a single 64-bit internal SCOM. Normally this register will
+/// always read as 0 indicating all data was collected successfully.  The PCB
+/// error codes (PCB_ERROR_*) are currently defined in ssx/pgp/pgp_common.h.
+
+typedef union {
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t mba01_rw : 3;         /// mba01_rd[+ wr]
+        uint64_t mba01_ap : 3;         /// mba01_act[+ powerups]
+        uint64_t mba23_rw : 3;         /// mba23_rd[+ wr]
+        uint64_t mba23_ap : 3;         /// mba23_act[+ powerups]
+        uint64_t mba_sc : 3;           /// mba01[+ 23]_spec_cancels
+        uint64_t lp2_exits : 3;        /// lp2_exits
+        uint64_t frame_count : 3;      /// frame_count
+        uint64_t mba01_chrw : 3;       /// mba01_cache_hits_rd[+ wr]
+        uint64_t mba23_chrw : 3;       /// mba23_cache_hits_rd[+ wr]
+        uint64_t mba01_iac_bl : 3;     /// mba01_intreq_arr_cnt_base[+ low]
+        uint64_t mba01_iac_mh : 3;     /// mba01_intreq_arr_cnt_med[+ high]
+        uint64_t mba23_iac_bl : 3;     /// mba23_intreq_arr_cnt_base[+ low]
+        uint64_t mba23_iac_mh : 3;     /// mba23_intreq_arr_cnt_med[+ high]
+        uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
+        uint64_t centaur01 : 3;        /// centaur_thermal_sensor[0 - 1]
+        uint64_t dimm03 : 3;           /// dimm_thermal_sensor[0 - 3]
+        uint64_t dimm47 : 3;           /// dimm_thermal_sensor[4 - 7]
+        uint64_t reserved : 13;
+#else
+        uint64_t reserved : 13;
+        uint64_t dimm47 : 3;           /// dimm_thermal_sensor[4 - 7]
+        uint64_t dimm03 : 3;           /// dimm_thermal_sensor[0 - 3]
+        uint64_t centaur01 : 3;        /// centaur_thermal_sensor[0 - 1]
+        uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
+        uint64_t mba23_iac_mh : 3;     /// mba23_intreq_arr_cnt_med[+ high]
+        uint64_t mba23_iac_bl : 3;     /// mba23_intreq_arr_cnt_base[+ low]
+        uint64_t mba01_iac_mh : 3;     /// mba01_intreq_arr_cnt_med[+ high]
+        uint64_t mba01_iac_bl : 3;     /// mba01_intreq_arr_cnt_base[+ low]
+        uint64_t mba23_chrw : 3;       /// mba23_cache_hits_rd[+ wr]
+        uint64_t mba01_chrw : 3;       /// mba01_cache_hits_rd[+ wr]
+        uint64_t frame_count : 3;      /// frame_count
+        uint64_t lp2_exits : 3;        /// lp2_exits
+        uint64_t mba_sc : 3;           /// mba01[+ 23]_spec_cancels
+        uint64_t mba23_ap : 3;         /// mba23_act[+ powerups]
+        uint64_t mba23_rw : 3;         /// mba23_rd[+ wr]
+        uint64_t mba01_ap : 3;         /// mba01_act[+ powerups]
+        uint64_t mba01_rw : 3;         /// mba01_rd[+ wr]
+#endif
+    } fields;
+} centaur_scom_status_t;
+
+/// The layout of the Centaur sensor cache line
+
+
+typedef struct {
+    uint32_t mba01_rd;                      // PP1/MBA01 Reads 
+    uint32_t mba01_wr;                      // PP1/MBA01 Writes
+    uint32_t mba01_act;                     // PP1/MBA01 Activations
+    uint32_t mba01_powerups;                // PP1/MBA01 PowerUps
+
+    uint32_t mba23_rd;                      // PP2/MBA23 Reads 
+    uint32_t mba23_wr;                      // PP2/MBA23 Writes
+    uint32_t mba23_act;                     // PP2/MBA23 Activations
+    uint32_t mba23_powerups;                // PP2/MBA23 PowerUps
+
+    uint32_t mba01_spec_cancels;            // PP1/MBA01 Speculative Cancels
+    uint32_t mba23_spec_cancels;            // PP2/MBA23 Speculative Cancels
+#ifdef _BIG_ENDIAN
+    uint32_t eventn     :4;                 // EVENTN
+    uint32_t reserved_0 :20;                // Reserved
+    uint32_t lp2_exits  :8;                 // LP2 Exits
+#else
+    uint32_t lp2_exits  :8;                 // LP2 Exits
+    uint32_t reserved_0 :20;                // Reserved
+    uint32_t eventn     :4;                 // EVENTN
+#endif
+    uint32_t frame_count;                   // Frame Count (timestamp)
+
+    uint32_t mba01_cache_hits_rd;           // PP1/MBA01 Cache Hits Reads
+    uint32_t mba01_cache_hits_wr;           // PP1/MBA01 Cache Hits Writes
+    uint32_t mba23_cache_hits_rd;           // PP2/MBA23 Cache Hits Reads
+    uint32_t mba23_cache_hits_wr;           // PP2/MBA23 Cache Hits Writes
+
+    uint32_t mba01_intreq_arr_cnt_base;     // PP1/MBA01 Inter-Req Arrival Count Base
+    uint32_t mba01_intreq_arr_cnt_low;      // PP1/MBA01 Inter-Req Arrival Count Low
+    uint32_t mba01_intreq_arr_cnt_med;      // PP1/MBA01 Inter-Req Arrival Count Med 
+    uint32_t mba01_intreq_arr_cnt_high;     // PP1/MBA01 Inter-Req Arrival Count High
+
+    uint32_t mba23_intreq_arr_cnt_base;     // PP2/MBA23 Inter-Req Arrival Count Base
+    uint32_t mba23_intreq_arr_cnt_low;      // PP2/MBA23 Inter-Req Arrival Count Low
+    uint32_t mba23_intreq_arr_cnt_med;      // PP2/MBA23 Inter-Req Arrival Count Med 
+    uint32_t mba23_intreq_arr_cnt_high;     // PP2/MBA23 Inter-Req Arrival Count High
+
+    uint32_t intreq_arr_cnt_high_latency;   // Inter-Req Arrival Count High Latency
+    centaur_sensor_t centaur_thermal_sensor[2];   // Centaur Thermal Sensors 0-1
+    centaur_dimm_sensor_t dimm_thermal_sensor[8]; // DIMM Thermal Sensors 0-7
+    centaur_scom_status_t status;           // Aggregated internal SCOM status
+} MemDataSensorCache;
+
+typedef struct {
+    MemDataSensorCache scache;              // OCC Centaur Sensor Cache Line (128 bytes)
+} CentaurMemData;
+
+/// \defgroup gpe_mem_data_rc gpe_get_mem_data() Error Return Codes
+///
+/// The gpe_get_mem_data() procedure deposits a non-0 return code into the \a
+/// rc field of its parameter structure in the event of failure. Note that the
+/// procedure stops on the first failure, and in particular the TOD timestamp
+/// is not valid in the event of failure.
+///
+/// @{
+
+/// The global G_centaurConfiguration is not valid
+#define CENTAUR_GET_MEM_DATA_NOT_CONFIGURED 4
+
+/// The workaround for HW256773 failed.  To diagnose the failure look at the
+/// 'rc' field of the global variable G_hw256773.
+#define CENTAUR_GET_MEM_DATA_HW256773_FAILED 5
+
+/// This code is established in the RC field prior to collecting the Centaur
+/// sensor cache data. If this RC is observed on a hard failure it most likely
+/// indicates an error assiciated with the Centaur whose data was being
+/// collected.
+#define CENTAUR_GET_MEM_DATA_SENSOR_CACHE_FAILED 6
+
+/// This code is established in the RC field prior to "poking" the Centaur (if
+/// any) that is being updated this pass. If this RC is observed on a hard
+/// failure it most likely indicates an error associated with the Centaur
+/// being updated.
+#define CENTAUR_GET_MEM_DATA_UPDATE_FAILED 7
+
+#endif
diff --git a/src/include/gpe_pba_parms.h b/src/include/gpe_pba_parms.h
new file mode 100644
index 0000000..35cbb94
--- /dev/null
+++ b/src/include/gpe_pba_parms.h
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/common/pmlib/include/gpe_pba_parms.h $               */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2017                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#if !defined(__GPE_PBA_PARMS_H__)
+#define __GPE_PBA_PARMS_H__
+
+#include <stdint.h>
+#include "pba_register_addresses.h"
+#include "pba_firmware_registers.h"
+
+typedef struct
+{
+
+    /// The 32-bit OCI address of the PBA_SLVCTLn register to set up
+    uint32_t slvctl_address;
+
+    /// The slave id (0 - 3)
+    uint32_t slave_id;
+    /// An image of the relevant parts of the PBA_SLVCTLn register in effect
+    /// for this procedure
+    //pba_slvctln_t slvctl;
+    pba_slvctln_t slvctl;
+
+    /// The mask in effect for this update of the PBA_SLVCTL
+    //pba_slvctln_t mask;
+    pba_slvctln_t mask;
+
+    /// The value to write to the PBA_SLVRST register to reset the slave
+    //pba_slvrst_t slvrst;
+    pba_slvrst_t slvrst;
+
+    /// The bit to AND-poll to check for slave reset in progress
+    //pba_slvrst_t slvrst_in_progress;
+    pba_slvrst_t slvrst_in_progress;
+
+} GpePbaParms;
+
+#endif
diff --git a/src/include/registers/centaur_firmware_registers.h b/src/include/registers/centaur_firmware_registers.h
new file mode 100644
index 0000000..7ec99be
--- /dev/null
+++ b/src/include/registers/centaur_firmware_registers.h
@@ -0,0 +1,1589 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/common/pmlib/include/registers/centaur_firmware_registers.h $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2017                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __CENTAUR_FIRMWARE_REGISTERS_H__
+#define __CENTAUR_FIRMWARE_REGISTERS_H__
+
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+    #ifdef __ASSEMBLER__
+        #define SIXTYFOUR_BIT_CONSTANT(x) x
+    #else
+        #define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+    #endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union centaur_device_id
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t cfam_id : 32;
+        uint64_t module_id : 2;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t module_id : 2;
+        uint64_t cfam_id : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_device_id_t;
+
+
+
+typedef union centaur_mbs_fir_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_reg_t;
+
+
+
+typedef union centaur_mbs_fir_reg_and
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_reg_and_t;
+
+
+
+typedef union centaur_mbs_fir_reg_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_reg_or_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_mask_reg_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg_and
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_mask_reg_and_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg_or
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_mask_reg_or_t;
+
+
+
+typedef union centaur_mbs_fir_action0_reg
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_fir_action0_reg_t;
+
+
+
+typedef union centaur_mbs_firact1
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t host_protocol_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t external_timeout : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t lru_error : 1;
+        uint64_t edram_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t _reserved0 : 30;
+#else
+        uint64_t _reserved0 : 30;
+        uint64_t internal_scom_error_copy : 1;
+        uint64_t internal_scom_error : 1;
+        uint64_t spare_fir31 : 1;
+        uint64_t spare_fir30 : 1;
+        uint64_t dir_purge_ce : 1;
+        uint64_t srb_buffer_sue : 1;
+        uint64_t srb_buffer_ue : 1;
+        uint64_t srb_buffer_ce : 1;
+        uint64_t occ_inband_write_error : 1;
+        uint64_t occ_inband_read_error : 1;
+        uint64_t host_inband_write_error : 1;
+        uint64_t host_inband_read_error : 1;
+        uint64_t emergency_throttle_set : 1;
+        uint64_t edram_error : 1;
+        uint64_t lru_error : 1;
+        uint64_t dir_all_members_deleted : 1;
+        uint64_t dir_member_deleted : 1;
+        uint64_t dir_ue : 1;
+        uint64_t dir_ce : 1;
+        uint64_t cache_co_sue : 1;
+        uint64_t cache_co_ue : 1;
+        uint64_t cache_co_ce : 1;
+        uint64_t cache_srw_sue : 1;
+        uint64_t cache_srw_ue : 1;
+        uint64_t cache_srw_ce : 1;
+        uint64_t int_parity_error : 1;
+        uint64_t int_buffer_sue : 1;
+        uint64_t int_buffer_ue : 1;
+        uint64_t int_buffer_ce : 1;
+        uint64_t internal_timeout : 1;
+        uint64_t external_timeout : 1;
+        uint64_t invalid_address_error : 1;
+        uint64_t int_protocol_error : 1;
+        uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbs_firact1_t;
+
+
+
+typedef union centaur_mbscfgq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t eccbp_exit_sel : 1;
+        uint64_t dram_ecc_bypass_dis : 1;
+        uint64_t mbs_scom_wat_trigger : 1;
+        uint64_t mbs_prq_ref_avoidance_en : 1;
+        uint64_t reserved4_6 : 3;
+        uint64_t occ_deadman_timer_sel : 4;
+        uint64_t sync_fsync_mba_strobe_en : 1;
+        uint64_t hca_timebase_op_mode : 1;
+        uint64_t hca_local_timer_inc_select : 3;
+        uint64_t mbs_01_rdtag_delay : 4;
+        uint64_t mbs_01_rdtag_force_dead_cycle : 1;
+        uint64_t sync_lat_pol_01 : 1;
+        uint64_t sync_lat_adj_01 : 2;
+        uint64_t mbs_23_rdtag_delay : 4;
+        uint64_t mbs_23_rdtag_force_dead_cycle : 1;
+        uint64_t sync_lat_pol_23 : 1;
+        uint64_t sync_lat_adj_23 : 2;
+        uint64_t _reserved0 : 32;
+#else
+        uint64_t _reserved0 : 32;
+        uint64_t sync_lat_adj_23 : 2;
+        uint64_t sync_lat_pol_23 : 1;
+        uint64_t mbs_23_rdtag_force_dead_cycle : 1;
+        uint64_t mbs_23_rdtag_delay : 4;
+        uint64_t sync_lat_adj_01 : 2;
+        uint64_t sync_lat_pol_01 : 1;
+        uint64_t mbs_01_rdtag_force_dead_cycle : 1;
+        uint64_t mbs_01_rdtag_delay : 4;
+        uint64_t hca_local_timer_inc_select : 3;
+        uint64_t hca_timebase_op_mode : 1;
+        uint64_t sync_fsync_mba_strobe_en : 1;
+        uint64_t occ_deadman_timer_sel : 4;
+        uint64_t reserved4_6 : 3;
+        uint64_t mbs_prq_ref_avoidance_en : 1;
+        uint64_t mbs_scom_wat_trigger : 1;
+        uint64_t dram_ecc_bypass_dis : 1;
+        uint64_t eccbp_exit_sel : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbscfgq_t;
+
+
+
+typedef union centaur_mbsemerthroq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t emergency_throttle_ip : 1;
+        uint64_t _reserved0 : 63;
+#else
+        uint64_t _reserved0 : 63;
+        uint64_t emergency_throttle_ip : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbsemerthroq_t;
+
+
+
+typedef union centaur_mbsocc01hq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t occ_01_rd_hit : 32;
+        uint64_t occ_01_wr_hit : 32;
+#else
+        uint64_t occ_01_wr_hit : 32;
+        uint64_t occ_01_rd_hit : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbsocc01hq_t;
+
+
+
+typedef union centaur_mbsocc23hq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t occ_23_rd_hit : 32;
+        uint64_t occ_23_wr_hit : 32;
+#else
+        uint64_t occ_23_wr_hit : 32;
+        uint64_t occ_23_rd_hit : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbsocc23hq_t;
+
+
+
+typedef union centaur_mbsoccitcq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t occ_cent_idle_th_cnt : 32;
+        uint64_t _reserved0 : 32;
+#else
+        uint64_t _reserved0 : 32;
+        uint64_t occ_cent_idle_th_cnt : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbsoccitcq_t;
+
+
+
+typedef union centaur_mbsoccscanq
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t occ_01_spec_can : 32;
+        uint64_t occ_23_spec_can : 32;
+#else
+        uint64_t occ_23_spec_can : 32;
+        uint64_t occ_01_spec_can : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbsoccscanq_t;
+
+
+
+typedef union centaur_mbarpc0qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t cfg_lp2_entry_req : 1;
+        uint64_t cfg_lp2_state : 1;
+        uint64_t cfg_min_max_domains_enable : 1;
+        uint64_t cfg_min_max_domains : 3;
+        uint64_t cfg_pup_avail : 5;
+        uint64_t cfg_pdn_pup : 5;
+        uint64_t cfg_pup_pdn : 5;
+        uint64_t reserved0 : 1;
+        uint64_t cfg_min_domain_reduction_enable : 1;
+        uint64_t cfg_min_domain_reduction_on_time : 10;
+        uint64_t cfg_pup_after_activate_wait_enable : 1;
+        uint64_t cfg_pup_after_activate_wait_time : 8;
+        uint64_t cfg_force_spare_pup : 1;
+        uint64_t _reserved0 : 21;
+#else
+        uint64_t _reserved0 : 21;
+        uint64_t cfg_force_spare_pup : 1;
+        uint64_t cfg_pup_after_activate_wait_time : 8;
+        uint64_t cfg_pup_after_activate_wait_enable : 1;
+        uint64_t cfg_min_domain_reduction_on_time : 10;
+        uint64_t cfg_min_domain_reduction_enable : 1;
+        uint64_t reserved0 : 1;
+        uint64_t cfg_pup_pdn : 5;
+        uint64_t cfg_pdn_pup : 5;
+        uint64_t cfg_pup_avail : 5;
+        uint64_t cfg_min_max_domains : 3;
+        uint64_t cfg_min_max_domains_enable : 1;
+        uint64_t cfg_lp2_state : 1;
+        uint64_t cfg_lp2_entry_req : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbarpc0qn_t;
+
+
+
+typedef union centaur_mba_farb3qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t cfg_nm_n_per_mba : 15;
+        uint64_t cfg_nm_n_per_chip : 16;
+        uint64_t cfg_nm_m : 14;
+        uint64_t cfg_nm_ras_weight : 3;
+        uint64_t cfg_nm_cas_weight : 3;
+        uint64_t cfg_nm_per_slot_enabled : 1;
+        uint64_t cfg_nm_count_other_mba_dis : 1;
+        uint64_t _reserved0 : 11;
+#else
+        uint64_t _reserved0 : 11;
+        uint64_t cfg_nm_count_other_mba_dis : 1;
+        uint64_t cfg_nm_per_slot_enabled : 1;
+        uint64_t cfg_nm_cas_weight : 3;
+        uint64_t cfg_nm_ras_weight : 3;
+        uint64_t cfg_nm_m : 14;
+        uint64_t cfg_nm_n_per_chip : 16;
+        uint64_t cfg_nm_n_per_mba : 15;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mba_farb3qn_t;
+
+
+
+typedef union centaur_mbapcn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t mode_hp_sub_cnt : 1;
+        uint64_t mode_lp_sub_cnt : 1;
+        uint64_t mode_static_idle_dly : 5;
+        uint64_t mode_emer_min_max_domain : 3;
+        uint64_t mode_pup_all_wr_pending : 2;
+        uint64_t mode_lp_ref_sim_enq : 1;
+        uint64_t _reserved0 : 51;
+#else
+        uint64_t _reserved0 : 51;
+        uint64_t mode_lp_ref_sim_enq : 1;
+        uint64_t mode_pup_all_wr_pending : 2;
+        uint64_t mode_emer_min_max_domain : 3;
+        uint64_t mode_static_idle_dly : 5;
+        uint64_t mode_lp_sub_cnt : 1;
+        uint64_t mode_hp_sub_cnt : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbapcn_t;
+
+
+
+typedef union centaur_mbasrqn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t emergency_m : 14;
+        uint64_t emergency_n : 15;
+        uint64_t _reserved0 : 35;
+#else
+        uint64_t _reserved0 : 35;
+        uint64_t emergency_n : 15;
+        uint64_t emergency_m : 14;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_mbasrqn_t;
+
+
+
+typedef union centaur_pmu0qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t read_count : 32;
+        uint64_t write_count : 32;
+#else
+        uint64_t write_count : 32;
+        uint64_t read_count : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu0qn_t;
+
+
+
+typedef union centaur_pmu1qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t activate_count : 32;
+        uint64_t pu_counts : 32;
+#else
+        uint64_t pu_counts : 32;
+        uint64_t activate_count : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu1qn_t;
+
+
+
+typedef union centaur_pmu2qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t frame_count : 32;
+        uint64_t _reserved0 : 32;
+#else
+        uint64_t _reserved0 : 32;
+        uint64_t frame_count : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu2qn_t;
+
+
+
+typedef union centaur_pmu3qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t low_idle_threshold : 16;
+        uint64_t med_idle_threshold : 16;
+        uint64_t high_idle_threshold : 32;
+#else
+        uint64_t high_idle_threshold : 32;
+        uint64_t med_idle_threshold : 16;
+        uint64_t low_idle_threshold : 16;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu3qn_t;
+
+
+
+typedef union centaur_pmu4qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t base_idle_count : 32;
+        uint64_t low_idle_count : 32;
+#else
+        uint64_t low_idle_count : 32;
+        uint64_t base_idle_count : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu4qn_t;
+
+
+
+typedef union centaur_pmu5qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t med_idle_count : 32;
+        uint64_t high_idle_count : 32;
+#else
+        uint64_t high_idle_count : 32;
+        uint64_t med_idle_count : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu5qn_t;
+
+
+
+typedef union centaur_pmu6qn
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t total_gap_counts : 18;
+        uint64_t specific_gap_counts : 18;
+        uint64_t gap_length_adder : 3;
+        uint64_t specific_gap_condition : 4;
+        uint64_t cmd_to_cmd_count : 18;
+        uint64_t command_pattern_to_count : 3;
+#else
+        uint64_t command_pattern_to_count : 3;
+        uint64_t cmd_to_cmd_count : 18;
+        uint64_t specific_gap_condition : 4;
+        uint64_t gap_length_adder : 3;
+        uint64_t specific_gap_counts : 18;
+        uint64_t total_gap_counts : 18;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_pmu6qn_t;
+
+
+
+typedef union centaur_sensor_cache_data0_3
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t crittrip0 : 1;
+        uint64_t abovetrip0 : 1;
+        uint64_t belowtrip0 : 1;
+        uint64_t signbit0 : 1;
+        uint64_t temperature0 : 8;
+        uint64_t temp_frac0 : 2;
+        uint64_t status0 : 2;
+        uint64_t crittrip1 : 1;
+        uint64_t abovetrip1 : 1;
+        uint64_t belowtrip1 : 1;
+        uint64_t signbit1 : 1;
+        uint64_t temperature1 : 8;
+        uint64_t temp_frac1 : 2;
+        uint64_t status1 : 2;
+        uint64_t crittrip2 : 1;
+        uint64_t abovetrip2 : 1;
+        uint64_t belowtrip2 : 1;
+        uint64_t signbit2 : 1;
+        uint64_t temperature2 : 8;
+        uint64_t temp_frac2 : 2;
+        uint64_t status2 : 2;
+        uint64_t crittrip3 : 1;
+        uint64_t abovetrip3 : 1;
+        uint64_t belowtrip3 : 1;
+        uint64_t signbit3 : 1;
+        uint64_t temperature3 : 8;
+        uint64_t temp_frac3 : 2;
+        uint64_t status3 : 2;
+#else
+        uint64_t status3 : 2;
+        uint64_t temp_frac3 : 2;
+        uint64_t temperature3 : 8;
+        uint64_t signbit3 : 1;
+        uint64_t belowtrip3 : 1;
+        uint64_t abovetrip3 : 1;
+        uint64_t crittrip3 : 1;
+        uint64_t status2 : 2;
+        uint64_t temp_frac2 : 2;
+        uint64_t temperature2 : 8;
+        uint64_t signbit2 : 1;
+        uint64_t belowtrip2 : 1;
+        uint64_t abovetrip2 : 1;
+        uint64_t crittrip2 : 1;
+        uint64_t status1 : 2;
+        uint64_t temp_frac1 : 2;
+        uint64_t temperature1 : 8;
+        uint64_t signbit1 : 1;
+        uint64_t belowtrip1 : 1;
+        uint64_t abovetrip1 : 1;
+        uint64_t crittrip1 : 1;
+        uint64_t status0 : 2;
+        uint64_t temp_frac0 : 2;
+        uint64_t temperature0 : 8;
+        uint64_t signbit0 : 1;
+        uint64_t belowtrip0 : 1;
+        uint64_t abovetrip0 : 1;
+        uint64_t crittrip0 : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_sensor_cache_data0_3_t;
+
+
+
+typedef union centaur_sensor_cache_data4_7
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t crittrip4 : 1;
+        uint64_t abovetrip4 : 1;
+        uint64_t belowtrip4 : 1;
+        uint64_t signbit4 : 1;
+        uint64_t temperature4 : 8;
+        uint64_t temp_frac4 : 2;
+        uint64_t status4 : 2;
+        uint64_t crittrip5 : 1;
+        uint64_t abovetrip5 : 1;
+        uint64_t belowtrip5 : 1;
+        uint64_t signbit5 : 1;
+        uint64_t temperature5 : 8;
+        uint64_t temp_frac5 : 2;
+        uint64_t status5 : 2;
+        uint64_t crittrip6 : 1;
+        uint64_t abovetrip6 : 1;
+        uint64_t belowtrip6 : 1;
+        uint64_t signbit6 : 1;
+        uint64_t temperature6 : 8;
+        uint64_t temp_frac6 : 2;
+        uint64_t status6 : 2;
+        uint64_t crittrip7 : 1;
+        uint64_t abovetrip7 : 1;
+        uint64_t belowtrip7 : 1;
+        uint64_t signbit7 : 1;
+        uint64_t temperature7 : 8;
+        uint64_t temp_frac7 : 2;
+        uint64_t status7 : 2;
+#else
+        uint64_t status7 : 2;
+        uint64_t temp_frac7 : 2;
+        uint64_t temperature7 : 8;
+        uint64_t signbit7 : 1;
+        uint64_t belowtrip7 : 1;
+        uint64_t abovetrip7 : 1;
+        uint64_t crittrip7 : 1;
+        uint64_t status6 : 2;
+        uint64_t temp_frac6 : 2;
+        uint64_t temperature6 : 8;
+        uint64_t signbit6 : 1;
+        uint64_t belowtrip6 : 1;
+        uint64_t abovetrip6 : 1;
+        uint64_t crittrip6 : 1;
+        uint64_t status5 : 2;
+        uint64_t temp_frac5 : 2;
+        uint64_t temperature5 : 8;
+        uint64_t signbit5 : 1;
+        uint64_t belowtrip5 : 1;
+        uint64_t abovetrip5 : 1;
+        uint64_t crittrip5 : 1;
+        uint64_t status4 : 2;
+        uint64_t temp_frac4 : 2;
+        uint64_t temperature4 : 8;
+        uint64_t signbit4 : 1;
+        uint64_t belowtrip4 : 1;
+        uint64_t abovetrip4 : 1;
+        uint64_t crittrip4 : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_sensor_cache_data4_7_t;
+
+
+
+typedef union centaur_dts_thermal_sensor_results
+{
+
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t dts0 : 12;
+        uint64_t thermal_trip0 : 2;
+        uint64_t spare0 : 1;
+        uint64_t valid0 : 1;
+        uint64_t dts1 : 12;
+        uint64_t thermal_trip1 : 2;
+        uint64_t spare1 : 1;
+        uint64_t valid1 : 1;
+        uint64_t _reserved0 : 32;
+#else
+        uint64_t _reserved0 : 32;
+        uint64_t valid1 : 1;
+        uint64_t spare1 : 1;
+        uint64_t thermal_trip1 : 2;
+        uint64_t dts1 : 12;
+        uint64_t valid0 : 1;
+        uint64_t spare0 : 1;
+        uint64_t thermal_trip0 : 2;
+        uint64_t dts0 : 12;
+#endif // _BIG_ENDIAN
+    } fields;
+} centaur_dts_thermal_sensor_results_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __CENTAUR_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/centaur_register_addresses.h b/src/include/registers/centaur_register_addresses.h
new file mode 100644
index 0000000..56dd415
--- /dev/null
+++ b/src/include/registers/centaur_register_addresses.h
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/common/pmlib/include/registers/centaur_register_addresses.h $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2017                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __CENTAUR_REGISTER_ADDRESSES_H__
+#define __CENTAUR_REGISTER_ADDRESSES_H__
+
+
+/// \file centaur_register_addresses.h
+/// \brief Symbolic addresses for the CENTAUR unit
+//
+//See MC chiplet
+//MBA_FARBnQ where (0 <= n <= 8) 0x7010913
+
+#define CENTAUR_PIB_BASE 0
+#define CENTAUR_DEVICE_ID 0x000f000f
+#define CENTAUR_MBS_FIR_REG 0x02011400
+#define CENTAUR_MBS_FIR_REG_AND 0x02011401
+#define CENTAUR_MBS_FIR_REG_OR 0x02011402
+#define CENTAUR_MBS_FIR_MASK_REG 0x02011403
+#define CENTAUR_MBS_FIR_MASK_REG_AND 0x02011404
+#define CENTAUR_MBS_FIR_MASK_REG_OR 0x02011405
+#define CENTAUR_MBS_FIR_ACTION0_REG 0x02011406
+#define CENTAUR_MBS_FIRACT1 0x02011407
+#define CENTAUR_MBSCFGQ 0x02011411
+#define CENTAUR_MBSEMERTHROQ 0x0201142d
+#define CENTAUR_MBSOCC01HQ 0x02011429
+#define CENTAUR_MBSOCC23HQ 0x0201142a
+#define CENTAUR_MBSOCCITCQ 0x02011428
+#define CENTAUR_MBSOCCSCANQ 0x0201142b
+#define CENTAUR_MBARPC0QN(n) (CENTAUR_MBARPC0Q0 + ((CENTAUR_MBARPC0Q1 - CENTAUR_MBARPC0Q0) * (n)))
+#define CENTAUR_MBARPC0Q0 0x03010434
+#define CENTAUR_MBARPC0Q1 0x03010c34
+#define CENTAUR_MBA_FARB3QN(n) (CENTAUR_MBA_FARB3Q0 + ((CENTAUR_MBA_FARB3Q1 - CENTAUR_MBA_FARB3Q0) * (n)))
+#define CENTAUR_MBA_FARB3Q0 0x03010416
+#define CENTAUR_MBA_FARB3Q1 0x03010c16
+#define CENTAUR_PMU0QN(n) (CENTAUR_PMU0Q0 + ((CENTAUR_PMU0Q1 - CENTAUR_PMU0Q0) * (n)))
+#define CENTAUR_PMU0Q0 0x03010437
+#define CENTAUR_PMU0Q1 0x03010c37
+#define CENTAUR_PMU1QN(n) (CENTAUR_PMU1Q0 + ((CENTAUR_PMU1Q1 - CENTAUR_PMU1Q0) * (n)))
+#define CENTAUR_PMU1Q0 0x03010438
+#define CENTAUR_PMU1Q1 0x03010c38
+#define CENTAUR_PMU2QN(n) (CENTAUR_PMU2Q0 + ((CENTAUR_PMU2Q1 - CENTAUR_PMU2Q0) * (n)))
+#define CENTAUR_PMU2Q0 0x03010439
+#define CENTAUR_PMU2Q1 0x03010c39
+#define CENTAUR_PMU3QN(n) (CENTAUR_PMU3Q0 + ((CENTAUR_PMU3Q1 - CENTAUR_PMU3Q0) * (n)))
+#define CENTAUR_PMU3Q0 0x0301043a
+#define CENTAUR_PMU3Q1 0x03010c3a
+#define CENTAUR_PMU4QN(n) (CENTAUR_PMU4Q0 + ((CENTAUR_PMU4Q1 - CENTAUR_PMU4Q0) * (n)))
+#define CENTAUR_PMU4Q0 0x0301043b
+#define CENTAUR_PMU4Q1 0x03010c3b
+#define CENTAUR_PMU5QN(n) (CENTAUR_PMU5Q0 + ((CENTAUR_PMU5Q1 - CENTAUR_PMU5Q0) * (n)))
+#define CENTAUR_PMU5Q0 0x0301043c
+#define CENTAUR_PMU5Q1 0x03010c3c
+#define CENTAUR_PMU6QN(n) (CENTAUR_PMU6Q0 + ((CENTAUR_PMU6Q1 - CENTAUR_PMU6Q0) * (n)))
+#define CENTAUR_PMU6Q0 0x0301043d
+#define CENTAUR_PMU6Q1 0x03010c3d
+#define CENTAUR_SENSOR_CACHE_DATA0_3 0x020115ca
+#define CENTAUR_SENSOR_CACHE_DATA4_7 0x020115cb
+#define CENTAUR_DTS_THERMAL_SENSOR_RESULTS 0x02050000
+
+#endif // __CENTAUR_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/mcs_firmware_registers.h b/src/include/registers/mcs_firmware_registers.h
new file mode 100644
index 0000000..6071755
--- /dev/null
+++ b/src/include/registers/mcs_firmware_registers.h
@@ -0,0 +1,102 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/common/pmlib/include/registers/mcs_firmware_registers.h $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2017                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#if !defined(__MCS_FIRWARE_REGISTERS_H__)
+#define __MCS_FIRWARE_REGISTERS_H__
+
+typedef union mcfgpr
+{
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t mcfgprq_valid : 1;
+        uint64_t reserved0 : 2;
+        uint64_t disable_extended_bar : 1 ; // low = P9 mode
+        uint64_t mcfgprq_base_address : 31;
+        uint64_t _reserved0 : 29;
+#else
+        uint64_t _reserved0 : 29;
+        uint64_t mcfgprq_base_address : 31;
+        uint64_t disable_extended_bar : 1 ; // low = p9 mode
+        uint64_t reserved0 : 2;
+        uint64_t mcfgprq_valid : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} mcfgpr_t;
+
+
+typedef union mcsmode0
+{
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t reserved0 : 64;
+#else
+        uint64_t reserved0 : 64;
+#endif
+    } fields;
+} mcsmode0_t;
+
+
+
+typedef union mcifir
+{
+    uint64_t value;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct
+    {
+#ifdef _BIG_ENDIAN
+        uint64_t reserved0 : 64;
+#else
+        uint64_t reserved0 : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} mcifir_t;
+
+#endif
diff --git a/src/include/registers/p9_misc_scom_addresses.h b/src/include/registers/p9_misc_scom_addresses.h
index 480bff4..1f2dd81 100644
--- a/src/include/registers/p9_misc_scom_addresses.h
+++ b/src/include/registers/p9_misc_scom_addresses.h
@@ -7,4 +7,32 @@
 #define PU_GPIO_OUTPUT_CLR  0x000B0053
 #define PU_GPIO_OUTPUT_EN   0x000B0054
 
+
+// Found in Cumulus nest "MC Fault Isolation Register"
+#define MCS_0_MCFIR         0x05010800
+#define MCS_1_MCFIR         0x05010880
+#define MCS_2_MCFIR         0x03010800
+#define MCS_3_MCFIR         0x03010880
+
+// found in Cumulus nest "MC Mode0 Register"
+#define MCS_0_MCMODE0       0x05010811
+#define MCS_1_MCMODE0       0x05010891
+#define MCS_2_MCMODE0       0x03010811
+#define MCS_3_MCMODE0       0x03010891
+
+// found in Cumulus nest "MC Primary Memory Configuration Register"
+#define    MCS_0_MCRSVDE    0x0501080E
+#define    MCS_0_MCRSVDF    0x0501080F
+#define    MCS_1_MCRSVDE    0x0501088E
+#define    MCS_1_MCRSVDF    0x0501088F
+#define    MCS_2_MCRSVDE    0x0301080E
+#define    MCS_2_MCRSVDF    0x0301080F
+#define    MCS_3_MCRSVDE    0x0301088E
+#define    MCS_3_MCRSVDF    0x0301088F
+
+// MC Primary Memory Configuration Register (MCFGP)
+#define    MCS_0_MCFGP      0x0501080A
+#define    MCS_1_MCFGP      0x0501088A
+#define    MCS_2_MCFGP      0x0301080A
+#define    MCS_3_MCFGP      0x0301088A
 #endif
diff --git a/src/include/registers/pba_firmware_constants.h b/src/include/registers/pba_firmware_constants.h
index 0fa6e19..2b462c2 100644
--- a/src/include/registers/pba_firmware_constants.h
+++ b/src/include/registers/pba_firmware_constants.h
@@ -24,7 +24,7 @@
 /* IBM_PROLOG_END_TAG                                                     */
 
 #define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
-#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
+#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x00fffffffff00000)
 #define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
 #define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
 #define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
diff --git a/src/include/registers/pba_register_addresses.h b/src/include/registers/pba_register_addresses.h
index 10db791..7b00385 100644
--- a/src/include/registers/pba_register_addresses.h
+++ b/src/include/registers/pba_register_addresses.h
@@ -31,7 +31,7 @@
 
 // *** WARNING *** - This file is generated automatically, do not edit.
 
-
+// OCI addresses
 #define PBA_OCI_BASE 0xC0040000
 #define PBA_MODE 0xc0040000
 #define PBA_SLVRST 0xc0040008
@@ -44,11 +44,13 @@
 #define PBA_BCDE_SET 0xc0040088
 #define PBA_BCDE_STAT 0xc0040090
 #define PBA_BCDE_PBADR 0xc0040098
+#define PBA_BCDE_DR    0xc0040098
 #define PBA_BCDE_OCIBAR 0xc00400a0
 #define PBA_BCUE_CTL 0xc00400a8
 #define PBA_BCUE_SET 0xc00400b0
 #define PBA_BCUE_STAT 0xc00400b8
 #define PBA_BCUE_PBADR 0xc00400c0
+#define PBA_BCUE_DR    0xc00400c0
 #define PBA_BCUE_OCIBAR 0xc00400c8
 #define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n)))
 #define PBA_PBOCR0 0xc00400d0
@@ -71,41 +73,42 @@
 #define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n)))
 #define PBA_XSHINC0 0xc0040140
 #define PBA_XSHINC1 0xc0040160
-#define PBA_PIB_BASE 0x68000
-#define PBA_FIR 0x00068000
-#define PBA_FIR_AND 0x00068001
-#define PBA_FIR_OR 0x00068002
-#define PBA_FIRMASK 0x00068003
-#define PBA_FIRMASK_AND 0x00068004
-#define PBA_FIRMASK_OR 0x00068005
-#define PBA_FIRACT0 0x00068006
-#define PBA_FIRACT1 0x00068007
-#define PBA_OCCACT 0x0006800a
-#define PBA_CFG 0x0006800b
-#define PBA_ERRRPT0 0x0006800c
-#define PBA_ERRRPT1 0x0006800d
-#define PBA_ERRRPT2 0x0006800e
+// The following are SCOM addresses, not OCI addresses
+#define PBA_PIB_BASE 0x05012840
+#define PBA_FIR 0x05012840
+#define PBA_FIR_AND 0x05012841
+#define PBA_FIR_OR 0x05012842
+#define PBA_FIRMASK 0x05012843
+#define PBA_FIRMASK_AND 0x05012844
+#define PBA_FIRMASK_OR 0x05012845
+#define PBA_FIRACT0 0x05012846
+#define PBA_FIRACT1 0x05012847
+#define PBA_OCCACT 0x0501284a
+#define PBA_CFG 0x0501284b
+#define PBA_ERRRPT0 0x0501284c
+#define PBA_ERRRPT1 0x0501284d
+#define PBA_ERRRPT2 0x0501284e
 #define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
-#define PBA_RBUFVAL0 0x00068010
-#define PBA_RBUFVAL1 0x00068011
-#define PBA_RBUFVAL2 0x00068012
-#define PBA_RBUFVAL3 0x00068013
-#define PBA_RBUFVAL4 0x00068014
-#define PBA_RBUFVAL5 0x00068015
+#define PBA_RBUFVAL0 0x05012850
+#define PBA_RBUFVAL1 0x05012851
+#define PBA_RBUFVAL2 0x05012852
+#define PBA_RBUFVAL3 0x05012853
+#define PBA_RBUFVAL4 0x05012854
+#define PBA_RBUFVAL5 0x05012855
 #define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
-#define PBA_WBUFVAL0 0x00068018
-#define PBA_WBUFVAL1 0x00068019
-#define PBA_TRUSTEDPIB_BASE 0x68020
+#define PBA_WBUFVAL0 0x05012858
+#define PBA_WBUFVAL1 0x05012859
+#define PBA_TRUSTEDPIB_BASE 0x05012B00
 #define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
-#define PBA_BAR0 0x00068020
-#define PBA_BAR1 0x00068021
-#define PBA_BAR2 0x00068022
-#define PBA_BAR3 0x00068023
+#define PBA_BAR0 0x05012b00
+#define PBA_BAR1 0x05012b01
+#define PBA_BAR2 0x05012b02
+#define PBA_BAR3 0x05012b03
 #define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
-#define PBA_BARMSK0 0x00068024
-#define PBA_BARMSK1 0x00068025
-#define PBA_BARMSK2 0x00068026
-#define PBA_BARMSK3 0x00068027
+#define PBA_BARMSK0 0x05012b04
+#define PBA_BARMSK1 0x05012b05
+#define PBA_BARMSK2 0x05012b06
+#define PBA_BARMSK3 0x05012b07
 
 #endif // __PBA_REGISTER_ADDRESSES_H__