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author | Douglas Gilbert <dgilbert@us.ibm.com> | 2018-04-30 09:36:52 -0500 |
---|---|---|
committer | Martha Broyles <mbroyles@us.ibm.com> | 2018-05-03 14:06:39 -0400 |
commit | ba4bad1ee5d645698c541067de1d69fa2fd4ca11 (patch) | |
tree | 83a366cbd4c39e1a739b8eea0ad7ebf0d9947b4d | |
parent | 8aa6ad0942ef15727db6ee5cbfee27972c1a2471 (diff) | |
download | talos-occ-ba4bad1ee5d645698c541067de1d69fa2fd4ca11.tar.gz talos-occ-ba4bad1ee5d645698c541067de1d69fa2fd4ca11.zip |
Fix reading EMPATH data from fused odd numbered cores
Change-Id: I1014ed6adf3fc7b22356f907532aa6f88259462c
CQ: FW678428
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58054
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
-rw-r--r-- | src/include/core_data.h | 8 | ||||
-rw-r--r-- | src/include/registers/cppm_firmware_registers.h | 8 | ||||
-rwxr-xr-x | src/occ_405/occbuildname.c | 2 | ||||
-rw-r--r-- | src/occ_gpe0/core_data.c | 31 |
4 files changed, 45 insertions, 4 deletions
diff --git a/src/include/core_data.h b/src/include/core_data.h index 1149000..138e126 100644 --- a/src/include/core_data.h +++ b/src/include/core_data.h @@ -39,6 +39,7 @@ #define TOD_VALUE_REG 0x00040020 #define STOP_STATE_HIST_OCC_REG 0x000F0112 +#define SELECT_ODD_CORE 0x100 #define CORE_RAW_CYCLES 0x200 #define CORE_RUN_CYCLES 0x208 #define CORE_WORKRATE_BUSY 0x210 @@ -88,6 +89,13 @@ #define WORKAROUND_SCOM_ADDRESS 0x10800 +typedef enum +{ + FUSED_UNKNOWN, + FUSED_FALSE, + FUSED_TRUE +} FusedCore; + typedef struct { uint32_t tod_2mhz; diff --git a/src/include/registers/cppm_firmware_registers.h b/src/include/registers/cppm_firmware_registers.h index 67078c9..9eeb54e 100644 --- a/src/include/registers/cppm_firmware_registers.h +++ b/src/include/registers/cppm_firmware_registers.h @@ -61,7 +61,9 @@ typedef union cppm_cpmmr { #ifdef _BIG_ENDIAN uint64_t ppm_write_disable : 1; uint64_t ppm_write_override : 1; - uint64_t reserved1 : 10; + uint64_t reserved0 : 7; + uint64_t fused_core_mode : 1; + uint64_t reserved1 : 2; uint64_t cme_err_notify_dis : 1; uint64_t wkup_notify_select : 1; uint64_t enable_pece : 1; @@ -73,7 +75,9 @@ typedef union cppm_cpmmr { uint64_t enable_pece : 1; uint64_t wkup_notify_select : 1; uint64_t cme_err_notify_dis : 1; - uint64_t reserved1 : 10; + uint64_t reserved1 : 2; + uint64_t fused_core_mode : 1; + uint64_t reserved0 : 7; uint64_t ppm_write_override : 1; uint64_t ppm_write_disable : 1; #endif // _BIG_ENDIAN diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c index d65d824..7917367 100755 --- a/src/occ_405/occbuildname.c +++ b/src/occ_405/occbuildname.c @@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = #else -volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_180425a\0" /*</BuildName>*/ ; +volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_180501a\0" /*</BuildName>*/ ; #endif diff --git a/src/occ_gpe0/core_data.c b/src/occ_gpe0/core_data.c index 7d52a75..343b5dd 100644 --- a/src/occ_gpe0/core_data.c +++ b/src/occ_gpe0/core_data.c @@ -32,6 +32,8 @@ #include "ppe42_msr.h" #include "ppe42_scom.h" #include "cme_register_addresses.h" +#include "cppm_register_addresses.h" +#include "cppm_firmware_registers.h" #include "pk.h" #define CME_VDSR_BASE (CME_SCOM_VDSR & 0x00ffffff) @@ -39,6 +41,7 @@ // Global variables uint32_t g_vdm_cache_large_droop_count[MAX_NUM_QUADS]__attribute__((section (".sbss"))); uint32_t g_vdm_core_small_droop_count[MAX_NUM_CORES]__attribute__((section (".sbss"))); +int g_fused_core = FUSED_UNKNOWN; uint32_t get_core_data(uint32_t i_core, CoreData* o_data) @@ -163,7 +166,33 @@ uint32_t get_core_data(uint32_t i_core, // Send command to select which emmpath counter to read do { - uint64_t empath_scom_data = CORE_RAW_CYCLES; + uint64_t empath_scom_data = CORE_RAW_CYCLES; + + if(FUSED_UNKNOWN == g_fused_core) + { + cppm_cpmmr_t cpmmr; + rc = getscom(coreSelect, CPPM_CPMMR, &(cpmmr.value)); + if (rc) + { + // Retry on next tick + break; + } + + if (1 == cpmmr.fields.fused_core_mode) + { + g_fused_core = FUSED_TRUE; + } + else + { + g_fused_core = FUSED_FALSE; + } + } + + if(g_fused_core == FUSED_TRUE && ((i_core % 2) != 0)) + { + empath_scom_data |= SELECT_ODD_CORE; + } + rc = putscom(coreSelect, PC_OCC_SPRC, empath_scom_data); if (rc) { |