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author | Andres Lugo-Reyes <aalugore@us.ibm.com> | 2018-06-05 10:23:25 -0500 |
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committer | Andres A. Lugo-Reyes <aalugore@us.ibm.com> | 2018-06-05 17:36:05 -0400 |
commit | e66f727bf40b9dbd00c0e9a527dbfe584c6eb8ba (patch) | |
tree | 1dad5e89cdb34834d0c824f00cc457f1952d9801 | |
parent | e03ec216c2a4af2283782c96b59f8f7e386dc2f9 (diff) | |
download | talos-occ-e66f727bf40b9dbd00c0e9a527dbfe584c6eb8ba.tar.gz talos-occ-e66f727bf40b9dbd00c0e9a527dbfe584c6eb8ba.zip |
Fix units in comments in OPPB to match ekb and actual units.
Change-Id: I327cfcf5ccccdf810960c0fd0cc9a691be46daad
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59959
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
-rw-r--r-- | src/include/p9_pstates_occ.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/include/p9_pstates_occ.h b/src/include/p9_pstates_occ.h index fb295e7..1ac9d6e 100644 --- a/src/include/p9_pstates_occ.h +++ b/src/include/p9_pstates_occ.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,7 +53,7 @@ extern "C" { #define OCC_PARMSBLOCK_MAGIC 0x4f43435050423030ull /* OCCPPB00 */ /// IDDQ Reading Type -/// Each entry is 2 bytes. The values are in 6.25mA units; this allow for a +/// Each entry is 2 bytes. The values are in 5mA units; this allow for a /// maximum value of 409.6A to be represented. /// typedef uint16_t iddq_entry_t; @@ -107,35 +107,35 @@ typedef struct /// Spare uint8_t spare[8]; - /// IVDD ALL Good Cores ON; 6.25mA units + /// IVDD ALL Good Cores ON; 5mA units iddq_entry_t ivdd_all_good_cores_on_caches_on[IDDQ_MEASUREMENTS]; - /// IVDD ALL Cores OFF; 6.25mA units + /// IVDD ALL Cores OFF; 5mA units iddq_entry_t ivdd_all_cores_off_caches_off[IDDQ_MEASUREMENTS]; - /// IVDD ALL Good Cores OFF; 6.25mA units + /// IVDD ALL Good Cores OFF; 5mA units iddq_entry_t ivdd_all_good_cores_off_good_caches_on[IDDQ_MEASUREMENTS]; - /// IVDD Quad 0 Good Cores ON, Caches ON; 6.25mA units + /// IVDD Quad 0 Good Cores ON, Caches ON; 5mA units iddq_entry_t ivdd_quad_good_cores_on_good_caches_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS]; - /// IVDDN 6.25mA units + /// IVDDN 5mA units iddq_entry_t ivdn[IDDQ_MEASUREMENTS]; - /// IVDD ALL Good Cores ON, Caches ON; 6.25mA units + /// IVDD ALL Good Cores ON, Caches ON; 0.5C units avgtemp_entry_t avgtemp_all_good_cores_on[IDDQ_MEASUREMENTS]; - /// avgtemp ALL Cores OFF, Caches OFF; 6.25mA units + /// avgtemp ALL Cores OFF, Caches OFF; 0.5C units avgtemp_entry_t avgtemp_all_cores_off_caches_off[IDDQ_MEASUREMENTS]; - /// avgtemp ALL Good Cores OFF, Caches ON; 6.25mA units + /// avgtemp ALL Good Cores OFF, Caches ON; 0.5C units avgtemp_entry_t avgtemp_all_good_cores_off[IDDQ_MEASUREMENTS]; - /// avgtemp Quad 0 Good Cores ON, Caches ON; 6.25mA units + /// avgtemp Quad 0 Good Cores ON, Caches ON; 0.5C units avgtemp_entry_t avgtemp_quad_good_cores_on[MAXIMUM_QUADS][IDDQ_MEASUREMENTS]; - /// avgtempN ; 6.25mA units + /// avgtempN ; 0.5C units avgtemp_entry_t avgtemp_vdn[IDDQ_MEASUREMENTS]; /// spare (per MVPD documentation |