Changes For P9 Enablement

Change-Id: I37e8174bcc6e99f602a66cff077ef41ad889b19c
RTC:165351
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34949
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

15 files changed, 102 insertions, 94 deletions

diff --git a/src/occBootLoader/bootInit.S b/src/occBootLoader/bootInit.S
index d7fe632..9b90143 100755
--- a/src/occBootLoader/bootInit.S
+++ b/src/occBootLoader/bootInit.S
@@ -5,8 +5,7 @@
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2017
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
@@ -47,9 +46,9 @@
 __boot_low_level_init:
 
 # enable machine check exception
-# initialize exception vector prefix to zero
+# initialize exception vector prefix to 0x80000000
 # enable machine check (19th bit)
-li      %r3, 0
+addis   %r3, 0, 0x8000
 mtevpr  %r3
 _liwa   %r4, MACHINE_CHECK_ENABLE
 mtmsr   %r4
diff --git a/src/occBootLoader/bootMain.c b/src/occBootLoader/bootMain.c
index 15d12fa..a50f5ea 100755
--- a/src/occBootLoader/bootMain.c
+++ b/src/occBootLoader/bootMain.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -61,7 +61,7 @@ IMAGE_HEADER(G_bootImageHdr,__boot_low_level_init,BOOT_LOADER_ID,
 // Function Prototypes
 //*************************************************************************
 //Forward declaration
-uint32_t boot_test_sram();
+uint32_t boot_test_sram(uint32_t i_start, uint32_t i_end);
 uint32_t boot_load_405(const imageHdr_t *i_hdrAddr);
 uint32_t boot_load_gpe0(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPtr);
 uint32_t boot_load_gpe1(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPtr);
@@ -93,15 +93,23 @@ void main()
 
 #ifndef VPO
     // This is ifdef'd out b/c it takes too long to run in VPO
-    // Test SRAM
-    l_rc = boot_test_sram();
-#endif
+
+    // Only test GPE0/GPE1/405 SRAM because SGPE and PGPE are
+    // loaded before us.
 
     // If failed to test SRAM, write failed return code to SPRG1 and halt
+    l_rc = boot_test_sram(SRAM_START_ADDRESS_GPE0, SRAM_END_ADDRESS_GPE1);
+    if(0 != l_rc)
+    {
+        WRITE_TO_SPRG1_AND_HALT(l_rc);
+    }
+
+    l_rc = boot_test_sram(SRAM_START_ADDRESS_405, SRAM_END_ADDRESS_405);
     if(0 != l_rc)
     {
         WRITE_TO_SPRG1_AND_HALT(l_rc);
     }
+#endif
 
     // set imageHdr_t pointer to point to boot image header to get to boot
     // image size. This way we can get to main application image header.
@@ -410,26 +418,26 @@ uint32_t boot_load_gpe1(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPt
 //
 // End Function Specification
 
-uint32_t boot_test_sram()
+uint32_t boot_test_sram(uint32_t i_start, uint32_t i_end)
 {
     uint32_t l_rc = 0;
 
     // Point start to SRAM start address
-    uint32_t *l_startPtr = (uint32_t *)SRAM_TEST_START_ADDRESS;
+    uint32_t *l_startPtr = (uint32_t *) i_start;
 
     // Copy bit pattern from start until SRAM end address
-    while((uint32_t)l_startPtr < SRAM_TEST_END_ADDRESS)
+    while((uint32_t)l_startPtr < i_end)
     {
         *l_startPtr = SRAM_TEST_BIT_PATTERN;
         l_startPtr++;
     }
 
     // Reset start pointer to point to SRAM start Address
-    l_startPtr = (uint32_t *)SRAM_TEST_START_ADDRESS;
+    l_startPtr = (uint32_t *) i_start;
 
     //Read and verify bit pattern that was written. If pattern does not match,
     // return address that failed to match the pattern.
-    while((uint32_t)l_startPtr < SRAM_TEST_END_ADDRESS)
+    while((uint32_t)l_startPtr < i_end)
     {
         if((*l_startPtr) != SRAM_TEST_BIT_PATTERN)
         {
diff --git a/src/occBootLoader/bootMain.h b/src/occBootLoader/bootMain.h
index f56aa8f..78862b2 100755
--- a/src/occBootLoader/bootMain.h
+++ b/src/occBootLoader/bootMain.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -45,7 +45,7 @@
 // Defines/Enums
 //*************************************************************************/
 #define MACHINE_CHECK_ENABLE        0x00001000
-#define DATA_CACHE_BLOCK_ENABLE     0x00008000
+#define DATA_CACHE_BLOCK_ENABLE     0x80000000
 #define DATA_CACHE_BLOCK_ADDR       0x00000000
 #define DATA_CACHE_SIZE             (16 * 1024)
 #define CACHE_LINE_SIZE             32
diff --git a/src/occ_405/amec/amec_sensors_fw.c b/src/occ_405/amec/amec_sensors_fw.c
index 07b3f5d..2854b8b 100644
--- a/src/occ_405/amec/amec_sensors_fw.c
+++ b/src/occ_405/amec/amec_sensors_fw.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -200,18 +200,20 @@ void amec_update_fw_sensors(void)
         }
         else if(L_consec_trace_count < MAX_CONSEC_TRACE)
         {
-            gpe_gpenxiramdbg_t xsr_sprg0;
-            gpe_gpenxiramedr_t ir_edr;
-            gpe_gpenxidbgpro_t iar_xsr;
+            gpe_gpenxiramdbg_t xsr_sprg0 = {0};
+            gpe_gpenxiramedr_t ir_edr = {0};
+            gpe_gpenxidbgpro_t iar_xsr = {0};
 
             // Reset will eventually be requested due to not having power measurement
             // data after X ticks, but add some additional FFDC to the trace that
             // will tell us what GPE job is currently executing.
             if(!l_gpe0_idle)
             {
-                xsr_sprg0.value  = in64(GPE_GPE0XIRAMDBG);
-                ir_edr.value     = in64(GPE_GPE0XIRAMEDR);
-                iar_xsr.value    = in64(GPE_GPE0XIDBGPRO);
+// TODO: Will need to figure out how to get this debug info. Currently causes a machine check
+//       when we try to read them.
+//                xsr_sprg0.value  = in64(GPE_GPE0XIRAMDBG);
+//                ir_edr.value     = in64(GPE_GPE0XIRAMEDR);
+//                iar_xsr.value    = in64(GPE_GPE0XIDBGPRO);
                 TRAC_ERR("GPE0 programs did not complete within one tick. "
                          "XSR[0x%08x]  IAR[0x%08x] IR[0x%08x] EDR[0x%08x]",
                          iar_xsr.fields.xsr, iar_xsr.fields.iar,
@@ -221,9 +223,11 @@ void amec_update_fw_sensors(void)
             }
             if(!l_gpe1_idle)
             {
-                xsr_sprg0.value  = in64(GPE_GPE1XIRAMDBG);
-                ir_edr.value     = in64(GPE_GPE1XIRAMEDR);
-                iar_xsr.value    = in64(GPE_GPE1XIDBGPRO);
+// TODO: Will need to figure out how to get this debug info. Currently causes a machine check
+//       when we try to read them.
+//                xsr_sprg0.value  = in64(GPE_GPE1XIRAMDBG);
+//                ir_edr.value     = in64(GPE_GPE1XIRAMEDR);
+//                iar_xsr.value    = in64(GPE_GPE1XIDBGPRO);
                 TRAC_ERR("GPE1 programs did not complete within one tick. "
                          "XSR[0x%08x]  IAR[0x%08x] IR[0x%08x] EDR[0x%08x]",
                          iar_xsr.fields.xsr, iar_xsr.fields.iar,
diff --git a/src/occ_405/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index de88369..44205a5 100644
--- a/src/occ_405/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -80,6 +80,7 @@ uint32_t dcom_build_slv_inbox(void)
     uint32_t l_slv_idx = 0;
 
     static uint8_t      L_seq = 0xFF;
+    static bool         L_traced = FALSE;
 
     L_seq++;
 
@@ -87,7 +88,15 @@ uint32_t dcom_build_slv_inbox(void)
     // interrupt context.
     if(G_pbax_rc)
     {
-        TRAC_INFO("PBAX Send Failure in transimitting multicast doorbell - RC[%08X], packet[%d]", G_pbax_rc, G_pbax_packet);
+        if (!L_traced)
+        {
+            TRAC_INFO("PBAX Send Failure in transimitting multicast doorbell - RC[%08X], packet[%d]", G_pbax_rc, G_pbax_packet);
+            L_traced = TRUE;
+        }
+    }
+    else
+    {
+        L_traced = FALSE;
     }
 
 
diff --git a/src/occ_405/dcom/dcomSlaveRx.c b/src/occ_405/dcom/dcomSlaveRx.c
index b4bbde8..bff8c09 100644
--- a/src/occ_405/dcom/dcomSlaveRx.c
+++ b/src/occ_405/dcom/dcomSlaveRx.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
diff --git a/src/occ_405/pss/apss.c b/src/occ_405/pss/apss.c
index e979477..76d813c 100755
--- a/src/occ_405/pss/apss.c
+++ b/src/occ_405/pss/apss.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -47,7 +47,7 @@ const apssGpioConfigStruct_t G_gpio_config[2] = { {0x00, 0xFF, 0x00}, {0x00, 0xF
 
 // G_apss_mode_config: system parms needed to select correct mode command options
 // Configure streaming of: APSS Mode, 16 ADCs, 2 GPIOs
-const apssModeConfigStruct_t G_apss_mode_config = { APSS_MODE_COMPOSITE, 16, 2 };
+const apssModeConfigStruct_t G_apss_mode_config = { APSS_MODE_AUTO2, 16, 2 };
 
 // Power Measurements (read from APSS every RealTime loop)
 apssPwrMeasStruct_t G_apss_pwr_meas = { {0} };
@@ -60,7 +60,7 @@ uint64_t G_gpe_apss_time_end;
 
 // Flag for requesting APSS recovery when OCC detects all zeroes or data out of sync
 bool G_apss_recovery_requested = FALSE;
-
+bool G_apss_data_traced = FALSE;
 GPE_BUFFER(apss_start_args_t    G_gpe_start_pwr_meas_read_args);
 GPE_BUFFER(apss_continue_args_t G_gpe_continue_pwr_meas_read_args);
 GPE_BUFFER(apss_complete_args_t G_gpe_complete_pwr_meas_read_args);
@@ -152,10 +152,13 @@ void do_apss_recovery(void)
     uint64_t        l_spi_adc_reset;
     uint64_t        l_spi_adc_wdata;
 
-
-    INTR_TRAC_ERR("detected invalid power data[%08x%08x]",
+    if (!G_apss_data_traced)
+    {
+        INTR_TRAC_ERR("detected invalid power data[%08x%08x]",
              (uint32_t)(G_gpe_continue_pwr_meas_read_args.meas_data[0] >> 32),
              (uint32_t)(G_gpe_continue_pwr_meas_read_args.meas_data[0] & 0x00000000ffffffffull));
+        G_apss_data_traced = TRUE;
+    }
 
     do
     {
@@ -344,7 +347,8 @@ void task_apss_start_pwr_meas(struct task *i_self)
         if(G_apss_recovery_requested)
         {
             // Do recovery then wait until next tick to do anything more.
-            do_apss_recovery();
+// TODO: RTC: 163275 Cannot SCOM from the 405. Move to GPE.
+//            do_apss_recovery();
             break;
         }
 
@@ -674,6 +678,10 @@ void reformat_meas_data()
             G_apss_recovery_requested = TRUE;
             break;
         }
+        else
+        {
+            G_apss_data_traced = FALSE;
+        }
 
         // Decrement up/down fail counter for backup on success.
         if(G_backup_fail_count)
diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h
index e6978c0..cf9c47a 100755
--- a/src/occ_405/ssx_app_cfg.h
+++ b/src/occ_405/ssx_app_cfg.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -153,6 +153,7 @@ do {                                                                \
 #endif
 
 // Default initializations for validation that affect SSX and library code
+#define PROCESSOR_EC_LEVEL
 
 #ifndef SIMICS_ENVIRONMENT
 #define SIMICS_ENVIRONMENT 0
diff --git a/src/occ_405/thread/threadSch.c b/src/occ_405/thread/threadSch.c
index b768935..025ff4c 100755
--- a/src/occ_405/thread/threadSch.c
+++ b/src/occ_405/thread/threadSch.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -142,7 +142,7 @@ void initThreadScheduler(void)
                  (void *)0,
                  (SsxAddress)dcomThreadStack,
                  THREAD_STACK_SIZE,
-                 THREAD_PRIORITY_6);
+                 THREAD_PRIORITY_4);
 
     // Create the thread scheduler timer
     l_timerRc = ssx_timer_create(&G_threadSchTimer, threadSwapcallback, 0);
diff --git a/src/occ_405/timer/timer.c b/src/occ_405/timer/timer.c
index 7893497..d314ae6 100755
--- a/src/occ_405/timer/timer.c
+++ b/src/occ_405/timer/timer.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -255,7 +255,10 @@ void task_poke_watchdogs(struct task * i_self)
         //@TODO: remove when PGPE code is integrated, RTC: 163934
         if(!G_simics_environment) // PGPE Beacon is not implemented in simics
         {
+// TODO: RTC: 163934 Enable this when PGPE beacon is enabled.
+#if 0
             check_pgpe_beacon();
+#endif
         }
     }
 
@@ -472,6 +475,7 @@ void check_pgpe_beacon(void)
     static bool     L_pgpe_beacon_unchanged_4ms = false; // pgpe beacon unchanged once (4ms)
     static bool     L_error_logged              = false; // trace and error log only once
     errlHndl_t      l_err                       = NULL;  // Error handler
+
     do
     {
         // return PGPE Beacon
@@ -503,7 +507,6 @@ void check_pgpe_beacon(void)
                 // Second time beacon unchanged (8ms), log timeout error
                 TRAC_ERR("Error PGPE Beacon didn't change for 8 ms: %d",
                          pgpe_beacon);
-
                 /*
                  * @errortype
                  * @moduleid    POKE_WD_TIMERS
diff --git a/src/occ_gpe0/apss_init.c b/src/occ_gpe0/apss_init.c
index 678dad3..702393a 100644
--- a/src/occ_gpe0/apss_init.c
+++ b/src/occ_gpe0/apss_init.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -183,30 +183,6 @@ void apss_init_gpio(ipc_msg_t* cmd, void* arg)
                 gpe_set_ffdc(&(args->error), SPIPSS_P2S_WDATA_REG, rc, regValue);
                 break;
             }
-            // Start SPI transaction
-            rc = apss_start_spi_command(args, 0);
-            if (rc)
-            {
-                PK_TRACE("apss_init_gpio: SPI command start failed. rc = 0x%08x", rc);
-                //FFDC already added.
-                break;
-            }
-
-            //--------------------
-            // Interrupt (APSS cmd 0x6xxx)
-            regValue = args->config0.interrupt;
-            regValue = regValue << 48;
-            regValue |= 0x6000000000000000;
-            regValue |= (port << 56);
-
-            rc = putscom_abs(SPIPSS_P2S_WDATA_REG, regValue);
-            if (rc)
-            {
-                PK_TRACE("apss_init_gpio: SPIPSS_P2S_WDATA_REG putscom failed. value:0x%X. rc = 0x%08x",
-                         regValue, rc);
-                gpe_set_ffdc(&(args->error), SPIPSS_P2S_WDATA_REG, rc, regValue);
-                break;
-            }
 
             // Start SPI transaction
             if (port == 0)
@@ -355,9 +331,6 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
             gpe_set_ffdc(&(args->error), SPIPSS_P2S_COMMAND_REG, rc, 0x8000000000000000);
         }
 
-        //Wait 20usec for apss becoming ready to send out the frame of composite mode
-        busy_wait(20);
-
     }while(0);
 
     // send back a response
diff --git a/src/occ_gpe0/apss_read.c b/src/occ_gpe0/apss_read.c
index 9ffd334..df33bfa 100644
--- a/src/occ_gpe0/apss_read.c
+++ b/src/occ_gpe0/apss_read.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
diff --git a/src/occ_gpe0/gpe0_main.c b/src/occ_gpe0/gpe0_main.c
index 5cb0174..da7640b 100644
--- a/src/occ_gpe0/gpe0_main.c
+++ b/src/occ_gpe0/gpe0_main.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -34,7 +34,7 @@
 #include "ipc_ping.h"
 #include "gpe_export.h"
 
-#define KERNEL_STACK_SIZE  256
+#define KERNEL_STACK_SIZE  512
 #define MAIN_THREAD_STACK_SIZE 512
 
 uint8_t        G_kernel_stack[KERNEL_STACK_SIZE];
diff --git a/src/occ_gpe1/gpe1_main.c b/src/occ_gpe1/gpe1_main.c
index e35720d..670dff0 100644
--- a/src/occ_gpe1/gpe1_main.c
+++ b/src/occ_gpe1/gpe1_main.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -33,7 +33,7 @@
 #include "ipc_api.h"
 #include "gpe_export.h"
 
-#define KERNEL_STACK_SIZE  256
+#define KERNEL_STACK_SIZE  512
 
 uint8_t        G_kernel_stack[KERNEL_STACK_SIZE];
 
diff --git a/src/tools/ffdcparser/ffdcparser.c b/src/tools/ffdcparser/ffdcparser.c
index 4c45936..e1bcb59 100644
--- a/src/tools/ffdcparser/ffdcparser.c
+++ b/src/tools/ffdcparser/ffdcparser.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -28,7 +28,7 @@
 // NOTE: This tool is to be used when FFDC is dumped by the OCC, and currently
 //       only accepts input files in binary format.
 
-typedef struct thread_dump
+typedef struct __attribute__((packed,aligned(4))) thread_dump
 {
     uint8_t     len;
     uint8_t     pri;
@@ -80,22 +80,22 @@ typedef struct __attribute__((packed,aligned(4))) ffdc
     uint32_t    dbsr;       // Debug Status Register
     uint32_t    ocb_oisr0;
     uint32_t    ocb_oisr1;
-    uint32_t    ocb_ouder0;
-    uint32_t    ocb_ouder1;
+    uint32_t    ocb_occmisc;
+    uint32_t    ocb_ohtmcr;
     uint32_t    ocb_oimr0;
     uint32_t    ocb_oimr1;
     uint32_t    ocb_oitr0;
     uint32_t    ocb_oitr1;
     uint32_t    ocb_oiepr0;
     uint32_t    ocb_oiepr1;
-    uint32_t    ocb_ocir0;
-    uint32_t    ocb_ocir1;
+    uint32_t    ocb_oehdr;
+    uint32_t    ocb_ocicfg;
     uint32_t    ocb_onisr0;
     uint32_t    ocb_onisr1;
     uint32_t    ocb_ocisr0;
     uint32_t    ocb_ocisr1;
-    uint32_t    ocb_her0;
-    uint32_t    ocb_her1;
+    uint32_t    ocb_occflg;
+    uint32_t    ocb_occhbr;
     uint32_t    ssx_timebase;
     char        buildname[16];
     uint64_t    occlfir;
@@ -224,7 +224,7 @@ void dump_ffdc(ffdc_t * data)
     printf("CR: 0x%08X\n", data->cr);
     printf("CTR: 0x%08X\n", data->ctr);
     for(i = 0; i < 32; i++)
-        printf("GPR%d: 0x%08X\n", i, data->gpr[i]);
+        printf("GPR%02d: 0x%08X\n", i, data->gpr[i]);
     printf("EVPR: 0x%08X\n", data->evpr);
     printf("XER: 0x%08X\n", data->xer);
     printf("ESR: 0x%08X\n", data->esr);
@@ -246,22 +246,22 @@ void dump_ffdc(ffdc_t * data)
     printf("DBSR: 0x%08X\n", data->dbsr);
     printf("OCB_OISR0: 0x%08X\n", data->ocb_oisr0);
     printf("OCB_OISR1: 0x%08X\n", data->ocb_oisr1);
-    printf("OCB_OUDER0: 0x%08X\n", data->ocb_ouder0);
-    printf("OCB_OUDER1: 0x%08X\n", data->ocb_ouder1);
+    printf("OCB_OCCMISC: 0x%08X\n", data->ocb_occmisc);
+    printf("OCB_OHTMCR: 0x%08X\n", data->ocb_ohtmcr);
     printf("OCB_OIMR0: 0x%08X\n", data->ocb_oimr0);
     printf("OCB_OIMR1: 0x%08X\n", data->ocb_oimr1);
     printf("OCB_OITR0: 0x%08X\n", data->ocb_oitr0);
     printf("OCB_OITR1: 0x%08X\n", data->ocb_oitr1);
     printf("OCB_OIEPR0: 0x%08X\n", data->ocb_oiepr0);
     printf("OCB_OIEPR1: 0x%08X\n", data->ocb_oiepr1);
-    printf("OCB_OCIR0: 0x%08X\n", data->ocb_ocir0);
-    printf("OCB_OCIR1: 0x%08X\n", data->ocb_ocir1);
+    printf("OCB_OEHDR: 0x%08X\n", data->ocb_oehdr);
+    printf("OCB_OCICFG: 0x%08X\n", data->ocb_ocicfg);
     printf("OCB_ONISR0: 0x%08X\n", data->ocb_onisr0);
     printf("OCB_ONISR1: 0x%08X\n", data->ocb_onisr1);
     printf("OCB_OCISR0: 0x%08X\n", data->ocb_ocisr0);
     printf("OCB_OCISR1: 0x%08X\n", data->ocb_ocisr1);
-    printf("OCB_HER0: 0x%08X\n", data->ocb_her0);
-    printf("OCB_HER1: 0x%08X\n", data->ocb_her1);
+    printf("OCB_OCCFLG: 0x%08X\n", data->ocb_occflg);
+    printf("OCB_OCCHBR: 0x%08X\n", data->ocb_occhbr);
     printf("SSX Timebase: 0x%08X\n", data->ssx_timebase);
     printf("OCC Buildname: %s\n", data->buildname);
     printf("OCC LFIR: 0x%016X\n", data->occlfir);
@@ -346,22 +346,22 @@ int main(int argc, char** argv)
     data.dbsr = get_uint32(ffdc_file);
     data.ocb_oisr0 = get_uint32(ffdc_file);
     data.ocb_oisr1 = get_uint32(ffdc_file);
-    data.ocb_ouder0 = get_uint32(ffdc_file);
-    data.ocb_ouder1 = get_uint32(ffdc_file);
+    data.ocb_occmisc = get_uint32(ffdc_file);
+    data.ocb_ohtmcr = get_uint32(ffdc_file);
     data.ocb_oimr0 = get_uint32(ffdc_file);
     data.ocb_oimr1 = get_uint32(ffdc_file);
     data.ocb_oitr0 = get_uint32(ffdc_file);
     data.ocb_oitr1 = get_uint32(ffdc_file);
     data.ocb_oiepr0 = get_uint32(ffdc_file);
     data.ocb_oiepr1 = get_uint32(ffdc_file);
-    data.ocb_ocir0 = get_uint32(ffdc_file);
-    data.ocb_ocir1 = get_uint32(ffdc_file);
+    data.ocb_oehdr = get_uint32(ffdc_file);
+    data.ocb_ocicfg = get_uint32(ffdc_file);
     data.ocb_onisr0 = get_uint32(ffdc_file);
     data.ocb_onisr1 = get_uint32(ffdc_file);
     data.ocb_ocisr0 = get_uint32(ffdc_file);
     data.ocb_ocisr1 = get_uint32(ffdc_file);
-    data.ocb_her0 = get_uint32(ffdc_file);
-    data.ocb_her1 = get_uint32(ffdc_file);
+    data.ocb_occflg = get_uint32(ffdc_file);
+    data.ocb_occhbr = get_uint32(ffdc_file);
     data.ssx_timebase = get_uint32(ffdc_file);
     fgets(data.buildname, 16, ffdc_file);
     fgetc(ffdc_file);
@@ -378,5 +378,8 @@ int main(int argc, char** argv)
     if(data.eye_catcher != 0xFFDCFFDC)
         printf("WARNING: Eye catcher(0x%08X) was not 0xFFDCFFDC\n", data.eye_catcher);
 
+    if(ffdc_file != NULL)
+        fclose(ffdc_file);
+
     return 0;
 }