P9a GPE support for up to 16 OCMBs

Change-Id: I627143674e883b5baec3a44e4884ac26f1b9aab5
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80212
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>

7 files changed, 102 insertions, 69 deletions

diff --git a/src/common/membuf_configuration.h b/src/common/membuf_configuration.h
index 576f6b4..57d7623 100644
--- a/src/common/membuf_configuration.h
+++ b/src/common/membuf_configuration.h
@@ -32,7 +32,10 @@
 #include "gpe_pba_parms.h"
 #include "centaur_firmware_registers.h"
 
-#define OCCHW_N_MEMBUF           8
+#define OCCHW_N_MEMBUF           16
+#define OCCHW_N_CENT              8
+#define OCCHW_N_MC_CHANNEL        8
+#define OCCHW_N_MC_PORT           4
 
 #define MEMTYPE_CENTAUR          1
 #define MEMTYPE_OCMB             2
@@ -71,7 +74,7 @@ typedef struct
     //  and module_id.
     //  (Not used on OCMB)
     ///
-    uint64_t deviceId[OCCHW_N_MEMBUF];
+    uint64_t deviceId[OCCHW_N_CENT];
 
     /// Designated sync scom address
     /// \note One and Only one of the MCS units can be targeted with SYNC
@@ -97,18 +100,16 @@ typedef struct
     /// A GpePbaParms parameter block for inband scom.
     GpePbaParms scomParms;
 
+    // Digital Thermal Sensor configuration bitmap.
+    // use CONFIG_UBDTS0(n) CONFIG_MEMDTS0(n) CONFIG_MEMDTS1(n) to set/test
+    uint64_t dts_config;
+
     /// A "chip configuration" bit mask denoting valid memory buffer.
     ///
     /// It shoud always be true that a bit denoting a configured memory buffer
     //  is associated with a non-0 \a baseAddress and vice-versa.
     uint32_t config;
 
-    // Digital Thermal Sensor configuration bitmap.
-    // use CONFIG_UBDTS0(n) CONFIG_MEMDTS0(n) CONFIG_MEMDTS1(n) to set/test
-    uint32_t dts_config;
-
-    uint32_t reserved;          // Keep structure size multiple of 8
-
     /// The final return code from gpe_*_configuration_create().
     /// @see MemBufConfigurationCreateRc
     /// If initialization fails then this value can be used to diagnose what
@@ -218,22 +219,26 @@ typedef enum
 #define PBA_SLAVE_MEMBUF 2
 
 // These are used to setup MemBufConfiguration.config field
-#define CHIP_CONFIG_MCS_BASE 16
+// [0:7] Mainstore Controller Channel is configured.
+// [16:31] Memory Buffer chip is configured.
+#define CHIP_CONFIG_MCS_BASE 0
 #define CHIP_CONFIG_MCS(n) \
     ((0x80000000ul >> CHIP_CONFIG_MCS_BASE) >> (n))
 
-#define CHIP_CONFIG_MEMBUF_BASE 24
+#define CHIP_CONFIG_MEMBUF_BASE 16
 #define CHIP_CONFIG_MEMBUF(n) \
     ((0x80000000ul >> CHIP_CONFIG_MEMBUF_BASE) >> (n))
 
+
+// These are used to setup the MemBufConfiguration.dts_config
 #define CONFIG_UBDTS0(n) \
-    (0x80000000ul >> (4*n))
+    (0x8000000000000000ull >> (4*n))
 
 #define CONFIG_MEMDTS0(n) \
-    (0x40000000ul >> (4*n))
+    (0x4000000000000000ull >> (4*n))
 
 #define CONFIG_MEMDTS1(n) \
-    (0x20000000ul >> (4*n))
+    (0x2000000000000000ull >> (4*n))
 
 #endif
 
diff --git a/src/occ_405/cent/ocmb_data.c b/src/occ_405/cent/ocmb_data.c
index 147d80e..fc3f8fa 100644
--- a/src/occ_405/cent/ocmb_data.c
+++ b/src/occ_405/cent/ocmb_data.c
@@ -57,39 +57,42 @@ void ocmb_init(void)
     {
         TRAC_INFO("ocmb_init: Initializing Memory Data Controller");
         // Create configuration data use G_membufConfiguration
+        G_membufConfiguration.config = 0;
+
+        for(membuf_idx = 0; membuf_idx<MAX_NUM_OCMBS; ++membuf_idx)
+        {
+            if(CENTAUR_PRESENT(membuf_idx)) //based on HTMGT config cmd
+            {
+                G_membufConfiguration.config |= CHIP_CONFIG_MEMBUF(membuf_idx);
+            }
+        }
+
         rc = membuf_configuration_create(&G_membufConfiguration);
         if( rc )
         {
             break;
         }
 
-        // Configure OCC_405 global membuf present and sensor enabled flags
-        G_present_centaurs = 0;
         for(membuf_idx=0; membuf_idx<MAX_NUM_OCMBS; ++membuf_idx)
         {
-            // Check if this membuf is even possible to be present
-            if( CENTAUR_BY_MASK(membuf_idx) )
+            if( G_membufConfiguration.baseAddress[membuf_idx] )
             {
-                if( G_membufConfiguration.baseAddress[membuf_idx] )
+                // A valid inband Bar Address was found, check which DTS are
+                // enabled.
+                if(G_membufConfiguration.dts_config & CONFIG_MEMDTS0(membuf_idx))
+                {
+                    G_dimm_enabled_sensors.bytes[membuf_idx] = DIMM_SENSOR0;
+                }
+                if(G_membufConfiguration.dts_config & CONFIG_MEMDTS1(membuf_idx))
                 {
-                    // A valid inband Bar Address was found
-                    G_present_centaurs |= (CENTAUR0_PRESENT_MASK >> membuf_idx);
-
-                    if(G_membufConfiguration.dts_config & CONFIG_MEMDTS0(membuf_idx))
-                    {
-                        G_dimm_enabled_sensors.bytes[membuf_idx] = DIMM_SENSOR0;
-                    }
-                    if(G_membufConfiguration.dts_config & CONFIG_MEMDTS1(membuf_idx))
-                    {
-                        G_dimm_enabled_sensors.bytes[membuf_idx] = (DIMM_SENSOR0 >> 1);
-                    }
-                    TRAC_INFO("ocmb_init: Membuf[%d] Found.",
-                              membuf_idx);
+                    G_dimm_enabled_sensors.bytes[membuf_idx] = (DIMM_SENSOR0 >> 1);
                 }
+                TRAC_INFO("ocmb_init: Membuf[%d] Found.",
+                          membuf_idx);
             }
         }
 
-        TRAC_IMP("ocmb_init: G_present_centaurs = 0x%08x", G_present_centaurs);
+        TRAC_IMP("ocmb_init: G_present_OCMBs = 0x%08x", G_present_centaurs);
 
         G_dimm_present_sensors = G_dimm_enabled_sensors;
 
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
index d81b91f..0ca1e04 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
@@ -2383,6 +2383,13 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
                             // Store the temperature sensor ID
                             g_amec->proc[0].memctl[l_membuf_num].centaur.temp_sid = l_data_set->temp_sensor_id;
 
+                            if (G_sysConfigData.mem_type == MEM_TYPE_OCM)
+                            {
+                                // Both OCMB and Centaur code use this global to idicate which MBs
+                                // are present, but Centaur sets this up later in centaur_init()
+                                G_present_centaurs |= (CENTAUR0_PRESENT_MASK >> l_membuf_num);
+                            }
+
                             l_num_mem_bufs++;
                         }
                         else // individual DIMM
diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c
index 3d3f3eb..54dcc23 100755
--- a/src/occ_405/occbuildname.c
+++ b/src/occ_405/occbuildname.c
@@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) =
 
 #else
 
-volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/  "op_occ_190723a\0"  /*</BuildName>*/ ;
+volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/  "op_occ_190723b\0"  /*</BuildName>*/ ;
 
 #endif
diff --git a/src/occ_gpe1/gpe_centaur.c b/src/occ_gpe1/gpe_centaur.c
index 09f3dbd..c54af3a 100644
--- a/src/occ_gpe1/gpe_centaur.c
+++ b/src/occ_gpe1/gpe_centaur.c
@@ -41,7 +41,7 @@
 #define PBA_HOST_OCC_CFG 0x0000000002000000ull;
 
 
-const uint32_t MCFGPR[OCCHW_N_MEMBUF] =
+const uint32_t MCFGPR[OCCHW_N_MC_CHANNEL] =
 {
     MCS_0_MCRSVDE,
     MCS_0_MCRSVDF,
@@ -53,7 +53,7 @@ const uint32_t MCFGPR[OCCHW_N_MEMBUF] =
     MCS_3_MCRSVDF
 };
 
-const uint32_t MCSYNC[OCCHW_N_MEMBUF/2] =
+const uint32_t MCSYNC[OCCHW_N_MC_PORT] =
 {
     MCS_0_MCSYNC,
     MCS_1_MCSYNC,
@@ -61,7 +61,7 @@ const uint32_t MCSYNC[OCCHW_N_MEMBUF/2] =
     MCS_3_MCSYNC
 };
 
-const uint32_t MCCHIFIR[OCCHW_N_MEMBUF] =
+const uint32_t MCCHIFIR[OCCHW_N_MC_CHANNEL] =
 {
     MCP_CHAN0_CHI_FIR,
     MCP_CHAN1_CHI_FIR,
@@ -73,7 +73,7 @@ const uint32_t MCCHIFIR[OCCHW_N_MEMBUF] =
     MCP_CHAN7_CHI_FIR
 };
 
-const uint32_t MCMCICFG1Q[OCCHW_N_MEMBUF] =
+const uint32_t MCMCICFG1Q[OCCHW_N_MC_CHANNEL] =
 {
     MCP_CHAN0_CHI_MCICFG1Q,
     MCP_CHAN1_CHI_MCICFG1Q,
@@ -229,7 +229,7 @@ int gpe_centaur_configuration_create(MemBufConfiguration_t* o_config)
         // hardware,  as well as for our VBU models where some of the "valid"
         // MCS are not in the simulation models.
 
-        for (i = 0; i < OCCHW_N_MEMBUF; ++i)
+        for (i = 0; i < OCCHW_N_CENT; ++i)
         {
             // check for channel checkstop
             rc = check_centaur_channel_chkstp(i);
@@ -278,7 +278,7 @@ int gpe_centaur_configuration_create(MemBufConfiguration_t* o_config)
         }
 
         // Find the designated sync
-        for (i = 0; i < (OCCHW_N_MEMBUF/2); ++i)
+        for (i = 0; i < (OCCHW_N_MC_PORT); ++i)
         {
             uint64_t mcsync;
             rc = getscom_abs(MCSYNC[i], &mcsync);
@@ -619,7 +619,7 @@ int get_centaur_sensorcache(MemBufConfiguration_t* i_config,
 
     if(i_parms->collect != -1)
     {
-        if((i_parms->collect >= OCCHW_N_MEMBUF) ||
+        if((i_parms->collect >= OCCHW_N_CENT) ||
            (0 == (CHIP_CONFIG_MEMBUF(i_parms->collect) & (i_config->config))))
         {
             rc = MEMBUF_GET_MEM_DATA_COLLECT_INVALID;
@@ -662,7 +662,7 @@ int get_centaur_sensorcache(MemBufConfiguration_t* i_config,
     if(i_parms->update != -1)
     {
         int update_rc = 0;
-        if((i_parms->update >= OCCHW_N_MEMBUF) ||
+        if((i_parms->update >= OCCHW_N_CENT) ||
            (0 == (CHIP_CONFIG_MEMBUF(i_parms->update) & (i_config->config))))
         {
             update_rc = MEMBUF_GET_MEM_DATA_UPDATE_INVALID;
diff --git a/src/occ_gpe1/gpe_membuf_scom.c b/src/occ_gpe1/gpe_membuf_scom.c
index 0a047ea..5aeb166 100644
--- a/src/occ_gpe1/gpe_membuf_scom.c
+++ b/src/occ_gpe1/gpe_membuf_scom.c
@@ -226,6 +226,7 @@ int membuf_get_scom_vector(MemBufConfiguration_t* i_config,
     int access_rc = 0;
     int pba_rc = 0;
     int instance = 0;
+    int max_mb = OCCHW_N_MEMBUF;
     uint64_t pba_slvctln_save;
 
     pbaslvctl_reset(&(i_config->scomParms));
@@ -234,7 +235,12 @@ int membuf_get_scom_vector(MemBufConfiguration_t* i_config,
     // clear SIB errors in MSR
     mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)));
 
-    for(instance = 0; instance < OCCHW_N_MEMBUF; ++instance)
+    if(i_config->membuf_type == MEMTYPE_CENTAUR)
+    {
+        max_mb = OCCHW_N_CENT;
+    }
+
+    for(instance = 0; instance < max_mb; ++instance)
     {
         if( CHIP_CONFIG_MEMBUF(instance) & (i_config->config))
         {
@@ -332,12 +338,18 @@ int membuf_put_scom_all(MemBufConfiguration_t* i_config,
     int pba_rc = 0;
     int access_rc = 0;
     int instance = 0;
+    int max_mb = OCCHW_N_MEMBUF;
     uint64_t pba_slvctln_save;
 
     pbaslvctl_reset(&(i_config->scomParms));
     pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
 
-    for(instance = 0; instance < OCCHW_N_MEMBUF; ++instance)
+    if(i_config->membuf_type == MEMTYPE_CENTAUR)
+    {
+        max_mb = OCCHW_N_CENT;
+    }
+
+    for(instance = 0; instance < max_mb; ++instance)
     {
         if( CHIP_CONFIG_MEMBUF(instance) & (i_config->config))
         {
@@ -473,12 +485,18 @@ int membuf_scom_rmw_all(MemBufConfiguration_t* i_config,
     int pba_rc = 0;
     int access_rc = 0;
     int instance = 0;
+    int max_mb = OCCHW_N_MEMBUF;
     uint64_t pba_slvctln_save;
 
     pbaslvctl_reset(&(i_config->scomParms));
     pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
 
-    for(instance = 0; (instance < OCCHW_N_MEMBUF); ++instance)
+    if(i_config->membuf_type == MEMTYPE_CENTAUR)
+    {
+        max_mb = OCCHW_N_CENT;
+    }
+
+    for(instance = 0; (instance < max_mb); ++instance)
     {
         if( CHIP_CONFIG_MEMBUF(instance) & (i_config->config))
         {
diff --git a/src/occ_gpe1/gpe_ocmb.c b/src/occ_gpe1/gpe_ocmb.c
index dfe7d89..2232991 100644
--- a/src/occ_gpe1/gpe_ocmb.c
+++ b/src/occ_gpe1/gpe_ocmb.c
@@ -33,7 +33,7 @@
 #include "ocmb_firmware_registers.h"
 #include "ocmb_mem_data.h"
 
-const uint32_t AXONE_MCFGPR[OCCHW_N_MEMBUF] =
+const uint32_t AXONE_MCFGPR[OCCHW_N_MC_CHANNEL] =
 {
     P9A_MI_0_MCFGPR0,
     P9A_MI_0_MCFGPR1,
@@ -45,7 +45,7 @@ const uint32_t AXONE_MCFGPR[OCCHW_N_MEMBUF] =
     P9A_MI_3_MCFGPR1
 };
 
-const uint32_t AXONE_MCSYNC[OCCHW_N_MEMBUF/2] =
+const uint32_t AXONE_MCSYNC[OCCHW_N_MC_PORT] =
 {
     P9A_MI_0_MCSYNC,
     P9A_MI_1_MCSYNC,
@@ -162,6 +162,8 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
     mtmsr((orig_msr & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM | MSR_IS1 | MSR_IS2 );
     sync();
 
+    uint32_t l_config = o_config->config; // Save
+    //Clear MemBufConfiguration
     for(i = 0; i < sizeof(MemBufConfiguration_t) / 8; ++i)
     {
         *ptr++ = 0ull;
@@ -169,6 +171,7 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
 
     o_config->configRc = MEMBUF_NOT_CONFIGURED;
     o_config->membuf_type = MEMTYPE_OCMB;
+    o_config->config = l_config;
 
     do
     {
@@ -230,7 +233,7 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
         }
 
         // Find all configured MEMBUFs
-        for (i = 0; i < OCCHW_N_MEMBUF; ++i)
+        for (i = 0; i < OCCHW_N_MC_CHANNEL; ++i)
         {
             uint64_t l_pba_addr = 0;
             uint32_t l_mmio_bar = 0;
@@ -279,19 +282,21 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
             //  to bits [8:38] of the Power Bus addresss
             l_pba_addr >>= 8;
 
-            if((i % 2) != 0)
-            {
-                l_pba_addr |= OCMB_IB_BAR_B_BIT;
-            }
-
             PK_TRACE("MMIO Base Address: 0x%08x%08x on ocmb %d",
                      (uint32_t)(l_pba_addr >> 32),
                      (uint32_t)(l_pba_addr),
                      i);
 
-            o_config->baseAddress[i] = l_pba_addr;
-            // Add this membuf to the configuration
-            o_config->config |= (CHIP_CONFIG_MCS(i) | CHIP_CONFIG_MEMBUF(i));
+            // If channel is configured then subchannelA must always have an MB.
+            // MB on subchannelB is optional - check config passed in from HTMGT
+            o_config->baseAddress[2*i] = l_pba_addr;
+            if(o_config->config & CHIP_CONFIG_MEMBUF((2*i)+1))
+            {
+                o_config->baseAddress[(2*i)+1] = l_pba_addr | OCMB_IB_BAR_B_BIT;
+            }
+
+            // Add this MC Channel
+            o_config->config |= (CHIP_CONFIG_MCS(i));
         }
 
         if( rc )
@@ -302,7 +307,7 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
         // Find the designated sync.
         // Find the register that HWPs used to sync the throttle n/m values
         // accross all membufs. Only one register should be setup.
-        for (i = 0; i < (OCCHW_N_MEMBUF/2); ++i)
+        for (i = 0; i < (OCCHW_N_MC_PORT); ++i)
         {
             uint64_t mcsync;
             rc = getscom_abs(AXONE_MCSYNC[i], &mcsync);
@@ -342,22 +347,13 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
 
         if(!rc)
         {
-            for(i = 0; i < OCCHW_N_MEMBUF; ++i)
-            {
-                if( CHIP_CONFIG_MEMBUF(i) & (o_config->config))
-                {
-                    // Attempt to reset any SCACHE FIR errors
-                    // and insure the SCACHE is enabled
-                    check_and_reset_mmio_fir(o_config, i);
-                    ocmb_check_sensor_cache_enabled(o_config,i);
-                }
-            }
-
             // Find out which DTS are present
+            // Note: The MB sensor cache supports three DTS readings, but
+            // what they will represent has not yet been decided 
             OcmbMemData escache;
             MemBufGetMemDataParms_t l_parms;
 
-            l_parms.update = -1;
+            l_parms.update = -1; //NONE
             l_parms.data = (uint64_t *)(&escache);
 
             for(i = 0; i < OCCHW_N_MEMBUF; ++i)
@@ -371,7 +367,11 @@ int gpe_ocmb_configuration_create(MemBufConfiguration_t* o_config)
                         PK_TRACE("gpe_ocmb_configuration_create failed to"
                                  " get sensorcache for MEMBUF %d, rc = %d.",
                                  i, rc);
-                          continue; // Thermal sensors not available.
+
+                        // Remove this OCMB from the configuration
+                        o_config->config &= ~(CHIP_CONFIG_MEMBUF(i));
+
+                        continue; // Thermal sensors not available.
                     }
 
                     if(escache.status.fields.ubdts0_present)