Prevent PGPE IPC communication if all cores are deconfigured

Change-Id: I7cea001833615dc3bcb6a282c20f205f1e7d9d87
CQ:SW401110
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46831
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>

7 files changed, 205 insertions, 120 deletions

diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index f80486e..ca66eb2 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -80,7 +80,7 @@ extern GpeRequest G_meas_complete_request;
 extern apss_start_args_t    G_gpe_start_pwr_meas_read_args;
 extern apss_continue_args_t G_gpe_continue_pwr_meas_read_args;
 extern apss_complete_args_t G_gpe_complete_pwr_meas_read_args;
-
+extern uint32_t G_present_cores;
 extern uint32_t G_proc_fmin_khz;
 extern uint32_t G_proc_fmax_khz;
 extern wof_header_data_t G_wof_header;
@@ -1129,17 +1129,31 @@ void read_hcode_headers()
         if (read_ppmr_header() == FALSE) break;
         CHECKPOINT(PPMR_IMAGE_HEADER_READ);
 
-        // Read OCC pstates parameter block
-        if (read_oppb_params() == FALSE) break;
-        CHECKPOINT(OPPB_IMAGE_HEADER_READ);
-
-        // Read PGPE header file, extract OCC/PGPE Shared SRAM address and size,
-        if (read_pgpe_header() == FALSE) break;
-        CHECKPOINT(PGPE_IMAGE_HEADER_READ);
-
-        // Extract important WOF data into global space
-        read_wof_header();
-        CHECKPOINT(WOF_IMAGE_HEADER_READ);
+        // If there are no configured cores, skip reading these headers
+        // since they will no longer be used.
+        if(G_present_cores == 0)
+        {
+            TRAC_INFO("read_hcode_headers: No configured cores detected."
+                      " Skipping read_oppb_params(), read_pgpe_header(),"
+                      " and read_wof_header()");
+            set_clear_wof_disabled( SET, WOF_RC_NO_CONFIGURED_CORES );
+            G_proc_pstate_status = PSTATES_DISABLED;
+        }
+        else
+        {
+            // Read OCC pstates parameter block
+            if (read_oppb_params() == FALSE) break;
+            CHECKPOINT(OPPB_IMAGE_HEADER_READ);
+
+            // Read PGPE header file, extract OCC/PGPE Shared SRAM address and size,
+            if (read_pgpe_header() == FALSE) break;
+            CHECKPOINT(PGPE_IMAGE_HEADER_READ);
+
+            // Extract important WOF data into global space
+            read_wof_header();
+            CHECKPOINT(WOF_IMAGE_HEADER_READ);
+            set_clear_wof_disabled( CLEAR, WOF_RC_NO_CONFIGURED_CORES );
+        }
 
         // PGPE Beacon is not implemented in simics
         if (!G_simics_environment)
diff --git a/src/occ_405/pgpe/pgpe_interface.c b/src/occ_405/pgpe/pgpe_interface.c
index 5674641..fad5bd6 100644
--- a/src/occ_405/pgpe/pgpe_interface.c
+++ b/src/occ_405/pgpe/pgpe_interface.c
@@ -45,6 +45,7 @@ extern pstateStatus G_proc_pstate_status;
 extern PMCR_OWNER G_proc_pmcr_owner;
 
 extern uint16_t G_proc_fmax_mhz;
+extern uint32_t G_present_cores;
 
 extern bool G_simics_environment;
 
@@ -649,7 +650,7 @@ int pgpe_clip_update(void)
             }
 
             // Schedule PGPE clip update IPC task
-            schedule_rc = gpe_request_schedule(&G_clip_update_req);
+            schedule_rc = pgpe_request_schedule(&G_clip_update_req);
         }
         else
         {
@@ -817,8 +818,9 @@ int pgpe_start_suspend(uint8_t action, PMCR_OWNER owner)
            {
                TRAC_IMP("pgpe_start_suspend: scheduling disable of pstates (owner=0x%02X)", owner);
            }
+
            // Schedule PGPE start_suspend task
-           schedule_rc = gpe_request_schedule(&G_start_suspend_req);
+           schedule_rc = pgpe_request_schedule(&G_start_suspend_req);
        }
 
        // couldn't schedule the IPC task?
@@ -932,7 +934,7 @@ int pgpe_pmcr_set(void)
         if (!G_simics_environment)
         {
             // Schedule PGPE PMCR update IPC task
-            schedule_rc = gpe_request_schedule(&G_pmcr_set_req);
+            schedule_rc = pgpe_request_schedule(&G_pmcr_set_req);
         }
 
         // Confirm Successfull completion of PGPE PMCR update task
@@ -1074,3 +1076,33 @@ int set_nominal_pstate(void)
 
    return l_rc;
 }
+
+// Function Specification
+//
+// Name: pgpe_request_schedule
+//
+// Description: Wrapper function that takes care of any overhead associated
+//              with scheduling a GpeRequest to the PGPE
+//
+// End Function Specification
+int pgpe_request_schedule(GpeRequest* request)
+{
+    int rc = 0;
+    static uint8_t L_traceCount = 10;
+    // Before sending any IPC task to the PGPE, make sure there are cores
+    // configured
+    if( G_present_cores != 0 )
+    {
+        rc = gpe_request_schedule(request);
+    }
+    else
+    {
+        if( L_traceCount )
+        {
+            // If we skip the IPC task, just send successful return code
+            TRAC_INFO("No Configured Cores. Skipping PGPE-bound IPC tasks");
+            L_traceCount--;
+        }
+    }
+    return rc;
+}
diff --git a/src/occ_405/pgpe/pgpe_interface.h b/src/occ_405/pgpe/pgpe_interface.h
index 16a3aef..2bfeeaa 100644
--- a/src/occ_405/pgpe/pgpe_interface.h
+++ b/src/occ_405/pgpe/pgpe_interface.h
@@ -29,24 +29,34 @@
 #include "errl.h"
 #include "state.h"
 #include "pstate_pgpe_occ_api.h"
+#include "occhw_async.h"
 
 void init_pgpe_ipcs(void);
 
 errlHndl_t pgpe_init_clips(void);
+
 errlHndl_t pgpe_init_pmcr(void);
+
 errlHndl_t pgpe_init_start_suspend(void);
+
 errlHndl_t pgpe_init_wof_control(void);
+
 errlHndl_t pgpe_init_wof_vfrt(void);
 
 int pgpe_set_clip_ranges(Pstate i_pstate);
+
 int pgpe_set_clip_blocking(Pstate i_pstate);
+
 int pgpe_clip_update(void);
 
 int pgpe_pmcr_set(void);
 
 int pgpe_start_suspend(uint8_t action, PMCR_OWNER owner);
+
 void pgpe_start_suspend_callback(void);
 
+int pgpe_request_schedule(GpeRequest* request);
+
 int set_nominal_pstate(void);
 
 #endif /* #ifndef _PGPE_INTERFACE_H_ */
diff --git a/src/occ_405/state.c b/src/occ_405/state.c
index e2a337a..7b2a4a5 100755
--- a/src/occ_405/state.c
+++ b/src/occ_405/state.c
@@ -49,7 +49,6 @@
 extern bool G_mem_monitoring_allowed;
 extern task_t G_task_table[TASK_END];  // Global task table
 extern bool G_simics_environment;
-
 extern pstateStatus G_proc_pstate_status;
 extern uint16_t G_proc_fmax_mhz;
 extern GpeRequest G_clip_update_req;
@@ -57,7 +56,8 @@ extern GPE_BUFFER(ipcmsg_clip_update_t*  G_clip_update_parms_ptr);
 
 // OCC is ready to transition to observation state?
 extern bool G_active_to_observation_ready;
-
+// bit mask of configured cores
+extern uint32_t G_present_cores;
 extern PMCR_OWNER G_proc_pmcr_owner;
 
 // State that OCC is currently in
@@ -592,79 +592,97 @@ errlHndl_t SMGR_observation_to_active()
                 }
             }
 
-            // Wait for pstates enablement completition.
-            SsxTimebase start = ssx_timebase_get();
-            SsxInterval timeout =  SSX_SECONDS(5);
-            while( ! proc_is_hwpstate_enabled() )
+            // If there are no cores configured, do not wait for PSTATES to
+            // become enabled.
+            if(G_present_cores != 0 )
             {
-                if ((ssx_timebase_get() - start) > timeout)
+                // Wait for pstates enablement completition.
+                SsxTimebase start = ssx_timebase_get();
+                SsxInterval timeout =  SSX_SECONDS(5);
+                while( ! proc_is_hwpstate_enabled() )
                 {
-                    l_rc = 1;
-                    if(FALSE == L_error_logged)
+                    if ((ssx_timebase_get() - start) > timeout)
                     {
-                        TRAC_ERR("SMGR_obs_to_active: Timeout waiting for Pstates to be enabled, "
-                                 "chips_present[%02x], Cores Present [%08x]",
-                                 G_sysConfigData.is_occ_present,
-                                 (uint32_t) ((in64(OCB_CCSR)) >> 32));
+                        l_rc = 1;
+                        if(FALSE == L_error_logged)
+                        {
+                            TRAC_ERR("SMGR_obs_to_active: Timeout waiting for Pstates to be enabled, "
+                                     "chips_present[%02x], Cores Present [%08x]",
+                                     G_sysConfigData.is_occ_present,
+                                     (uint32_t) ((in64(OCB_CCSR)) >> 32));
+                        }
+                        l_extRc = ERC_GENERIC_TIMEOUT;
+                        break;
                     }
-                    l_extRc = ERC_GENERIC_TIMEOUT;
-                    break;
+                    ssx_sleep(SSX_MICROSECONDS(10));
                 }
-                ssx_sleep(SSX_MICROSECONDS(10));
-            }
 
-            // if pstates are now enabled, all conditions are already met
-            // to transition to active state.
-            if(proc_is_hwpstate_enabled() )
-            {
-                TRAC_IMP("SMGR_obs_to_active: Pstates are enabled, continuing with state trans");
+                // if pstates are now enabled, all conditions are already met
+                // to transition to active state.
+                if(proc_is_hwpstate_enabled() )
+                {
+                    TRAC_IMP("SMGR_obs_to_active: Pstates are enabled, continuing with state trans");
 
-                L_error_logged = FALSE;
+                    L_error_logged = FALSE;
 
-                // Set the RTL Flags to indicate which tasks can run
-                //   - Clear OBSERVATION b/c not in OBSERVATION State
-                //   - Set ACTIVE b/c we're in ACTIVE State
-                rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
-                rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
+                    // Set the RTL Flags to indicate which tasks can run
+                    //   - Clear OBSERVATION b/c not in OBSERVATION State
+                    //   - Set ACTIVE b/c we're in ACTIVE State
+                    rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
+                    rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
 
-                // Pstates enabled, update OPAL static table in main memory with pState info
-                proc_pstate_kvm_setup();
+                    // Pstates enabled, update OPAL static table in main memory with pState info
+                    proc_pstate_kvm_setup();
+
+                    // Set the actual STATE now that we have finished everything else
+                    CURRENT_STATE() = OCC_STATE_ACTIVE;
+                    TRAC_IMP("SMGR: Observation to Active Transition Completed. OCC role = %d", G_occ_role);
+                }
+                else
+                {
+                    TRAC_ERR("SMGR: Observation to Active Transition Failed, because pstates are not enabled");
+                }
+
+                if(l_rc && FALSE == L_error_logged)
+                {
+                    L_error_logged = TRUE;
+                    /* @
+                     * @errortype
+                     * @moduleid    MAIN_STATE_TRANSITION_MID
+                     * @reasoncode  INTERNAL_FAILURE
+                     * @userdata1   SMGR_MASK_ACTIVE_READY
+                     * @userdata2   valid states
+                     * @userdata4   ERC_GENERIC_TIMEOUT
+                     * @devdesc     Failed changing from observation to active
+                     */
+                    l_errlHndl = createErrl(MAIN_STATE_TRANSITION_MID,        //modId
+                                            INTERNAL_FAILURE,                 //reasoncode
+                                            l_extRc,                          //Extended reason code
+                                            ERRL_SEV_UNRECOVERABLE,           //Severity
+                                            NULL,                             //Trace Buf
+                                            DEFAULT_TRACE_SIZE,               //Trace Size
+                                            SMGR_MASK_ACTIVE_READY,           //userdata1
+                                            SMGR_validate_get_valid_states());//userdata2
+
+                    // Callout firmware
+                    addCalloutToErrl(l_errlHndl,
+                                     ERRL_CALLOUT_TYPE_COMPONENT_ID,
+                                     ERRL_COMPONENT_ID_FIRMWARE,
+                                     ERRL_CALLOUT_PRIORITY_HIGH);
+                }
 
-                // Set the actual STATE now that we have finished everything else
-                CURRENT_STATE() = OCC_STATE_ACTIVE;
-                TRAC_IMP("SMGR: Observation to Active Transition Completed. OCC role = %d", G_occ_role);
             }
-            else
+            else // We have no cores configured
             {
-                TRAC_ERR("SMGR: Observation to Active Transition Failed, because pstates are not enabled");
-            }
+                // Set rtl flags to indicate which tasks can run since
+                // we do not have to wait for pstates to be enabled
+                rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
+                rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
 
-            if(l_rc && FALSE == L_error_logged)
-            {
-                L_error_logged = TRUE;
-                /* @
-                 * @errortype
-                 * @moduleid    MAIN_STATE_TRANSITION_MID
-                 * @reasoncode  INTERNAL_FAILURE
-                 * @userdata1   SMGR_MASK_ACTIVE_READY
-                 * @userdata2   valid states
-                 * @userdata4   ERC_GENERIC_TIMEOUT
-                 * @devdesc     Failed changing from observation to active
-                 */
-                l_errlHndl = createErrl(MAIN_STATE_TRANSITION_MID,        //modId
-                                        INTERNAL_FAILURE,                 //reasoncode
-                                        l_extRc,                          //Extended reason code
-                                        ERRL_SEV_UNRECOVERABLE,           //Severity
-                                        NULL,                             //Trace Buf
-                                        DEFAULT_TRACE_SIZE,               //Trace Size
-                                        SMGR_MASK_ACTIVE_READY,           //userdata1
-                                        SMGR_validate_get_valid_states());//userdata2
-
-                // Callout firmware
-                addCalloutToErrl(l_errlHndl,
-                                 ERRL_CALLOUT_TYPE_COMPONENT_ID,
-                                 ERRL_COMPONENT_ID_FIRMWARE,
-                                 ERRL_CALLOUT_PRIORITY_HIGH);
+                // Set the actual STATE now that we have finished everything else
+                CURRENT_STATE() = OCC_STATE_ACTIVE;
+                TRAC_IMP("SMGR: Observation to Active Transition Completed."
+                        " OCC role = %d", G_occ_role);
             }
         }   // Active Ready
         else
@@ -712,27 +730,43 @@ errlHndl_t SMGR_characterization_to_active()
             break;
         }
 
-        // Wait for ownership change to complete
-        SsxTimebase start = ssx_timebase_get();
-        SsxInterval timeout =  SSX_SECONDS(5);
-        while( ! proc_is_hwpstate_enabled() )
+        // If there are no cores configured, do not wait for PSTATES to
+        // become enabled.
+        if(G_present_cores != 0)
         {
-            if ((ssx_timebase_get() - start) > timeout)
+            // Wait for ownership change to complete
+            SsxTimebase start = ssx_timebase_get();
+            SsxInterval timeout =  SSX_SECONDS(5);
+            while( ! proc_is_hwpstate_enabled() )
             {
-                rc = 1;
-                TRAC_ERR("SMGR_char_to_active: Timeout waiting for PMCR ownership change");
-                break;
+                if ((ssx_timebase_get() - start) > timeout)
+                {
+                    rc = 1;
+                    TRAC_ERR("SMGR_char_to_active: Timeout waiting for PMCR ownership change");
+                    break;
+                }
+                ssx_sleep(SSX_MICROSECONDS(10));
             }
-            ssx_sleep(SSX_MICROSECONDS(10));
-        }
 
-        if(proc_is_hwpstate_enabled())
-        {
-            L_error_logged = FALSE;
+            if(proc_is_hwpstate_enabled())
+            {
+                L_error_logged = FALSE;
 
-            // Set the RTL Flags to indicate which tasks can run
-            //   - Clear OBSERVATION b/c not in CHARACTERIZATION State
-            //   - Set ACTIVE b/c we're in ACTIVE State
+                // Set the RTL Flags to indicate which tasks can run
+                //   - Clear OBSERVATION b/c not in CHARACTERIZATION State
+                //   - Set ACTIVE b/c we're in ACTIVE State
+                rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
+                rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
+
+                // Set the actual STATE now that we have finished everything else
+                CURRENT_STATE() = OCC_STATE_ACTIVE;
+                TRAC_IMP("SMGR: Characterization to Active Transition Completed");
+            }
+        }
+        else // We have no cores configured
+        {
+            // Set rtl flags to indicate which tasks can run since
+            // we do not have to wait for pstates to be enabled
             rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
             rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
 
diff --git a/src/occ_405/timer/timer.c b/src/occ_405/timer/timer.c
index 16b25c8..8bcbfc4 100755
--- a/src/occ_405/timer/timer.c
+++ b/src/occ_405/timer/timer.c
@@ -44,7 +44,8 @@
 extern uint32_t G_mainThreadLoopCounter;
 // Running in simics?
 extern bool G_simics_environment;
-
+// bit mask of configured cores
+extern uint32_t G_present_cores;
 //*************************************************************************/
 // Macros
 //*************************************************************************/
@@ -228,36 +229,35 @@ void init_mem_deadman_reset_task(void)
 void task_poke_watchdogs(struct task * i_self)
 {
     ocb_occhbr_t hbr;                          // OCC heart beat register
-
-    static bool             L_check_pgpe_beacon = false;  // Check GPE beacon this time?
+    static bool L_check_pgpe_beacon = false;  // Check GPE beacon this time?
 
 // 1. Enable OCC heartbeat
 
     hbr.fields.occ_heartbeat_count = 8000; // count corresponding to 8 ms
     hbr.fields.occ_heartbeat_en   = true;  // enable heartbeat timer
-
     out32(OCB_OCCHBR, hbr.value);             // Enable heartbeat register, and set it
 
-
 // 2. Reset memory deadman timer
     if(G_sysConfigData.mem_type == MEM_TYPE_NIMBUS)
     {
         manage_mem_deadman_task();
     }
 
-// 3. Verify PGPE Beacon is not frozen for 8 ms
-    if(true == L_check_pgpe_beacon)
+// 3. Verify PGPE Beacon is not frozen for 8 ms if there are cores configured
+    if(G_present_cores != 0)
     {
-        // Examine pgpe Beacon every other call (every 4ms)
-        if(!G_simics_environment) // PGPE Beacon is not implemented in simics
+        if(true == L_check_pgpe_beacon)
         {
-            check_pgpe_beacon();
+            // Examine pgpe Beacon every other call (every 4ms)
+            if(!G_simics_environment) // PGPE Beacon is not implemented in simics
+            {
+                check_pgpe_beacon();
+            }
         }
+        // toggle pgpe beacon check flag, check only once every other call (every 4ms)
+        L_check_pgpe_beacon = !L_check_pgpe_beacon;
     }
 
-    // toggle pgpe beacon check flag, check only once every other call (every 4ms)
-    L_check_pgpe_beacon = !L_check_pgpe_beacon;
-
 }
 
 // Function Specification
diff --git a/src/occ_405/wof/wof.c b/src/occ_405/wof/wof.c
index b5e5c71..ae8d732 100644
--- a/src/occ_405/wof/wof.c
+++ b/src/occ_405/wof/wof.c
@@ -35,7 +35,7 @@
 #include <occ_sys_config.h>
 #include <wof.h>
 #include <amec_freq.h>
-
+#include <pgpe_interface.h>
 //******************************************************************************
 // External Globals
 //******************************************************************************
@@ -355,7 +355,7 @@ void wof_main(void)
     send_vfrt_to_pgpe( g_wof->next_vfrt_main_mem_addr );
     if(async_request_is_idle(&G_wof_vfrt_req.request))
     {
-        g_wof->gpe_req_rc = gpe_request_schedule(&G_wof_vfrt_req);
+        g_wof->gpe_req_rc = pgpe_request_schedule(&G_wof_vfrt_req);
     }
     else
     {
@@ -1389,7 +1389,7 @@ void set_clear_wof_disabled( uint8_t i_action,
     // Check for error
     if( l_logError )
     {
-        if( g_wof->wof_disabled & SUPPRESS_ERROR_RC )
+        if( g_wof->wof_disabled & (~(ERRL_RETURN_CODES)) )
         {
             INTR_TRAC_ERR("Encountered an error, but WOF is off. RC: 0x%08x",
                     i_bit_mask);
@@ -1466,7 +1466,7 @@ void disable_wof( void )
             {
                 // Set parameters for the GpeRequest
                 G_wof_control_parms.action = PGPE_ACTION_WOF_OFF;
-                user_data_rc = gpe_request_schedule( &G_wof_control_req );
+                user_data_rc = pgpe_request_schedule( &G_wof_control_req );
 
                 if( user_data_rc != 0 )
                 {
@@ -1550,7 +1550,7 @@ bool enable_wof( void )
             // Set parameters for the GpeRequest
             G_wof_control_parms.action = PGPE_ACTION_WOF_ON;
 
-            rc = gpe_request_schedule( &G_wof_control_req );
+            rc = pgpe_request_schedule( &G_wof_control_req );
 
             if( rc != 0 )
             {
@@ -1655,7 +1655,7 @@ void send_initial_vfrt_to_pgpe( void )
     send_vfrt_to_pgpe( g_wof->next_vfrt_main_mem_addr );
     if(async_request_is_idle(&G_wof_vfrt_req.request))
     {
-        g_wof->gpe_req_rc =  gpe_request_schedule(&G_wof_vfrt_req);
+        g_wof->gpe_req_rc =  pgpe_request_schedule(&G_wof_vfrt_req);
     }
     else
     {
diff --git a/src/occ_405/wof/wof.h b/src/occ_405/wof/wof.h
index c97efad..f923f57 100644
--- a/src/occ_405/wof/wof.h
+++ b/src/occ_405/wof/wof.h
@@ -68,22 +68,18 @@
 #define WOF_RC_SYSTEM_WOF_DISABLE                  0x00080000
 #define WOF_RC_RESET_LIMIT_REACHED                 0x00100000
 #define WOF_RC_UNSUPPORTED_FREQUENCIES             0x00200000
+#define WOF_RC_NO_CONFIGURED_CORES                 0x00400000
 
 //***************************************************************************
 // Temp space used to save hard coded addresses
 //***************************************************************************
 #define PSTATE_TBL_ADDR 0xFFF2B85C
 
-
 // Reason codes which should NOT create an error log should be added here
 #define ERRL_RETURN_CODES ~(WOF_RC_MODE_CHANGE  | \
                             WOF_RC_STATE_CHANGE | \
-                            WOF_RC_MODE_NO_SUPPORT_MASK)
-
-// Reason codes that if set, should suppress all other unrecoverable errors.
-#define SUPPRESS_ERROR_RC ~(ERRL_RETURN_CODES)
-
-
+                            WOF_RC_MODE_NO_SUPPORT_MASK | \
+                            WOF_RC_NO_CONFIGURED_CORES)
 
 // Enumeration to define the WOF initialization steps
 enum wof_init_states
@@ -105,7 +101,6 @@ enum wof_disabled_htmgt_rc
     WOF_UNSUPPORTED_FREQ        = 0x0003,
 };
 
-
 // Enumeration
 enum wof_disabled_actions
 {