Processor Thermal Control Loop

Enable processor thermal control loop.
Enable frequency votes due to thermal and error reading temperatures.
Verify The following:
*Error log generation when a proc reaches Error limit
*Reach throttle points when:
-- Processor reached over temperature limit
-- Processor temperature sensors timeout
enable transition to active mode

Change-Id: Iae24f64a872e031e1cf93ff0d9248d3fa3847ed7
RTC: 130210
RTC: 133942
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25458
Tested-by: FSP CI Jenkins
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

13 files changed, 56 insertions, 176 deletions

diff --git a/src/include/proc_shared.h b/src/include/proc_shared.h
index ea05737..6b71bff 100644
--- a/src/include/proc_shared.h
+++ b/src/include/proc_shared.h
@@ -29,7 +29,7 @@
 #include "core_data.h"
 #include "gpe_export.h"
 
-// Paramaters for gpe_get_core_data() & gpe_get_per_core_data()
+// Paramaters for gpe_get_core_data()
 
 typedef struct ipc_core_data_parms
 {
diff --git a/src/occ_405/amec/amec_freq.c b/src/occ_405/amec/amec_freq.c
index ea14c29..0afe676 100755
--- a/src/occ_405/amec/amec_freq.c
+++ b/src/occ_405/amec/amec_freq.c
@@ -213,9 +213,6 @@ errlHndl_t amec_set_freq_range(const OCC_MODE i_mode)
     return l_err;
 }
 
-// @TODO - TEMP - Code not ready yet
-#if 0
-
 // Function Specification
 //
 // Name: amec_slv_voting_box
@@ -501,9 +498,6 @@ void amec_slv_voting_box(void)
     }
 }
 
-#endif // @TODO - TEMP - Code not ready yet
-
-
 // Function Specification
 //
 // Name: amec_slv_freq_smh
diff --git a/src/occ_405/amec/amec_health.c b/src/occ_405/amec/amec_health.c
index 45986ab..1e061bf 100755
--- a/src/occ_405/amec/amec_health.c
+++ b/src/occ_405/amec/amec_health.c
@@ -746,8 +746,8 @@ void amec_health_check_proc_temp()
     /*  Local Variables                                                       */
     /*------------------------------------------------------------------------*/
     uint16_t                    l_ot_error;
-    static uint32_t             l_error_count = 0;
-    static BOOLEAN              l_ot_error_logged = FALSE;
+    static uint32_t             L_error_count = 0;
+    static BOOLEAN              L_ot_error_logged = FALSE;
     sensor_t                    *l_sensor;
     errlHndl_t                  l_err = NULL;
 
@@ -765,18 +765,18 @@ void amec_health_check_proc_temp()
         if (l_sensor->sample > l_ot_error)
         {
             // Increment the error counter for this FRU
-            l_error_count++;
+            L_error_count++;
 
             // Trace and log error the first time this occurs
-            if (l_error_count == AMEC_HEALTH_ERROR_TIMER)
+            if (L_error_count == AMEC_HEALTH_ERROR_TIMER)
             {
                 // Have we logged an OT error for this FRU already?
-                if (l_ot_error_logged == TRUE)
+                if (L_ot_error_logged == TRUE)
                 {
                     break;
                 }
 
-                l_ot_error_logged = TRUE;
+                L_ot_error_logged = TRUE;
 
                 TRAC_ERR("amec_health_check_error_temp: processor has exceeded OT error! temp[%u] ot_error[%u]",
                          l_sensor->sample,
@@ -821,14 +821,14 @@ void amec_health_check_proc_temp()
         else
         {
             // Trace that we have now dropped below the error threshold
-            if (l_error_count >= AMEC_HEALTH_ERROR_TIMER)
+            if (L_error_count >= AMEC_HEALTH_ERROR_TIMER)
             {
                 TRAC_INFO("amec_health_check_proc_temp: We have dropped below error threshold for processors. error_count[%u]",
-                          l_error_count);
+                          L_error_count);
             }
 
             // Reset the error counter for this FRU
-            l_error_count = 0;
+            L_error_count = 0;
         }
     }while (0);
 
@@ -844,8 +844,6 @@ void amec_health_check_proc_temp()
 // End Function Specification
 void amec_health_check_proc_timeout()
 {
-/* TEMP/TODO: Enable when needed */
-#if 0
     /*------------------------------------------------------------------------*/
     /*  Local Variables                                                       */
     /*------------------------------------------------------------------------*/
@@ -907,16 +905,11 @@ void amec_health_check_proc_timeout()
                 // Get pointer to core data
                 l_core_data_ptr = proc_get_bulk_core_data_ptr(l_bad_core_index);
 
-                // Trace some critical registers to understand this error better
-                TRAC_ERR("OHA_Status_Reg[0x%08X] PM_State_Hist_Reg[0x%08X]",
-                         l_core_data_ptr->oha.oha_ro_status_reg.words.low_order,
-                         l_core_data_ptr->pcb_slave.pm_history.words.high_order);
 
-                TRAC_ERR("SensorV0[0x%08X%08X] SensorV1[0x%08X%08X]",
-                         (uint32_t)(l_core_data_ptr->dts_cpm.sensors_v0.value >> 32),
-                         (uint32_t)(l_core_data_ptr->dts_cpm.sensors_v0.value & 0x00000000ffffffffull),
-                         (uint32_t)(l_core_data_ptr->dts_cpm.sensors_v1.value >> 32),
-                         (uint32_t)(l_core_data_ptr->dts_cpm.sensors_v1.value & 0x00000000ffffffffull));
+                TRAC_ERR("Core Sensors[0x%04X%04X] Quad Sensor[0x%04X]",
+                         (uint16_t)(l_core_data_ptr->dts.core[0].result ),
+                         (uint16_t)(l_core_data_ptr->dts.core[0].result ),
+                         (uint16_t)(l_core_data_ptr->dts.cache.result));
 
                 /* @
                  * @errortype
@@ -948,7 +941,6 @@ void amec_health_check_proc_timeout()
             }
         }
     }while(0);
-#endif
 }
 
 // Function Specification
diff --git a/src/occ_405/amec/amec_init.c b/src/occ_405/amec/amec_init.c
index 18da9f5..c4c16a6 100644
--- a/src/occ_405/amec/amec_init.c
+++ b/src/occ_405/amec/amec_init.c
@@ -79,8 +79,6 @@ extern void amec_slv_update_gpe_sensors(uint8_t i_gpe_engine);
 // Function Prototypes
 //*************************************************************************
 
-// @TODO - TEMP: not ready yet
-#if 0
 //*************************************************************************
 // Functions
 //*************************************************************************
@@ -239,7 +237,6 @@ void amec_init_vector_sensors(void)
   }
 #endif
 }
-#endif // #if 0 @TODO - TEMP: not ready yet
 
 // Function Specification
 //
@@ -437,10 +434,11 @@ void amec_slave_init()
     G_fw_timing.gpe1_timing_request = &G_gpe_nop_request[1];
   }
 
+#endif // #if 0 - @TODO - TEMP - Not ready yet
+
   // Initialize Vector Sensors for AMEC use
   amec_init_vector_sensors();
 
-#endif // #if 0 - @TODO - TEMP - Not ready yet
 
   // Initialize AMEC internal parameters
   amec_init_gamec_struct();
diff --git a/src/occ_405/amec/amec_oversub.c b/src/occ_405/amec/amec_oversub.c
index 3aaf6ac..6b5ab3c 100755
--- a/src/occ_405/amec/amec_oversub.c
+++ b/src/occ_405/amec/amec_oversub.c
@@ -120,7 +120,7 @@ void amec_oversub_isr(void)
         g_amec->oversub_status.oversubActiveTime = ssx_timebase_get();
 
         // Setup the IRQ
-        ssx_irq_setup(PGP_IRQ_EXTERNAL_TRAP,
+        ssx_irq_setup(OCCHW_IRQ_EXTERNAL_TRAP,
                       SSX_IRQ_POLARITY_ACTIVE_HIGH,
                       SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
         l_polarity = SSX_IRQ_POLARITY_ACTIVE_HIGH;
@@ -135,7 +135,7 @@ void amec_oversub_isr(void)
         g_amec->oversub_status.oversubInactiveTime = ssx_timebase_get();
 
         // Setup the IRQ
-        ssx_irq_setup(PGP_IRQ_EXTERNAL_TRAP,
+        ssx_irq_setup(OCCHW_IRQ_EXTERNAL_TRAP,
                       SSX_IRQ_POLARITY_ACTIVE_LOW,
                       SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
 
diff --git a/src/occ_405/amec/amec_slave_smh.c b/src/occ_405/amec/amec_slave_smh.c
index 07ad2ff..e12dca1 100755
--- a/src/occ_405/amec/amec_slave_smh.c
+++ b/src/occ_405/amec/amec_slave_smh.c
@@ -212,8 +212,6 @@ smh_state_timing_t G_amec_slv_state_timings = {amec_slv_update_smh_sensors};
 // Functions
 //*************************************************************************
 
-// @TODO - TEMP: Not Ready yet in Phase 1.
-#if 0
 
 // Function Specification
 //
@@ -273,7 +271,6 @@ void amec_slv_check_apss_fail(void)
     g_amec->proc[0].pwr_votes.apss_pmax_clip_freq = l_pmax_rail_freq;
 }
 
-#endif // #if 0 @TODO - TEMP - Not ready yet in Phase 1
 
 // Function Specification
 //
@@ -330,9 +327,6 @@ void amec_slv_common_tasks_pre(void)
 //  amec_oversub_check();
 }
 
-// @TODO - TEMP: Not Ready yet in Phase 1.
-#if 0
-
 // Function Specification
 //
 // Name: amec_slv_cmmon_tasks_post
@@ -374,7 +368,6 @@ void amec_slv_common_tasks_post(void)
       amec_tb_record(AMEC_TB_250US);
   }
 }
-#endif // #if 0 -  @TODO - TEMP: Not Ready yet in Phase 1.
 
 // Function Specification
 //
@@ -391,11 +384,10 @@ void amec_slv_state_0(void)
   // Update Proc Core sensors (for this tick)
   //-------------------------------------------------------
 
-/* Not yet supported
   //-------------------------------------------------------
   // Update Centaur sensors (for this tick)
   //-------------------------------------------------------
-  amec_update_centaur_sensors(CENTAUR_0);
+//  amec_update_centaur_sensors(CENTAUR_0);
 
   //-------------------------------------------------------
   // Update Sleep Count & Winkle Count Sensors
@@ -420,7 +412,6 @@ void amec_slv_state_0(void)
   // Call the trace function for 2ms tracing if it has been configured via
   // Amester. If not configured, this call will return immediately.
   amec_tb_record(AMEC_TB_2MS);
-*/
 }
 
 
@@ -1026,9 +1017,8 @@ void amec_slv_substate_5_0(void)
     //-------------------------------------------------------
     amec_update_proc_core_group(2);
 
-// @TODO - TEMP: Not Ready yet in Phase 1.
     // Call processor-based thermal controller
-//    amec_controller_proc_thermal();
+    amec_controller_proc_thermal();
 }
 
 void amec_slv_substate_5_1(void)
@@ -1050,8 +1040,8 @@ void amec_slv_substate_5_1(void)
     //-------------------------------------------------------
     amec_update_proc_core_group(6);
 
-// @TODO - TEMP: Not Ready yet in Phase 1.
     // Call controller on VRHOT signal from processor regulator
+// @TODO - Verify VRM monitoring
 //    amec_controller_vrhotproc();
 }
 
@@ -1371,9 +1361,8 @@ void amec_slv_substate_7_7(void)
     //-------------------------------------------------------
     amec_update_proc_core_group(7);
 
-// @TODO - TEMP: Not Ready yet in Phase 1.
-// Call health monitor to check for processor error temperature conditions
-//    amec_health_check_proc_temp();
+    // Call health monitor to check for processor error temperature conditions
+    amec_health_check_proc_temp();
 }
 
 void amec_update_proc_core_group(uint8_t group)
diff --git a/src/occ_405/amec/amec_tasks.c b/src/occ_405/amec/amec_tasks.c
index 0b68331..ce306a9 100755
--- a/src/occ_405/amec/amec_tasks.c
+++ b/src/occ_405/amec/amec_tasks.c
@@ -281,10 +281,8 @@ void task_amec_slave( task_t *i_self)
 
   amec_generic_smh( amec_slv_state_table, &G_amec_slv_state, &G_amec_slv_state_timings );
 
-// @TODO TEMP: Not ready yet in phase 1
-/*
   amec_slv_common_tasks_post();
-*/
+
   // Set the total AMEC int task time for this tick, to the duration of the slave tasks.
   G_fw_timing.ameint_dur = DURATION_IN_US_UNTIL_NOW_FROM(l_start);
 }
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index a7b9e43..ff2f3d9 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -51,8 +51,8 @@
 //#include <vrm.h>
 #include <chom.h>
 #include <homer.h>
-//#include <amec_health.h>
-//#include <amec_freq.h>
+#include <amec_health.h>
+#include <amec_freq.h>
 #include "scom.h"
 //#include <fir_data_collect.h>
 #include <pss_service_codes.h>
@@ -449,8 +449,6 @@ void occ_ipc_setup()
  */
 void hmon_routine()
 {
-/* TEMP -- NOT SUPPORTED IN PHASE1 */
-#if 0
     static uint32_t L_critical_phantom_count = 0;
     static uint32_t L_noncritical_phantom_count = 0;
     static bool L_c_phantom_logged = FALSE;
@@ -517,6 +515,7 @@ void hmon_routine()
         amec_health_check_proc_vrhot();
     }
 
+#if 0  // Memory thermal control loop is not ready yet
     //if we are in active state with memory temperature data being collected
     //then monitor the temperature collections for overtemp and timeout conditions
     if(IS_OCC_STATE_ACTIVE() &&
@@ -527,7 +526,7 @@ void hmon_routine()
         amec_health_check_dimm_timeout();
         amec_health_check_dimm_temp();
     }
-#endif
+#endif   // Memory thermal control loop is not ready yet
 }
 
 
@@ -869,9 +868,8 @@ void Main_thread_routine(void *private)
             }
             else
             {
-                // For Simics phase 1, we don't want to call the health monitor thread
                 // call health monitor routine
-                //hmon_routine();
+                hmon_routine();
             }
         }
 
diff --git a/src/occ_405/occLinkInputFile b/src/occ_405/occLinkInputFile
index eb3f48d..b65eafe 100644
--- a/src/occ_405/occLinkInputFile
+++ b/src/occ_405/occLinkInputFile
@@ -1,9 +1,11 @@
-INPUT ( amec_data.o
+INPUT ( amec_controller.o
+        amec_data.o
         amec_freq.o
         amec_health.o
         amec_init.o
         amec_amester.o
         amec_master_smh.o
+        amec_oversub.o
         amec_parm.o
         amec_pcap.o
         amec_parm_table.o
@@ -30,6 +32,7 @@ INPUT ( amec_data.o
         dcomSlaveRx.o
         dcomSlaveTx.o
         dimm.o
+        dpss.o
         errl.o
         ffdc.o
         fir_data_collect.o
diff --git a/src/occ_405/proc/proc_pstate.c b/src/occ_405/proc/proc_pstate.c
index 4c4030d..23fa2c1 100755
--- a/src/occ_405/proc/proc_pstate.c
+++ b/src/occ_405/proc/proc_pstate.c
@@ -251,6 +251,10 @@ void proc_pstate_initialize(void)
     // sets the G_proc_pstate_enabled flag to true, so that the OCC is then
     // able to switch to the active state.
 
+    // @TODO: FIXME - TEMP Hack to enable Active State, until PGPE is ready
+    G_proc_pstate_enabled = 1;
+
+
     // Set up Key Globals for use by proc_freq2pstate functions
     G_proc_fmax = 4322500;
     G_proc_fmin = 2028250;
diff --git a/src/occ_405/pss/dpss.c b/src/occ_405/pss/dpss.c
index 6db3cdc..a333531 100755
--- a/src/occ_405/pss/dpss.c
+++ b/src/occ_405/pss/dpss.c
@@ -123,10 +123,10 @@ errlHndl_t dpss_oversubscription_irq_initialize()
     __ppc405_phantom_irq.handler = occ_phantom_irq_handler;
 
     // Disable the IRQ while we work on it
-    ssx_irq_disable(PGP_IRQ_EXTERNAL_TRAP);
+    ssx_irq_disable(OCCHW_IRQ_EXTERNAL_TRAP);
 
     // Setup the IRQ
-    rc = ssx_irq_setup(PGP_IRQ_EXTERNAL_TRAP,
+    rc = ssx_irq_setup(OCCHW_IRQ_EXTERNAL_TRAP,
                        SSX_IRQ_POLARITY_ACTIVE_LOW,
                        SSX_IRQ_TRIGGER_LEVEL_SENSITIVE);
 
@@ -152,7 +152,7 @@ errlHndl_t dpss_oversubscription_irq_initialize()
     }
     else {
         // Set the IRQ handler
-        rc = ssx_irq_handler_set(PGP_IRQ_EXTERNAL_TRAP,
+        rc = ssx_irq_handler_set(OCCHW_IRQ_EXTERNAL_TRAP,
                                  isr_dpss_oversubscription_handler,
                                  NULL,
                                  SSX_NONCRITICAL);
@@ -179,8 +179,8 @@ errlHndl_t dpss_oversubscription_irq_initialize()
         }
         else {
             // Enable the IRQ
-            ssx_irq_status_clear(PGP_IRQ_EXTERNAL_TRAP);
-            ssx_irq_enable(PGP_IRQ_EXTERNAL_TRAP);
+            ssx_irq_status_clear(OCCHW_IRQ_EXTERNAL_TRAP);
+            ssx_irq_enable(OCCHW_IRQ_EXTERNAL_TRAP);
         }
     }
 
diff --git a/src/occ_405/state.c b/src/occ_405/state.c
index 20d711b..cf0094f 100755
--- a/src/occ_405/state.c
+++ b/src/occ_405/state.c
@@ -36,8 +36,6 @@
 #include "cmdh_fsp_cmds_datacnfg.h"
 #include "cmdh_fsp.h"
 #include "proc_data.h"
-// TEMP -- Doesn't exist anymore
-//#include "heartbeat.h"
 #include "scom.h"
 #include <fir_data_collect.h>
 #include <dimm.h>
@@ -220,16 +218,14 @@ errlHndl_t SMGR_observation_to_standby()
 errlHndl_t SMGR_observation_to_active()
 {
     errlHndl_t      l_errlHndl = NULL;
-/* TEMP -- UNNECCESSARY IN PHASE1 */
-#if 0
     static bool l_error_logged = FALSE;  // To prevent trace and error log happened over and over
     int                l_extRc = OCC_NO_EXTENDED_RC;
     int                l_rc = 0;
 
     // Pstates are enabled via an IPC call to PGPE once the OCC reaches the
     // observation state. We still have to check that the enable_pstates() IPC job
-    // on the PGPE has completed before transitioned to the active state. otherwise,
-    // wait TBD seconds in case we are going directly from Standby to Active
+    // on the PGPE has completed before transitioning to active state. Otherwise,
+    //  we wait TBD seconds in case we are going directly from Standby to Active
     // (pstate init only happens in observation state, so it might not be
     // done yet...must call it in this while loop since it is done in this
     // same thread...)
@@ -251,12 +247,14 @@ errlHndl_t SMGR_observation_to_active()
             SsxInterval timeout =  SSX_SECONDS(5);
             if ((ssx_timebase_get() - start) > timeout)
             {
+                l_rc = 1;
                 if(FALSE == l_error_logged)
                 {
-                    TRAC_ERR("SMGR: Timeout waiting for Pstates to be enabled, pmc_mode[%08x], chips_present[%02x], pmc_deconfig[%08x]",
+                    TRAC_ERR("SMGR: Timeout waiting for Pstates to be enabled, "
+                             "pmc_mode[%08x], chips_present[%02x], Cores Present [%08x]",
                             in32(PMC_MODE_REG),
                             G_sysConfigData.is_occ_present,
-                            in32(PMC_CORE_DECONFIGURATION_REG));
+                             (uint32_t) ((in64(OCB_CCSR)) >> 32));
                 }
                 l_extRc = ERC_GENERIC_TIMEOUT;
                 break;
@@ -285,113 +283,17 @@ errlHndl_t SMGR_observation_to_active()
         rtl_clr_run_mask_deferred(RTL_FLAG_OBS);
         rtl_set_run_mask_deferred(RTL_FLAG_ACTIVE);
 
-        // Ensure that the dpll override (enabled when mfg biases freq) has been disabled.
-        int l_core;
-        uint32_t l_configured_cores;
-        pcbs_pmgp1_reg_t l_pmgp1;
-        l_configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);
-        for(l_core = 0; l_core < PGP_NCORES; l_core++, l_configured_cores <<= 1)
-        {
-            if(!(l_configured_cores & 0x80000000)) continue;
-            l_pmgp1.value = 0;
-            l_pmgp1.fields.dpll_freq_override_enable = 1;
-            l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_AND, l_core),
-                           ~l_pmgp1.value, NULL); //commit errors internally
-            if(l_rc)
-            {
-                TRAC_ERR("Failed disabling dpll frequency override.  rc=0x%08x, core=%d", l_rc, l_core);
-                break;
-            }
-        }
-        if(!l_rc)
-        {
-
-            // Set the actual STATE now that we have finished everything else
-            CURRENT_STATE() = OCC_STATE_ACTIVE;
-            TRAC_IMP("SMGR: Observation to Active Transition Completed");
-
-            // Configure and enable the PCB slave heartbeat timer
-            //
-            // task_core_data is running in every RTL tick and scheduling a run
-            // of gpe_get_per_core_data which will do a getscom on
-            // PCBS_PMSTATEHISTOCC_REG.  We will use PCBS_PMSTATEHISTOCC_REG as
-            // the PCBS heartbeat trigger register.
-            unsigned int l_actual_pcbs_hb_time = 0;
-            ChipConfigCores l_cfgd_cores =
-                    (ChipConfigCores)((uint64_t)core_configuration() >> 16);
-            TRAC_IMP("Configuring PCBS heartbeat for configured cores=0x%8.8x", l_cfgd_cores);
-            TRAC_IMP("OCC configuration view: G_present_hw_cores=0x%8.8x, G_present_cores=0x%8.8x",
-                    G_present_hw_cores, G_present_cores);
-
-            // Setup the pcbs heartbeat timer
-            l_rc = pcbs_hb_config(1, // enable = yes
-                                  l_cfgd_cores,
-                                  PCBS_PMSTATEHISTOCC_REG,
-                                  PCBS_HEARBEAT_TIME_US,
-                                  0, // force = no
-                                  &l_actual_pcbs_hb_time);
-
-            if (l_rc)
-            {
-                TRAC_ERR("Failure configuring the PCBS heartbeat timer, rc=%d",
-                         l_rc);
-                // FIXME #state_c_002 Add appropriate callouts for
-                // serviceability review
-                l_extRc = ERC_STATE_HEARTBEAT_CFG_FAILURE;
-            }
-            else
-            {
-                TRAC_IMP("PCBS heartbeat enabled, requested time(us)=%d, actual time(us)=%d",
-                         PCBS_HEARBEAT_TIME_US,
-                         l_actual_pcbs_hb_time);
-            }
-
-            // TODO: #state_c_001 Manually configuring the PMC
-            // heartbeat until pmc_hb_config is shown to be working
-            // Reference SW238882 for more information on updates needed in
-            // pmc_hb_config.  Note that if PMC parameter hangpulse pre-divider
-            // is 0 then the PMC heartbeat counter uses nest_nclck/4 instead of
-            // the hangpulse to count the heartbeat timeout.
-            pmc_parameter_reg0_t ppr0;
-            pmc_occ_heartbeat_reg_t pohr;
-            pohr.value = in32(PMC_OCC_HEARTBEAT_REG);
-            ppr0.value = in32(PMC_PARAMETER_REG0);
-            pohr.fields.pmc_occ_heartbeat_en = 0;
-            // This combined with the hang pulse count and pre-divider yields
-            // about a 2 second timeout
-            pohr.fields.pmc_occ_heartbeat_time = 0xffff;
-            TRAC_IMP("Configure PMC heartbeat, heartbeat_time=0x%x",
-                    pohr.fields.pmc_occ_heartbeat_time);
-            ppr0.fields.hangpulse_predivider = 1;
-            TRAC_IMP("Configure PMC parm reg predivider=%d",
-                    ppr0.fields.hangpulse_predivider);
-
-            // Write registers twice, known issue with heartbeat reg
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-            out32(PMC_PARAMETER_REG0, ppr0.value);
-            out32(PMC_PARAMETER_REG0, ppr0.value);
-            TRAC_IMP("Enable PMC heartbeat timer");
-            pohr.value = in32(PMC_OCC_HEARTBEAT_REG);
-            pohr.fields.pmc_occ_heartbeat_en = 1;
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-            out32(PMC_OCC_HEARTBEAT_REG, pohr.value);
-        }
-    }
-    else
-    {
-        //trace and log an error.
-        l_rc = -1;
+        // Set the actual STATE now that we have finished everything else
+        CURRENT_STATE() = OCC_STATE_ACTIVE;
+        TRAC_IMP("SMGR: Observation to Active Transition Completed");
     }
-
-    if(l_rc)
+    else if(l_rc)
     {
         TRAC_ERR("SMGR: Observation to Active Transition Failed, cnfgdata=0x%08x, reqd=0x%08x",
                 DATA_get_present_cnfgdata(),
                 SMGR_VALIDATE_DATA_ACTIVE_MASK);
     }
 
-
     if(l_rc && FALSE == l_error_logged)
     {
         l_error_logged = TRUE;
@@ -419,7 +321,6 @@ errlHndl_t SMGR_observation_to_active()
                  ERRL_COMPONENT_ID_FIRMWARE,
                  ERRL_CALLOUT_PRIORITY_HIGH);
     }
-#endif
     return l_errlHndl;
 }
 
diff --git a/src/occ_405/topfiles.mk b/src/occ_405/topfiles.mk
index 807e4de..87693db 100644
--- a/src/occ_405/topfiles.mk
+++ b/src/occ_405/topfiles.mk
@@ -22,12 +22,14 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-TOP-C-SOURCES = amec/amec_data.c \
+TOP-C-SOURCES = amec/amec_controller.c \
+                amec/amec_data.c \
                 amec/amec_freq.c \
                 amec/amec_health.c \
                 amec/amec_init.c \
                 amec/amec_amester.c \
                 amec/amec_master_smh.c \
+                amec/amec_oversub.c \
                 amec/amec_parm.c \
                 amec/amec_pcap.c \
                 amec/amec_parm_table.c \
@@ -68,6 +70,7 @@ TOP-C-SOURCES = amec/amec_data.c \
                 proc/proc_data.c \
                 proc/proc_pstate.c \
                 pss/apss.c \
+                pss/dpss.c \
                 reset.c \
                 rtls/rtls_tables.c \
                 rtls/rtls.c \