diff options
| author | Sooraj Nair <soonair3@in.ibm.com> | 2018-01-04 01:06:45 -0600 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2018-01-09 14:38:07 -0500 |
| commit | d868b77dfc6afd90d4fea874ae4a1175fffffaed (patch) | |
| tree | 7cefa349083c2a007886f4e22e15eb6b2727d854 | |
| parent | c358181383374e84976982ac8d650db358a32c08 (diff) | |
| download | talos-occ-d868b77dfc6afd90d4fea874ae4a1175fffffaed.tar.gz talos-occ-d868b77dfc6afd90d4fea874ae4a1175fffffaed.zip | |
nvlink,xlink,phb fixes
Change-Id: Ied42068958a941cfac9973c889a080865e37d0e0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51445
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
| -rw-r--r-- | src/occ_gpe1/gpe1_24x7.c | 502 | ||||
| -rwxr-xr-x | src/occ_gpe1/gpe1_24x7.h | 187 |
2 files changed, 438 insertions, 251 deletions
diff --git a/src/occ_gpe1/gpe1_24x7.c b/src/occ_gpe1/gpe1_24x7.c index 219f387..a2342ca 100644 --- a/src/occ_gpe1/gpe1_24x7.c +++ b/src/occ_gpe1/gpe1_24x7.c @@ -1,27 +1,27 @@ -/* IBM_PROLOG_BEGIN_TAG */
-/* This is an automatically generated prolog. */
-/* */
-/* $Source: src/occ_gpe1/gpe1_24x7.c $ */
-/* */
-/* OpenPOWER OnChipController Project */
-/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2017 */
-/* [+] International Business Machines Corp. */
-/* */
-/* */
-/* Licensed under the Apache License, Version 2.0 (the "License"); */
-/* you may not use this file except in compliance with the License. */
-/* You may obtain a copy of the License at */
-/* */
-/* http://www.apache.org/licenses/LICENSE-2.0 */
-/* */
-/* Unless required by applicable law or agreed to in writing, software */
-/* distributed under the License is distributed on an "AS IS" BASIS, */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
-/* implied. See the License for the specific language governing */
-/* permissions and limitations under the License. */
-/* */
-/* IBM_PROLOG_END_TAG */
+/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ_gpe1/gpe1_24x7.c $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #include "pk.h"
#include "pk_app_cfg.h"
@@ -47,8 +47,8 @@ *
* End Function Specification
*/
-uint8_t G_test_array_24x7[100];
-uint64_t* test_addr = (uint64_t*) (TEST_ADDR | PBA_ENABLE);
+//uint8_t G_test_array_24x7[100];
+//uint64_t* test_addr = (uint64_t*) (TEST_ADDR | PBA_ENABLE);
void gpe_24x7(ipc_msg_t* cmd, void* arg)
{
// Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it.
@@ -56,6 +56,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) // to the gpe_24x7_args_t struct.
int rc = 0;
+ int iter = 0;
ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
gpe_24x7_args_t *args = (gpe_24x7_args_t*)async_cmd->cmd_data;
@@ -71,6 +72,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) static uint8_t L_DELAY_7 = 0;
static uint8_t L_CUR_DELAY = 0;
static uint64_t L_cur_speed = 0;
+ static uint64_t L_prev_status = 0;
//
static bool L_configure = false;
static bool L_DONT_RUN = false;
@@ -84,12 +86,13 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) static volatile uint64_t* L_speed = (uint64_t*) (CNTL_SPEED_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_uav = (uint64_t*) (CNTL_UAV_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_mode = (uint64_t*) (CNTL_MODE_OFFSET | PBA_ENABLE);
+ static volatile uint64_t* L_mode_state = (uint64_t*) (CNTL_MODE_STATE_OFFSET | PBA_ENABLE);
//
+ static volatile uint64_t* L_version = (uint64_t*) (DBG_VER_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_tics_exceded = (uint64_t*) (DBG_TICS_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_marker = (uint64_t*) (DBG_MARK | PBA_ENABLE);
static volatile uint64_t* L_DBG_ITER = (uint64_t*) (DBG_ITER | PBA_ENABLE);
volatile uint8_t* L_DBG_STATE = (uint8_t*) (DBG_STATE | PBA_ENABLE);
- //
//uint64_t temp;
args->error.error = 0; // default success
args->error.ffdc = 0;
@@ -107,7 +110,8 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) initialize_postings();
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
-
+ //set code version
+ *L_version = VERSION;
//set status as initializing
*L_status = CNTL_STATUS_INIT;
//initialize cmd to NOP
@@ -120,7 +124,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) set_speed(&L_cur_speed,&L_CUR_DELAY,L_status);
//check if mode is set to monitor
//support for debug modes (flexible IMA) not present currently.
- if(*L_mode != CNTL_MODE_MONITOR)
+ if((*L_mode != CNTL_MODE_MONITOR)&&(*L_mode != CNTL_MODE_DEBUG1))
*L_status = CNTL_STATUS_ERR2;
//set Dont run if the speed and mode info is not set to legal values.
if( (*L_status == CNTL_STATUS_ERR1)||(*L_status == CNTL_STATUS_ERR2) )
@@ -144,6 +148,11 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) *L_status = CNTL_STATUS_PAUSE;
*L_cmd = CNTL_CMD_NOP;
PK_TRACE("gpe_24x7: in CNTL_CMD_PAUSE");
+ for(iter = 0;iter < 24;iter++)
+ {
+ G_PHB_pmulets[iter] = 0;
+ G_MBA_pmulets[iter] = 0;
+ }
break;
case CNTL_CMD_RESUME:
L_DONT_RUN = false;
@@ -161,16 +170,32 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) }
//3.get any new speed setting
if (*L_speed != L_cur_speed)
- {
+ {
L_INIT = true;
PK_TRACE("gpe_24x7: speed change, L_INIT set to true");
- }
+ set_speed(&L_cur_speed,&L_CUR_DELAY,L_status);
+ }
//4.check for any system config changes via uav
if (*L_uav != G_CUR_UAV)
{
L_INIT = true;
L_PART_INIT = true;
}
+//5.check for mode change
+ if (*L_mode != G_CUR_MODE)
+ {
+ L_INIT = true;
+ L_prev_status = *L_status;
+ L_PART_INIT = true;
+ L_DONT_RUN = false;
+ PK_TRACE("gpe_24x7: mode change, L_INIT set to true");
+ }
+ //if(*L_mode != CNTL_MODE_MONITOR)//&&(*L_mode != CNTL_MODE_DEBUG1))
+ if((*L_mode != CNTL_MODE_MONITOR)&&(*L_mode != CNTL_MODE_DEBUG1))
+ *L_status = CNTL_STATUS_ERR2;
+ //set Dont run if the speed and mode info is not set to legal values.
+ if( (*L_status == CNTL_STATUS_ERR1)||(*L_status == CNTL_STATUS_ERR2) )
+ L_DONT_RUN = true;
//initialize postings if required from new cmd or change of speed or UAV change.
if (L_INIT)
{
@@ -185,6 +210,7 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) L_configure = true;
L_cur_speed = *L_speed;
G_CUR_UAV = *L_uav;
+ G_CUR_MODE = *L_mode;
//SW399904 patch until HWP output for UAV is debugged.
//G_CUR_UAV = CNTL_UAV_TEMP;
*L_marker = MARKER1;
@@ -287,6 +313,15 @@ void gpe_24x7(ipc_msg_t* cmd, void* arg) configure_pmu(L_current_state, L_cur_speed);
L_configure = false;
*L_status = CNTL_STATUS_RUN;
+ //*L_status = L_prev_status;
+ if(L_prev_status == CNTL_STATUS_PAUSE)
+ {
+ L_DONT_RUN = true;
+ *L_status = L_prev_status;
+ }
+ *L_mode_state = G_CUR_MODE;
+ //*L_mode = 0;
+ L_prev_status = 0;
}
else
{
@@ -435,9 +470,9 @@ void configure_pmu(uint8_t state, uint64_t speed) continue;
else if( (i==7) && !(G_CUR_UAV & MASK_MBA7) )
continue;
- else if( ((i==8)||(i==9)||(i==10)||(i==11)) && (!(G_CUR_UAV & MASK_MBA4)||!(G_CUR_UAV & MASK_MBA5)) )
+ else if( ((i==8)||(i==9)||(i==10)||(i==11)) && (!(G_CUR_UAV & MASK_MBA4)) && (!(G_CUR_UAV & MASK_MBA5)) )
continue;
- else if( ((i==12)||(i==13)||(i==14)||(i==15)) && (!(G_CUR_UAV & MASK_MBA6)||!(G_CUR_UAV & MASK_MBA7)) )
+ else if( ((i==12)||(i==13)||(i==14)||(i==15)) && (!(G_CUR_UAV & MASK_MBA6)) && (!(G_CUR_UAV & MASK_MBA7)) )
continue;
else if( (i==16) && !(G_CUR_UAV & MASK_MBA0) )
continue;
@@ -447,11 +482,11 @@ void configure_pmu(uint8_t state, uint64_t speed) continue;
else if( (i==19) && !(G_CUR_UAV & MASK_MBA3) )
continue;
- else if( ((i==20)||(i==21)||(i==22)||(i==23)) && (!(G_CUR_UAV & MASK_MBA0)||!(G_CUR_UAV & MASK_MBA1)) )
+ else if( ((i==20)||(i==21)||(i==22)||(i==23)) && (!(G_CUR_UAV & MASK_MBA0)) && (!(G_CUR_UAV & MASK_MBA1)) )
continue;
- else if( ((i==24)||(i==25)||(i==26)||(i==27)) && (!(G_CUR_UAV & MASK_MBA2)||!(G_CUR_UAV & MASK_MBA3)) )
+ else if( ((i==24)||(i==25)||(i==26)||(i==27)) && (!(G_CUR_UAV & MASK_MBA2)) && (!(G_CUR_UAV & MASK_MBA3)) )
continue;
- else if( (i==28) && ((!(G_CUR_UAV & MASK_XLNK0))||(!(G_CUR_UAV & MASK_XLNK1))||(!(G_CUR_UAV & MASK_XLNK2))) )
+ else if( (i==28) && ((!(G_CUR_UAV & MASK_XLNK0)) && (!(G_CUR_UAV & MASK_XLNK1)) && (!(G_CUR_UAV & MASK_XLNK2))) )
continue;
else if( ((i==29)||(i==30)||(i==31)||(i==32)) && !(G_CUR_UAV & MASK_NX) )
continue;
@@ -467,8 +502,8 @@ void configure_pmu(uint8_t state, uint64_t speed) continue;
else if( (i==38) && !(G_CUR_UAV & MASK_NVLNK5) )
continue;
- else if( ((i==39)||(i==40)) && (!(G_CUR_UAV & MASK_NVLNK5)||!(G_CUR_UAV & MASK_NVLNK4)||!(G_CUR_UAV & MASK_NVLNK3)||
- !(G_CUR_UAV & MASK_NVLNK2)||!(G_CUR_UAV & MASK_NVLNK1)||!(G_CUR_UAV & MASK_NVLNK0)) )
+ else if( ((i==39)||(i==40)) && (!(G_CUR_UAV & MASK_NVLNK5)) && (!(G_CUR_UAV & MASK_NVLNK4)) && (!(G_CUR_UAV & MASK_NVLNK3)) &&
+ (!(G_CUR_UAV & MASK_NVLNK2)) && (!(G_CUR_UAV & MASK_NVLNK1)) && (!(G_CUR_UAV & MASK_NVLNK0)) )
continue;
else if( (i==41) && !(G_CUR_UAV & MASK_PHB0) )
continue;
@@ -482,11 +517,11 @@ void configure_pmu(uint8_t state, uint64_t speed) continue;
else if( (i==46) && !(G_CUR_UAV & MASK_PHB5) )
continue;
- else if( (i==47) && (!(G_CUR_UAV & MASK_NVLNK1)||!(G_CUR_UAV & MASK_NVLNK0)) )
+ else if( (i==47) && (!(G_CUR_UAV & MASK_NVLNK1)) && (!(G_CUR_UAV & MASK_NVLNK0)) )
continue;
- else if( (i==48) && (!(G_CUR_UAV & MASK_NVLNK3)||!(G_CUR_UAV & MASK_NVLNK2)) )
+ else if( (i==48) && (!(G_CUR_UAV & MASK_NVLNK3)) && (!(G_CUR_UAV & MASK_NVLNK2)) )
continue;
- else if( (i==49) && (!(G_CUR_UAV & MASK_NVLNK5)||!(G_CUR_UAV & MASK_NVLNK4)) )
+ else if( (i==49) && (!(G_CUR_UAV & MASK_NVLNK5)) && (!(G_CUR_UAV & MASK_NVLNK4)) )
continue;
else if( ((i==50)||(i==51)||(i==52)||(i==53)) && !(G_CUR_UAV & MASK_CAPP0) )
continue;
@@ -518,9 +553,14 @@ void post_pmu_events(int grp) static int L_phb_events =0;
static volatile uint64_t* L_DBG_GRP = (uint64_t*) (DBG_GRP_OFFSET | PBA_ENABLE);
static volatile uint64_t* L_DBG_UNIT = (uint64_t*) (DBG_UNIT_OFFSET | PBA_ENABLE);
- static uint64_t L_PHB_pmulets[24];
- static uint64_t L_MBA_pmulets[16];
+ //static volatile uint64_t* L_DBG_4 = (uint64_t*) (DBG_4 | PBA_ENABLE);
+ //static volatile uint64_t* L_DBG_5 = (uint64_t*) (DBG_5 | PBA_ENABLE);
+ //static volatile uint64_t* L_DBG_6 = (uint64_t*) (DBG_6 | PBA_ENABLE);
+ //static volatile uint64_t* L_DBG_7 = (uint64_t*) (DBG_7 | PBA_ENABLE);
+ //static uint64_t L_PHB_pmulets[24];
+ //static uint64_t L_MBA_pmulets[24];
uint64_t temp;
+ volatile uint64_t temp1;
//union to split a pmulet containg 4 counters into its constituents.
union u1
{
@@ -530,9 +570,19 @@ void post_pmu_events(int grp) } ev;
uint64_t pmulet;
} u3;
+
+ union u_mba
+ {
+ struct event_mba
+ {
+ uint32_t e[2];
+ } ev;
+ uint64_t pmulet;
+ } u3_mba;
int i=0,j=0,phb_epoch=0;
uint64_t TOD;
+ int iter=0, ev_count=0;
post_addr = (uint64_t*) (POSTING_START | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
//FIXME:restricting groups for test on witherspoon
@@ -543,7 +593,10 @@ void post_pmu_events(int grp) //switch(test_grp)
{
case G1://cnpm group - always written
- post_addr = (uint64_t*) (POST_OFFSET_G1H | PBA_ENABLE);
+ if(G_CUR_MODE == CNTL_MODE_MONITOR)
+ post_addr = (uint64_t*) (POST_OFFSET_G1H | PBA_ENABLE);
+ else if(G_CUR_MODE == CNTL_MODE_DEBUG1)
+ post_addr = (uint64_t*) (POST_OFFSET_DBG1H | PBA_ENABLE);
*L_DBG_GRP = 1;
*L_DBG_UNIT = 1;
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
@@ -558,7 +611,10 @@ void post_pmu_events(int grp) post_addr++;
}
}
- post_addr = (uint64_t*) (POST_OFFSET_G1T | PBA_ENABLE);
+ if(G_CUR_MODE == CNTL_MODE_MONITOR)
+ post_addr = (uint64_t*) (POST_OFFSET_G1T | PBA_ENABLE);
+ else if(G_CUR_MODE == CNTL_MODE_DEBUG1)
+ post_addr = (uint64_t*) (POST_OFFSET_DBG1T | PBA_ENABLE);
*post_addr = INC_UPD_COUNT;
break;
case G2://XLINKS and NX. Read scoms based on availability.
@@ -567,7 +623,7 @@ void post_pmu_events(int grp) putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
*post_addr = INC_UPD_COUNT;
post_addr++;
- if (G_CUR_UAV & MASK_XLNK1)
+ if ((G_CUR_UAV & MASK_XLNK0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
@@ -586,7 +642,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_XLNK0)
+ if ((G_CUR_UAV & MASK_XLNK1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
@@ -605,7 +661,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_XLNK2)
+ if ((G_CUR_UAV & MASK_XLNK2) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
@@ -624,7 +680,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NX)
+ if ((G_CUR_UAV & MASK_NX) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
@@ -652,7 +708,7 @@ void post_pmu_events(int grp) putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
*post_addr = INC_UPD_COUNT;
post_addr++;
- if (G_CUR_UAV & MASK_NVLNK0)
+ if ((G_CUR_UAV & MASK_NVLNK0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
@@ -665,7 +721,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NVLNK1)
+ if ((G_CUR_UAV & MASK_NVLNK1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
@@ -678,7 +734,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NVLNK2)
+ if ((G_CUR_UAV & MASK_NVLNK2) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
@@ -691,7 +747,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NVLNK3)
+ if ((G_CUR_UAV & MASK_NVLNK3) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
@@ -704,7 +760,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NVLNK4)
+ if ((G_CUR_UAV & MASK_NVLNK4) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 5;
@@ -717,7 +773,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_NVLNK5)
+ if ((G_CUR_UAV & MASK_NVLNK5) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 6;
@@ -730,8 +786,8 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if ((G_CUR_UAV & MASK_NVLNK0)||(G_CUR_UAV & MASK_NVLNK1)||(G_CUR_UAV & MASK_NVLNK2)||
- (G_CUR_UAV & MASK_NVLNK3)||(G_CUR_UAV & MASK_NVLNK4)||(G_CUR_UAV & MASK_NVLNK5) )
+ if ( ((G_CUR_UAV & MASK_NVLNK0) > 0) || ((G_CUR_UAV & MASK_NVLNK1) > 0) || ((G_CUR_UAV & MASK_NVLNK2) > 0)||
+ ((G_CUR_UAV & MASK_NVLNK3) > 0) || ((G_CUR_UAV & MASK_NVLNK4) > 0) || ((G_CUR_UAV & MASK_NVLNK5) > 0) )
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 7;
@@ -771,7 +827,7 @@ void post_pmu_events(int grp) switch(phb_epoch)
{
case 0:
- if (G_CUR_UAV & MASK_PHB0)
+ if ((G_CUR_UAV & MASK_PHB0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
@@ -780,8 +836,12 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4a[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
@@ -790,7 +850,7 @@ void post_pmu_events(int grp) L_phb_events += 4;
- if (G_CUR_UAV & MASK_PHB1)
+ if ((G_CUR_UAV & MASK_PHB1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
@@ -799,17 +859,22 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4b[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
}
else
L_phb_events += 4;
+
break;
case 1:
- if (G_CUR_UAV & MASK_PHB2)
+ if ((G_CUR_UAV & MASK_PHB2) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
@@ -818,15 +883,20 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4c[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
}
else
L_phb_events += 4;
- if (G_CUR_UAV & MASK_PHB3)
+
+ if ((G_CUR_UAV & MASK_PHB3) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
@@ -835,17 +905,22 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4d[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
}
else
L_phb_events += 4;
+
break;
case 2:
- if (G_CUR_UAV & MASK_PHB4)
+ if ((G_CUR_UAV & MASK_PHB4) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 5;
@@ -854,15 +929,19 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4e[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
}
else
L_phb_events += 4;
- if (G_CUR_UAV & MASK_PHB5)
+ if ((G_CUR_UAV & MASK_PHB5) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 6;
@@ -871,8 +950,12 @@ void post_pmu_events(int grp) for(i=0; i<4; i++)
{
getscom_abs(G_PMULETS_4f[i], &temp);
- L_PHB_pmulets[L_phb_events] = temp - L_PHB_pmulets[L_phb_events];
- *post_addr = L_PHB_pmulets[L_phb_events];
+ temp >>=16;
+ temp1 = temp;
+ temp = get_phb_event(temp, G_PHB_pmulets[L_phb_events] );
+ if(G_PHB_pmulets[L_phb_events] != 0)
+ *post_addr = temp;
+ G_PHB_pmulets[L_phb_events] = temp1;
post_addr++;
L_phb_events++;
}
@@ -890,61 +973,117 @@ void post_pmu_events(int grp) putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
*post_addr = INC_UPD_COUNT;
post_addr++;
- if (G_CUR_UAV & MASK_MBA0)
+ if ((G_CUR_UAV & MASK_MBA0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G5_1 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_5[0], &temp);
- L_MBA_pmulets[0] = temp - L_MBA_pmulets[0];
- *post_addr = L_MBA_pmulets[0];
- post_addr++;
- getscom_abs(G_PMULETS_5[1], &temp);
- L_MBA_pmulets[1] = temp - L_MBA_pmulets[1];
- *post_addr = L_MBA_pmulets[1];
+ getscom_abs(G_PMULETS_5[0], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=0;iter<2;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_5[1], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[2]);
+ if(G_MBA_pmulets[2] != 0)
+ *post_addr = temp<<1;//needs scaling by 2;
+ G_MBA_pmulets[2] = temp1;
}
- if (G_CUR_UAV & MASK_MBA1)
+ if ((G_CUR_UAV & MASK_MBA1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
post_addr = (uint64_t*) (POST_OFFSET_G5_2 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_5[2], &temp);
- L_MBA_pmulets[2] = temp - L_MBA_pmulets[2];
- *post_addr = L_MBA_pmulets[2];
- post_addr++;
- getscom_abs(G_PMULETS_5[3], &temp);
- L_MBA_pmulets[3] = temp - L_MBA_pmulets[3];
- *post_addr = L_MBA_pmulets[3];
+ getscom_abs(G_PMULETS_5[2], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=3;iter<5;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_5[3], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[5]);
+ if(G_MBA_pmulets[5] != 0)
+ *post_addr = temp<<1;//needs scaling by 2;
+ G_MBA_pmulets[5] = temp1;
}
- if (G_CUR_UAV & MASK_MBA2)
+ if ((G_CUR_UAV & MASK_MBA2) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
post_addr = (uint64_t*) (POST_OFFSET_G5_3 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_5[4], &temp);
- L_MBA_pmulets[4] = temp - L_MBA_pmulets[4];
- *post_addr = L_MBA_pmulets[4];
- post_addr++;
- getscom_abs(G_PMULETS_5[5], &temp);
- L_MBA_pmulets[5] = temp - L_MBA_pmulets[5];
- *post_addr = L_MBA_pmulets[5];
+ getscom_abs(G_PMULETS_5[4], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=6;iter<8;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_5[5], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[8]);
+ if(G_MBA_pmulets[8] != 0)
+ *post_addr = temp<<1;//needs scaling by 2;
+ G_MBA_pmulets[8] = temp1;
}
- if (G_CUR_UAV & MASK_MBA3)
+ if ((G_CUR_UAV & MASK_MBA3) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
post_addr = (uint64_t*) (POST_OFFSET_G5_4 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_5[6], &temp);
- L_MBA_pmulets[6] = temp - L_MBA_pmulets[6];
- *post_addr = L_MBA_pmulets[6];
- post_addr++;
- getscom_abs(G_PMULETS_5[7], &temp);
- L_MBA_pmulets[7] = temp - L_MBA_pmulets[7];
- *post_addr = L_MBA_pmulets[7];
+ getscom_abs(G_PMULETS_5[6], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=9;iter<11;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_5[7], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[11]);
+ if(G_MBA_pmulets[11] != 0)
+ *post_addr = temp<<1;//needs scaling by 2;
+ G_MBA_pmulets[11] = temp1;
}
post_addr = (uint64_t*) (POST_OFFSET_G5T | PBA_ENABLE);
*post_addr = INC_UPD_COUNT;
@@ -955,61 +1094,117 @@ void post_pmu_events(int grp) putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
*post_addr = INC_UPD_COUNT;
post_addr++;
- if (G_CUR_UAV & MASK_MBA4)
+ if ((G_CUR_UAV & MASK_MBA4) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
post_addr = (uint64_t*) (POST_OFFSET_G6_1 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_6[0], &temp);
- L_MBA_pmulets[8] = temp - L_MBA_pmulets[8];
- *post_addr = L_MBA_pmulets[8];
- post_addr++;
- getscom_abs(G_PMULETS_6[1], &temp);
- L_MBA_pmulets[9] = temp - L_MBA_pmulets[9];
- *post_addr = L_MBA_pmulets[9];
+ getscom_abs(G_PMULETS_6[0], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=12;iter<14;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_6[1], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[14]);
+ if(G_MBA_pmulets[14] != 0)
+ *post_addr = temp<<1;//needs scaling by 2;
+ G_MBA_pmulets[14] = temp1;
}
- if (G_CUR_UAV & MASK_MBA5)
+ if ((G_CUR_UAV & MASK_MBA5) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
post_addr = (uint64_t*) (POST_OFFSET_G6_2 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_6[2], &temp);
- L_MBA_pmulets[10] = temp - L_MBA_pmulets[10];
- *post_addr = L_MBA_pmulets[10];
- post_addr++;
- getscom_abs(G_PMULETS_6[3], &temp);
- L_MBA_pmulets[11] = temp - L_MBA_pmulets[11];
- *post_addr = L_MBA_pmulets[11];
+ getscom_abs(G_PMULETS_6[2], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=15;iter<17;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_6[3], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[17]);
+ if(G_MBA_pmulets[17] != 0)
+ *post_addr = temp<<1;//needs scaling by 2
+ G_MBA_pmulets[17] = temp1;
}
- if (G_CUR_UAV & MASK_MBA6)
+ if ((G_CUR_UAV & MASK_MBA6) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
post_addr = (uint64_t*) (POST_OFFSET_G6_3 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_6[4], &temp);
- L_MBA_pmulets[12] = temp - L_MBA_pmulets[12];
- *post_addr = L_MBA_pmulets[12];
- post_addr++;
- getscom_abs(G_PMULETS_6[5], &temp);
- L_MBA_pmulets[13] = temp - L_MBA_pmulets[13];
- *post_addr = L_MBA_pmulets[13];
+ getscom_abs(G_PMULETS_6[4], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=18;iter<20;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_6[5], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[20]);
+ if(G_MBA_pmulets[20] != 0)
+ *post_addr = temp<<1;//needs scaling by 2
+ G_MBA_pmulets[20] = temp1;
}
- if (G_CUR_UAV & MASK_MBA7)
+ if ((G_CUR_UAV & MASK_MBA7) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
post_addr = (uint64_t*) (POST_OFFSET_G6_4 | PBA_ENABLE);
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
- getscom_abs(G_PMULETS_6[6], &temp);
- L_MBA_pmulets[14] = temp - L_MBA_pmulets[14];
- *post_addr = L_MBA_pmulets[14];
- post_addr++;
- getscom_abs(G_PMULETS_6[7], &temp);
- L_MBA_pmulets[15] = temp - L_MBA_pmulets[15];
- *post_addr = L_MBA_pmulets[15];
+ getscom_abs(G_PMULETS_6[6], &u3_mba.pmulet);
+ ev_count = 0;
+ for(iter=21;iter<23;iter++)
+ {
+ temp = u3_mba.ev.e[ev_count];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[iter]);
+ if(G_MBA_pmulets[iter] != 0)
+ *post_addr = temp;
+ G_MBA_pmulets[iter] = temp1;
+ post_addr++;
+ ev_count++;
+ }
+ //only first 32-bit counter is used to get cycles.
+ getscom_abs(G_PMULETS_6[7], &u3_mba.pmulet);
+ temp = u3_mba.ev.e[0];
+ temp1 = temp;
+ temp = get_mba_event(temp, G_MBA_pmulets[23]);
+ if(G_MBA_pmulets[23] != 0)
+ *post_addr = temp<<1;//needs scaling by 2
+ G_MBA_pmulets[23] = temp1;
}
post_addr = (uint64_t*) (POST_OFFSET_G6T | PBA_ENABLE);
*post_addr = INC_UPD_COUNT;
@@ -1020,7 +1215,7 @@ void post_pmu_events(int grp) putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_ATOMIC);
*post_addr = INC_UPD_COUNT;
post_addr++;
- if ((G_CUR_UAV & MASK_NVLNK0)||(G_CUR_UAV & MASK_NVLNK1))
+ if ( ((G_CUR_UAV & MASK_NVLNK0) > 0) || ((G_CUR_UAV & MASK_NVLNK1) > 0) )
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 1;
@@ -1033,7 +1228,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if ((G_CUR_UAV & MASK_NVLNK2)||(G_CUR_UAV & MASK_NVLNK3))
+ if ( ((G_CUR_UAV & MASK_NVLNK2) > 0) || ((G_CUR_UAV & MASK_NVLNK3) > 0) )
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 2;
@@ -1046,7 +1241,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if ((G_CUR_UAV & MASK_NVLNK4)||(G_CUR_UAV & MASK_NVLNK5))
+ if ( ((G_CUR_UAV & MASK_NVLNK4) > 0) || ((G_CUR_UAV & MASK_NVLNK5) > 0) )
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 3;
@@ -1059,7 +1254,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_CAPP0)
+ if ((G_CUR_UAV & MASK_CAPP0) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 4;
@@ -1078,7 +1273,7 @@ void post_pmu_events(int grp) post_addr++;
}
}
- if (G_CUR_UAV & MASK_CAPP1)
+ if ((G_CUR_UAV & MASK_CAPP1) > 0)
{
putscom_abs(PBASLVCTL3_C0040030, PBASLV_SET_DMA);
*L_DBG_UNIT = 5;
@@ -1169,3 +1364,22 @@ void set_speed(uint64_t* speed, uint8_t* delay, volatile uint64_t* status) break;
}
}
+
+uint64_t get_mba_event(uint64_t cur, uint64_t prev)
+{
+ if(cur >= prev)
+ prev = cur - prev;
+ else
+ prev = (MAX_32 - prev) + cur;
+ return prev;
+}
+
+uint64_t get_phb_event(uint64_t cur, uint64_t prev)
+{
+ if(cur >= prev)
+ prev = cur - prev;
+ else
+ prev = (MAX_48 - prev) + cur;
+ return prev;
+}
+
diff --git a/src/occ_gpe1/gpe1_24x7.h b/src/occ_gpe1/gpe1_24x7.h index 91d9cc5..4c53f14 100755 --- a/src/occ_gpe1/gpe1_24x7.h +++ b/src/occ_gpe1/gpe1_24x7.h @@ -1,27 +1,27 @@ -/* IBM_PROLOG_BEGIN_TAG */
-/* This is an automatically generated prolog. */
-/* */
-/* $Source: src/occ_gpe1/gpe1_24x7.h $ */
-/* */
-/* OpenPOWER OnChipController Project */
-/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2017 */
-/* [+] International Business Machines Corp. */
-/* */
-/* */
-/* Licensed under the Apache License, Version 2.0 (the "License"); */
-/* you may not use this file except in compliance with the License. */
-/* You may obtain a copy of the License at */
-/* */
-/* http://www.apache.org/licenses/LICENSE-2.0 */
-/* */
-/* Unless required by applicable law or agreed to in writing, software */
-/* distributed under the License is distributed on an "AS IS" BASIS, */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
-/* implied. See the License for the specific language governing */
-/* permissions and limitations under the License. */
-/* */
-/* IBM_PROLOG_END_TAG */
+/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/occ_gpe1/gpe1_24x7.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef _GPE1_24x7_H
#define _GPE1_24x7_H
@@ -34,18 +34,18 @@ #define TOTAL_CONFIG_SCOMS 60
#define TOTAL_COUNTER_SCOMS 71
//
+#define MAX_32 4294967295ULL
+#define MAX_48 281474976710655ULL
static volatile uint64_t G_CUR_UAV = 0;
+static volatile uint64_t G_CUR_MODE = 0;
+static volatile uint64_t G_MBA_pmulets[24];
+static volatile uint64_t G_PHB_pmulets[24];
uint64_t G_PMU_CONFIGS_8[][2] =
{
//cnpm//
- //{0x5011c13, 0x92aaaa82ac000bf8},//0
- //{0x5011c13, 0x92aaaaaaac002bf8},//0
{0x5011c13, 0x92aaaaaaac000bf8},//0
- //{0x5011c14, 0x92a8aaaaac000bf8},//1
- //{0x5011c14, 0x92a8aaaaac002bf8},//1
{0x5011c14, 0x92a8aaaaac000bf8},//1
{0x5011c15, 0xaaaaaaaaaaaaaaaa},//2
- //{0x5011c16, 0x0400c0ffffffff00},//3
{0x5011c16, 0x0400c0ff00ff0000},//3
//MC23//
{0x3010829, 0x0500000000000000},//port0//4
@@ -53,18 +53,12 @@ uint64_t G_PMU_CONFIGS_8[][2] = {0x30108a9, 0x0500000000000000},//port2//6
{0x30108b9, 0x0500000000000000},//port3//7
{0x301083c, 0x0000000000000000},//port0,1//8
- //{0x301083d, 0x0000000053457500},//port0,1//9
{0x301083d, 0x000000005345755b},//port0,1//9
- //{0x301083e, 0x0000000000000000},//port0,1//10
{0x301083e, 0x6471000000000000},//port0,1//10
- //{0x301083f, 0x00c0800000000000},//port0,1//11
{0x301083f, 0x00f0800000000000},//port0,1//11
{0x30108bc, 0x0000000000000000},//port2,3//12
- //{0x30108bd, 0x000000000000005b},//port2,3//13
{0x30108bd, 0x0000000000000000},//port2,3//13
- //{0x30108be, 0x64715345755b6000},//port2,3//14
{0x30108be, 0x00005345755b6000},//port2,3//14
- //{0x30108bf, 0x003e800000000000},//port2,3//15
{0x30108bf, 0x000e800000000000},//port2,3//15
//MC01//
{0x5010829, 0x0500000000000000},//port0//16
@@ -72,9 +66,7 @@ uint64_t G_PMU_CONFIGS_8[][2] = {0x50108a9, 0x0500000000000000},//port2//18
{0x50108b9, 0x0500000000000000},//port3//19
{0x501083c, 0x0000000000000000},//port0,1//20
- //{0x501083d, 0x0000000053457557},//port0,1//21
{0x501083d, 0x000000005345755b},//port0,1//21
- //{0x501083e, 0x5471000000000000},//port0,1//22
{0x501083e, 0x6471000000000000},//port0,1//22
{0x501083f, 0x00f0800000000000},//port0,1//23
{0x50108bc, 0x0000000000000000},//port2,3//24
@@ -82,28 +74,20 @@ uint64_t G_PMU_CONFIGS_8[][2] = {0x50108be, 0x00005345755b6000},//port2,3//26
{0x50108bf, 0x000e800000000000},//port2,3//27
//xlinks//
- {0x501341a, 0xff015daad55aa000},//all xlinks//28
+ {0x501341a, 0xff015daa15555000},//all xlinks//28
//nx//
- {0x20110a6, 0xcaa00000e0000000},//29
- {0x20110a9, 0xcaa04924f0000000},//30
+ {0x20110a6, 0xcaa0000080000000},//29
+ {0x20110a9, 0xcaa0492480000000},//30
{0x2011054, 0x0000000000000000},//31
{0x2011055, 0x00000000600002aa},//32
//nvlinks-NTL,ATS,XTS//
- //{0x501111e, 0x90aa01444f8a0000},//NTL0//33
- {0x501111e, 0xb0aa01444f8a0000},//NTL0//33
- //{0x501113e, 0x90aa01444f8a0000},//NTL1//34
- {0x501113e, 0xb0aa01444f8a0000},//NTL1//34
- //{0x501131e, 0x90aa01444f8a0000},//NTL2//35
- {0x501131e, 0xb0aa01444f8a0000},//NTL2//35
- //{0x501133e, 0x90aa01444f8a0000},//NTL3//36
- {0x501133e, 0xb0aa01444f8a0000},//NTL3//36
- //{0x501151e, 0x90aa01444f8a0000},//NTL4//37
- {0x501151e, 0xb0aa01444f8a0000},//NTL4//37
- //{0x501153e, 0x90aa01444f8a0000},//NTL5//38
- {0x501153e, 0xb0aa01444f8a0000},//NTL5//38
- //{0x5011600, 0x80aa420000000000},//ATS//39
+ {0x501111e, 0xb0aa0144868a0000},//NTL0//33
+ {0x501113e, 0xb0aa0144868a0000},//NTL1//34
+ {0x501131e, 0xb0aa0144868a0000},//NTL2//35
+ {0x501133e, 0xb0aa0144868a0000},//NTL3//36
+ {0x501151e, 0xb0aa0144868a0000},//NTL4//37
+ {0x501153e, 0xb0aa0144868a0000},//NTL5//38
{0x5011600, 0xb0aa420000000000},//ATS//39
- //{0x5011645, 0x80aa03050d0e0000},//XTS//40
{0x5011645, 0xb0aa03050d0e0000},//XTS//40
//PHB
{0xd010917, 0x8000011516190000},//PHB0//41
@@ -113,11 +97,8 @@ uint64_t G_PMU_CONFIGS_8[][2] = {0xf010957, 0x8000011516190000},//PHB4//45
{0xf010997, 0x8000011516190000},//PHB5//46
//nvlinks-NPCQ//
- //{0x50110C7, 0x80aa1012181a0000},//NPCQ01//47
{0x50110C7, 0x90aa1012181a0000},//NPCQ01//47
- //{0x50112C7, 0x80aa1012181a0000},//NPCQ02//48
{0x50112C7, 0x90aa1012181a0000},//NPCQ02//48
- //{0x50114C7, 0x80aa1012181a0000},//NPCQ03//49
{0x50114C7, 0x90aa1012181a0000},//NPCQ03//49
//CAPP
{0x2010814, 0x8058812200000000},//CAPP01//50
@@ -135,12 +116,9 @@ uint64_t G_PMU_CONFIGS_8[][2] = uint64_t G_PMU_CONFIGS_16[][2] =
{
//cnpm
- //{0x5011c13, 0x92aaaa82ac000bf8},//0
{0x5011c13, 0x92aaaaaaac000bf8},//0
- //{0x5011c14, 0x92a8aaaaac000bf8},//1
{0x5011c14, 0x92a8aaaaac000bf8},//1
{0x5011c15, 0x5555555555555555},//2
- //{0x5011c16, 0x0400c0ffffffff00},//3
{0x5011c16, 0x0400c0ff00ff0000},//3
//MC23//
{0x3010829, 0x0500000000000000},//port0//4
@@ -148,18 +126,12 @@ uint64_t G_PMU_CONFIGS_16[][2] = {0x30108a9, 0x0500000000000000},//port2//6
{0x30108b9, 0x0500000000000000},//port3//7
{0x301083c, 0x0000000000000000},//port0,1//8
- //{0x301083d, 0x0000000053457500},//port0,1//9
{0x301083d, 0x000000005345755b},//port0,1//9
- //{0x301083e, 0x0000000000000000},//port0,1//10
{0x301083e, 0x6471000000000000},//port0,1//10
- //{0x301083f, 0x00c0800000000000},//port0,1//11
{0x301083f, 0x00f0800000000000},//port0,1//11
{0x30108bc, 0x0000000000000000},//port2,3//12
- //{0x30108bd, 0x000000000000005b},//port2,3//13
{0x30108bd, 0x0000000000000000},//port2,3//13
- //{0x30108be, 0x64715345755b6000},//port2,3//14
{0x30108be, 0x00005345755b6000},//port2,3//14
- //{0x30108bf, 0x003e800000000000},//port2,3//15
{0x30108bf, 0x000e800000000000},//port2,3//15
//MC01//
{0x5010829, 0x0500000000000000},//port0//16
@@ -167,9 +139,7 @@ uint64_t G_PMU_CONFIGS_16[][2] = {0x50108a9, 0x0500000000000000},//port2//18
{0x50108b9, 0x0500000000000000},//port3//19
{0x501083c, 0x0000000000000000},//port0,1//20
- //{0x501083d, 0x0000000053457557},//port0,1//21
{0x501083d, 0x000000005345755b},//port0,1//21
- //{0x501083e, 0x5471000000000000},//port0,1//22
{0x501083e, 0x6471000000000000},//port0,1//22
{0x501083f, 0x00f0800000000000},//port0,1//23
{0x50108bc, 0x0000000000000000},//port2,3//24
@@ -177,28 +147,20 @@ uint64_t G_PMU_CONFIGS_16[][2] = {0x50108be, 0x00005345755b6000},//port2,3//26
{0x50108bf, 0x000e800000000000},//port2,3//27
//xlinks
- {0x501341a, 0xff015d55d55aa000},//all xlinks//28
+ {0x501341a, 0xff015d5515555000},//all xlinks//28
//nx
- {0x20110a6, 0xc5500000e0000000},//29
- {0x20110a9, 0xc5504924f0000000},//30
+ {0x20110a6, 0xc550000080000000},//29
+ {0x20110a9, 0xc550492480000000},//30
{0x2011054, 0x0000000000000000},//31
{0x2011055, 0x00000000600002aa},//32
//nvlinks-NTL,ATS,XTS//
- //{0x501111e, 0x805501444f8a0000},//NTL0//33
- {0x501111e, 0xb05501444f8a0000},//NTL0//33
- //{0x501113e, 0x805501444f8a0000},//NTL1//34
- {0x501113e, 0xb05501444f8a0000},//NTL1//34
- //{0x501131e, 0x805501444f8a0000},//NTL2//35
- {0x501131e, 0xb05501444f8a0000},//NTL2//35
- //{0x501133e, 0x805501444f8a0000},//NTL3//36
- {0x501133e, 0xb05501444f8a0000},//NTL3//36
- //{0x501151e, 0x805501444f8a0000},//NTL4//37
- {0x501151e, 0xb05501444f8a0000},//NTL4//37
- //{0x501153e, 0x805501444f8a0000},//NTL5//38
- {0x501153e, 0xb05501444f8a0000},//NTL5//38
- //{0x5011600, 0x8055420000000000},//ATS//39
+ {0x501111e, 0xb0550144868a0000},//NTL0//33
+ {0x501113e, 0xb0550144868a0000},//NTL1//34
+ {0x501131e, 0xb0550144868a0000},//NTL2//35
+ {0x501133e, 0xb0550144868a0000},//NTL3//36
+ {0x501151e, 0xb0550144868a0000},//NTL4//37
+ {0x501153e, 0xb0550144868a0000},//NTL5//38
{0x5011600, 0xb055420000000000},//ATS//39
- //{0x5011645, 0x805503050d0e0000},//XTS//40
{0x5011645, 0xb05503050d0e0000},//XTS//40
//PHB
{0xd010917, 0x8000011516190000},//PHB0//41
@@ -208,11 +170,8 @@ uint64_t G_PMU_CONFIGS_16[][2] = {0xf010957, 0x8000011516190000},//PHB4//45
{0xf010997, 0x8000011516190000},//PHB5//46
//nvlinks-NPCQ//
- //{0x50110C7, 0x80551012181a0000},//NPCQ01//47
{0x50110C7, 0x90551012181a0000},//NPCQ01//47
- //{0x50112C7, 0x80551012181a0000},//NPCQ02//48
{0x50112C7, 0x90551012181a0000},//NPCQ02//48
- //{0x50114C7, 0x80551012181a0000},//NPCQ03//49
{0x50114C7, 0x90551012181a0000},//NPCQ03//49
//CAPP
{0x2010814, 0x803840a100000000},//CAPP01//50
@@ -360,13 +319,10 @@ uint64_t G_PMULETS_6[] = uint64_t G_PMULETS_7[] =
{
//NPCQ01
- //0x5011086,//0//64
0x50110c6,//0//64
//NPCQ02
- //0x5011186,//1//65
0x50112c6,//1//65
//NPCQ03
- //0x5011286,//2//66
0x50114c6,//2//66
//CAPP01
0x2010815,//3//67
@@ -448,6 +404,11 @@ enum POST_OFFSET_G7_5 = 0x00180708,
POST_OFFSET_G7_6 = 0x00180748,
POST_OFFSET_G7T = 0x00180768,
+//DEBUG mode offsets start here
+ POSTING_START_DBG = 0x00190000,
+ POST_OFFSET_DBG1H = 0x00190000,
+ POST_OFFSET_DBG1T = 0x00190108,
+//
//CONTROL BLOCK FIELD OFFSETS
//cntl block @ last 1k of 24x7 space
CNTL_STATUS_OFFSET = 0x001BFC00,
@@ -455,22 +416,29 @@ enum CNTL_SPEED_OFFSET = 0x001BFC10,
CNTL_UAV_OFFSET = 0x001BFC18,
CNTL_MODE_OFFSET = 0x001BFC20,
+ CNTL_MODE_STATE_OFFSET = 0x001BFC28,
///////////////////////////////////////////////////
//error tracking fields(internal)
//last conf scom
- DBG_CONF_OFFSET = 0x001BFC40,
- DBG_GRP_OFFSET = 0x001BFC50,
- DBG_UNIT_OFFSET = 0x001BFC58,
- DBG_TICS_OFFSET = 0x001BFC60,
- DBG_MARK = 0x001AFC00,
- DBG_ITER = 0x001AFC08,
- DBG_STATE = 0x001AFC10,
- DBG_CONF_I = 0x001AFC18,
- DBG_UAV = 0x001AFC20,
- DBG_0 = 0x001AFC28,
- DBG_1 = 0x001AFC30,
- DBG_2 = 0x001AFC38,
- DBG_3 = 0x001AFC40,
+ DBG_VER_OFFSET = 0x001AFC00,
+ DBG_CONF_OFFSET = 0x001AFC08,
+ DBG_GRP_OFFSET = 0x001AFC10,
+ DBG_UNIT_OFFSET = 0x001AFC18,
+ DBG_TICS_OFFSET = 0x001AFC20,
+ DBG_MARK = 0x001AFC28,
+ DBG_ITER = 0x001AFC30,
+ DBG_STATE = 0x001AFC38,
+ DBG_CONF_I = 0x001AFC40,
+ DBG_UAV = 0x001AFC48,
+ DBG_0 = 0x001AFC50,
+ DBG_1 = 0x001AFC58,
+ DBG_2 = 0x001AFC60,
+ DBG_3 = 0x001AFC68,
+ DBG_4 = 0x001AFC70,
+ DBG_5 = 0x001AFC78,
+ DBG_6 = 0x001AFC80,
+ DBG_7 = 0x001AFC88,
+ DBG_8 = 0x001AFC90,
//////////////////////////////////////////////////
//cntl status values
CNTL_STATUS_INIT = 0x0,
@@ -496,14 +464,17 @@ enum CNTL_SPEED_512MS = 0x9,
CNTL_SPEED_1024MS = 0xA,
CNTL_SPEED_2048MS = 0xB,
- //cntl cmd uav temp
CNTL_UAV_TEMP = 0xFFFF8073F007E000,
- //CNTL_UAV_TEMP = 0xf800007000000000,
MARKER1 = 0xCAFEBABEFA11DEA1,
MARKER2 = 0xCAFEBABEFA11DEA2,
MARKER3 = 0xCAFEBABEFA11DEA3,
+ MARKER4 = 0xCAFEBABEFA11DEA4,
+ MARKER5 = 0xCAFEBABEFA11DEA5,
//cntl block modes
- CNTL_MODE_MONITOR = 0x0
+ CNTL_MODE_MONITOR = 0x0,
+ CNTL_MODE_DEBUG1 = 0x1,
+ //code version
+ VERSION = 0x0000000100000005
};
//MASKS used to identify individual units from Unit availability vector (UAV)
enum MASKS
@@ -567,4 +538,6 @@ void configure_pmu (uint8_t, uint64_t); void post_pmu_events (int);
void initialize_postings();
void set_speed(uint64_t*, uint8_t*, volatile uint64_t*);
+uint64_t get_mba_event(uint64_t, uint64_t);
+uint64_t get_phb_event(uint64_t, uint64_t);
#endif //_GPE1_24x7_H
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