talos-occ/src/occ_405/timer/timer.c, branch master

Prevent Nimbus tasks from running prior to knowing memory type

2018-04-02T13:34:43+00:00

Change-Id: I8c4a3566f111235a50066a06f3b4f9153f9fcd3b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56539 Tested-by: FSP CI Jenkins Reviewed-by: Christopher J. Cain Reviewed-by: Douglas R. Gilbert Reviewed-by: Martha Broyles

Memory Throttle Sensors

2018-03-27T15:57:42+00:00

RTC:131184 Change-Id: I2582a1eb9d599f700182f17047cc95accad03725 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51407 Tested-by: FSP CI Jenkins Reviewed-by: Andres A. Lugo-Reyes Reviewed-by: Martha Broyles Reviewed-by: William A. Bryan

Remove interrupt handlers for hardware errors

2017-11-08T22:42:16+00:00

Errors will be detected by the PGPE beacon. Change-Id: I2d24ec9becc319a1cf1fce6b06714ac638faade1 RTC: 134619 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49421 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: William A. Bryan Reviewed-by: Christopher J. Cain

Prevent PGPE IPC communication if all cores are deconfigured

2017-10-16T19:58:00+00:00

Change-Id: I7cea001833615dc3bcb6a282c20f205f1e7d9d87 CQ:SW401110 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46831 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: William A. Bryan Reviewed-by: Andres A. Lugo-Reyes

Re-enable PGPE beacon error detection

2017-05-30T19:04:56+00:00

Change-Id: I870baf3fc389995b8be30d489e531d131a7c84a0 RTC: 170963 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40611 Tested-by: FSP CI Jenkins Reviewed-by: Andres A. Lugo-Reyes Reviewed-by: William A. Bryan Reviewed-by: Christopher J. Cain

Remove antiquated PMC code

2017-05-15T15:57:05+00:00

Change-Id: I0a7e9fe5c854ce17602c4c0293fd59f8c4a7c7b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40419 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: Christopher J. Cain Reviewed-by: William A. Bryan

Enable PGPE support on hardware

2017-04-25T19:45:49+00:00

Change-Id: Id709ec36d82a2b6c03b1a4b901cf64f45f241d36 RTC: 163934 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39562 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: Andres A. Lugo-Reyes Reviewed-by: Christopher J. Cain

PGPE init updates

2017-04-13T18:07:15+00:00

Change-Id: I0140184371619983fb38b27199f241efe7f30f16 RTC: 169886 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37770 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan Reviewed-by: Martha Broyles Reviewed-by: Christopher J. Cain

Changes For P9 Enablement

2017-02-15T23:50:20+00:00

Change-Id: I37e8174bcc6e99f602a66cff077ef41ad889b19c RTC:165351 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34949 Tested-by: FSP CI Jenkins Reviewed-by: Andres A. Lugo-Reyes Reviewed-by: Christopher J. Cain Reviewed-by: Martha Broyles Reviewed-by: William A. Bryan

Pstates Support in OCC

2017-01-27T17:00:02+00:00

1. Initialize Pstates global parameters (G_proc_fmax, G_proc_fmin, G_khz_per_pstate and G_proc_pmin from the OCC Pstate Parameter Block) 2. When frequency config data packet is received and OCC is NOT already in Active state: Send IPC command to PGPE to set pState clips to be wide open from min frequency to turbo First verify min/max frequency from TMGT is within what PGPE allows saved in G_proc_fmax and G_proc_fmin if not within bounds trace and clip to G_proc_fmax/fmin) 3. Transition to active state: Send IPC command to PGPE to start pState protocol (give correct data for OCC vs OPAL in control of Pstates) and if OPAL system update OPAL shared memory with Pstate information. 4. amec_slv_freq_smh(): Send IPC command to PGPE to set requested pState (PowerVM) or set clips (OPAL). 5. Address all the TODO/TEMP/#if 0 in amec_freq.c either remove or add RTC# for when it will be addressed Change-Id: Ic323321b8c66945732a6b7345ad85d6f41a62edd RTC: 130201 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33704 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: Andres A. Lugo-Reyes Reviewed-by: Wael El-Essawy