1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
|
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _XOR_H
#define _XOR_H
#define SRAM_BASE 0x40000000
#include "ddr3_hws_hw_training_def.h"
#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
#define MV_XOR_MAX_CHAN 4 /* total channels for all units */
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
/*
* This structure describes address space window. Window base can be
* 64 bit, window size up to 4GB
*/
struct addr_win {
u32 base_low; /* 32bit base low */
u32 base_high; /* 32bit base high */
u32 size; /* 32bit size */
};
/* This structure describes SoC units address decode window */
struct unit_win_info {
struct addr_win addr_win; /* An address window */
int enable; /* Address decode window is enabled/disabled */
u8 attrib; /* chip select attributes */
u8 target_id; /* Target Id of this MV_TARGET */
};
/*
* This enumerator describes the type of functionality the XOR channel
* can have while using the same data structures.
*/
enum xor_type {
MV_XOR, /* XOR channel functions as XOR accelerator */
MV_DMA, /* XOR channel functions as IDMA channel */
MV_CRC32 /* XOR channel functions as CRC 32 calculator */
};
enum mv_state {
MV_IDLE,
MV_ACTIVE,
MV_PAUSED,
MV_UNDEFINED_STATE
};
/*
* This enumerator describes the set of commands that can be applied on
* an engine (e.g. IDMA, XOR). Appling a comman depends on the current
* status (see MV_STATE enumerator)
*
* Start can be applied only when status is IDLE
* Stop can be applied only when status is IDLE, ACTIVE or PAUSED
* Pause can be applied only when status is ACTIVE
* Restart can be applied only when status is PAUSED
*/
enum mv_command {
MV_START, /* Start */
MV_STOP, /* Stop */
MV_PAUSE, /* Pause */
MV_RESTART /* Restart */
};
enum xor_override_target {
SRC_ADDR0, /* Source Address #0 Control */
SRC_ADDR1, /* Source Address #1 Control */
SRC_ADDR2, /* Source Address #2 Control */
SRC_ADDR3, /* Source Address #3 Control */
SRC_ADDR4, /* Source Address #4 Control */
SRC_ADDR5, /* Source Address #5 Control */
SRC_ADDR6, /* Source Address #6 Control */
SRC_ADDR7, /* Source Address #7 Control */
XOR_DST_ADDR, /* Destination Address Control */
XOR_NEXT_DESC /* Next Descriptor Address Control */
};
enum mv_state mv_xor_state_get(u32 chan);
void mv_xor_hal_init(u32 xor_chan_num);
int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
int mv_xor_command_set(u32 chan, enum mv_command command);
int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
int enable);
#endif
|
