blob: f2b4177082c41f626ae958edc280057e683941f7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DDR3_TRAINING_LEVELING_H_
#define _DDR3_TRAINING_LEVELING_H_
#define MAX_DQ_READ_LEVELING_DELAY 15
int ddr3_tip_print_wl_supp_result(u32 dev_num);
int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
u32 *cs_mask);
u32 hws_ddr3_tip_max_cs_get(void);
#endif /* _DDR3_TRAINING_LEVELING_H_ */
|
