summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-uniphier/arm64/timer.c
blob: 4beab9dca87ca423439dd0466602f9af317e6419 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
/*
 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>

#define CNT_CONTROL_BASE	0x60E00000

#define CNTCR			0x000
#define   CNTCR_EN			BIT(0)

/* setup ARMv8 Generic Timer */
int timer_init(void)
{
	void __iomem *base;
	u32 tmp;

	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);

	/*
	 * Note:
	 * In a system that implements both Secure and Non-secure states,
	 * this register is only writable in Secure state.
	 */
	tmp = readl(base + CNTCR);
	tmp |= CNTCR_EN;
	writel(tmp, base + CNTCR);

	unmap_sysmem(base);

	return 0;
}
OpenPOWER on IntegriCloud