/* * (C) Copyright 2000-2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * SPDX-License-Identifier: GPL-2.0+ */ /* * board/config.h - configuration options, board specific */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...or on a SYCAMORE board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 /* * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME walnut #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \ "" #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_HAS_ETH0 1 #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ /* * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ /* * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. * The Linux BASE_BAUD define should match this configuration. * baseBaud = cpuClock/(uartDivisor*16) * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ #define PCI_HOST_FORCE 1 /* configure as pci host */ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) */ #define CONFIG_SYS_FLASH_BASE 0xFFF80000 /* * Define here the location of the environment variables (FLASH or NVRAM). * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only * supported for backward compatibility. */ #if 1 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif /*----------------------------------------------------------------------- * FLASH organization */ #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CONFIG_SYS_FLASH_ADDR0 0x5555 #define CONFIG_SYS_FLASH_ADDR1 0x2aaa #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- * NVRAM organization */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ #ifdef CONFIG_ENV_IS_IN_NVRAM #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ #endif /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ /* Memory Bank 0 (Flash Bank 0) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x9B015480 #define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ #define CONFIG_SYS_EBC_PB1AP 0x02815480 #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ #define CONFIG_SYS_EBC_PB2AP 0x04815A80 #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ #define CONFIG_SYS_EBC_PB3AP 0x01815280 #define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ #define CONFIG_SYS_EBC_PB7AP 0x01815280 #define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * External peripheral base address *----------------------------------------------------------------------- */ #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area */ #define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) */ #define SPD_EEPROM_ADDRESS 0x50 #endif /* __CONFIG_H */