/* * (C) Copyright 2013 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * Based on: * Copyright (c) 2011 IDS GmbH, Germany * Sergej Stepanov * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options */ #define CONFIG_MPC831x #define CONFIG_MPC8313 #define CONFIG_IDS8313 #define CONFIG_FSL_ELBC #define CONFIG_MISC_INIT_R #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN #define CONFIG_SYS_IMMR 0xF0000000 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ /* * Hardware Reset Configuration Word * if CLKIN is 66.000MHz, then * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz */ #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ HRCWL_DDR_TO_SCB_CLK_2X1 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1) #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_8BIT |\ HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_MII |\ HRCWH_TSEC2M_IN_MII |\ HRCWH_BIG_ENDIAN) #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) #define CONFIG_HWCONFIG #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ HID0_ENABLE_INSTRUCTION_CACHE |\ HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) /* * Definitions for initial stack pointer and data area (in DCACHE ) */ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ #define CONFIG_SYS_GBL_DATA_SIZE 0x100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* * Local Bus LCRR and LBCR regs */ #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ (0xFF << LBCR_BMT_SHIFT) |\ 0xF) #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* * Internal Definitions */ /* * DDR Setup */ #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE /* * Manually set up DDR parameters, * as this board has not the SPD connected to I2C. */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ 0x00010000 |\ CSCONFIG_ROW_BIT_13 |\ CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ CSCONFIG_BANK_BIT_3) #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ (3 << TIMING_CFG0_WRT_SHIFT) |\ (3 << TIMING_CFG0_RRT_SHIFT) |\ (3 << TIMING_CFG0_WWT_SHIFT) |\ (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_MRS_CYC_SHIFT)) #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ (7 << TIMING_CFG1_CASLAT_SHIFT) |\ (4 << TIMING_CFG1_REFREC_SHIFT) |\ (4 << TIMING_CFG1_WRREC_SHIFT) |\ (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ (2 << TIMING_CFG1_WRTORD_SHIFT)) #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ (5 << TIMING_CFG2_CPO_SHIFT) |\ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ SDRAM_CFG_DBW_32 |\ SDRAM_CFG_SDRAM_TYPE_DDR2) #define CONFIG_SYS_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ (0x0242 << SDRAM_MODE_SD_SHIFT)) #define CONFIG_SYS_DDR_MODE_2 0x00000000 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ DDRCDR_PZ_NOMZ |\ DDRCDR_NZ_NOMZ |\ DDRCDR_ODT |\ DDRCDR_M_ODR |\ DDRCDR_Q_DRN) /* * on-board devices */ #define CONFIG_TSEC1 #define CONFIG_TSEC2 #define CONFIG_TSEC_ENET #define CONFIG_HARD_SPI #define CONFIG_HARD_I2C /* * NOR FLASH setup */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_FLASH_SHOW_PROGRESS 50 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ BR_PS_8 |\ BR_MS_GPCM |\ BR_V) #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ OR_GPCM_SCY_10 |\ OR_GPCM_EHTR |\ OR_GPCM_TRLX |\ OR_GPCM_CSNT |\ OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* * NAND FLASH setup */ #define CONFIG_SYS_NAND_BASE 0xE1000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_PAGE_SIZE (2048) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ (2<